JP2002314394A - Circuit for controlling output buffer capability - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an output buffer capability control circuit which can eliminate small characteristic deviation or the like liable to occur when a semiconductor is manufactured and when a device is used and in which power consumption is also small. SOLUTION: A pair of a P-MOS transistor and an N-MOS transistor is arranged, and a circuit network obtained by combining serial connections of resistors having different resistances and switching means with a serial connection as a base unit is connected between the source terminal of the P-MOS transistor and the drain terminal of the N-MOS transistor. The performance of the pair of the P-MOS transistor and the N-MOS transistor can be controlled by making on-off selectively controllable according to the data in a register which includes the switching means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit in a semiconductor integrated circuit, and more particularly to an output buffer capacity control circuit having a function capable of controlling the capacity as required.

[0002]

2. Description of the Related Art In developing an electric device, an integrated circuit must be designed. At that time, the amount of noise radiation and the integrated circuit and peripheral circuits must be mounted on the substrate,
Problems such as signal delay and waveform dulling cannot often be completely understood. Although a certain amount of prediction is possible in advance by simulation, accurate and actual waveform prediction in a state configured as an apparatus is difficult.

[0003] At the stage of designing an integrated circuit, the buffer output capability of the output terminal is determined.
It happens that the buffering capacity is not appropriate. At present, as a countermeasure for the case where the buffer capacity is too large, a series resistor is inserted into its output terminal to allow a signal to pass, thereby reducing noise, undershoot, and overshoot.

On the other hand, when the buffer capacity is small, the problem is often solved by inserting an IC or the like having a circuit with a large buffer capacity near the output terminal into the series.

[0005] In consideration of such inconveniences, many countermeasure techniques have been proposed. Japanese Patent Application Laid-Open No. 2-44415 discloses an output buffer circuit in which a plurality of CMOS circuits are combined and a switch circuit is provided between the gates of MOSFETs corresponding to each other. By providing a control signal from the switch control circuit to each of these switches, an appropriate combination of switches can be turned on and off, and an output buffer configured to be able to control the output signal drive capability even after commercialization. Circuit.

[0006] Also, JP-A-3-238917 discloses that
A plurality of output buffers arranged to correspond individually are disclosed. A plurality of output buffers for transmitting signals via these output buffers are configured as semiconductor circuits including buffer control means for selectively forming a state in which they are commonly connected to the same terminal. As a result, the load driving capability can be changed according to the user usage state.

Another prior art for adjusting the driving capability of an output buffer according to the load capacity of a circuit is disclosed in Japanese Patent Laid-Open No. 9-21431.
Japanese Patent Application Laid-Open No. 5 (1999) -125 discloses an output buffer provided with a plurality of transistors connected in parallel between an input node to which an input signal is applied and a signal output pad, a semiconductor circuit, and a method for adjusting the driving capability of the output buffer. . A plurality of switch means capable of individually switching the inputs of these transistors are provided, and the switching state of each switch means can be set by referring to the load capacitance of an external circuit connected to the signal output pad.

Further, there is another prior art which discloses a CMOS output buffer circuit for driving current control using a plurality of CMOS stages (Japanese Patent Laid-Open No. 9-27098). In this prior art, switch circuits are provided between the gates of MOSFETs corresponding to each stage, and a switch control circuit supplies a control signal to these switches to perform on-off control.

The above-mentioned solution according to the prior art is based on reducing on-resistance by providing many parallel circuits. Therefore, there is a possibility that a noise component is superimposed on the waveform due to a minute shift of the ON timing of each circuit. In addition, power consumption increases due to the increase in the number of semiconductor elements used, and a large power supply capacity is required.
This is contrary to the demand for extending the duration, which is an important factor when used in mobile devices and the like.

[0010]

SUMMARY OF THE INVENTION The present invention solves the above-mentioned drawbacks of the prior art, reduces power consumption by a simple circuit configuration, does not cause noise or the like, and also causes noise during semiconductor manufacturing. An object of the present invention is to provide an output buffer capacity control circuit capable of solving even a minute characteristic deviation by changing software.

[0011]

The object of the present invention is to provide a pair of P
A channel MOS transistor (hereinafter also referred to as P-MOS) and an N-channel MOS transistor (hereinafter referred to as N-
-MOS), and a series connection of resistors having different resistance values and switch means is connected between the source terminal of the P-MOS transistor and the drain terminal of the N-MOS transistor as a basic unit. Connected to a pair of P-MOS transistors and N-MOSs by selectively turning on and off the switch means in accordance with data in a built-in register.
The problem is solved by an output buffer capacity control circuit configured so that the capacity of the transistor can be controlled.

Further, the object of the present invention is advantageously solved by an output buffer capacity control circuit in which the data of the register can be set by software after completion of the electronic device and / or according to the state of use of the device.

Furthermore, the minimum resistance value of the resistor is advantageously solved by an output buffer capacity control circuit selected to be substantially 0 [Ω].

According to the output buffer capacity control circuit according to the present invention, when the electronic apparatus is adjusted and / or when the electronic apparatus is in a usable state, generation of noise or abnormal waveform due to inappropriate buffer capacity is prevented. , Can be easily avoided and improved by changing the software, shortening the development period required for device development, reducing man-hours, and miniaturizing and reducing weight by simplifying device circuits, which has the advantage of contributing to cost reduction. .

According to the integrated circuit having the circuit configuration of the output buffer capacity control circuit according to the present invention, the buffer capacity of the output terminal of the integrated circuit is changed by software in response to the problem of signal dullness and radiation noise from the signal. Thus, noise radiated from the signal can be reduced, and undershoot, overshoot, and the like can be reduced. Also, even when the signal load is large and the waveform becomes dull, the software can be modified to increase the buffer capacity of the output terminal in the same manner, and the target waveform can be output. Become.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An output buffer capacity control circuit according to the present invention will be disclosed below with reference to the accompanying drawings. The configuration of the embodiment will be described with reference to FIGS. FIG. 3 is a block diagram symbolically showing various electronic / electric devices. The peripheral circuit 10 shown here is a generic name for circuit parts of various devices, and a CPU 11 and a memory 12 are connected to the peripheral circuit 10.

Output terminals of various integrated circuits in the CPU 11 and the peripheral circuit 10 are constituted by circuits as shown in FIG. Here, an output signal from an upper circuit element, not shown, enters from the left input terminal IN and is transmitted to the next stage from the right output terminal OUT.

In the circuit of FIG. 1, the P-MOS 21 and the N-MO
S31 is disposed above and below, and each gate is connected to the input terminal IN. Source terminal 2 of P-MOS 21
3 and the drain terminal 32 of the N-MOS 31 are connected in three ways based on a series connection of the switch means SW and the resistor R, that is, (1) SW1-R0-R0 '.
-SW2, (2) SW3-R1-R2-SW4, (3)
A combination network in which SW5-R3-R4-SW6 are connected in parallel is connected. Each resistor R0-R0 ',
A lead line that electrically connects the respective connection points of R1-R2 and R3-R4 becomes the output terminal OUT.

The drain terminal 22 of the P-MOS 21
Is applied with a drain voltage, and the source terminal 33 of the N-MOS is grounded.

The switch means SW1 to SW shown here
6 is controlled on-off according to the output of a register provided in the integrated circuit as described later. Also,
Resistors R0-R connected in series with these switches
0 ', R1-R2 and R3-R4 are selected to have different resistance values, for example, R0 <R1
<R3, and R0 ′ <R2 <R4. Note that the minimum resistances R0 and R0 ′ can be configured to be substantially 0 [Ω] only as the resistance of the connection conductor.

In the embodiment shown in FIG. 1, the switch SW and the resistor R
Are connected in parallel in three types, but may be four or more.

Hereinafter, details of the operation of the embodiment will be described with reference to FIGS.
4 will be described. According to the electronic / electric device according to the block diagram shown in FIG. 3, the CPU 11 issues an operation instruction to the peripheral circuit 10 in accordance with the contents of software installed in the memory 12. The means for executing the instruction is performed by a bus line, a port signal, and other signal lines, each of which is connected to a corresponding part.

A register which operates according to the logic shown in FIG. 2 is provided inside the integrated circuit in the CPU 11 and the peripheral circuit 10.
It has a configuration that can be written by an instruction from 1. According to the logic of FIG. 2, when the data is 01H, only the smallest resistances R0 and R0 'shown in FIG. 1, for example, only the switches SW1 and SW2 of the circuit having substantially 0 [Ω] are turned on. Connecting such a small resistor increases the buffer capacity.

Similarly, when the data is 02H, SW3,
When only SW4 is turned on, and when the data is 04H, S
Only W5 and SW6 are turned on, and a series circuit of resistors R1-R2 or R3-R4 having a large resistance value connected to each can be inserted, and the corresponding capability can be achieved. When a resistor having a large resistance value is connected, the buffer capacity becomes small.

To summarize these operations, in the data "01H" of FIG. 2, only SW1 and SW2 are turned on and the resistance is minimum, so that the buffer capacity is maximum. In the data "02H", only the switches SW3 and SW4 are turned on and the resistance is medium, so that the buffer capacity is medium. Further, in the data "04H", only the switches SW5 and SW6 are turned on and the resistance is the maximum, so that the buffer capacity is the minimum. In an actual operation, the buffer capacity is set to a medium level in the initial state as data “02H”, the data is set to “04H” when the buffer capacity is reduced, and the data is “01H” when the buffer capacity is increased. Can be controlled. It is to be noted that what is shown here is merely an example, and it is also possible to operate by a different logic.

SW1, SW2; SW of the circuit shown in FIG.
3, SW4; SW5 and SW6 have a circuit that is controlled on-off according to the value of the register of FIG. 2 as described above, and are connected in the circuit by the on-off operation of each of the switches SW0 to SW6. Since the resistance value varies in various ways, a change in the buffer capacity viewed from the output terminal OUT is realized. Further, this output buffer has a buffer capacity known in advance, and an arbitrary capacity can be changed by a combination of the respective resistance values.

The inventor has confirmed the waveform with a certain register value. For example, when there is an undershoot or overshoot waveform as shown in FIG. 4, or when there is a problem of noise radiation due to a harmonic that operates, a resistor having a large resistance value is connected to increase the buffer capacity. The data for determining the register value of the software is changed in the direction of decreasing the size, and the buffer capacity can be changed.

As shown in FIG. 5, when there is a problem of waveform dulling due to the size of the substrate capacitance or the wiring length, a software having a small resistance value is used to increase the buffer capacity by using a circuit having a small resistance value. The data can be changed so as to determine the register value, and the buffer capacity can be changed. It should be noted that the maximum buffer capacity is obtained when both MOS transistors are connected at substantially 0 [Ω].

[0029]

[Effect] By mounting the output buffer capacity control circuit according to the present invention in an electrical device in a device development stage, noise and abnormal waveforms due to inappropriate buffer capacity can be easily avoided by changing the circuit configuration by software. Becomes

Further, since the number of required circuit elements is smaller than that of the same configuration in the prior art, power consumption does not increase. Therefore, it is possible to expect a great effect that the development period of the electronic device can be shortened, the number of steps can be reduced, and the device circuit can be reduced in size and weight and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of an output buffer capacity control circuit according to the present invention.

FIG. 2 is a configuration example of a register that controls each switch in an output buffer capacity control circuit according to the present invention.

FIG. 3 is a block diagram symbolically showing an electronic / electric device using the output buffer capacity control circuit according to the present invention.

FIG. 4 is a waveform diagram showing an example of overshoot and undershoot output waveforms in an electronic / electric device using the output buffer capacity control circuit according to the present invention.

FIG. 5 is a waveform diagram showing an example of an output waveform in the case of inappropriate capacity in an electronic / electric device using the output buffer capacity control circuit according to the present invention.

[Explanation of symbols]

10 Peripheral circuit 11 CPU 12 Memory 21 P-channel MOS transistor (P-MO
S) 22 Drain terminal 23 Source terminal 31 N-channel MOS transistor (N-MO
S) 32 drain terminal 33 source terminal SW1 to SW6 switch means R0, R0 ', R1, R2, R3, R4 Resistance

Claims (4)

[Claims] 1. A pair of P-MOS transistors and N-M
A circuit network in which an OS transistor is provided, and a series connection of a resistor and a switch having different resistance values is connected between a source terminal of the P-MOS transistor and a drain terminal of the N-MOS transistor as a basic unit. And the switch means can be selectively turned on / off in accordance with data of a built-in register, whereby the pair of P-MOS transistors and N-MOS
An output buffer capacity control circuit characterized in that the capacity of a transistor can be controlled. 2. The output buffer capacity control circuit according to claim 1, wherein the data of the register can be set by software after completion of the electronic device and / or in accordance with the use condition of the device. 3. The output buffer capacity control circuit according to claim 1, wherein the resistance value of the resistor is selected so that the resistance value sequentially changes from small to large. 4. The output buffer capacity control circuit according to claim 3, wherein a minimum resistance value of said resistor is selected to be substantially zero [Ω].