JP2002314335A - Clock generator circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure desired duty about a clock output and also to start from a prescribed state at an initial oscillation stage about a clock generator circuit. SOLUTION: CMOS inverters 20 and 22 to which an oscillation output by a crystal resonator 14 is inputted are provided. A rectifier circuit consisting of a transistor Q4 to which the oscillation output is inputted, a capacitor C3 and a resistor R5, a comparator 26 for comparing the output of the rectifier circuit with a reference voltage, and a p type transistor M1 for changing states of the CMOS inverter 22 in accordance with the output of the comparator 26 are also provided. The connection point between the drain of a p type transistor M5 of the CMOS inverter 22 and the drain of an n type transistor M3 is made as an output terminal OUT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a clock generation circuit including an oscillation circuit having a vibrator and an inverter buffer connected to an output terminal of the oscillation circuit.

[0002]

2. Description of the Related Art Conventionally, a clock generation circuit using a Colpitts-type crystal oscillation circuit has been known.

FIG. 5 is a circuit diagram showing an example of a conventional clock generation circuit. The clock generation circuit shown in FIG. 5 includes a crystal unit 14 and a variable capacitance diode 16 connected in series between the input terminal 10 and the GND terminal 12. The input terminal 10 is connected to the base of the npn transistor Q1, one end of the capacitor CA1, and one end of the resistor R1. One end of the emitter of the transistor Q1 is GND.
It is connected to the other end of the resistor R3 connected to the terminal 12 and grounded. The other end of the capacitor CA1 is connected to the other end of the resistor R3, and one end is connected to the other end of the capacitor CA2 connected to the GND terminal 12 and grounded.

The collector of the transistor Q1 has npn
The emitter of the transistor Q2 is cascaded. The base of the transistor Q2 is connected to the other end of the resistor R1, and one end is connected to the other end of the resistor R2 connected to the reference terminal 18 where the reference voltage VREF appears. The collector of the transistor Q2 is connected to the other end of the resistor R4 whose one end is connected to the reference terminal 18. An output terminal O connected to an output load capacitance (not shown) is provided between the collector of the transistor Q2 and the resistor R4.
A UT is provided.

In such a circuit configuration, the transistor Q1 is an oscillating transistor and the transistor Q2
Is a transistor that functions as an output buffer that limits oscillation amplitude by saturation. The clock generation circuit shown in FIG. 5 oscillates by the action of the crystal oscillator 14, the capacitors CA1 and CA2, and the transistor Q1, and the output terminal OU
From T, an output signal having a predetermined oscillation frequency is output.

However, in the conventional clock generating circuit, when the output load capacitance changes, a load current flows from the reference terminal 18 via the resistor R4. Therefore, the oscillation amplitude may change, and a desired output signal may not be obtained from the output terminal OUT.

FIG. 6 is a diagram for solving such an inconvenience.
1 shows a circuit diagram of an example of a conventional clock generation circuit. 6, the same components as those shown in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.
In the clock generation circuit shown in FIG.
One end of a resistor R9 and one end of a resistor R10 are connected to the collector of the capacitor 2 via a capacitor C1. Resistance R9
Is connected to the reference terminal 18, and the other end of the resistor R10 is grounded to the GND terminal 12. Capacitor C1
Has a function of cutting direct current included in an output component appearing at the collector of the transistor Q2.

The collector of the transistor Q2 also has
The CMOS inverter 20 is connected via the capacitor C1. The CMOS inverter 20 is a p-channel type MOS transistor (hereinafter, referred to as a p-type transistor).
M4 and an n-channel MOS transistor (hereinafter referred to as an n-type transistor) M2. Specifically, the collector of the transistor Q2 is connected to the gate of the p-type transistor M4 and the gate of the n-type transistor M2. The drains of the p-type transistor M4 and the n-type transistor M2 are connected. The source of the p-type transistor M4 is connected to the reference terminal 18 where the reference voltage VREF appears. The source of the n-type transistor M2 is grounded to the GND terminal 12.

The drains of the p-type and n-type transistors M4 and M2 are connected to the gate of the p-type transistor M5 and the gate of the n-type transistor M3 constituting the CMOS inverter 22. In the CMOS inverter 22, similarly to the CMOS inverter 20, the drains of the p-type transistor M5 and the n-type transistor M3 are connected to each other. The source of the p-type transistor M5 is connected to the reference terminal 18 where the reference voltage VREF appears. The source of the n-type transistor M3 is connected to the GND terminal 12
Grounded. That is, the CMOS inverters 20 and 22 are connected in series. In the clock generation circuit shown in FIG. 6, an output terminal OUT connected to an output load capacitance (not shown) is provided between the drain of the p-type transistor M5 and the drain of the n-type transistor M3 of the CMOS inverter 22. ing.

In this configuration, the oscillating output appearing at the collector of the transistor Q2 is subjected to a DC cut by the capacitor C1, and then a bias voltage lower than the reference voltage VREF by an amount corresponding to the resistance division of the resistors R9 and R10. It fluctuates around the center. The threshold voltage VINV of the CMOS inverters 20 and 22 is represented by the following equation (1).

VINV = (√β _P (VREF + VTHP) + √β _N VTHN) / (√β _P + √β _N ) (1) where β is a function of the gate length and gate width of the transistor. A certain process gain coefficient, and VTH * is a threshold voltage of the MOS transistor.

In the CMOS inverter 20, when the oscillation output appearing on the gate side is lower than the threshold voltage VINV, the p-type transistor M4 is turned on and the n-type transistor M2 is turned off. , P
A voltage substantially equal to the reference voltage VREF appears at the drains of the type and n-type transistors M4 and M2. At this time, CMO
In the S inverter 22, the p-type transistor M5 is turned off and the n-type transistor M3 is turned on, so that the p-type and n-type transistors M5 and M3 are turned on.
A voltage substantially equal to the ground potential appears at the drain of the transistor. Therefore, when the oscillation output on the gate side of the CMOS inverter 20 is lower than the threshold voltage VINV, the output terminal OU
T outputs a low signal.

On the other hand, when the oscillation output on the gate side of the CMOS inverter 20 exceeds the threshold voltage VINV, the p-type transistor M4 is turned off, the n-type transistor M2 is turned on, and the p-type transistor M5 is turned on. Is turned on and the n-type transistor M3 is turned off, whereby a high signal is output from the output terminal OUT. Thus, the clock generation circuit shown in FIG.
4. Capacitors CA1 and CA2 and transistor Q1
Oscillates due to the action of the resistor R9, R10 and the p-type and n-type of the CMOS inverter 20 from the output terminal OUT.
A clock signal having a duty determined by the relationship with the characteristics (specifically, gate length and gate width) of the type transistors M4 and M2 is output.

In such a configuration, the oscillation output is output via the CMOS inverter 22 functioning as an inverter buffer. Therefore, when the output load capacitance changes, the amplitude fluctuation is caused by the p-type and n-type transistors M5, M
3 can be suppressed only to the variation due to the on-resistance. Therefore, according to the clock generation circuit shown in FIG. 6, even if the output load capacitance changes, the amplitude fluctuation of the oscillation output can be suppressed small, and a desired output signal can be obtained from the output terminal OUT. .

[0015]

The duty of the clock signal output from the clock generation circuit is 50.
%, And it is desirable that the clock signal is always output from either the low state or the high state at the start of oscillation (that is, immediately after power-on). However, in the clock generation circuit shown in FIG.
Resistors R9, R10 and p-type and n-type transistors M
If the characteristics of M4 and M2 are adjusted, a duty of 50% can be secured, but in that state, the clock signal cannot be maintained in any state at the beginning of oscillation. That is,
To keep the clock signal in any state at the beginning of oscillation, it is necessary to set the characteristics of the p-type and n-type transistors M4 and M2 so as to be extremely shifted. In this case, it is necessary to secure a duty of 50%. Can not be done. As described above, the clock generation circuit shown in FIG. 6 cannot satisfy both the requirement to secure a desired duty for the clock signal and the requirement to start clock output from a predetermined state at the beginning of oscillation. Was.

The present invention has been made in view of the above points, and provides a clock generation circuit capable of securing a desired duty for a clock output and starting from a predetermined state at an initial stage of oscillation. With the goal.

[0017]

According to a first aspect of the present invention, an oscillation circuit having a vibrator (14) is connected to an output terminal (collector terminal of a transistor Q2) of the oscillation circuit. Buffer (CMOS inverters 20, 2) that outputs a clock signal based on the output of
2) a rectifier circuit (transistor Q4, capacitor C3, resistor R3) connected to the output terminal of the oscillation circuit and rectifying the output of the oscillation circuit.
5) a comparator (26) for comparing the output of the rectifier circuit with a predetermined threshold value; and the comparator (26).
Of the inverter buffer (CMOS
And a switching element (M1) for switching the input of the inverters 20 and 22).

According to the first aspect of the present invention, the output terminal of the oscillation circuit is connected to an inverter buffer and to a rectifier circuit. The rectifier circuit is also connected to a comparator that compares the output of the rectifier circuit with a predetermined threshold. The comparator is connected to a switching element that switches an input to the inverter buffer according to a result of the comparison. In such a configuration, the output of the rectifier circuit input to the comparator indicates either an increasing tendency or a decreasing tendency as the oscillation oscillation advances after the power is turned on. in this case,
Until the output of the rectifier circuit reaches a predetermined threshold, the output of the comparator is maintained in any state, so that the switching element is in any state at the beginning of oscillation,
The clock signal is either low or high.
Therefore, according to the present invention, the clock signal can be started from the low state or the high state at the initial stage of oscillation without changing the characteristics of the inverter buffer. Therefore, according to the present invention, it is possible to secure a desired duty for the clock output and to start from a predetermined state at the beginning of oscillation.

In this case, as in the second aspect of the present invention, in the clock generating circuit according to the first aspect, the rectifier circuit includes a transistor (Q4) and a capacitor (C).
3) and a resistor (R5).

According to a third aspect of the present invention, there is provided an oscillation circuit having a vibrator (14), an inverter buffer (CMOS inverters 36, 38) for outputting a clock signal based on an output of the oscillation circuit, A clock generation circuit including the inverter buffer (CMOS inverters 36 and 3) when the reference voltage is in a transient state.
And 8) a switching element for connecting the input of (8) to the GND terminal and connecting the input of the inverter buffer (CMOS inverters 36 and 38) to the output side of the oscillation circuit after the transient state of the reference voltage is completed. And

According to a third aspect of the present invention, the switching element connects the input of the inverter buffer to the GND terminal when the reference voltage is in a transient state, and outputs the output of the oscillation circuit after the transient of the reference voltage is completed. To the side. Therefore, in a transition period after the power is turned on, the inverter buffer is in one of the states, and the clock signal is in either the low state or the high state. Therefore, according to the present invention, without changing the characteristics of the inverter buffer,
The clock signal can be started from a low state or a high state at the beginning of oscillation. Therefore, according to the present invention, it is possible to secure a desired duty for the clock output and start from a predetermined state at the beginning of oscillation.

In this case, as in the invention according to claim 4, in the clock generation circuit according to claim 3, an input terminal is connected to an output of the oscillation circuit, and an output terminal is connected to an input of the inverter buffer. A hysteresis comparator may be provided.

Further, as in the invention described in claim 5,
5. The clock generation circuit according to claim 4, wherein a threshold value of the hysteresis comparator is switched according to an output of the inverter buffer.

Note that the reference numerals in the parentheses are provided for easy understanding, are merely examples, and are not limited to the illustrated embodiment.

[0025]

FIG. 1 is a circuit diagram of a clock generation circuit according to a first embodiment of the present invention. In FIG. 1, the same components as those shown in FIG. 5 or FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted.
As shown in FIG. 1, in the clock generation circuit, a capacitor C2 is connected to the collector of the transistor Q2 in parallel with the capacitor C1.

The base of the npn transistor Q4 is connected to the capacitor C2. The collector of the transistor Q4 is connected to the reference terminal 18. Transistor Q
The four emitters are both connected to the other end of the capacitor C3 and one end of the resistor R5, one end of which is grounded to the GND terminal 12. Thus, a rectifier circuit is configured. The emitter of the transistor Q4 is connected to a pnp transistor Q
5 connected to the base. The emitter of the transistor Q5 is connected to the reference terminal 18 via the constant current source 24. The collector of the transistor Q5 is grounded to the GND terminal 12.

The emitter of the transistor Q5 also has
The non-inverting input terminal of the comparator 26 is connected.
The inverting input terminal of the comparator 26 is connected to the reference terminal 18 via the resistor R8, and is also grounded to the GND terminal 12 via the resistor R6 and the capacitor C4. The inverting input terminal of the comparator 26 is connected to the base of the transistor Q4 via the resistor R7. The comparator 26 outputs a low signal when the voltage input to the non-inverting input terminal is smaller than the voltage input to the inverting input terminal, and outputs a high signal when the voltage is opposite thereto.

The output terminal of the comparator 26 is connected to the gate of the p-type transistor M1. The source of the p-type transistor M1 is connected to the reference terminal 18. The drain of the p-type transistor M1 is connected to the gate side of the CMOS inverter 22 and the resistance R1
1 is connected to the drain side of the CMOS inverter 20. The p-type transistor M1 is connected to the comparator 26
Is turned on when the output of
The reference voltage VREF is supplied to the gate of the CMOS inverter 22. On the other hand, when the output of the comparator 26 is in the high state, the output is turned off, so that the supply of the reference voltage VREF to the gate of the CMOS inverter 22 is stopped. In the present embodiment, p of the CMOS inverter 22
Drain of n-type transistor M5 and n-type transistor M3
The output terminal OUT is provided between the output terminal OUT and the drain.

Next, the operation of the clock generation circuit of this embodiment will be described.

In the clock generation circuit of the present embodiment, the transistor Q4 is biased by the resistors R8 and R6 in the initial stage of oscillation immediately after the power is turned on. The transistor Q5 has an emitter connected to the constant current source 24,
The collector is configured to be grounded. Therefore, if the current flowing through the transistor Q4 and the current flowing through the transistor Q5 are adjusted, the voltage input to the non-inverting input terminal of the comparator 26 at the initial stage of the oscillation is lower than the voltage input to the inverting input terminal. Can also be set lower.

When such setting is made, the comparator 2
6 outputs a low signal, and the p-type transistor M1 is turned on, whereby the gate of the CMOS inverter 22 is supplied with the reference voltage VREF. In this case, the p-type transistor M5 is turned off and the n-type transistor M3 is turned on, so that a low signal is output from the output terminal OUT. Therefore, according to the clock generation circuit of the present embodiment, by adjusting the current flowing through the transistor Q4 and the current flowing through the transistor Q5, it becomes possible to start the output at the initial stage of oscillation from the low state.

In this embodiment, when the oscillation by the crystal oscillator 14 starts after the power is turned on, the charge and discharge of the capacitor C3 are repeatedly performed in accordance with the oscillation cycle by the action of the transistor Q4. At this time, the base voltage of the transistor Q5 gradually increases due to the relationship with the time constant determined by the capacitor C3 and the resistor R5. When the emitter voltage rises with the rise of the base voltage, the voltage eventually exceeds the input voltage input to the inverting input of the comparator 26. That is, the voltage input to the non-inverting input terminal of the comparator 26 may be higher than the voltage input to the inverting input terminal.

When such a situation occurs, the comparator 2
6 is inverted, and the p-type transistor M1 is turned off. After the p-type transistor M1 is turned off,
The voltage input to the gate of the CMOS inverter 22 fluctuates according to the state of the oscillation output input to the base of the CMOS inverter 20 via the capacitor C1. Therefore, according to the clock generation circuit of the present embodiment, after the oscillation is started, a clock signal corresponding to the oscillation output of the crystal oscillator 14 can be output from the output terminal OUT.

In the clock generation circuit of the present embodiment, similarly to the clock generation circuit shown in FIG.
By adjusting R10 and the characteristics of the p-type and n-type transistors M4 and M2, the duty of the clock signal can be maintained at a value near 50%. Therefore, according to the clock generation circuit of the present embodiment, it is possible to start the clock signal from the low state at the initial stage of the oscillation while securing the duty of the clock signal at 50%. That is, it is possible to satisfy both the requirement of ensuring a 50% duty for the clock signal and the requirement of starting from a low state.

In this embodiment, an inverter buffer including CMOS inverters 20 and 22 is used as a clock signal generating circuit. For this reason,
Even if the oscillation output gain is high and the crystal oscillator 14 is oscillating with a minute amplitude, the amplitude of the clock output can be sufficiently ensured, and an output with a short amplitude startup time can be obtained. .

Next, a second embodiment of the present invention will be described with reference to FIGS.

FIG. 2 is a circuit diagram of the clock generation circuit of the present embodiment. In FIG. 2, the same components as those shown in FIG. 5 or FIG. 6 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 2, in the clock generation circuit of the present embodiment, one end of the resistor R12 and one end of the resistor R13 are connected to the capacitor C1 connected to the collector of the transistor Q2. The other end of the resistor R12 is connected to the reference terminal 18, and the other end of the resistor R13 is connected to G
The ND terminal 12 is grounded.

The gate of the n-type transistor M6 is connected to the capacitor C1, one end of the resistor R12, and one end of the resistor R13. The drain of the n-type transistor M6 is connected to the reference terminal 18 via the constant current source 30. The source of the n-type transistor M6 is grounded to the GND terminal 12 via the constant current source 32. The substrate gate of the n-type transistor M6 is connected to the GND terminal 1
2 and to the substrate gate of the n-type transistor M7. n-type transistor M
The drain of 7 is connected to the reference terminal 18 via a constant current source 34. The source of the n-type transistor M7 is grounded to the GND terminal 12 via the constant current source 32 described above. That is, the n-type transistors M6 and M7 constitute a differential amplifier.

The gate of the n-type transistor M7 is connected to a resistor R
14 and one end of the resistor R15. The other end of the resistor R14 is connected to the reference terminal 18. The resistor R15 is grounded to the GND terminal 12. In the present embodiment, the resistance values of the resistors R12, R13, R14, and R15 are set so that the resistance division ratio of the resistors R14 and R15 substantially matches the resistance division ratio of the resistors R12 and R13. I have.

The gate of the n-type transistor M7 is connected to the gate of the p-type transistor M17 of the CMOS inverter 36 and the n-type transistor M1 via the resistor R16.
6 gates are connected. P-type transistor M17
Are connected to the reference terminal 18. The source of the n-type transistor M16 is connected to the GND terminal 12.
The drains of the p-type transistor M17 and the n-type transistor M16 are connected. An output terminal OUT is provided between the two drains.

The drain of the p-type transistor M8 is connected to the drain of the n-type transistor M6. The gate of the p-type transistor M8 is grounded to the GND terminal 12. The source of the p-type transistor M8 has n
The drain of the type transistor M10 is connected, and the gate is connected. N-type transistor M10
Are grounded to the GND terminal 12. The gate of the n-type transistor M10 also has an n-type transistor M
Eleven gates are connected. n-type transistor M1
1 is grounded to the GND terminal 12. The n-type transistors M10 and M11 form a current mirror circuit.

The drain of the n-type transistor M11 has
The drain of the p-type transistor M9 is connected. p
The source of the type transistor M9 is connected to the drain of the n-type transistor M7. The gate of the p-type transistor M9 is connected to the gate of the p-type transistor M8, and is grounded to the GND terminal 12.

The drain of the p-type transistor M9 and the drain of the n-type transistor M11 (hereinafter, these drain terminals are referred to as point A) are connected to the drain of the p-type transistor M14 and the n-type transistor M13 constituting the CMOS inverter 38. The drain is connected. The source of the p-type transistor M14 is connected to the reference terminal 18. The source of the n-type transistor M13 is grounded to the GND terminal 12. The drains of the p-type transistor M14 and the n-type transistor M13 are connected to each other.
The two drains are connected to the gate side of the CMOS inverter 36 described above.

At point A, an n-type transistor M12
Drain is connected. N-type transistor M12
Are grounded to the GND terminal 12. The drain of the n-type transistor M15 (hereinafter, this drain terminal is referred to as point B) is connected to the gate of the n-type transistor M12. The source of the n-type transistor M15 is GN
The D terminal 12 is grounded. The drain of the n-type transistor M15 is connected to the reference terminal 18 via the constant current source 40. The gate of the n-type transistor M15 (hereinafter, this terminal is referred to as point C) is connected to one end of the resistor R17 and the resistor R17.
18 is connected to one end. The other end of the resistor R17 is connected to the reference terminal 18. The other end of the resistor R18 is GN
The D terminal 12 is grounded.

Next, the operation of the clock generation circuit of this embodiment will be described with reference to FIG. FIG. 3 is a timing chart for explaining the operation of the clock generation circuit of this embodiment. FIG. 4 is a diagram showing the relationship between the oscillation by the crystal oscillator 14 and the clock output in the clock generation circuit of the present embodiment. In the transition period immediately after the power is turned on, the n-type transistor M15 operates at the voltage V _{C at the} point _C.
Until a threshold value V _TH15 (shown by a broken line in FIG. 3A) exceeds the threshold value V _TH15 , the off state is maintained. At this time, the voltage V B at the point _B (shown by a thick solid line in FIG.
As shown in (A), the voltage rises along the reference voltage VREF. The n-type transistor M12 is kept off until the voltage V B at the point _B exceeds the threshold value V _TH12 . At this time, the voltage VA at the point _A increases in proportion to the reference voltage VREF, as shown in FIG.

Then, at time t1 after the power is turned on, B
The point voltage V _B is equal to the threshold value V of the n-type transistor M12.
Upon reaching _TH12, by n-type transistor M12 is turned on, the voltage V _A at point A as shown in FIG. 3 (B) 0
V is the ground potential. At this time, the CMOS inverter 38
Becomes low, the p-type transistor M14
Is turned on and the n-type transistor M13 is turned off, so that the p-type and n-type transistors M1 are turned off.
4, a voltage equal to the reference voltage VREF appears at the drain of M13.

When such a situation is realized, the gate of the n-type transistor M7 is pulled up via the p-type transistor M14. Further, the gate voltage V _M6G of the n-type transistor M6 is a voltage according to the resistance division ratio between the resistors R11 and R12 before the oscillation by the crystal oscillator 14 is started. Therefore, when the above situation is realized, the gate voltage _M6G of the n-type transistor M6 becomes n
It becomes smaller than the gate voltage _M7G of the type transistor M7. In this case, when the n-type transistor M7 is turned on, the current from the n-type transistor M7 to the constant current source 32 increases, and the current from the n-type transistor M6 to the constant current source 32 decreases. As a result, the current flowing from the constant current source 30 to the p-type transistor M8 increases, so that the current flows to the source side of the p-type transistor M8 and the n-type transistors M11 and M12 are turned on. The voltage _{VA at the} point becomes the ground potential of 0V.

When the voltage VA at the point _A becomes 0 V, the CMOS
As a result of the input of the inverter 38 going low, the CMOS
The output of the inverter 38 becomes high. In this case, C
Since the input of the MOS inverter 36 goes high, p
The p-type and n-type transistors M17 are turned off and the n-type transistor M16 is turned on.
A ground potential of 0 V appears at the drains of the type transistors M17 and M16, and the output of the CMOS inverter 36 goes low.

Therefore, in the present embodiment, the input of the CMOS inverter 38 is set to the low state by turning on the n-type transistor M12 in the transition period after the power is turned on, and the low level is output from the output terminal OUT. A signal is output. Therefore, according to the clock generation circuit of the present embodiment, it is possible to start the clock output from the low state at the initial stage of the oscillation.

When the voltage V _C reaches the threshold value V _TH15 as a result of the voltage increase at point C continuing at time t2 after the power is turned on, the n-type transistor M15 is turned on, and the point B is turned on. the voltage V _B to the ground potential of 0V as shown in FIG. 3 (a) of. At this time, the n-type transistor M
12 is in the off state, but the voltage at point _A is 0 V, so that the output signal from the output terminal OUT is still kept in the low state.

Thereafter, the oscillation by the crystal oscillator 14 is started. As a result, when the gate voltage V _M6G of the n-type transistor M6 becomes larger than the gate voltage V _M7G of the n-type transistor M7, the n-type transistor M6 is turned on. By entering the state, the current from the n-type transistor M6 to the constant current source 32 increases, and the current from the n-type transistor M7 to the constant current source 32 decreases. As a result, the constant current source 3
When the current flowing from 0 to the p-type transistor M8 decreases, the n-type transistors M11 and M12 are turned off, and the current from the constant current source 32 to the p-type transistor M9 increases, thereby increasing the p-type transistor. A current flows to the source side of M9. In this case, the voltage VA at the point _A is inverted from 0 V as shown in FIG.

When the voltage VA at the point _A becomes high, the p-type transistor M14 is turned off and the n-type transistor M13 is turned on.
8 is in a low state, as a result, the p-type transistor M17 is turned on, and the n-type transistor M16 is turned on.
Is turned off, the output of the CMOS inverter 36 becomes high, and a high signal is output from the output terminal OUT.

When the output of the CMOS inverter 38 goes low, the gate of the n-type transistor M7 is pulled down via the n-type transistor M13.
The gate voltage V _M7G of the type transistor M7 is shown in FIG.
_Is switched to the low voltage _VM7GL side as shown in _FIG . Thus n
Even switched gate voltage V _M7G type transistor M7, the gate voltage V _M6G the n-type transistor M6 to below the gate voltage V _M7GL of n-type transistors M7, the output of the CMOS inverter 36 in FIG. 4 (B) It is maintained at a high state as shown.

When the gate voltage V _M6G of the n-type transistor M6 falls below the gate voltage V _M7G of the n-type transistor M7 due to the action of the oscillation of the crystal oscillator 14, the voltage _VA at the point _A becomes 0V as described above. When the potential becomes C
The output of the MOS inverter 36 becomes low, and a low signal is output from the output terminal OUT. At this time, CMOS
When the output of the inverter 38 goes low, the gate of the n-type transistor M7 is pulled up, and the gate voltage _VM7G of the n-type transistor M7 switches to the high voltage _VM7GH .

As described above, in this embodiment, FIG.
As (A), the gate voltage V _M7G of n-type transistors M7 in accordance with the oscillation state due to the crystal oscillator 14 is switched between a high voltage V _M7GH side and the low voltage V _M7GL side. That is,
By the transistors M6 to M11 and the resistors 12 to R15, the gate voltages V _M6G ,
Hysteresis comparator for comparing the V _{M 7G} each other is formed. In such a configuration, the resistors R12 to R1
By adjusting the resistance values of _R5 and R16, the hysteresis width of the gate voltage V _M7G of the n-type transistor M7 can be arbitrarily set.

Therefore, according to the clock generation circuit of the present embodiment, it is possible to secure a value near 50% as the duty of the clock signal output from the output terminal OUT. As described above, the clock signal starts from a low state at the beginning of oscillation. Therefore, according to the clock generation circuit of the present embodiment, it is possible to secure the duty of the clock output to a desired 50% and to start from the low state at the beginning of oscillation.

In this embodiment, only one capacitor C1 requires a relatively large area. Therefore, according to the circuit configuration of the present embodiment, it is possible to avoid an increase in the size of the clock generation circuit,
The chip area can be reduced.

As described above, according to the first to fifth aspects of the present invention, it is possible to secure a desired duty for the clock output and start from a predetermined state at the beginning of oscillation.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a clock generation circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a clock generation circuit according to a second embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the clock generation circuit according to the embodiment.

FIG. 4 is a diagram illustrating a relationship between oscillation by a vibrator and a clock output in the clock generation circuit of the present embodiment.

FIG. 5 is a circuit diagram of an example of a conventional clock generation circuit.

FIG. 6 is a circuit diagram of an example of a conventional clock generation circuit.

[Explanation of symbols]

12 GND terminal 14 Quartz crystal oscillator 18 Reference terminal 20, 22, 36, 38 CMOS inverter 26 Comparator M1, M4, M5, M8, M9, M14, M17 P-channel MOS transistor (p-type transistor) M2, M3, M6 M7, M10, M11, M12, M
13, M15, M16 n-channel MOS transistor (n-type transistor) Q * transistor C * capacitor R * resistor OUT output terminal

Claims (5)

[Claims] 1. A clock generation circuit comprising: an oscillation circuit having a vibrator; and an inverter buffer connected to an output terminal of the oscillation circuit and outputting a clock signal based on an output of the oscillation output. A rectifier circuit connected to an output terminal of the oscillating circuit, for rectifying the output of the oscillating circuit; a comparator for comparing the output of the rectifying circuit with a predetermined threshold value; A clock generation circuit, comprising: a switching element that switches an input; 2. The clock generation circuit according to claim 1, wherein said rectifier circuit is constituted by a transistor, a capacitor, and a resistor. 3. A clock generation circuit comprising: an oscillation circuit having a vibrator; and an inverter buffer that outputs a clock signal based on an output of the oscillation circuit, wherein the inverter is provided when a reference voltage is in a transient state. A clock generation circuit comprising: a switching element that connects an input of a buffer to a GND terminal and connects an input of the inverter buffer to an output side of the oscillation circuit after a transient state of a reference voltage ends. 4. The clock generation circuit according to claim 3, further comprising a hysteresis comparator having an input terminal connected to an output of said oscillation circuit and an output terminal connected to an input of said inverter buffer. . 5. The clock generation circuit according to claim 4, wherein a threshold value of said hysteresis comparator is switched according to an output of said inverter buffer.