JP2002313957A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a gate insulating film from being contaminated when a contact which connects a cell and a gate of a semiconductor integrated circuit device, specially, a static type semiconductor storage device is formed and to sufficiently reduce the cell area. SOLUTION: At an end part of a first common gate which included in a second CMOS inverter 20, a first contact part 20c is formed which is electrically connected to a p-type drain diffusion layer 21d of a p-type MOSFET 21p of the second CMOS inverter 20. The first common gate 10G is in a polymetal electrode structure in a first CMOS inverter 10, but in the second CMOS inverter 20, a gate insulating film 32 and a gate lower layer 33 are broken and a bimetal layer 34 and a gate upper layer 35 are electrically connected to a contact area 21dc of the p-type drain diffusion layer 21d.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device capable of reducing the area of a memory cell of a static semiconductor memory device and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 27 shows an SRAM (static random acces).
s memory) shows a general circuit configuration of one memory cell of the device. As shown in FIG. 27, the memory cell of the SRAM device is a p-type MOS having drains connected to each other.
A first CMOS inverter 101 comprising an FET 101p and an n-type MOSFET 101n, a p-type MOSFET 102p and an n-type MOSFET
Second CMOS inverter 102 composed of ET102n
The input / output terminals of the first CMOS inverter 101 and the input / output terminals of the second CMOS inverter 102 are connected alternately, and are so-called cross-coupled.

That is, the first CMOS inverter 10
1 shared gate 101g is connected to the second CMOS inverter 1
02 is connected to the drain region 102d of the second
The common gate 102g of the CMOS inverter 102 is connected to the drain region 101d of the first CMOS inverter 101.
When the semiconductor device is formed, the contacts of the shared gates 101g and 102g and the contacts of the drain diffusion regions 101d and 102d are separately formed, and these are connected by wiring.

Normally, the contact with each of the shared gates 101g and 102g and the contact with the drain regions 101d and 102d are separately formed, which is a factor that cannot reduce the cell area of the SRAM device.

Japanese Patent Application Laid-Open No. 2000-188340 describes a shared contact technique for connecting a shared gate and a drain diffusion region with one contact. FIG. 28 shows an SRAM disclosed in the above publication.
2 shows a plan configuration of a memory cell of the device.

As shown in FIG. 28, in the first CMOS inverter 101, the drain diffusion region 201d of the p-type MOSFET 101p and the drain diffusion region 201d of the n-type MOSFET 101n are electrically connected by a metal wiring 203. In the second CMOS inverter 102, the drain diffusion region 202d of the p-type MOSFET 102p and the drain diffusion region 202d of the n-type MOSFET 102n are electrically connected by a metal wiring 203.

The gate wiring 201g made of polysilicon of the first CMOS inverter 101 is a p-type MO.
A branch between the SFET 101p and the n-type MOSFET 101n,
It is electrically connected to the drain diffusion region 202d of the type MOSFET 102p by a shared contact 204. Similarly, the gate wiring 202g of the second CMOS inverter 102 branches between the p-type MOSFET 102p and the n-type MOSFET 102n, and
Drain diffusion region 201d of p-type MOSFET 101p in inverter 101 and shared contact 20
4 are electrically connected.

As described above, the three members of the gate wiring 201g, the drain diffusion region 202d, and the metal wiring 203 can be simultaneously connected by one shared contact like the shared contact 204. So you can reduce the number,
Generally, the area of a memory cell can be reduced.

[0009]

However, in the conventional SRAM device, although the cell area is reduced by the shared contact 204, for example, a contact between the metal wiring 203 and the drain diffusion region 201d is formed. When forming the shared contact 204 that connects the metal wiring 203, the drain diffusion region 202d, and the gate wiring 201g in common, it is necessary to set a margin for mask alignment.
For this reason, there is a problem that it is difficult to further reduce the cell area.

In the manufacturing method, when a contact is generally formed on a drain diffusion region, a mask pattern is formed on a gate insulating film. When the mask pattern is formed and removed, the surface of the gate insulating film is contaminated, and there is a problem that the reliability of the gate insulating film is deteriorated.

The present invention solves the above-mentioned conventional problems, and in a semiconductor integrated circuit device, in particular, in a static semiconductor memory device, prevents contamination of a gate insulating film at the time of forming a contact and improves reliability of the gate insulating film. A first object is to achieve this, and a second object is to enable the cell area to be sufficiently reduced.

[0012]

In order to achieve the first object, according to the present invention, a gate electrode has a two-layer structure, and a contact hole is formed simultaneously with a gate insulating film and a lower layer of the gate electrode during contact formation. Is formed.

According to another aspect of the present invention, a shared contact for connecting a diffusion layer and a shared gate is a self-aligned contact.

Specifically, a first semiconductor integrated circuit device according to the present invention achieves the first object, and has a first shared gate formed on a semiconductor region via a gate insulating film. And a second complementary transistor pair having a second shared gate formed on the semiconductor region via a gate insulating film, wherein the first shared gate is the second shared transistor pair.
Connected to a common drain of the complementary transistor pair of
For a static semiconductor memory device in which a second shared gate is connected to a common drain of the first complementary transistor pair, the first shared gate is located on the region of the first complementary transistor pair from below. A first layer and a second layer are sequentially formed, and a second layer has a common drain and gate insulating film and a first layer on a region of the second complementary transistor pair.
A first contact portion that is electrically connected without the interposition of a layer, the second shared gate includes a first layer and a second layer that are sequentially formed from below on a region of the second complementary transistor pair;
The second layer has a second contact portion on the region of the first complementary transistor pair, the second layer being electrically connected to the common drain and the gate insulating film without passing through the first layer. .

According to the first semiconductor integrated circuit device, the first
The second shared gate has a configuration including a first layer and a second layer, and the second layer is connected to a common drain of each complementary transistor pair without a gate insulating film and the first layer. This means that the gate insulating film and the first layer must be etched at the same time because the second layer needs to be in contact with the semiconductor region when forming the connection holes for the first and second contact portions during manufacturing. become. Therefore, the contamination of the surface of the gate insulating film, which has a large effect on the operation characteristics of the transistor, when forming or removing the mask pattern of the connection hole is prevented, so that the reliability of the gate insulating film is improved. When a material having a lower resistivity than the first layer is used for the second layer, the contact resistance between the shared gate and the common drain can be reliably reduced.

In the first semiconductor integrated circuit device, the first
The first shared gate side of the contact portion includes a first layer below the second layer, and the first shared gate side of the second contact portion includes the first layer below the second layer. It is preferred that Here, for example, in the case where the semiconductor region and the first layer of the shared gate have the same composition, assuming that all the contact portions are only the second layer and do not include the first layer, When the gate patterning is performed, the semiconductor region may be damaged. In this case, the first layer remains below the side end of the contact portion even after the patterning of the second layer. , First
Since the semiconductor region is protected during patterning of the layer, the semiconductor region is not damaged.

In the first semiconductor integrated circuit device, the first
Preferably, the layer comprises silicon and the second layer comprises a metal or a metal silicide. With this configuration, the first shared gate and the second shared gate can be so-called polymetal electrodes.

A second semiconductor integrated circuit device according to the present invention achieves the second object, and includes a first complementary transistor pair having a first shared gate formed on a semiconductor region, and a first complementary transistor pair having a first shared gate formed on the semiconductor region. And a second pair of complementary transistors having a second common gate formed in the first pair, the first common gate is connected to a common drain of the second pair of complementary transistors, and the second common gate is connected to the first common gate. For a static semiconductor memory device connected to a common drain of a complementary transistor pair, the static semiconductor memory device is formed on a second complementary transistor pair so as to straddle the side of the first shared gate, First connecting means for connecting the common drain of the second complementary transistor pair to a common drain of the second complementary transistor pair; and a second common gate formed on the first complementary transistor pair so as to straddle the side of the second shared gate. Gate and A second connection means for connecting to a common drain of one complementary transistor pair, wherein the first shared gate and the second shared gate are formed on the semiconductor region from the lower side in the order of the first layer and the first layer. The first shared gate is formed of two layers, and the second layer of the first shared gate is electrically connected to the drain via first connection means, and the second shared gate is connected to the second shared gate. A second layer of the gate is electrically connected to the drain via second connection means.

According to the second semiconductor integrated circuit device, the first
Connecting means for connecting the common gate of the second complementary transistor pair and the common drain of the second complementary transistor pair so as to straddle the side of the first shared gate on the second complementary transistor pair, that is, to perform self-connection. Since it is formed as an aligned contact, it is possible to reduce a margin for mask alignment when patterning the first or second connection means.
The cell area can be reduced.

In this case, it is preferable that the first layer contains silicon and the second layer is made of metal or metal silicide.

A third semiconductor integrated circuit device according to the present invention achieves the second object, and has a first complementary transistor pair having a first shared gate formed on a semiconductor region made of silicon; A second complementary transistor pair having a second shared gate formed on the semiconductor region, a first shared gate connected to a common drain of the second complementary transistor pair, and a second shared gate connected to the second complementary gate. For a static semiconductor memory device connected to a common drain of a first complementary transistor pair, a first shared gate and a second shared gate are formed of a first layer and a second layer formed sequentially from a semiconductor region side. A first shared gate and a second shared gate.
Are electrically connected to the common drain of the pair of complementary transistors by the first silicide layer in which both the side surface of the first layer and the upper part of the drain are silicided.
The shared gate and the common drain of the first complementary transistor pair are electrically connected by a second silicide layer in which both the side surface of the first layer and the upper part of the drain are silicided.

According to the third semiconductor integrated circuit device, the first
The side of the first layer of the shared gate and the upper part of the common drain of the second complementary transistor pair are silicided, and the side of the first layer of the second shared gate and the common of the first complementary transistor pair are silicided. Since the upper part of the drain is silicided, a shared contact is not required, so that the cell area can be reduced.

The first to third semiconductor integrated circuit devices of the present invention are formed on the first complementary transistor pair so as to straddle the side of the first shared gate. Third connection means for connecting the source of the complementary transistor pair and a second connection gate formed on the second complementary transistor pair so as to straddle the side of the second shared gate; Preferably, the semiconductor device further includes fourth connection means for connecting the source of the type transistor pair. In this case, not only the connection between the shared gate and the common drain, but also the contact for connecting the source to another wiring is a self-aligned contact, which further promotes a reduction in cell area. it can.

According to the first method of manufacturing a semiconductor integrated circuit device of the present invention, a gate insulating film is formed on each of a first complementary transistor pair and a second complementary transistor pair, each having a diffusion layer. Forming a first opening portion on the diffusion layer of the second complementary transistor pair in the gate insulating film and the gate first forming layer, and forming the gate insulating film and the gate. Forming a second opening on the diffusion layer of the first complementary transistor pair in the first formation layer; and forming a gate opening inside the first opening and the second opening and on the gate first formation layer. Depositing a second forming layer, forming a first contact forming portion including a gate second forming layer in the first opening, and forming a second contact forming portion including the gate second forming layer in the second opening; And game By patterning the first formation layer and the gate second formation layer so as to extend over the diffusion layer of the first complementary transistor pair, the gate second gate at the end on the second complementary transistor pair side is formed. Forming a first shared gate having a first contact portion in which a formation layer is electrically connected to the diffusion layer of the second complementary transistor pair without interposing the gate first formation layer; and a gate first formation layer. And patterning the gate second formation layer so as to extend over the diffusion layer of the second complementary transistor pair, so that the gate second formation layer has a gate at the end on the first complementary transistor pair side. The first without the first forming layer
Forming a second shared gate having a second contact portion electrically connected to the diffusion layer of the complementary transistor pair.

According to the first method for manufacturing a semiconductor integrated circuit device, focusing only on the first complementary transistor pair,
Since the first opening is formed on the diffusion layer of the second complementary transistor pair in the gate insulating film and the gate first formation layer, the second opening is formed at the time of forming the first shared gate of the first complementary transistor pair. Since the gate insulating film of the complementary transistor pair is not exposed, the first semiconductor integrated circuit device of the present invention can be realized.

In the first method of manufacturing a semiconductor integrated circuit device, the step of patterning the first shared gate includes the step of forming the first gate formed layer on the second shared gate side of the first contact portion and below the second gate formed layer. Patterned to include,
It is preferable that the patterning step of the second shared gate is performed so as to include the first gate forming layer on the first common gate side of the second contact portion and below the second gate forming layer. In this case, for example, when each complementary transistor pair is formed on the semiconductor substrate and the semiconductor substrate and the first layer of the shared gate have the same composition, all the contact portions are formed only of the second layer and If one layer is not included, the semiconductor substrate may be damaged when patterning the gate on the first layer.
In this case, even after the patterning of the second layer, the first layer remains below the side end of the contact portion, so that the semiconductor substrate is protected during the patterning of the first layer,
The semiconductor substrate is not damaged.

According to a second method of manufacturing a semiconductor integrated circuit device according to the present invention, a gate insulating film and a gate first formation layer are formed in a formation region of a first complementary transistor pair and a formation region of a second complementary transistor pair. Forming a gate and a second gate forming layer in sequence, and, with respect to the first gate forming layer and the second gate forming layer, extending over a region where the first complementary transistor pair is formed and having one end at the second end. Forming a first shared gate composed of a gate first formation layer and a gate second formation layer by patterning so as to be included in the formation region of the complementary transistor pair of Patterning the formation layer so that it extends over the formation region of the second complementary transistor pair and one end is included in the formation region of the first complementary transistor pair; Forming a second shared gate composed of a gate first formation layer and a gate second formation layer; and forming a first conductivity type and a second conductivity type in each formation region of the first complementary transistor pair and the second complementary transistor pair. Forming a second conductive type diffusion layer, depositing an insulating film so as to include the first shared gate and the second shared gate, and diffusing a second complementary transistor pair in the deposited insulating film. Forming a first connection hole exposing both the layer and the end of the first shared gate; and forming, in the deposited insulating film, a diffusion layer of the first complementary transistor pair and an end of the second shared gate. Forming a second connection hole exposing the first common gate and the diffusion layer of the second complementary transistor pair by filling the first connection hole with a conductive material. And filling the second connection hole with a conductive material. By,
Electrically connecting the second shared gate and the diffusion layer of the first complementary transistor pair.

According to the second method of manufacturing a semiconductor integrated circuit device, when attention is focused only on the first complementary transistor pair, the second complementary type transistor is formed on the insulating film deposited so as to include the first shared gate. Forming a first connection hole exposing both the diffusion layer of the transistor pair and an end of the first shared gate;
By filling the formed first connection hole with a conductive material, the first shared gate is electrically connected to the diffusion layer of the second complementary transistor pair. The second semiconductor integrated circuit device according to the present invention, in which the shared gate is electrically connected to the diffusion layer of the second complementary transistor pair by the first connection means, can be realized.

The second method for manufacturing a semiconductor integrated circuit device is as follows.
A third connection hole exposing another diffusion layer in which the second connection hole of the first complementary transistor pair is not formed in the insulating film;
Forming a fourth connection hole exposing another diffusion layer where the first connection hole of the second complementary transistor pair is not formed; and filling the first connection hole with the first connection hole. Filling the hole and the fourth connection hole with a conductive material,
Preferably, the step of filling the second connection hole includes a step of filling the second connection hole and the third connection hole with a conductive material.

According to a third method of manufacturing a semiconductor integrated circuit device of the present invention, a gate insulating film and a gate first formation layer are formed in a formation region of a first complementary transistor pair and a formation region of a second complementary transistor pair. Forming a gate and a second gate forming layer in sequence, and, with respect to the first gate forming layer and the second gate forming layer, extending over a region where the first complementary transistor pair is formed and having one end at the second end. Forming a first shared gate composed of a gate first formation layer and a gate second formation layer by patterning so as to be included in the formation region of the complementary transistor pair of Patterning the formation layer so that it extends over the formation region of the second complementary transistor pair and one end is included in the formation region of the first complementary transistor pair; Forming a second shared gate composed of a gate first formation layer and a gate second formation layer; and forming a first conductivity type and a second conductivity type in each formation region of the first complementary transistor pair and the second complementary transistor pair. Forming a second conductive type diffusion layer; forming an insulating film covering the first complementary transistor pair and the second complementary transistor; and forming the second complementary transistor pair on the formed insulating film. Forming a first opening exposing both the diffusion layer and the end of the first shared gate; and forming both the diffusion layer of the first complementary transistor pair and the end of the second shared gate in the insulating film. Forming an exposed second opening, and silicidizing an exposed portion of the diffusion layer of the second complementary transistor pair and a side surface of the gate first formation layer of the first shared gate from the first opening. As a result, the diffusion layer and the first Electrically connecting the gates, and silicidizing portions of the diffusion layer of the first complementary transistor pair and the side surfaces of the gate first formation layer of the second shared gate from the second opening. Electrically connecting the diffusion layer and the second shared gate.

According to the third method of manufacturing a semiconductor integrated circuit device, also paying attention only to the first complementary transistor pair, the diffusion of the second complementary transistor pair is formed on the insulating film covering the first shared gate. Forming a first opening exposing both the layer and the end of the first shared gate; forming a first opening in the diffusion layer of the second complementary transistor pair and the side surface of the gate first formation layer of the first shared gate; By silicidizing the exposed portion from one opening, the diffusion layer of the second complementary transistor pair and the first shared gate are electrically connected.
The third semiconductor integrated circuit device of the present invention can be realized in which the first shared gate of the first complementary transistor pair is electrically connected to the diffusion layer of the second complementary transistor pair and the first silicide layer.

In the third method of manufacturing a semiconductor integrated circuit device, the step of silicidation of the exposed portion from the first opening and the exposed portion from the second opening includes the second connection of the first complementary transistor pair. It is preferable to include a step of silicidizing the upper surface of the other diffusion layer where the hole is not formed and the upper surface of the other diffusion layer where the first connection hole of the second complementary transistor pair is not formed.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention, which shows one memory cell of an SRAM device.

As shown in FIG. 1, for example, silicon (S
The memory cell formed on the semiconductor substrate composed of i) includes a first CMOS inverter 1 which is a complementary transistor pair.
0 and a second CMOS inverter 20.

The first CMOS inverter 10 includes a p-type MOSFET 11p having a p-type source diffusion layer 11s and a p-type drain diffusion layer 11d, and an n-type source diffusion layer 12s
N-type MOSFE having n-type drain diffusion layer 12d
T12n, the second CMOS inverter 20
Are the p-type drain diffusion layer 21d and the p-type source diffusion layer 2
It comprises a p-type MOSFET 21p having 1 s and an n-type MOSFET 22n having an n-type drain diffusion layer 22d and an n-type source diffusion layer 22s.

The first CMOS inverter 10 includes a p-type drain diffusion layer 11d and an n-type drain diffusion layer 12 in the p-type MOSFET 11p and the n-type MOSFET 12n.
d are arranged in parallel at an interval from each other. The p-type source diffusion layer 11s and the n-type source diffusion layer 12s
Are arranged in parallel at an interval from each other. P-type drain diffusion layer 1 in first CMOS inverter 10
Regions outside 1d and p-type source diffusion layer 11s, and n-type drain diffusion layer 12d and n-type source diffusion layer 12s
Is an element isolation region made of silicon oxide (SiO ₂ ). A linear first shared gate 10G is formed so as to cross over the respective central portions of the p-type diffusion layers 11s and 11d of the p-type MOSFET 11p and the n-type diffusion layers 12s and 12d of the n-type MOSFET 12n.

Similarly, the second CMOS inverter 20 includes a p-type MOSFET 21p and an n-type MOSFET 22
The n-type p-type drain diffusion layer 21d and the n-type drain diffusion layer 22d in n are arranged in parallel at an interval from each other. Further, a p-type source diffusion layer 21s and an n-type source diffusion layer 22s are arranged in parallel at an interval from each other.
A region outside the p-type drain diffusion layer 21d and the p-type source diffusion layer 21s in the second CMOS inverter 20;
A region outside the n-type drain diffusion layer 22d and the n-type source diffusion layer 22s is an element isolation region made of silicon oxide (SiO ₂ ). The p-type diffusion layers 21d and 21s of the p-type MOSFET 21p and n of the n-type MOSFET 22n
A second common gate 20G having a linear shape is formed so as to cross over the central portion of each of the mold diffusion layers 22d and 22s and extend in parallel with the first common gate 10G.

The first shared gate 10G of the first CMOS inverter 10 includes a p-type MOSFET 11p and an n-type MOS
It extends straight without branching between the FET 12n,
The end on the side of the second CMOS inverter 20 is connected to the p-type drain diffusion layer 2 of the p-type MOSFET 21p of the second CMOS inverter 20 by a hatched contact region 21dc.
1d.

Similarly, the second shared gate 20G of the second CMOS inverter 20 is connected to the p-type MOSFET 21p and the n-type MOSFET 21p.
The first CMOS inverter 10 has a p-type drain diffusion of a p-type MOSFET 11p of the first CMOS inverter 10 which extends linearly without branching between the p-type MOSFET 11n and the p-type MOSFET 11p. It is electrically connected to the layer 11d.

Further, the p of the first CMOS inverter 10
The n-type drain diffusion layer 11d and the n-type drain diffusion layer 12d are electrically connected by a diffusion layer formed on a silicon substrate, and the p-type drain diffusion layer 21d and the n-type drain diffusion layer 22d of the second CMOS inverter 20 are connected to each other. Are also electrically connected by a diffusion layer formed on the silicon substrate.

A power supply voltage is applied to the p-type source diffusion layers 11s and 21s of the p-type MOSFETs 11p and 21p via the first self-aligned contact 14 and the second self-aligned contact 24, respectively.
A ground voltage is applied to the n-type source diffusion layers 12s and 22s of 12n and 22n, respectively. Here, the self-aligned contact is, as shown in FIG.
A p-type source diffusion layer 11s over the side portions of 0G and 20G,
21s and a contact having a configuration for making electrical connection with each other.

As a feature of the first embodiment, the end included in the second CMOS inverter 20 in the gate width direction of the first shared gate 10G (along the line AB in FIG. 1) P-type MOS in CMOS inverter 20
A first contact portion 10c that is electrically connected to the p-type drain diffusion layer 21d of the FET 21p is formed, and the first contact portion 10c is located in the gate width direction (the AB line direction in FIG. 1) of the second shared gate 20G. A second contact portion 20c electrically connected to the p-type drain diffusion layer 11d of the p-type MOSFET 11p in the first CMOS inverter 10 is formed at an end portion included in the CMOS inverter 10 of FIG. As described above, the first contact portion 10c and the second
The contact portion 20c includes the respective contact regions 21dc, 1dc,
At 1dc, they are electrically connected to the respective p-type drain diffusion layers 21d and 11d.

Further, between the first CMOS inverter 10 and the second CMOS inverter 20, a p-type M
OSFETs 11p and 21p are adjacent to each other, and the n-type MO
SFETs 12n and 22n are p-type MOSFETs 11p, 1
Each of them is arranged outside 2p.

Both the first shared gate 10G and the second shared gate 20G have a linear shape, and the first CMO
The S inverter 10 and the second CMOS inverter 20 are arranged so as to be point-symmetric with a center point between the p-type drain diffusion layer 11d and the p-type drain diffusion layer 21d.

As described above, according to the first embodiment, the layout area of the memory cell can be reliably reduced for the following reasons.

(1) The first shared gate 10G is connected to the first C
The second CM without branching on the MOS inverter 10
The second CMO extends linearly on the OS inverter 20 and
At the end on the S inverter 20, the p-type drain diffusion layer 2
1d must be electrically connected. Similarly, a second shared gate 20G extends linearly on the first CMOS inverter 10 without branching on the second CMOS inverter 20, and at its end on the first CMOS inverter 10, its p-type It is electrically connected to the drain diffusion layer 11d.

(2) The p-type drain diffusion layer 11 of the p-type MOSFET 11p in the first CMOS inverter 10
d and the p-type MO in the second CMOS inverter 20
The p-type drain diffusion layer 21d of the SFET 21p is adjacent to the first CMOS inverter 10 and the second CM
The OS inverter 20 and the OS inverter 20 are arranged so as to be point-symmetrical.

As a result, the layout area of the memory cell can be reliably reduced. In addition, since the contact portion 10c connected to the p-type drain diffusion layer 21d of the second CMOS inverter 20 is provided at the end of the first shared gate 10G above the second CMOS inverter 20, the first shared gate 10G and p-type drain diffusion layer 21
It is not necessary to separately provide a wiring for connecting d.
Similarly, there is no need to provide a wiring for connecting the second shared gate 20G and the p-type drain diffusion layer 11d of the first CMOS inverter 10.

The SRAM device according to the first embodiment is characterized not only in the arrangement of the first shared gate 10G, the second shared gate 20G, and the diffusion layers 11d, 11s, 21d, 21s, but also in the first and second gates. Second shared gate 10G, 2
Since the configuration of each of the contact portions 10c and 20c of 0G also has a characteristic, the configuration of this SRAM device will be described below.

FIG. 2A is a sectional view taken along line IIa-IIa (AB) of FIG.
(Line direction) is shown. Here, FIG.
The line AB in (a) is the gate width direction and coincides with the line AB in FIG.

The first shared gate 10G is a p-type MOSFET
Contact region 2 of 21p p-type drain diffusion layer 21d
The configuration connected by 1dc will be described in detail.

As shown in FIG. 2A, the first shared gate 10G has a gate insulating film 32 made of silicon oxide (SiO ₂ ) and a gate made of polysilicon in a region on the first CMOS inverter 10. The lower layer 33 includes a barrier metal layer 34 made of titanium nitride (TiN) and a gate upper layer 35 made of tungsten (W). The gate electrode including the gate lower layer 33 made of polysilicon and the gate upper layer 35 made of metal formed in this order from the substrate side is called a polymetal electrode structure. Here, since titanium nitride and tungsten have lower resistivity than polysilicon, the barrier metal layer 34
The gate upper layer 35 has a lower resistivity than the gate lower layer 32. On the gate upper layer 35, a first protective insulating film 36 made of silicon nitride (Si ₃ N ₄ ) and protecting the gate upper layer 35 is formed.

As shown in FIG. 2A, the first shared gate 10G has a polymetal electrode structure in the first CMOS inverter 10, and the second CMOS inverter 2
0, the gate insulating film 32 and the gate lower layer 33
The barrier metal layer 34 and the gate upper layer 35 are electrically connected to the contact region 21dc of the p-type drain diffusion layer 21d. Thus, the first shared gate 1
The end of the 0G on the side of the second CMOS inverter 20 is electrically connected to the p-type drain diffusion layer 21d by a metal part having a polymetal electrode structure, that is, a barrier metal layer. Here, the barrier metal layer 34 is connected to the p-type drain diffusion layer 21d.
, The gate upper layer 35 made of tungsten may be directly connected to the p-type drain diffusion layer 21d.

Although not shown, the cross-sectional structure of the second shared gate 20G is the same as that of the first shared gate 10G.
The end on the MOS inverter 10 side is electrically connected to the contact region 11dc of the p-type drain diffusion layer 11d of the p-type MOSFET 11p in the first CMOS inverter 10 by a metal part (barrier metal layer 34) having a polymetal electrode structure. ing.

Next, a cross-sectional structure in the direction perpendicular to the line AB in FIG. 1 and along the line ab which is the gate length direction of the first and second shared gates 10G and 20G will be described.

FIG. 2B shows a cross-sectional structure taken along the line IIb-IIb in FIG. Here, the second self-aligned contact 24, the source diffusion layer 21s, and the drain diffusion layer 21d are omitted to simplify the drawing.

First, the configuration of the second shared gate 20G will be described.

As shown in FIG. 2B, the second CMOS
On the p-type MOSFET 21p of the inverter 20,
The second shared gate 20G includes a gate insulating film 32 made of silicon oxide (SiO ₂ ) and a gate lower layer 3 made of polysilicon (Si), which are sequentially formed on the semiconductor substrate 30.
3. Barrier metal layer 34 made of titanium nitride (TiN)
And a polymetal electrode structure constituted by a gate upper layer 35 made of tungsten (W). Also,
A first protective insulating film 3 made of silicon nitride (Si ₃ N ₄ ) for protecting the gate upper layer 35 on the gate upper layer 35
6 are formed.

Next, as shown in FIG. 1, the first shared gate 10G has its first contact portion 10c electrically connected to the contact region 21dc of the p-type drain diffusion layer 21d. The cross section of the part 10c is shown in FIG.
As shown in (b), a part of the barrier metal layer 34 is electrically connected to the contact region 21dc of the p-type drain diffusion layer 21d.

The first contact portion 10c of the first shared gate 10G is a region above the p-type drain diffusion layer 21 of the p-type MOSFET 21p and the second shared gate 20G.
The lower part of the side includes a gate lower layer 33 with a gate insulating film 32 interposed therebetween. Since the gate insulating film 32 is interposed between the gate lower layer 33 and the p-type drain diffusion layer 21, the gate lower layer 33 is not electrically connected to the p-type drain diffusion layer 21. As described above, a part of the barrier metal layer 34 is formed in the contact region 21dc of the p-type drain diffusion layer 21d.
Only connected by. This first contact portion 10c
, The gate lower layer 33 included in the first
Contact portion 10c, that is, the first shared gate 10G
This is an extremely effective member when patterning the substrate.

An element isolation region 31 having an STI structure is formed below the side of the semiconductor substrate 30 opposite to the first shared gate 10G and opposite to the second shared gate 20G. The second contact part 20c of the second shared gate 20G has the same structure as the first contact part 10c.

With this structure, the first shared gate 10G and the second shared gate 20G are electrically connected to the p-type drain diffusion layers 21d and 11d, respectively, by the barrier metal layer 34 having a lower resistivity than polysilicon. The semiconductor substrate 3 of each shared gate 10G, 20G
The contact resistance with zero can be reduced.

In the first embodiment, the barrier metal layer 34 and the semiconductor substrate 30 are connected. However, as described above, the gate upper layer 35 (tungsten) and the semiconductor substrate 30 are directly connected. Is also good.

Next, the dimensions and relative positional relationship of the mask used for patterning the first shared gate 10G, the second shared gate 20G, and the contact portions 10c, 20c, which are features of the first embodiment, will be described.

FIG. 3A shows the first shared gate 10G.
FIG. 3B shows a cross-sectional structure taken along line IIIb-IIIb of FIG. 3A. Here, in FIGS. 3A and 3B, the same components as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and are taken in the AB line direction and the AB line direction. Corresponds to the AB line direction and the ab line direction in FIGS. 1 and 2.

As shown in FIGS. 3A and 3B,
The width of the first contact portion 10c in the ab line direction is 1B, and the width of the contact region 21dc in the ab line direction is 1C.
The width in the ab line direction, which is the gate length of the first shared gate 10G, is 1D.

Further, in the first contact portion 10c, the width of the gate insulating film 32 in the a-b line direction is set to 1E,
The width in the a-b line direction of the overlapping portion with the element isolation region 31 is 1F. Therefore, the width 1B of the first contact portion 10c is equal to the width 1E of the gate insulating film 32 in the ab line direction.
And the width 1C of the contact region 21dc and the width 1F of the overlapping portion with the element isolation region 31 (1B = 1E
+ 1C + 1F).

Hereinafter, a method of manufacturing the memory cell of the SRAM device configured as described above will be described with reference to the drawings.

FIGS. 4 to 12 show a method of manufacturing the SRAM device according to the first embodiment of the present invention. FIGS. 4 and 5 show a partial plan configuration of the first contact portion in the order of steps.
6 to 12 show cross-sectional configurations in the order of steps. In addition,
Here, FIGS. 6 to 12 show cross sections taken along line IIa-IIa in FIG. The a-b line direction corresponds to the a-b direction in FIGS.
It is matched with the b-line direction.

First, the plan view of FIG. 4A and the plan view of FIG.
As shown in the cross-sectional view of FIG.
The element isolation region 31 and the p-type drain diffusion layer 21d are selectively formed on the upper part of 0. The semiconductor substrate 30 is not limited to silicon, but may be any substrate such as an SOI substrate on which transistors can be formed.

Next, as shown in FIGS. 4B and 6A, a gate insulating film 32 having a thickness of about 5 nm is formed on the entire main surface of the semiconductor substrate 30 made of silicon by thermal oxidation. Thereafter, a gate lower layer 33 of polysilicon having a thickness of about 100 nm is deposited by a chemical vapor deposition (CVD) method using silane gas.

Next, as shown in FIGS. 5A and 6A, the contact p-type diffusion layer 41 in the gate lower layer 33 and the gate insulating film 32 and the element isolation region are formed by lithography and etching. An opening 33a having a width in the a-b line direction of 1A is formed in a region including a boundary portion with 31. Thereby, as shown in FIG. 5A, the p-type drain diffusion layer 21d and the element isolation region 31 located around the p-type drain diffusion layer 21d are exposed from the opening 33a. At this time, since the openings 33a are simultaneously formed in the gate insulating film 32 and the gate lower layer 33 thereon, the gate insulating film 32 is not exposed. Therefore, since the surface of the gate insulating film 32 is not contaminated by the mask film or the like, the reliability of the gate insulating film 32 which affects the operation characteristics of the transistor can be improved.

Next, as shown in FIGS. 5 (b) and 6 (b), a barrier made of titanium nitride having a thickness of about 20 nm is formed on the entire surface including the opening 33a on the gate lower layer 33 by sputtering. Metal layer 34 and thickness about 10 nm
A gate upper layer 35 made of tungsten is deposited.
Thereby, the opening 33a of the semiconductor substrate 30
A barrier metal layer 34 and a gate upper layer 35 are formed, and the first shared gate 10G and the p-type drain diffusion layer 2 are formed.
1d is electrically connected. Subsequently, a first protective insulating film 36 made of silicon nitride having a thickness of about 100 nm is deposited by a CVD method. In FIG. 6B, a region 1B is a first contact portion 10c of the first shared gate 10G.
The region 1D is a region where the second shared gate 20G is formed.

Subsequently, a mask pattern made of a resist film is formed on the first protective insulating film 36 by using a lithography method, and a gas mainly containing carbon fluoride, for example, CF ₃ or CHF ₄ is added to oxygen. The mask pattern is transferred to the first protective insulating film 36 by etching the first protective insulating film 36 using the mixed gas to which (O ₂ ) is added. Subsequently, after the resist film is removed by ashing and washing, the patterned first protective insulating film 36 is used as a mask, and an etching gas mainly containing a fluorine-based CHF ₄ gas or a chlorine-based gas is used. FIG. 7 (a)
As shown in FIG. 3, the gate upper layer 35 and the barrier metal layer 34
Is etched. Here, the gate lower layer 33 made of polysilicon is not etched.

Subsequently, the gate lower layer 33 is etched using an etching gas containing hydrogen bromide (HBr) as a main component to form a first shared gate 10G having a first contact portion 10c shown in FIG. The second shared gate 20G is formed.

By the above steps, the first shared gate 10G
Denotes a contact region 21dc of the p-type drain diffusion layer 21d
And can be electrically connected.

Here, the first shared gate 10G has a portion on the side of the second shared gate 20G above the p-type drain diffusion layer 21d that is not electrically connected to the p-type drain diffusion layer 21d, that is, the gate lower layer 33 and Part of the gate insulating film 32 is included. Thus, the p-type drain diffusion layer 21
The reason for including a part that is not electrically connected to d will be described.

As shown in FIG. 5B, the mask pattern 3 corresponding to the first shared gate 10G whose width in the ab line direction at the portion corresponding to the first contact portion 10c is 1B.
Are arranged to be larger than the opening width 1A of the opening 33a of the gate lower layer 33 and shifted by the width 1E toward the second shared gate 20G, as shown in FIG. , The second of the first contact portion 10c
The gate lower layer 33 remains below the side end on the shared gate 20G side. Since the gate lower layer 33 made of polysilicon remains in the first contact portion 10c, etching damage to the semiconductor substrate 30 made of silicon in the step of patterning the gate lower layer 33 for forming the first shared gate 10G is reduced. Can be prevented.

More specifically, if the first shared gate 1
If the gate lower layer 33 made of polysilicon is formed so as not to be left below the side edge of the 0G, the semiconductor substrate made of silicon is etched when the gate upper layer 35 made of tungsten and the barrier metal layer 34 made of titanium nitride are etched. 30 is exposed (see FIG. 7A). In this state,
That is, if the gate lower layer 33 made of polysilicon is etched with the semiconductor substrate 30 exposed, the etching selectivity of polysilicon to silicon is small. Is etched, and as a result, the exposed surface of the semiconductor substrate 30, for example, p
Even the mold drain diffusion layer 21d is etched. Therefore, the gate upper layer 35 and the barrier metal layer 34
Before etching the polysilicon layer 33 and before etching the polysilicon layer 33, the semiconductor substrate 30 made of silicon must not be exposed.

In FIG. 7A, the semiconductor substrate 30 appears to be exposed on the opposite side of the first shared gate 10G from the second shared gate 20G (on the right side in the drawing), but this portion is oxidized. Element isolation region 31 made of silicon
Therefore, even in the polysilicon etching step, the surface of the element isolation region 31 is not dug deep by etching. This is because the silicon oxide forming the element isolation region 31 has a large etching selectivity with respect to the polysilicon forming the gate lower layer 33.

In FIG. 5B, the formation position of the end (1G at the left end) of the mask pattern 3 opposite to the first CMOS inverter 10 is set outside the opening 33a. As shown in FIG. 5C, the left end may be set inside the opening 33a. This is because, as shown in FIG.
3a, the gate lower layer 33 remains on the left end of the first contact portion 10c when patterning the first shared gate 10G, and conversely, the left end of the mask pattern 3 is opened as shown in FIG. This is because the element isolation region 31 is exposed at the time of patterning the first shared gate 10G even if it is set inside 33a. Therefore, since the exposed element isolation region 31 and the shared gate 10G have a large etching selectivity, the semiconductor substrate 30 is not damaged by etching.

The first contact portion 10c of the first shared gate 10G has been described above.
The G second contact portion 20c is the same as the first contact portion 10c.

Next, a method for electrically connecting the source diffusion layer and the drain diffusion layer to the upper wiring layer from the shared gate will be described with reference to the drawings.

As shown in FIG. 8A, using the first shared gate 10G and the second shared gate 20G including the first contact portion 10c as a mask, for example, the implantation energy is 1.0 keV and the dose is 1.0. A boron (B) ion which is a p-type impurity of about × 10 ¹⁴ cm ⁻² is added to the semiconductor substrate 30.
To form a p-type extension layer 42 of the p-type source diffusion layer 21s and the p-type drain diffusion layer 21d in the semiconductor substrate 30.

Next, as shown in FIG. 8B, a sidewall insulating film 43 made of silicon nitride is formed on the side surfaces of the first shared gate 10G and the second shared gate 20G.
Using the first shared gate 10G and the second shared gate 20G including the formed sidewall insulating film 43 as a mask, for example, the implantation energy is 5.0 keV and the dose is 1.
By implanting boron (B) ions of about 0 × 10 ¹⁵ cm ⁻² into the semiconductor substrate 30, a p-type source diffusion layer 21 s and a p-type drain diffusion layer 21 d are formed in the semiconductor substrate 30. At this time, the first CMOS inverter 1
0 p-type source diffusion layer 11s and p-type drain diffusion layer 1
1d is also formed at the same time.

Next, as shown in FIG. 9A, a metal layer made of cobalt (Co) is deposited on the semiconductor substrate 30 over the entire surface including the first shared gate 10G and the second shared gate 20G by a sputtering method. Then, by performing an appropriate heat treatment, for example, a heat treatment at a temperature of about 800 ° C. for about 30 seconds, the p-type diffusion layers 21 s and 2 s 2, 2
A cobalt silicide (CoSi ₂ ) layer 44 formed by reacting silicon and cobalt constituting 1d is formed. After that, the metal layer that has not reacted with silicon is removed by washing. Here, the metal to be silicided is not limited to cobalt, and may be any metal that can form a good metal silicide with silicon such as nickel (Ni), chromium (Cr), or molybdenum (Mo).

Next, as shown in FIG. 9B, a second protective insulating film made of silicon nitride is formed on the semiconductor substrate 30 over the entire surface including the first shared gate 10G and the second shared gate 20G by the CVD method. Deposit 45.

Next, as shown in FIG. 10, after an interlayer insulating film 46 of BPSG is deposited on the entire surface of the second protective insulating film 45, the upper surface is flattened. Subsequently, a second region is provided above the p-type source diffusion layer 21s in the planarized interlayer insulating film 46 and including the side surface of the second shared gate 20G.
A contact hole 46a exposing the protective insulating film 45 is formed. At this time, the etching gas for the interlayer insulating film 46 is mainly composed of C ₅ F ₈ which is fluorocarbon in order to provide etching selectivity with respect to the silicon nitride forming the second protective insulating film 45. , With argon (A
r) and a mixed gas to which oxygen (O ₂ ) is added.

Next, as shown in FIG. 11, the etching selectivity with respect to the cobalt silicide layer 44 is
The contact hole 46a of the second protective insulating film 45 is formed by etching using a mixed gas containing a fluorocarbon-based material, for example, CHF ₃ as a main component and argon (Ar) added thereto.
By removing the exposed portion from the substrate, the cobalt silicide layer 44 is removed.
Is exposed from the contact hole 46a.

Next, on the bottom of the contact hole 46a,
Forming a barrier metal layer (not shown) made of titanium nitride
After that, as shown in FIG.
(WF ₆ ) Contact method by CVD using gas
Second self-alignment made of tungsten
The contact 24 is formed by filling. At this time, the first
The first self-alignment is also performed in the CMOS inverter 10.
A contact 14 is formed.

As described above, the memory cell according to the first embodiment includes the first CMOS inverter 10 and the second CM.
The OS inverter 20 includes CMOS inverters 10 and 20 each having a first shared gate 10G and a second shared gate 20G that do not have a branch portion and are parallel to each other in the region of the OS inverter 20. Further, the second C of the first shared gate 10G
The end on the MOS inverter 20 side is located on the p-type drain diffusion layer 21d of the second CMOS inverter 20, and the end directly serves as the first contact portion 10c and is electrically connected to the contact region 21dc. You. Similarly,
First CMOS inverter 10 of second shared gate 20G
Is located on the p-type drain diffusion layer 11 d of the first CMOS inverter 10, and the end of the
The contact portion 20c becomes the contact region 11dc
Is electrically connected to Thereby, the area of the memory cell of the SRAM device can be reduced.

The first shared gate 10G and the second shared gate 20G have the same structure as that of the first contact part, although the gate lower layer 33 is made of polysilicon and the gate upper layer 35 is made of metal. 10c and the second contact portion 20c, the gate upper layer 35 made of metal is not interposed via the gate lower layer 33, and the p-type drain diffusion layer 21 is formed via the barrier metal layer 34.
d, 11d. Therefore, the contact resistance can be reduced. Note that, as described above, the gate upper layer 35 may be directly connected to the p-type drain diffusion layers 21d and 11d without using the barrier metal layer 34.

Further, the first contact portion 10c and the second
Since both contact portions 20c are patterned so that the polysilicon of the gate lower layer 33 remains at the side end in contact with the contact p-type diffusion layer 41, the gate lower layer 33 is formed.
The semiconductor substrate 30 is not damaged at the time of patterning.

Further, the contacts for the diffusion layer where the contact portions 10c and 20c such as the p-type source diffusion layer 21s are not formed are so-called self-aligned contacts 14 and 24 which straddle the side of the shared gate. Can be further reduced.

Although a thermal oxide film is used for the gate insulating film 32, a deposited oxide film may be used.
An MIS structure using silicon oxynitride (SiNO) for 2 may be used.

The gate lower layer 33 and the gate upper layer 3
5, the barrier metal layer 34 is provided, but is not necessarily provided. Although tungsten is used for the gate upper layer 34, molybdenum (Mo) may be used instead. Further, a silicide material such as tungsten silicide (WSi) may be used.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 13 shows a semiconductor integrated circuit device according to the second embodiment of the present invention, and shows a plan configuration of one memory cell of an SRAM device.

As shown in FIG. 13, a memory cell formed on a semiconductor substrate made of, for example, silicon includes a first CMOS inverter 50, which is a complementary transistor pair, and a second CMOS inverter.
CMOS inverter 60.

The first CMOS inverter 50 includes a p-type MOSFET 51p having a p-type source diffusion layer 51s and a p-type drain diffusion layer 51d, and an n-type source diffusion layer 52s
-Type MOSFE having an n-type drain diffusion layer 52d
T52n, the second CMOS inverter 60
Are the p-type drain diffusion layer 61d and the p-type source diffusion layer 6
It comprises a p-type MOSFET 61p having 1 s and an n-type MOSFET 62n having an n-type drain diffusion layer 62d and an n-type source diffusion layer 62s.

The first CMOS inverter 50 includes a p-type drain diffusion layer 51d and an n-type drain diffusion layer 52 in a p-type MOSFET 51p and an n-type MOSFET 52n.
d are arranged in parallel at an interval from each other. The p-type source diffusion layer 51s and the n-type source diffusion layer 52s
Are arranged in parallel at an interval from each other. p-type M
A linear first shared gate 50 is formed so as to cross over the central part of each of the p-type diffusion layers 51s and 51d of the OSFET 51p and the n-type diffusion layers 52s and 52d of the n-type MOSFET 52n.
G is formed. In the first CMOS inverter 50, a region outside the p-type source diffusion layer 51s and the p-type drain diffusion layer 51d and a region outside the n-type source diffusion layer 52s and the n-type drain diffusion layer 52d are formed of silicon oxide. Area.

Similarly, the second CMOS inverter 60 has a p-type MOSFET 61p and an n-type MOSFET 62
A p-type drain diffusion layer 61d and an n-type drain diffusion layer 62d for n are arranged in parallel at an interval from each other. Further, a p-type source diffusion layer 61s and an n-type source diffusion layer 62s are arranged in parallel at an interval from each other.
The p-type diffusion layers 61d and 61s of the p-type MOSFET 61p and the n-type diffusion layers 62d and 62s of the n-type MOSFET 62n
A second common gate 60G is formed in a linear shape that traverses over each central portion of the second common gate and extends without branching in parallel with the second common gate 50G. Regions outside p-type source diffusion layer 61s and p-type drain diffusion layer 61d in second CMOS inverter 60, and n-type source diffusion layer 6
The region outside the 2s and n-type drain diffusion layers 62d is an element isolation region made of silicon oxide.

The first shared gate 50G of the first CMOS inverter 50 includes a p-type MOSFET 51p and an n-type MOS
Extend straight without branching with the FET 52n,
The end on the side of the second CMOS inverter 60 is connected to a second CMO by a contact region (first shared contact) 63.
It is electrically connected to the p-type drain diffusion layer 61d of the p-type MOSFET 61p of the S inverter 60.

Similarly, the second shared gate 60G of the second CMOS inverter 60 is composed of the p-type MOSFET 61p and the n-type MOSFET 61p.
And extends linearly without branching between the first MOSFET 62n and the first CMOS inverter 50 side end portion at a contact region (second shared contact) 53 of the first CMOS inverter 50.
Electrically connected to the p-type drain diffusion layer 51d of the p-type MOSFET 51p of the CMOS inverter 50 of FIG.

Also, the p of the first CMOS inverter 50
The n-type drain diffusion layer 51d and the n-type drain diffusion layer 52d are electrically connected by a diffusion layer formed on a silicon substrate, and the p-type drain diffusion layer 61d and the n-type drain diffusion layer 62d of the second CMOS inverter 60 are connected to each other. Are also electrically connected by a diffusion layer formed on the silicon substrate.

A power supply voltage is applied to the p-type source diffusion layers 51s and 61s of the p-type MOSFETs 51p and 61p via the first self-aligned contact 54 and the second self-aligned contact 64, respectively.
A ground voltage is applied to the n-type source diffusion layers 52s and 62s of 52n and 62n, respectively. Here, the self-aligned contact means, as shown in FIG. 13, the p-type source diffusion layer 51 over the side of each of the shared gates 50G and 60G.
s, 61s, respectively.

In the second embodiment, the first shared gate 50G is connected to the second CMOS inverter 60 by the first shared contact 63 as the first connection means provided at the end included in the second CMOS inverter 60. Inverter 60
The second shared gate 60 </ b> G is electrically connected to the p-type drain diffusion layer 61 d of the first CMOS inverter 50, and a second shared contact 53 as a second connection means provided at an end included in the first CMOS inverter 50. Is the first CMO
It is electrically connected to the p-type drain diffusion layer 51d of the S inverter 50.

Hereinafter, a method of manufacturing the memory cell of the SRAM device configured as described above will be described with reference to the drawings.

FIGS. 14 to 20 show sectional structures in the order of steps of a method for manufacturing an SRAM device according to the second embodiment of the present invention. Here, a cross section taken along line XX-XX in FIG. 13 is shown, and the direction of the line ab is ab
It matches with the line direction.

First, a film thickness of about 5 nm is formed over the entire main surface of a semiconductor substrate 30 made of silicon by thermal oxidation.
Gate insulating film 32 is formed, and the formed gate insulating film 3 is formed.
A gate lower layer 33 of polysilicon having a thickness of about 100 nm is deposited on the substrate 2 by a CVD method using silane gas. Subsequently, the gate lower layer 3 is formed by sputtering.
3 has a thickness of about 20 over the entire surface including the opening 33a.
metal layer 34 made of titanium nitride having a thickness of 50 nm and a gate upper layer 35 made of tungsten having a thickness of about 50 nm.
Is deposited. Here, the barrier metal layer 34 and the gate upper layer 35 have lower resistivity than the gate lower layer 33.

Subsequently, a film thickness of about 100
A first protective insulating film 36 made of silicon nitride of nm and protecting the gate upper layer 35 is deposited. The semiconductor substrate 30 is not limited to silicon, and may be any substrate on which transistors can be formed, such as an SOI substrate.

Subsequently, a gate pattern made of a resist film is formed on the first protective insulating film 36 by using a lithography method. Then, using the formed resist film as a mask, carbon fluoride, for example, CF _The gate pattern is transferred to the first protective insulating film 36 by etching the first protective insulating film 36 using a mixed gas obtained by adding oxygen (O ₂ ) to a gas containing ₃ or CHF ₄ as a main component. I do.

Subsequently, after the resist film is removed by ashing and washing, using the patterned first protective insulating film 36 as a mask, an etching gas mainly containing a fluorine-based CHF ₄ gas or a chlorine-based gas is used. Then, the gate upper layer 35 and the barrier metal layer 34 are etched.

Subsequently, the gate lower layer 33 is etched using an etching gas containing hydrogen bromide (HBr) as a main component to form a first shared gate 50G and a second shared gate 60G shown in FIG. I do.

Then, using the first shared gate 50G and the second shared gate 60G as masks, for example, boron ions which are p-type impurities having an implantation energy of 1.0 keV and a dose of about 1.0 × 10 ¹⁴ cm ⁻² are used. Is injected into the semiconductor substrate 30 to form the p-type extension layer 42 of the p-type source diffusion layer 61s and the p-type drain diffusion layer 61d in the semiconductor substrate 30.

Next, as shown in FIG. 14B, a sidewall insulating film 43 made of silicon nitride is formed on the side surfaces of the first shared gate 50G and the second shared gate 60G, and each of the formed sidewall insulating films is formed. Using the first shared gate 50G and the second shared gate 60G including the film 43 as a mask, for example, boron ions having an implantation energy of 5.0 keV and a dose of about 1.0 × 10 ¹⁵ cm ⁻² are implanted into the semiconductor substrate 30. Thereby, the p-type source diffusion layer 61s and the p-type drain diffusion layer 61d are formed on the semiconductor substrate 30. At this time, the first CMOS inverter 5
0 p-type source diffusion layer 51s and p-type drain diffusion layer 5
1d is also formed at the same time.

Next, as shown in FIG. 15A, a metal layer made of, for example, cobalt is deposited over the entire surface including the first shared gate 50G and the second shared gate 60G on the semiconductor substrate 30 by, for example, a sputtering method. And then
By performing an appropriate heat treatment, for example, a heat treatment at a temperature of about 800 ° C. for about 30 seconds, the p-type source diffusion layer 61 is formed.
On the s and p-type drain diffusion layers 61d, a cobalt silicide layer 44 formed by reacting silicon and cobalt constituting the p-type diffusion layers 61s and 61d is formed. After that, the metal layer that has not reacted with silicon is removed by washing.

Next, as shown in FIG.
By a method, a second protective insulating film 45 made of silicon nitride is deposited over the entire surface including the first shared gate 50G and the second shared gate 60G on the semiconductor substrate 30.

Next, as shown in FIG. 16, an interlayer insulating film 46 made of BPSG is deposited on the entire surface of the second protective insulating film 45 by the CVD method, and the upper surface is flattened.
Subsequently, the first protective insulating film 45 is exposed in a region of the planarized interlayer insulating film 46 above the p-type drain diffusion layer 61d and including the side surface of the first shared gate 50G, for forming a shared contact first. Contact hole 46b
To form At this time, the etching gas for the interlayer insulating film 46 is mainly composed of C ₅ F ₈ , which is a fluorocarbon, and has argon (Ar) and oxygen ( O ₂ ) is used.

Next, as shown in FIG. 17, a gate upper layer 35 made of tungsten and a cobalt silicide layer 4 are formed.
CHF which is a fluorocarbon so that silicon nitride can be etched while having an etching selectivity between
By performing etching using a mixed gas containing ₃ as a main component and argon (Ar) added thereto, the second protective insulating film 45, the sidewall insulating film 43, and the first protective insulating film 36 are etched. 1 contact hole 46b
Is removed to expose the gate upper layer 35 and the cobalt silicide layer 44 from the first contact hole 46b.

Next, as shown in FIG. 18, after filling the contact hole 46b with a resist material 47 for protecting the exposed surface of the first contact hole 46b, the interlayer insulating film 46 is formed.
In the region above the p-type source diffusion layer 61s and over the side portion of the second shared gate 60G, the second protective insulating film 4
A second contact hole 46c for forming a self-aligned contact exposing 5 is formed. As described above, a mixed gas obtained by adding argon (Ar) and oxygen (O ₂ ) to C ₅ F ₈ gas is used as an etching gas for the interlayer insulating film 46 at this time.

Next, as shown in FIG. 19, CHF ₃ , which is a fluorocarbon, is used as a main component so that silicon nitride can be etched while having etching selectivity with the cobalt silicide layer 44. The second protective insulating film 45 exposed from the second contact hole 46c is removed by performing etching using a mixed gas obtained by adding argon (Ar) to the second contact hole 46c, and the cobalt silicide is removed from the second contact hole 46c. The layer 44 is exposed. At this time, it is necessary to perform etching so that the gate lower layer 33, the barrier metal layer 34, or the gate upper layer 35 is not exposed from the first protective insulating film 36 and the sidewall insulating film 43 made of silicon nitride.

Next, as shown in FIG. 20, the resist material 47 filling the inside of the first contact hole 46b is removed, and then the first contact hole 46b and the second contact hole 46b are removed.
A barrier metal layer (not shown) made of titanium nitride is formed on the bottom surface of the contact hole 46c. Thereafter, the first method is performed by a CVD method using tungsten hexafluoride gas.
By simultaneously burying tungsten in the contact hole 46b and the second contact hole 46c,
The first shared contact 63 is formed in the first contact hole 46b, and the second contact hole 4 is formed.
6c, a second self-aligned contact 64 is formed.

As described above, the memory cells according to the second embodiment have the first memory cells each having no branching part and being parallel to each other.
First having a shared gate 50G and a second shared gate 60G
, And a second CMOS inverter 60.

The second common gate 50G in the first shared gate 50G
P-type drain diffusion layer 61d of CMOS inverter 60
The first shared contact 63 provided near the upper end electrically connects the first shared gate 50G and the p-type drain diffusion layer 61d, and the first CMOS inverter in the second shared gate 60G. 50, the second shared contact 53 provided near the end on the p-type drain diffusion layer 51d.
And the p-type drain diffusion layer 51d are electrically connected, so that the cell area of the memory cell of the SRAM device can be reduced.

Further, since the contacts in which the shared contacts 53 and 63 are not formed, such as the p-type source diffusion layer 61s, are used as self-aligned contacts, the cell area can be further reduced.

A first contact for forming a shared contact is provided.
When the second contact hole 46c for forming the self-aligned contact is formed after the formation of the contact hole 46b of
The exposed portion from b is masked and protected, the mask is removed, and the shared contacts 53 and 63 and the self-aligned contacts 54 and 64 are formed in one step, thus simplifying the manufacturing process. be able to.

Although a thermal oxide film is used for the gate insulating film 32, a deposited oxide film may be used.
2 may be an MIS structure using silicon oxynitride.

The gate lower layer 33 and the gate upper layer 3
5, the barrier metal layer 34 is provided, but is not necessarily provided.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIG. 21 shows a semiconductor integrated circuit device according to the third embodiment of the present invention, and shows a plan configuration of one memory cell of an SRAM device.

As shown in FIG. 21, a memory cell formed on a semiconductor substrate made of silicon includes a first CMOS inverter 50 as a complementary transistor pair and a second CM.
And an OS inverter 60. Here, in FIG. 21, the same components as those shown in FIG. 13 are denoted by the same reference numerals, and description thereof will be omitted.

The difference between the third embodiment and the second embodiment is that the second CMOS inverter 60
Instead of using a shared contact for the electrical connection between the first shared gate 50G and the p-type drain diffusion layer 61d of the p-type MOSFET 61p, the first shared gate 50G
Sidewall silicide layer formed on the side of the gate lower layer and p
A first sidewall contact (first silicide layer) 66 composed of a silicide layer formed on the upper surface of the drain diffusion layer 61d is used.

Similarly, in the first CMOS inverter 50, the second shared gate 60G and the p-type MOSFET 51
The second sidewall made of the silicide layer formed on the side surface of the gate lower layer of the second shared gate 60G and the upper surface of the p-type drain diffusion layer 51d also serves as an electrical connection means for the p-type drain diffusion layer 51d. A contact (second silicide layer) 56 is used.

Hereinafter, a method of manufacturing the memory cell of the SRAM device configured as described above will be described with reference to the drawings.

FIGS. 22 to 26 show sectional structures in the order of steps of a method for manufacturing an SRAM device according to the third embodiment of the present invention. Here, a cross section taken along the line XXVI-XXVI of FIG. 21 is shown, and the direction of the line ab is a
-Matched with the line b direction.

First, a film thickness of about 5 nm is formed on the entire main surface of a semiconductor substrate 30 made of silicon by thermal oxidation.
Gate insulating film 32 is formed, and the formed gate insulating film 3 is formed.
A gate lower layer 33 of polysilicon having a thickness of about 100 nm is deposited on the substrate 2 by a CVD method using silane gas. Subsequently, the gate lower layer 3 is formed by sputtering.
3 has a thickness of about 20 over the entire surface including the opening 33a.
metal layer 34 made of titanium nitride having a thickness of 50 nm and a gate upper layer 35 made of tungsten having a thickness of about 50 nm.
Is deposited. Here, the barrier metal layer 34 and the gate upper layer 35 have lower resistivity than the gate lower layer 33.
Subsequently, a first protective insulating film 36 made of silicon nitride having a thickness of about 100 nm and protecting the gate upper layer 35 is deposited by a CVD method.

Next, a gate pattern made of a resist film shown in FIG. 21 is formed on the first protective insulating film 36 by using a lithography method. First, a mixed gas obtained by adding oxygen (O ₂ ) to a gas mainly containing carbon, for example, CF ₄ is used.
By etching the protective insulating film 36 of FIG.
The gate pattern is transferred to the protective insulating film 36 of FIG.

Subsequently, after the resist film is removed by ashing and washing, the gate upper layer 35 and the barrier layer are removed by using the patterned first protective insulating film 36 as a mask and an etching gas containing CF ₄ as a main component. Metal layer 3
4 is etched. Subsequently, hydrogen bromide (H
The gate lower layer 33 is etched using an etching gas mainly containing (Br) to form a first shared gate 50G and a second shared gate 60G as shown in FIG.

Subsequently, using the shared gates 50G and 60G as a mask, for example, boron ions as a p-type impurity having an implantation energy of 1.0 keV and a dose of about 1 × 10 ¹⁴ cm ⁻² are implanted into the semiconductor substrate 30. Thereby, the p-type extension layer 42 of the p-type source diffusion layer 61s and the p-type drain diffusion layer 61d is formed on the semiconductor substrate 30. Thereafter, a sidewall insulating film 43 made of silicon nitride is formed on the side surface of each of the gates 50G and 60G, and the shared gate 5 including the formed sidewall insulating film 43 is formed.
Using 0 G and 60 G as a mask, for example, boron ions having an implantation energy of 5.0 keV and a dose of about 1.0 × 10 ¹⁵ cm ⁻² are implanted into the semiconductor substrate 30, so that p-type source A layer 61s and a p-type drain diffusion layer 61d are respectively formed. At this time,
P-type source diffusion layer 51 of first CMOS inverter 50
The s and p-type drain diffusion layers 51d are also formed at the same time.

Next, as shown in FIG. 22B, after a resist film 48 is applied on the semiconductor substrate 30, the first shared gate 5 in the resist film 48 is formed by lithography.
An opening pattern 48a exposing a side portion of the 0G on the side of the second shared gate 60G is formed. Subsequently, the opening pattern 48a
CHF, for example, using the resist film 48 having
The first protective insulating film 36 and the sidewall insulating film 43 are etched using a mixed gas in which argon (Ar) is added to a gas containing ₃ as a main component, whereby the first protective insulating film 36 and the sidewall insulating film are etched. The portion of the film 43 exposed from the opening pattern 48a is removed to expose the gate lower layer 33 and the gate upper layer 35.

Next, as shown in FIG. 23A, a metal layer made of, for example, cobalt is deposited over the entire surface including the first shared gate 50G and the second shared gate 60G on the semiconductor substrate 30 by, for example, a sputtering method. I do. Subsequently, by performing a first heat treatment at a temperature of about 500 ° C. for about 30 seconds, the cobalt silicide layer 4 on the p-type source diffusion layer 61s and the p-type drain diffusion layer 61d is formed.
4, and a side wall silicide layer 44a made of cobalt silicide is formed on the side of the gate lower layer 33 in a self-aligned manner. After that, the metal layer that has not reacted with silicon is removed by washing. As shown in FIG. 23B, a first silicide layer 44 and a side wall silicide layer 44a are formed on the p-type drain diffusion layer 61d. A sidewall contact 66 is formed. Subsequently, a second heat treatment is performed at about 750 ° C., which is higher than the first heat treatment, for about 30 seconds, so that the first sidewall contacts 66 and p
Electrical connection with the mold drain diffusion layer 61d becomes more reliable.

Next, as shown in FIG.
By a method, a second protective insulating film 45 made of silicon nitride is deposited over the entire surface including the first shared gate 50G and the second shared gate 60G on the semiconductor substrate 30.

Next, as shown in FIG.
After an interlayer insulating film 46 of BPSG is deposited on the entire surface of the second protective insulating film 45 by a method, the upper surface is planarized. Subsequently, the second shared gate 60G is located above the p-type source diffusion layer 61s in the planarized interlayer insulating film 46.
Contact hole 46 for forming a self-aligned contact exposing second protective insulating film 45 in a region including a side portion of
forming d. At this time, the etching gas for the interlayer insulating film 46 is mainly composed of C ₅ F ₈ , which is a fluorocarbon, and has argon (Ar) and oxygen ( O ₂ ) is used.

Next, as shown in FIG. 25, CHF ₃ , which is a fluorocarbon, is used as a main component so that silicon nitride can be etched while giving etching selectivity to the cobalt silicide layer 44. By performing etching using a mixed gas to which argon (Ar) is added, contact holes 46d of the second protective insulating film 45 are formed.
By removing the exposed portion from the contact hole 46d
To expose the cobalt silicide layer 44. At this time,
Etching is performed so that the gate lower layer 33, the barrier metal layer 34, or the gate upper layer 35 is not exposed from the first protective insulating film 36 and the sidewall insulating film 43 made of silicon nitride.

Next, a barrier metal layer (not shown) made of titanium nitride is formed on the bottom surface of the contact hole 46d, and thereafter, as shown in FIG. 26, by a CVD method using tungsten hexafluoride gas. Contact hole 46
A second self-aligned contact 64 is formed on d. At this time, also in the first CMOS inverter 50, the first self-aligned contact 54 is formed similarly to the second self-aligned contact 64.

As described above, the memory cells according to the third embodiment have the first memory cells each having no branching part and being parallel to each other.
First having a shared gate 50G and a second shared gate 60G
, And a second CMOS inverter 60.

The second common gate 50G has the second
P-type drain diffusion layer 61d of CMOS inverter 60
The first shared gate 50G and the p-type drain diffusion layer 61d are electrically connected by the first sidewall contact 66 provided near the upper end, and the first CMOS in the second shared gate 60G is provided. Inverter 50 p
The second shared gate 60G and the p-type drain diffusion layer 51d are electrically connected to each other by the second sidewall contact 56 provided near the end on the drain diffusion layer 51d. Cell area can be reduced.

Further, since the contacts, such as the p-type source diffusion layer 61s, on which the side wall contacts 56, 66 are not formed are self-aligned contacts, the cell area can be further reduced.

Each side wall contact 56,
66 can be formed on the p-type source diffusion layer 61s and the like in the same step as the cobalt silicide layer 44, so that the manufacturing process can be simplified.

Although a thermal oxide film is used for the gate insulating film 32, a deposited oxide film may be used, or a MIS structure using silicon oxynitride may be used.

The gate lower layer 33 and the gate upper layer 3
5, the barrier metal layer 34 is provided, but is not necessarily provided.

[0154]

According to the first semiconductor integrated circuit device and the method of manufacturing the same according to the present invention, the gate insulating film and the first layer which is the lower layer of the gate are simultaneously etched. Since the surface of the gate insulating film is not contaminated during the removal, the reliability of the gate insulating film is improved. When a material having a lower resistivity than the lower first layer is used for the upper second layer, the contact resistance between the shared gate and the common drain can be reliably reduced.

According to the second or third semiconductor integrated circuit device and the method of manufacturing the same according to the present invention, the first connecting means for connecting the first shared gate and the second complementary transistor pair includes the second connecting means. Is formed as a self-aligned contact on the complementary transistor pair described above, the margin for mask alignment when patterning the first connection means can be reduced, and the cell area can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view showing one memory cell of an SRAM device, which is a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2A is a sectional view taken along line IIa-IIa in FIG. FIG. 2B is a sectional view taken along the line IIb-IIb in FIG. 1.

FIG. 3A is an SRA according to the first embodiment of the present invention;
FIG. 13 is a partial plan view showing a mask pattern for forming a first contact portion of a first shared gate in the M device. (B) shows a cross-sectional configuration along line IIIb-IIIb corresponding to the shared gate patterned by the mask pattern of (a).

FIGS. 4A and 4B are plan views showing a method of manufacturing the SRAM device according to the first embodiment of the present invention, showing a first contact portion in a process order.

FIGS. 5A and 5B are plan views showing a method of manufacturing the SRAM device according to the first embodiment of the present invention, showing a first contact portion in a process order. (C) is the first of the present invention.
FIG. 21 is a plan view showing another patterning shape of the first contact portion in the method for manufacturing the SRAM device according to the embodiment.

FIGS. 6A and 6B show a method of manufacturing the SRAM device according to the first embodiment of the present invention, and show IIa-II of FIG.
It is sectional drawing of a process order in a line a.

FIGS. 7A and 7B show a method of manufacturing the SRAM device according to the first embodiment of the present invention, and show IIa-II of FIG.
It is sectional drawing of a process order in a line a.

FIGS. 8A and 8B show a method of manufacturing the SRAM device according to the first embodiment of the present invention, and show IIa-II of FIG.
It is sectional drawing of a process order in a line a.

FIGS. 9A and 9B show a method of manufacturing the SRAM device according to the first embodiment of the present invention, and show IIa-II of FIG.
It is sectional drawing of a process order in a line a.

10 is a cross-sectional view of the SRAM device manufacturing method according to the first embodiment of the present invention in the order of steps along line IIa-IIa in FIG. 1;

FIG. 11 is a sectional view of the SRAM device manufacturing method according to the first embodiment of the present invention in the order of steps taken along line IIa-IIa of FIG. 1;

12 is a sectional view of the SRAM device manufacturing method according to the first embodiment of the present invention in the order of steps along line IIa-IIa in FIG. 1;

FIG. 13 is a plan view showing one memory cell of an SRAM device, which is a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIGS. 14A and 14B are views showing a method of manufacturing an SRAM device according to a second embodiment of the present invention, and FIG.
It is sectional drawing of a process order in XX line.

FIGS. 15A and 15B show a method of manufacturing an SRAM device according to a second embodiment of the present invention, and show XX- in FIG.
It is sectional drawing of a process order in XX line.

FIG. 16 is a sectional view of the SRAM device manufacturing method according to the second embodiment in the order of steps along line XX-XX in FIG. 13;

FIG. 17 is a cross-sectional view illustrating a method of manufacturing the SRAM device according to the second embodiment of the present invention in the order of steps along line XX-XX in FIG. 13;

FIG. 18 is a sectional view illustrating the method of manufacturing the SRAM device according to the second embodiment of the present invention in the order of steps along line XX-XX in FIG. 13;

FIG. 19 is a sectional view of the manufacturing method of the SRAM device according to the second embodiment of the present invention in the order of steps along line XX-XX in FIG. 13;

FIG. 20 is a sectional view of the SRAM device manufacturing method according to the second embodiment in the order of steps along line XX-XX in FIG. 13;

FIG. 21 is a plan view showing one memory cell of an SRAM device, which is a semiconductor integrated circuit device according to a third embodiment of the present invention.

FIGS. 22 (a) and (b) show a method of manufacturing an SRAM device according to a third embodiment of the present invention.
It is sectional drawing of a process order in the -XXVI line.

FIGS. 23 (a) and (b) show a method of manufacturing an SRAM device according to a third embodiment of the present invention.
It is sectional drawing of a process order in the -XXVI line.

FIGS. 24 (a) and (b) show a method of manufacturing an SRAM device according to a third embodiment of the present invention.
It is sectional drawing of a process order in the -XXVI line.

FIG. 25 is a sectional view of the SRAM device manufacturing method according to the third embodiment of the present invention in the order of steps along line XXVI-XXVI in FIG. 21;

FIG. 26 is a sectional view of the SRAM device manufacturing method according to the third embodiment of the present invention in the order of steps along line XXVI-XXVI in FIG. 21;

FIG. 27 is a circuit diagram showing one memory cell of a normal SRAM device.

FIG. 28 is a plan view showing one memory cell using a shared contact in a conventional SRAM device.

[Explanation of symbols]

3 Mask pattern (of first shared gate) 10 First CMOS inverter (first complementary transistor pair) 10G First shared gate 10c First contact portion 11p p-type MOSFET 11s p-type source diffusion layer 11d p-type drain diffusion Layer 11dc contact region 12n n-type MOSFET 12s n-type source diffusion layer 12d n-type drain diffusion layer 14 first self-aligned contact 20 second CMOS inverter (second complementary transistor pair) 20G second shared gate 20c second contact Part 21p p-type MOSFET 21s p-type source diffusion layer 21d p-type drain diffusion layer 21dc contact region 22n n-type MOSFET 22s n-type source diffusion layer 22dn n-type drain diffusion layer 24 second self-aligned contact 30 semiconductor substrate 31 Element isolation region 32 Gate insulating film 33 Gate lower layer (first layer / gate first forming layer) 33a Opening 34 Barrier metal layer 35 Gate upper layer (second layer / gate second forming layer) 36 First protective insulation Film 42 p-type extension layer 43 sidewall insulating film 44 cobalt silicide layer 44a sidewall silicide layer 45 second protective insulating film 46 interlayer insulating film 46a contact hole 46b first contact hole (first connection hole) 46c second Contact hole (fourth connection hole) 46d contact hole 47 resist material 48 resist film 48a opening pattern (first opening) 50 first CMOS inverter (first complementary transistor pair) 50G first shared gate 50c 1 contact portion 51p p-type MOSFET 51s p-type source diffusion layer 51d p-type drain diffusion layer 52n n-type MOSFET 52s n-type source diffusion layer 52d n-type drain diffusion layer 53 second shared contact (second connection means) 54 first self-aligned contact 56 second sidewall contact (second (Silicide layer) 60 second CMOS inverter (second complementary transistor pair) 60G second shared gate 60c second contact portion 61p p-type MOSFET 61s p-type source diffusion layer 61d p-type drain diffusion layer 62n n-type MOSFET 62s n -Type source diffusion layer 62d n-type drain diffusion layer 63 first shared contact (first connection means) 64 second self-aligned contact 66 first sidewall contact (first silicide layer)

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takayuki Matsuda 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 72) Inventor Hideo Ichimura 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture F-term in Matsushita Electric Industrial Co., Ltd.

Claims (13)

[Claims] 1. A first complementary transistor pair having a first shared gate formed on a semiconductor region via a gate insulating film, and a second shared transistor pair formed on the semiconductor region via a gate insulating film. A second complementary transistor pair having a gate, wherein the first shared gate is connected to a common drain of the second complementary transistor pair, and the second shared gate is connected to the first complementary transistor pair. A static semiconductor memory device connected to a common drain, wherein the first shared gate is a first layer and a second layer sequentially formed from below on a region of the first complementary transistor pair And a first layer electrically connected to a region of the second complementary transistor pair without interposing the common drain and the gate insulating film and the first layer.
A contact portion, wherein the second shared gate comprises a first layer and a second layer sequentially formed from below on a region of the second complementary transistor pair; The second layer is electrically connected to the common drain without the gate insulating film and the first layer on the region of the second layer.
A semiconductor integrated circuit device having a contact portion. 2. The second shared gate side of the first contact portion includes the first layer below the second layer, and the first shared gate side of the second contact portion includes:
2. The semiconductor integrated circuit device according to claim 1, wherein the first layer is included below the second layer. 3. The method according to claim 2, wherein the first layer includes silicon, and the second layer includes silicon.
3. The semiconductor integrated circuit device according to claim 1, wherein the layer is made of metal or metal silicide. 4. A first complementary transistor pair having a first shared gate formed on a semiconductor region and a second complementary transistor pair having a second shared gate formed on the semiconductor region. A static semiconductor memory having the first shared gate connected to a common drain of a second complementary transistor pair and the second shared gate connected to a common drain of a first complementary transistor pair An apparatus is formed on the second complementary transistor pair so as to straddle a side portion of the first shared gate, and includes a common drain of the first shared gate and the second complementary transistor pair. A first connecting means for connecting the second shared gate and the first complementary transistor, the first connecting means being formed on the first complementary transistor pair so as to straddle a side portion of the second shared gate. Second connection means for connecting the common drain of the data pair to the common drain, wherein the first shared gate and the second shared gate are a first layer and a second layer sequentially formed on the semiconductor region from below. Wherein the second layer of the first shared gate is electrically connected to the drain via the first connection means, and the second shared gate is 2. A semiconductor integrated circuit device, wherein a second layer of the shared gate is electrically connected to the drain via the second connection means. 5. The method according to claim 1, wherein the first layer includes silicon, and the second layer includes silicon.
The semiconductor integrated circuit device according to claim 4, wherein the layer is made of metal or metal silicide. 6. A first complementary transistor pair having a first shared gate formed on a semiconductor region made of silicon, and a second complementary transistor having a second shared gate formed on the semiconductor region. A first common gate is connected to a common drain of a second complementary transistor pair, and the second common gate is connected to a common drain of the first complementary transistor pair. A semiconductor memory device, wherein the first shared gate and the second shared gate are constituted by a first layer and a second layer sequentially formed from the semiconductor region side, wherein the first shared gate and the second shared gate A common drain of the complementary transistor pair is electrically connected to a side of the first layer and a first silicide layer in which an upper portion of the drain is silicided together; The second shared gate and the common drain of the first complementary transistor pair are electrically connected by a second silicide layer in which both the side surface of the first layer and the upper portion of the drain are silicided. A semiconductor integrated circuit device. 7. A transistor is formed on the first complementary transistor pair so as to straddle the side of the first shared gate, and connects the first shared gate to a source of the first complementary transistor pair. A third connecting means, and a source formed between the second shared gate and the second complementary transistor pair, the third connecting means being formed on the second complementary transistor pair so as to straddle a side portion of the second shared gate. 7. The semiconductor integrated circuit device according to claim 1, further comprising: a fourth connection unit configured to connect the semiconductor integrated circuit to the semiconductor integrated circuit device. 8. 8. A step of sequentially forming a gate insulating film and a gate first formation layer on respective formation regions of a first complementary transistor pair and a second complementary transistor pair each having a diffusion layer; A first opening is formed on the diffusion layer of the second complementary transistor pair in the gate insulating film and the gate first formation layer, and the first complementary type in the gate insulating film and the gate first formation layer is formed. Forming a second opening on the diffusion layer of the transistor pair; depositing a gate second forming layer inside the first opening and the second opening and on the gate first forming layer; Forming a first contact formation portion made of the gate second formation layer in the first opening and forming a second contact formation portion made of the gate second formation layer in the second opening; No. For the first formation layer and the gate second formation layer,
By patterning so as to extend over the diffusion layer of the first complementary transistor pair, the gate second formation layer interposes the gate first formation layer at the end on the second complementary transistor pair side. Forming a first shared gate having a first contact portion electrically connected to a diffusion layer of the second complementary transistor pair without forming a first shared gate; hand,
By patterning so as to extend over the diffusion layer of the second complementary transistor pair, the gate second formation layer interposes the gate first formation layer at the end on the first complementary transistor pair side. Forming a second shared gate having a second contact portion that is electrically connected to the diffusion layer of the first complementary transistor pair without forming the second shared gate. Method. 9. The patterning step of the first shared gate is performed so as to include the first gate forming layer on the second shared gate side of the first contact portion and below the second gate forming layer. The patterning step of the second shared gate is characterized in that the patterning is performed so as to include the first gate forming layer on the first common gate side of the second contact portion and below the second gate forming layer. The method for manufacturing a semiconductor integrated circuit device according to claim 8. 10. A step of sequentially forming a gate insulating film, a gate first formation layer, and a gate second formation layer in a formation region of a first complementary transistor pair and a formation region of a second complementary transistor pair; For the first gate formation layer and the second gate formation layer,
The gate first formation layer and the gate are formed by extending over the formation region of the first complementary transistor pair and patterning such that one end is included in the formation region of the second complementary transistor pair. Forming a first shared gate made of a second formation layer;
The gate first formation layer and the gate are formed by extending over the formation region of the second complementary transistor pair and patterning one end to be included in the formation region of the first complementary transistor pair. Forming a second shared gate composed of a second formation layer; and forming a diffusion layer of a first conductivity type and a second conductivity type in each formation region of the first complementary transistor pair and the second complementary transistor pair. Forming an insulating film so as to include the first shared gate and the second shared gate; and providing the deposited insulating film with a diffusion layer of the second complementary transistor pair and the first shared gate. Forming a first connection hole exposing both ends of the shared gate; and forming a diffusion layer of the first complementary transistor pair and an end of the second shared gate on the deposited insulating film. both Forming an exposed second connection hole; and filling the first connection hole with a conductive material to electrically connect the first shared gate and the diffusion layer of the second complementary transistor pair. Connecting, and filling the second connection hole with a conductive material to electrically connect the second shared gate and the diffusion layer of the first complementary transistor pair. A method for manufacturing a semiconductor integrated circuit device. 11. A third connection hole exposing another diffusion layer in which the second connection hole of the first complementary transistor pair is not formed in the insulating film; and a second complementary transistor pair. Forming a fourth connection hole exposing another diffusion layer in which the first connection hole is not formed, wherein the step of filling the first connection hole includes the step of filling the first connection hole with the first connection hole. And a step of filling the second connection hole with a conductive material. The step of filling the second connection hole includes a step of filling the second connection hole and the third connection hole with a conductive material. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein: 12. A step of sequentially forming a gate insulating film, a gate first formation layer, and a gate second formation layer in a formation region of a first complementary transistor pair and a formation region of a second complementary transistor pair; For the gate first formation layer and the gate second formation layer,
The gate first formation layer and the gate are formed by extending over the formation region of the first complementary transistor pair and patterning such that one end is included in the formation region of the second complementary transistor pair. Forming a first shared gate made of a second formation layer;
The gate first formation layer and the gate are formed by extending over the formation region of the second complementary transistor pair and patterning one end to be included in the formation region of the first complementary transistor pair. Forming a second shared gate composed of a second formation layer; and forming a diffusion layer of a first conductivity type and a second conductivity type in each formation region of the first complementary transistor pair and the second complementary transistor pair. Forming an insulating film covering the first complementary transistor pair and the second complementary transistor, and forming a diffusion layer of the second complementary transistor pair and the first Forming a first opening for exposing both ends of the shared gate; exposing both the diffusion layer of the first complementary transistor pair and the end of the second shared gate to the insulating film; Forming a second opening; and siliciding an exposed portion of the diffusion layer of the second complementary transistor pair and a side surface of the first gate forming layer of the first shared gate from the first opening. Electrically connecting the diffusion layer and the first shared gate, and the diffusion layer of the first complementary transistor pair and the side surface of the gate first formation layer of the second shared gate. Electrically connecting the diffusion layer and the second shared gate by silicidizing a portion exposed from the second opening in the semiconductor integrated circuit device. Method. 13. A silicidation process for a portion exposed from the first opening and a portion exposed from the second opening, wherein the silicidation is performed on another portion where the second connection hole of the first complementary transistor pair is not formed. 13. The method according to claim 12, further comprising a step of silicidizing an upper surface of the diffusion layer and an upper surface of another diffusion layer in which the first connection hole of the second complementary transistor pair is not formed. A method for manufacturing a semiconductor integrated circuit device.