JP2002313946A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor product having arsenic N+ diffusion that prevents the deterioration of protectiveness caused by a rise (walkout) in trigger voltage which occurs when an ESD pulse is applied to the product several times in the case where the product has a phosphorus-diffused ESD protective off-transistor. SOLUTION: The semiconductor product is constituted in such a structure that the drain diffusion of the phosphorus-diffused ESD protective off-transistor is not provided adjacently to an off-gate and the arsenic N+ diffusion 5 is provided in the adjacent area of an element separating region 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ESD protection element for protecting a semiconductor device from electrostatic damage.

[0002]

2. Description of the Related Art In a CMOS semiconductor device, an NMOS transistor having a conventional drain structure in which a gate is dropped to a substrate potential is often used as an ESD protection element. cm
Utilizes the surface breakdown of this transistor, which occurs in the voltage range that is higher than the maximum operating voltage of the OS semiconductor device and does not lead to breakdown with a normal NMOS transistor, causes current between the drain and the P-substrate, and becomes an emitter By applying a forward voltage between the source and the base P-substrate, the NPN bipolar operation is switched and a large charge is released.

In this type of protection element, phosphorus is often used as an impurity so that a deeper and more uniform diffusion can be obtained so that the current is uniform and sufficient heat capacity is provided during the discharge of the ESD charge. On the other hand, in the drain diffusion layer of a normal transistor, arsenic, which can obtain a shallower diffusion suitable for fineness, is often used as an impurity. In addition, a normal transistor uses a lighter-diffusion diffusion at a drain portion adjacent to a gate, and has a higher surface breakdown than a protection element having a conventional structure.

[0004]

However, in such a structure, when an ESD pulse is repeatedly received many times, charges are injected into the gate oxide film near the drain of the protection element every time the surface breakdown occurs. As a result, a phenomenon such as walkout in which surface breakdown is increased occurs. Eventually, there is a problem that the junction breakdown in the drain arsenic diffusion layer of a normal transistor is activated first, leading to destruction.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problems, the present invention provides an ESD protection element of a phosphorus diffusion conventional NMOS off transistor as follows. In an ESD protection element of a phosphorus diffusion conventional NMOS off transistor of a MOS semiconductor device having arsenic diffusion, a structure in which a drain diffusion layer that is not adjacent to an off gate and in contact with an element isolation region is formed of arsenic is used. The semiconductor device was characterized.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of an ESD protection element of a phosphorus diffusion conventional type NMOS off transistor according to the present invention. Normally, a transistor 11 and a conventional NMOS 12 are present on the same P-type silicon substrate 1. In both cases, a gate oxide film 2 and a gate electrode 3 on the gate oxide film 2 are formed, and the source / drain portion adjacent to the gate electrode 3 is a normal and transistor 11 in which an arsenic diffusion N + diffusion layer 5 and a low concentration N− diffusion layer 6 are doubled. The conventional NMOS 12 has a structure in which the phosphorus diffusion N + diffusion layer 4 exists. The difference from the conventional structure shown in FIG. 2 is that an arsenic diffusion N + diffusion layer 5 is provided on the element isolation oxide film 7 side on the drain side of the conventional NMOS 12. A channel stop layer 8 exists below the element isolation oxide film 7 and is in contact with the arsenic diffusion N + diffusion layer 5 at the end of the drain element isolation oxide film 7.

The wiring shown by the center line in the figure is connected to the electrodes of the input / output terminals of the semiconductor device, from which the ESD pulse is input. The input positive charge pulse increases the drain voltages of the conventional NMOS 12 and the normal transistor 11. The electric field between the phosphorus diffusion N + diffusion layer 4 and the gate electrode 3, which is the drain of the conventional NMOS 12, causes breakdown and discharges current to the P-type silicon substrate. In addition, the substrate voltage drop due to the substrate current causes a source-substrate-drain NPN bipolar. In the normal transistor 11 having the double diffusion structure, no electric current is generated because the electric field in the drain is weakened, and all charges are sent to the region of the conventional NMOS 12.

The relationship between the withstand voltage within the reach of the ESD pulse is as follows.
The lowest is the surface breakdown occurring between the phosphorus N + diffusion layer 4 and the gate electrode 2, and the second lowest is the junction breakdown voltage between the channel stop layer 8 and the drain. Generally, the junction breakdown voltage is lower in a shallow arsenic drain than in a deep phosphorus diffusion drain.

The severe breakdown occurring near the gate oxide film 2 in the phosphorus diffusion N + diffusion layer 4 serving as a trigger causes charges having high energy to be transferred to the gate oxide film 2 in the vicinity.
And changes the electric field distribution.
This phenomenon may cause the breakdown voltage serving as a trigger to shift to a higher direction. If the trigger voltage rises due to many breakdowns, the junction breakdown in the arsenic diffusion N + diffusion layer 5 and the channel stop layer 8 which is the second lowest after the surface breakdown of the conventional NMOS 12 occurs first, and the normal transistor 11 Substrate current starts to increase. Arsenic diffusion N + also in the drain of the conventional NMOS 12
By providing a junction between the diffusion 4 and the channel stop layer 8, a similar increase in substrate current can be achieved by a conventional NMOS.
In the conventional NMOS 12, the increase in the substrate current is always dominant, and the breakdown of the transistor 11 can be prevented. .

[0011]

As described above, according to the present invention, it is possible to supply a semiconductor element which is hard to be broken even if it is input many times of ESD pulses.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating an embodiment of an ESD protection element of a phosphorus diffusion conventional NMOS off transistor according to the present invention.

FIG. 2 is a cross-sectional view showing a conventional ESD protection element of a phosphorus diffusion conventional NMOS off transistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 P-type silicon substrate 2 Gate oxide film 3 Gate electrode 4 Phosphorus diffusion N + diffusion layer 5 Arsenic diffusion N + diffusion layer 6 Low concentration N- diffusion layer 7 Isolation oxide film 8 Channel stop diffusion layer 11 Normal transistor 12 Conventional type NMOS

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Claims (1)

[Claims] 1. An ESD protection element for a conventional NMOS off transistor of a CMOS semiconductor device having arsenic diffusion, wherein a drain region adjacent to an off gate is formed of a phosphorus diffusion layer, and is not adjacent to the off gate, and an element is provided. A semiconductor device having a structure in which at least a part of a drain diffusion layer in contact with an isolation region is formed of an arsenic diffusion layer.