JP2002305529A - Gbic communication interface device and gbic communication interface system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a GBIC(Giga Bit Interface Converter) communication interface device that can realize support of various standards of 10 Mbps/100 Mbps/1000 Mbps. SOLUTION: GBIC I/F control sections 26, 27, 36, 37 controlling a relation between a GMII(Gigabit Media Independent Interface) and a GBIC I/F depending on the type of a connected GBIC module are provided between MACs(Media Access Control) 22, 23, 32, 33 and GBIC modules 28, 29, 38, 39 incorporating PHY(Physical layers) of various standards such as 10 Mbps/100 Mbps/1000 Mbps in order to support various standards of the 10BASE/100BASE/1000BASE. Furthermore, a GMII bridge interconnecting the GBIC interface and the GMII is provided to attain data transmission/reception in the GBIC modules 28, 29, 38, 39.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a GBIC communication interface device and a GBIC communication interface system, and more particularly, to a communication interface system specified in IEEE 802.3.

[0002]

2. Description of the Related Art 1000BASE-X (1000BASE-SX / LX) defined in IEEE 802.3
/ CX), 1000BASE-T, 10 / 100BAS
The relationship between MAC and PHY in E-TX is shown in FIGS.

In FIG. 5, the P of 1000BASE-X
The HY (physical layer) 5 is a PCS (Physical Code).
ing Sublayer (physical coding sublayer) 51 and PMA (Physical Media)
Attachment sublayer: physical media attachment 52 and PMD (Physical)
Media Dependent sublaye
r: physical media dependent) 53 and M
The AC (Media Access Control) 4 is GMII (Gigabit Me).
dia Independent Interfac
e: Gigabit speed medium independent interface) (8-bit parallel data signal + 4-bit control signal + transmit / receive clock signal) (125 MHz)
ASE-X receives a differential serial data signal (1.25 GHz).
z).

[0004] Here, the MAC 4 controls access to the PHY 5 to schedule data transmission and reception.
The PCS 51 encodes data to be transmitted in a form suitable for a physical medium, and the PMA 52 performs serialization (serialization) of a packet to be transmitted and deserialization that is the reverse process. Further, the PMD 53 converts the transmitted voltage change pattern into a light wave or a pulse so that it can be transmitted by a cable.

In 1000BASE-X, PCS51, P
Since the MA52 is common, PMD is used for GBIC (Gigabit Interface Converter) interface.
53, 1000BASE-SX GBIC (Gi
gabbit Interface Converte
r: Gigabit interface converter) module, 1000BASE-LX GBIC module, 1
000BASE-CX GBIC module.

In FIG. 6, P of 1000BASE-T
HY7 is composed of T_PCS71 and T_PMA72, and GMII (8-bit parallel data signal + 4-bit control signal + transmit / receive clock signal) (125M
Hz) and transmits a differential parallel data signal (125 MHz) to 1000BASE-T. T_PCS
71 and T_PMA72 are PCs of 1000BASE-X
Different from S51 / PMA52.

[0007] In FIG. 7, 10/100 BASE-T
PHY 9 of X is TX_PCS 91 and TX_PMA 92
And TX_PMD93.
(Media Independent Interf
ace: medium-independent interface) (4-bit parallel data signal + 4-bit control signal + transmit / receive clock signal) (25 / 2.5 MHz)
BASE-TX receives a differential serial data signal (125/2
5 MHz). TX_PCS91 and TX_P
MA92 is 1000BASE-X PCS51 / PMA
52 is different.

[0008]

In the above-mentioned conventional communication interface system, 1000BASE-T is 100
T_PC different from PCS / PMA of 0BASE-X
Since it is composed of S and T_PMA, it cannot support the GBIC interface.

[0009] Also, since 10/10 / BASE-TX is constituted by TX_PCS and TX_PMA different from PCS / PMA of 1000BASE-X, GBI
Cannot support C interface.

Furthermore, since the GMII 4-bit control signal and the transmission / reception clock signal used in 1000BASE-X are not supplied to the GBIC interface, 1000BASE-TPHY and 10 / 100B which require the 4-bit control signal and the transmission / reception clock signal as input / output signals.
ASE-TX PHY cannot be connected to GBIC interface.

As described above, in the conventional GBIC interface, 1000BASE-T and 10 / 100B
There is a problem that ASE-TX cannot support the GBIC interface.

[0012] Therefore, an object of the present invention is to solve the above-mentioned problems and to solve the above problems by 10 Mbps / 100 Mbps / 1000 Mbps.
GBI that can support various standards of s
It is to provide a C communication interface device and a GBIC communication interface system.

[0013]

SUMMARY OF THE INVENTION A GBIC communication interface device according to the present invention includes a physical coding sublayer for encoding data to be transmitted in a form suitable for a physical medium, and serialization and deserialization of a packet for transmission. A physical layer including a physical media attachment for performing the communication, a medium access control for controlling access to the physical layer and scheduling data transmission and reception, and 10 Mbps / 100 Mbps / 1000 Mbps.
GBIC (Gigabi) with a built-in physical layer of various standards
t Interface Converter) module, control means for controlling the operation of the physical coding sublayer in accordance with the type of the GBIC module, and the medium access control and the control in the GBIC module in accordance with the determined type of the GBIC module. Signal control means for performing signal control with the physical layer.

The GBIC communication interface system according to the present invention comprises a physical coding sublayer for encoding data to be transmitted in a form suitable for a physical medium, and a physical media attachment for serializing and deserializing a packet for transmission. , A medium access control for controlling access to the physical layer and scheduling data transmission and reception, 10 Mbps
GBIC (Gigabit Interf.) With a built-in physical layer of various standards of / 100Mbps / 1000Mbps
ACE Converter) module, and controls the operation of the physical coding sublayer, the medium access control, and the signal control between the physical layer in the GBIC module according to the type of the GBIC module to be connected. I have to.

That is, the GBIC communication interface device of the present invention is an SFF-805 compatible with the Ethernet (registered trademark) communication interface of IEEE802.3.
3GBIC (Gigabit Interface C
inverter: Gigabit interface converter) 10BASE / 10 in communication interface
In order to support Ethernet functions of 0BASE / 1000BASE, MAC (Media Access)
Control: medium access control) and 10 Mbp
P of various standards of s / 100Mbps / 1000Mbps
According to the type of the GBIC module to be connected, the GM
II (Gigabit Media Independent)
entInterface: a GBIC I / F (interface) control unit for controlling between a gigabit-speed medium independent interface) and a GBIC interface, and a GBIC interface and a GMII for enabling data transmission and reception in a GBIC module. And a GMII bridge unit to be connected.

More specifically, the GBI of the present invention
In the C communication interface device, in the GBIC communication interface, from the MAC to the P in the GBIC module
To control HY, TX_D defined by GBIC (Gigabit Interface Converter) connector
M via each signal of ISABLE (transmission impossible), TX_FAULT (transmission failure), RX_LOS (reception loss)
II (Media Independent Inte
rface: medium independent interface) / MDC (control data clock), M of GMII interface signal
DIO (control data input / output) and GTX_CLK (gigabit transmission clock) are connected.

In the GBIC communication interface device of the present invention, MDC / MDIO / GTX_CLK / RX_C is set according to the type of the GBIC module to be connected.
8B of LK signal and 1000BASE-X PHY circuit
GB for controlling 10B (8-bit 10-bit encoding)
It has an IC I / F control circuit.

Further, in the GBIC communication interface device of the present invention, in the GBIC communication interface,
PHY MII / GMII in GBIC module
TXD to connect interface signal to MAC
(Transmission data) <0-7>, TX_EN (transmission enable), TX_ER (transmission error), RXD (reception data) <0-7>, RX_DV (reception enable), RX
It has a GMII bridge circuit for connecting _ER (reception error).

As a result, in the communication interface using the GBIC I / F, the conventional IEEE 80
1000BASE-X defined in 2.3, that is, 1000BASE-SX, 1000BASE-LX, 1
While only 000BASE-CX can be supported, according to the present invention, 10 Mbps / 100 Mbps /
Support for various standards of 1000 Mbps can be realized.

[0020]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a GBIC communication interface device according to one embodiment of the present invention. In FIG. 1, a switching hub 1 has a console 11 for connecting a memory 11 used for storing and holding data and an external management console terminal (not shown).
/ O8 input / output circuit) 12, a packet switching mechanism 13 for switching packets, a CPU (central processing unit) 14 for performing routing processing and the like, and interface cards 2 and 3.

The interface card 2 has a packet forwarding mechanism 21 for transferring a packet, and a MAC (Media Access) for processing and processing the packet.
Control: medium access control) 22, 23 and P
HY (physical layers) 24, 25 and GBIC (Gigabi)
t Media Independent Inter
face: Gigabit interface converter) I /
F (interface) control units 26 and 27, 1000B
ASE-T GBIC module 28 and 1000BA
An SE-SX GBIC module 29 is mounted.

The interface card 3 includes a packet forwarding mechanism 31 for transferring packets, MACs 32 and 33 for processing and processing packets, and PHYs 34 and 3.
5, GBIC I / F control units 36 and 37, 10/1
00BASE-TX GBIC module 38 and 10
A 00BASE-SX GBIC module 39 is mounted.

The PHYs 24, 25, 34, and 35 are 10
00BASE-X (1000BASE-SX, 1000
BASE-LX, 1000BASE-CX) and a 1000BASE-T GBIC module 2
8, 1000BASE-SXGBIC module 29,
10 / 100BASE-TX GBIC module 3
8, 1000BASE-SX GBIC module 39
10Mbps / 100Mbps / 1000 respectively
Mbps standards (1000BASE-T, 1000BASE
BASE-SX (10/100 BASE-TX).

FIG. 2 shows the MAC 22, PHY 24 and GBIC constituting the port # 1 of the interface card 2 of FIG.
I / F control unit 26 and 1000BASE-T GBIC
FIG. 3 is a block diagram showing a detailed configuration of a module 28. In FIG. 2, the PHY 24 is a PCS (Phys
ical coding sublayer: 241 and a PMA (Physic)
al Media Attachment subla
yer: physical media attachment) 242.

Here, the MAC 22 controls access to the PHY 24 to schedule data transmission and reception. The PCS 241 encodes data to be transmitted in a form suitable for a physical medium, and the PMA 242 performs serialization (serialization) of a packet to be transmitted and deserialization that is the reverse process.

The GBIC I / F control unit 26 includes a clock recovery circuit 261, a switch circuit 262, a comparison circuit 263, a signal control circuit 264, and a GBIC detection circuit 2.
65.

The 1000BASE-T GBIC module 28 is a GMII (Gigabit Media India)
independent interface: gigabit speed medium independent type interface) bridge unit 281, serial ROM 284, 1000BASE-T PHY2
85. GMII bridge section 281
Is composed of a serial / parallel conversion circuit 282 and a parallel / serial conversion circuit 283.

That is, on the port # 1 side of the interface card 2, the GMII [MDC (control data clock) / MDC] between the MAC 22 and the GBIC interface depends on the type of the GBIC module connected.
MDIC (control data input / output) / TX_CLK (transmission clock) / RX_CLK (reception clock)] and the PCS 241 for controlling transmission and reception of data.
GBIC bridge unit 281 and GMI for enabling transmission and reception of data to and from BASE-T PHY 285
A 1000BASE-T PHY 285 connected by I is arranged inside the 1000BASE-T GBIC module 28.

As a result, the S corresponding to the Ethernet (registered trademark) communication interface of IEEE802.3 can be used.
In FF-8053 GBIC communication interface, 10BASE / 100BASE / 1000BASE
Ethernet function can be supported.

FIG. 3 shows a MAC 23, a PHY 25 and a GBIC constituting the port # 2 of the interface card 2 of FIG.
I / F control unit 27 and 1000BASE-SX GBI
FIG. 3 is a block diagram showing a detailed configuration of a C module 29. In FIG. 3, PHY 25 is PCS 251
And a PMA 252.

The GBIC I / F control unit 27 includes a clock recovery circuit 271, a switch circuit 272, a comparison circuit 273, a signal control circuit 274, and a GBIC detection circuit 2.
75. 1000BASE-TG
The BIC module 29 includes a serial ROM 291,
0BASE-SX PMD (Physical Med
ia Dependent sublayer (physical media dependent) 292.

FIG. 4 shows a MAC 32, a PHY 34 and a GBIC constituting the port # 3 of the interface card 3 in FIG.
I / F control unit 36 and 10 / 100BASE-TX G
FIG. 3 is a block diagram showing a detailed configuration of a BIC module 38; In FIG. 4, PHY 34 is PCS 34
1 and a PMA 342.

The GBIC I / F control unit 36 includes a clock recovery circuit 361, a switch circuit 362, a comparison circuit 363, a signal control circuit 364, and a GBIC detection circuit 3
65.

The 10/100 BASE-TX GBIC module 38 includes a GMII bridge section 381, a serial ROM 384, and a 10/100 BASE-TX PHY3.
85. GMII bridge section 381
Is composed of a serial / parallel conversion circuit 382 and a parallel / serial conversion circuit 383.

That is, on the port # 3 side of the interface card 3, the MAC 32 and the 10/100 BAS
A GMII bridge unit 381 and a MII (MII) for enabling transmission and reception of data to and from the E-TX PHY 385
edia Independent Interfac
e: 10/0 connected by media independent type interface)
00BASE-TX PHY385 is 10 / 100B
The ASE-TX GBIC module 38 is provided inside.

With reference to FIGS. 1 to 4, an overall flow when data is transmitted and received at ports # 1 to # 3 in one embodiment of the present invention will be described. First, the data transmission / reception operation on port # 1 will be described with reference to FIG.

The transmission data is transmitted from the packet forwarding mechanism 21 to the MAC 22 in the interface card 2.
GMII TXD (transmission data) <0-7
>, TX_EN (transmission enable) and TX_ER (transmission error) to the PCS 241 of the PHY 24.

At this time, since the data sent to the PCS 241 is controlled by the GBIC I / F control unit 26 so that the internal function of the PCS 241 does not operate, the data is sent to the PMA 242 without any processing. GBIC I
The detailed operation of the / F control unit 26 will be described later. PMA
242 is converted into a serial signal,
000BASE-T GBIC module 28 as transmission data.

The transmission data sent to the 1000BASE-T GBIC module 28 is transmitted to the GMII bridge 2
81, is converted into a parallel signal by the serial / parallel conversion circuit 282, and the GMII RXD (receive data) <0-7>, RX_DV (receive enable), R
1000 BASE-TP as X_ER (reception error)
Input to HY285.

At this time, the received data clock RX_C
The LK is supplied from the MAC 22 to the 1000BASE-T PHY 285 via the GBIC I / F control unit 26, and the data input to the RXD <0-7> is RX_CL
In synchronization with K, the data is transmitted to the port # 1 through the internal processing of the 1000BASE-T PHY 285.

GBIC I / F control units 26, 27, 36
The detailed operation of will be described below. GBIC I / F
The control units 26, 27 and 36 are compatible with the existing 1000BASE-X.
GBIC module (not shown), 1000BASE
-T GBIC module 28, 1000BASE-S
X GBIC module 29, 10 / 100BASE-
It has a function of switching various signals and the like so that the TX GBIC module 38 can be connected.

A 1000BASE-X GBIC module, a 1000BASE-T GBIC module 28,
1000BASE-SX GBIC module 29, 1
When the 0/100 BASE-TX GBIC module 38 is connected, the GBIC detection circuits 265, 275, 36
5 is a serial ROM 284, 291, 384 in which the type of the connected GBIC module is described.
/ F (interface) is read, and the type of the GBIC module to be connected is recognized.

Next, the GBIC I / F controllers 26 and 2
7 and 36 use the comparison circuits 263, 273 and 383,
The GBIC module is 1000BASE-X GB
Determine whether the module is an IC module and switch circuit 2
62, 272, and 362 according to the type of the GBIC module to be connected.
1 operation control and RX_CLK, TX_CLK, MDI
O, MDC signal control. Each signal control is performed as follows.

When the 1000BASE-X GBIC module is connected, PCS 241, 251
341 is operated. At this time, the clock recovery circuits 261, 271 and 361 output RX_CLK
Is controlled so as not to be output, and the signal control circuit 264,
274, 364: TX_CLK, MDIO, MDC
Control is performed so as not to supply to the BIC module.

Next, when a GBIC module other than the 1000BASE-X GBIC module is connected, control is performed so that the PCSs 241, 251 and 341 are not operated. At this time, the clock recovery circuit 26
1, 271 and 361 extract a clock from RXD <0> and perform control to supply RX_CLK to the MACs 22, 23 and 32, and the signal control circuit 24
3, 32 GMII TX_CLK (transmission clock),
It operates to supply MDIO (control data input / output) and MDC (control data clock) to the GBIC module.

On the other hand, the received data is processed as follows. The data received by port # 1 is 1000BASE-
TXD (transmission data) of GMII of T PHY285 <
0-7>, TX_EN (transmission enable), TX_ER
(Transmission error) to the GMII bridge unit 281.

The GMII bridge section 281 converts the received data into serial data, and the serially converted received data is transmitted to the GBIC interface.
2 is input. The PMA 242 converts the data into parallel data and transmits the data to the PCS 241. At that time, PCS241
Is controlled not to operate by the GBIC I / F control unit 26, and the data is directly used as RXD (reception data) <0-7>, RX_DV (reception enable), and RX_ER (reception error) in the MAC 22.
Sent to MII.

At this time, the receiving data clock RX_C
LK is supplied from the clock recovery circuit 261 of the GBIC I / F control unit 26, and the signal sent to the MAC 22 is sent to the packet forwarding mechanism 21 and processed as received data.

Also, MAC22, 1000BASE-T
The communication control signals between the PHY 285, MDIO and MDC are TX_FAULT (transmission failure), RX defined by the GBIC I / F control unit 26 and the GBIC interface.
_LOS (reception loss), 1000BASE-T PHY285
To the MAC 22.

The data transmission / reception operation at port # 2 will be described with reference to FIG. The transmission data is sent from the packet forwarding mechanism 21 of the interface card 2 to the MA.
C23, GMII TXD (transmission data) <
0-7>, TX_EN (transmission enable), TX_ER
The message is sent to the PCS 251 as (transmission error).

The data sent to PCS 251 is 8B10
B-encoded and sent to PMA 252. P
The data sent to the MA 252 is converted into a serial signal, and the 1000BASE-SX GBIC module 29
Is transmitted as transmission data.

The transmission data sent to the 1000BASE-SX GBIC module 29 is 1000BASE-SX.
SX Sent to PMD292, 1000BASE-SX
The electric signal is converted into an optical signal by the PMD 292 and transmitted to the port # 2.

The received data is processed as follows. The data received by port # 2 is 1000BASE-SX
The optical signal is converted to an electric signal by the PMD 292, sent to the GBIC interface as received data, and
252.

The received data is parallel-converted by the PMA 252 and transmitted to the PCS 251.
0B8B decoded and RXD (received data) <
0-7>, RX_DV (reception enable), RX_ER
It is sent to the GMII of the MAC 23 as (reception error). The signal sent to the MAC 23 is sent to the packet forwarding mechanism 21 of the interface card 2 and processed as received data.

The data transmission / reception operation at port # 3 will be described with reference to FIG. The transmission data is sent from the packet forwarding mechanism 31 of the interface card 3 to the MA.
Sent to C32, GMII TXD (transmission data) <0
-3>, TX_EN (transmission enable), TX_ER
(Transmission error) is sent to PCS341.

At this time, the internal function of PCS 341 is GBI
The data sent to the PCS 341 is sent to the PMA 342 without any processing because it is controlled not to operate by the C I / F control unit 36. The data sent to PMA 342 is converted into a serial signal and
The data is transmitted to the BASE-TX GBIC module 38 as transmission data.

The transmission data sent to the 10/100 BASE-TX GBIC module 38 is sent to the GMII bridge section 381, converted into a parallel signal by the serial / parallel conversion circuit 382, and the MII RXD (received data) <0-3>. , RX_DV (reception enable),
10/10 / BASE as RX_ER (reception error)
-Input to TX PHY385.

At this time, the received data clock RX_C
The LK is supplied from the MAC 32 to the 10/100 BASE-TX PHY 385 via the GBIC I / F control unit 36, and the data input to the RXD <0-3> is RX_
10 / 100BASE-TX PH in synchronization with CLK
The data is transmitted to port # 3 through the internal processing of Y385.

The received data is processed as follows. The data received by port # 3 is 10 / 100BASE-T
X PHY385 MII TXD (transmission data) <0
-3>, TX_EN (transmission enable), TX_ER
(Transmission error) to the GMII bridge unit 381.

The received data sent to the GMII bridge section 381 is serial-converted, sent to the GBIC interface, and then input to the PMA 342. The received data is parallel-converted by the PMA 342 and the PCS 341
Is transmitted to the PCS 341 by the GBIC I
/ F control section 36 does not operate, so that the data is not changed and RXD (received data) <0-3
>, RX_DV (reception enable) and RX_ER (reception error) to the GMII of the MAC 32.

At this time, the receiving data clock RX_C
The LK is supplied from the clock recovery circuit 361 of the GBIC I / F control unit 36, and the signal sent to the MAC 32 is sent to the packet forwarding mechanism 31 of the interface card 3 and processed as received data.

Also, MAC32, 10 / 100BASE
Communication control signal between TX PHY 385, MDIO and M
DC is connected via the GBIC I / F control unit 36 and TX_FAULT (transmission failure) and RX_LOS (reception loss) defined by the GBIC interface,
When establishing a link, for example, 10 / 100BASE-TX
Information is sent from the PHY 385 to the MAC 32.

As described above, in the communication interface using the GBIC I / F, conventionally, the IEEE 80
1000BASE-SX, 10 defined in 2.3
Although only 00BASE-LX and 1000BASE-CX can be supported, according to the present invention, 10 Mbps /
Support for various standards of 100 Mbps / 1000 Mbps can also be realized.

[0064]

As described above, according to the present invention, a physical coding sublayer for encoding data to be transmitted in a form suitable for a physical medium, and serialization and deserialization of a packet for transmission are performed. A physical layer including a physical media attachment; a medium access control for controlling access to the physical layer to schedule data transmission / reception;
In a GBIC communication interface device provided with a GBIC module having a physical layer of various standards of bps / 1000 Mbps, operation control of a physical coding sublayer, medium access control, and a GBIC module according to the type of the GBIC module to be connected 10Mbp by performing signal control with the physical layer in the
There is an effect that support for various standards of s / 100 Mbps / 1000 Mbps can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a GBIC communication interface device according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a MAC, a PHY, a GBIC I / F controller, and 10 constituting port # 1 of the interface card of FIG. 1;
It is a block diagram which shows a detailed structure in a 00BASE-T GBIC module.

FIG. 3 is a diagram illustrating a MAC, a PHY, a GBIC I / F controller, and 10 constituting port # 2 of the interface card of FIG. 1;
It is a block diagram which shows a detailed structure in a 00BASE-SX GBIC module.

FIG. 4 shows a MAC, a PHY, a GBIC I / F controller, and a port 10 constituting the port # 3 of the interface card of FIG.
It is a block diagram which shows a detailed structure in / 100BASE-TX GBIC module.

FIG. 5: 100 defined in IEEE 802.3
It is a figure showing the relation of MAC and PHY in 0BASE-X.

FIG. 6: 100 defined in IEEE 802.3
It is a figure which shows the relationship of MAC and PHY in 0BASE-T respectively in FIGS.

FIG. 7 is a diagram illustrating a 10/10 standard defined in IEEE 802.3.
It is a figure showing the relation of MAC and PHY in 100BASE-TX.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Switching hub 2, 3 Interface card 11 Memory 11 12 Console I / O 13 Packet switching mechanism 14 CPU 21, 31 Packet forwarding mechanism 22, 23, 32, 33 MAC 24, 25, 34, 35 PHY 26, 27, 36, 37 GBIC I / F control unit 28 1000BASE-T GBIC module 29 1000BASE-SX GBIC module 38 10 / 100BASE-TX GBIC module 39 1000BASE-SX GBIC module 241,251,341 PCS 242,252,342 PMA 261,271,361 Clock recovery circuit 262, 272, 362 Switch circuit 263, 273, 363 Comparison circuit 264, 274, 364 Signal control circuit 265, 2 5,365 GBIC detection circuit 281,381 GMII bridge portion 282,382 serial-parallel conversion circuit 283,293 parallel-serial conversion circuit 284,291,384 serial ROM 285 1000BASE-T PHY 292 1000BASE-SX PMD 385 10 / 100BASE-TX PHY

Claims (11)

[Claims] A physical coding sub-layer for encoding data to be transmitted in a form suitable for the physical media;
A physical layer including a physical media attachment for serializing and deserializing a packet to be transmitted, a medium access control for controlling access to the physical layer and scheduling data transmission and reception;
GBIC (Gigabit Int) which incorporates physical layers of various standards of bps / 100Mbps / 1000Mbps.
module), control means for controlling the operation of the physical coding sub-layer according to the type of the GBIC module, and the medium access control and physical control within the GBIC module according to the determined type of the GBIC module. A GBIC communication interface device, comprising: signal control means for performing signal control between layers. 2. The GBIC communication interface device according to claim 1, further comprising means for judging a type of said GBIC module to be connected. 3. The signal control means controls a physical layer in the GBIC module from the medium access control through a signal line of transmission disable, transmission failure, and reception loss defined by a GBIC connector. A control data clock, a control data input / output, and a transmission clock of a medium independent interface / gigabit speed medium independent interface signal are connected between the medium access control and a physical layer in the GBIC module. The GBIC communication interface device according to claim 1 or 2, wherein 4. The signal control means according to the type of the GBIC module, controls the GBI of a control data clock, a control data input / output, a transmission clock, and a reception clock.
4. The GBIC according to claim 1, wherein the supply to the C module is controlled.
Communication interface device. 5. The apparatus according to claim 1, wherein said control means controls the physical coding sublayer not to operate when a GBIC module other than a predetermined GBIC module is connected. The GBIC communication interface device according to any one of claims 1 to 4. 6. A transmission data, a transmission enable, a transmission error, a reception data, and a reception enable for linking the medium independent interface / gigabit speed medium independent interface signal of the physical layer in the GBIC module to the medium access control. The GB according to any one of claims 3 to 5, wherein a bridge circuit for connecting to a reception error is included in the GBIC module.
IC communication interface device. 7. A physical coding sub-layer for encoding data to be transmitted in a form suitable for the physical media;
A physical layer including a physical media attachment for serializing and deserializing a packet to be transmitted, a medium access control for controlling access to the physical layer and scheduling data transmission and reception;
GBIC (Gigabit Int) which incorporates physical layers of various standards of bps / 100Mbps / 1000Mbps.
module is provided to control the operation of the physical coding sublayer, the medium access control, and the signal control between the physical layer in the GBIC module according to the type of the GBIC module to be connected. A GBIC communication interface system, characterized in that: 8. The method according to claim 1, wherein the medium access control determines the GBIC
Data clock and control of media independent interface / gigabit speed media independent interface signals via transmission disable, transmission failure and reception loss signal lines defined by GBIC connector to control the physical layer in the module 8. The G according to claim 7, wherein data input / output and a transmission clock are connected between the medium access control and a physical layer in the GBIC module.
BIC communication interface method. 9. The supply of a control data clock, a control data input / output, a transmission clock, and a reception clock to the GBIC module according to the type of the GBIC module. The GBIC communication interface system according to claim 8. 10. The physical coding sublayer is controlled so as not to operate when a GBIC module other than a predetermined GBIC module set in advance is connected. The GBIC communication interface system according to any one of the above. 11. A transmission data, a transmission enable, a transmission error, a reception data, and a reception enable for linking the medium independent interface / gigabit speed medium independent interface signal of the physical layer in the GBIC module to the medium access control. The reception error and the GBI
11. The GBIC communication interface system according to claim 8, wherein the connection is made by a bridge circuit in the C module.