JP2002305248A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a DC/DC converter wherein conversion efficiency does not decrease in the case of conversion to at most one-half of a battery voltage, efficiency of a voltage conversion part is at least 90%, and on-chip constitution is easily realized. SOLUTION: A power source unit 200 is equipped with an energy supply circuit 210 for supplying energy at a prescribed timing and an energy storage circuit 220 for receiving the energy supplied the supply circuit 210 and storing the energy. The storing circuit 220 includes an inductor 221, a capacitor 223 which is connected at a connection point 222, with one end of the inductor 221 and a capacitor 225 which is connected, at a connection point 224 with the other end of the inductor 221. The energy is supplied to a load via at least one from among the connection point 222 and the connection point 224.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to a power supply device and a voltage converter suitable for a low-power LSI.

2. Description of the Related Art A circuit for increasing, decreasing, and inverting a DC input voltage value to a different DC output voltage value includes:
There is a DC / DC converter. The DC / DC converter has a higher conversion efficiency and a smaller heat generation amount than the regulator from the viewpoint of the conversion efficiency and the heat generation amount. The volume of the device is smaller than that of a transformer. Because of these characteristics, they are widely used in work stations and personal computers, which have strong requirements for conversion efficiency, heat generation and device volume.

FIGS. 51A and 51B show a conventional DC / DC converter.
3 shows a configuration of a DC converter 61. FIG. 51A shows a portion that steps down the input voltage and outputs it. The voltage of the power supply is applied to the voltage input terminal. The NMOS transistors 50 and 51 are changed between an open state and a closed state according to the pulse signals supplied to the signal input terminal A and the signal input terminal B. NMOS
When the transistor 50 is closed and the NMOS transistor 51 is open, current is supplied to the LC unit. The time change of the supplied current is converted into a voltage by the inductance L, and the voltage of the terminal A increases faster than that of the output terminal. Next, when the NMOS transistor 50 is opened and the NMOS transistor 51 is closed,
Current is emitted from the part C. The output voltage is determined by the ratio between the supplied current and the released current. NM
When the time when the OS transistor 50 is closed is longer than the time when the NMOS transistor 51 is closed, the output voltage increases, and the time when the NMOS transistor 50 is closed is longer than the time when the NMOS transistor 51 is closed. If it is short, the output voltage drops. For example, the time when the NMOS transistor 50 is in the closed state is the time when the NMOS transistor 5 is closed.
Assume that the output voltage is 1.5 V when 1 is equal to the closed state time. If the time when the NMOS transistor 50 is closed is longer than the time when the NMOS transistor 51 is closed, the output voltage becomes a voltage higher than 1.5 V, and the time when the NMOS transistor 50 is closed is NMO.
If the S transistor 51 is shorter than the time in the closed state, the output voltage will be lower than 1.5V.

[0004] As shown in FIG.
A signal indicating the open / close state of the transistors 50 and 51 is
Input from signal input terminals A and B, signal input terminals A and B
Are generated by the pulse generator 55. The cycle and the pulse width of the output pulse of the pulse generator 55 are controlled by the controller 57. The control unit 57 compares the voltage output from the reference voltage generation unit 56 with the voltage at the monitor terminal of the voltage conversion unit 54, and sets the period and pulse width of the pulse signal output from the pulse generation unit to the target voltage of the monitor terminal. Is controlled so that the voltage becomes

[0005] Recently, DC / DC converters have been used in mobile phones and P
It has been proposed to extend the life of lithium-ion batteries by using them in portable devices such as HS. By reducing the output voltage of a lithium ion battery having an output voltage of 3V to around 1V by a DC / DC converter and operating the LSI used in the mobile phone at around 1V, the power consumption of the LSI can be reduced. This is because there is a possibility.

However, in order to extend the life of such a battery, the DC / DC converter needs to simultaneously solve the following problems (1) and (2). (1) Even if the voltage of the battery is converted to half or less, the conversion efficiency should not be reduced.

[0007] The output voltage of a lithium ion battery used in a mobile phone is 3V. In order to reduce the power consumption of the LSI, it is necessary to efficiently reduce the output voltage of the lithium ion battery to 1V. However, if such a step-down is performed using the conventional DC / DC converter 61 (FIG. 51B), the conversion efficiency is reduced. Conventional DC
This is because the power consumption of the control system circuit 58 in the / DC converter 61 is large. For example, when the power supply voltage is 1 V, L
While the power consumption of the SI is about 10 mW, the power consumption of the control system circuit 58 including the pulse generation unit 55, the control unit 57, and the reference voltage generation unit 56 is about 100 mW. As described above, when the power supply voltage is low, the LSI
Control system circuit 5 of DC / DC converter 61
The fact that the power consumption of No. 8 becomes larger is a cause of lowering the conversion efficiency. (2) The efficiency of the voltage converter is 90% or more.

[0008] In the conventional DC / DC converter 61, the efficiency of the voltage converter 54 is reduced by the NMOS transistor 5.
It is generated by the current flowing through 0 and 51. Voltage converter 5
In No. 4, the efficiency is reduced twice for one cycle. This is because in the voltage conversion unit 54, the NMOS transistors 50 and 51 are opened in one cycle.

[0009] Further, the following (3) is given as a problem relating to the on-chip. (3) Easy on-chip implementation.

In the conventional DC / DC converter 61,
The value of the inductor 52 is about 100 μH. But,
It is difficult to form an inductor having such a large value on a silicon substrate. This is because an inductor of at most about 200 nH can be formed on a silicon substrate. If an inductor of about 100 μH is used, radiated electromagnetic noise may cause malfunction of another LSI.

Further, in the conventional DC / DC converter 61, in order to realize a conversion efficiency of 80% or more, the resistance value (ON resistance) in the closed state of the switches 50 and 51 is set to 0.1.
It is necessary to be about 1 mΩ. However, it is difficult to form a switch having such a small on-resistance on a silicon substrate. A switch can be formed on a silicon substrate because the switch has an on-resistance of at most about 500 mΩ. When a switch having an on-resistance of about 500 mΩ is used, the conversion efficiency is reduced to 60% or less.

As described above, the conventional DC / DC converter 61
Then, none of the above-mentioned problems (1) to (3) can be solved.

One of the objects of the present invention is the above (1) to (4).
An object of the present invention is to provide a voltage converter that solves the problem (3) at the same time and realizes high-efficiency voltage conversion even when a small output current is output.

Further, the present invention is a basic invention of a power supply device suitable for a low power LSI. The present invention provides a power supply device characterized by (1) little energy loss, (2) generation of various types of voltage waveforms, and (3) suitable as a power supply for LSI. The purpose is to:

Further, according to the present invention, in a semiconductor integrated circuit including a power supply device including an LC resonance circuit and at least one circuit block to which a power supply voltage is supplied from the power supply device, noise generated by the operation of the LC resonance circuit is reduced. It is an object to provide a semiconductor integrated circuit that can be reduced.

According to a first aspect of the present invention, there is provided a power supply unit for supplying energy at a predetermined timing, receiving the energy supplied from the energy supply unit, and storing the energy. Energy storage means. The energy storage means includes: an inductor; a first capacitor connected to one end of the inductor at a first connection point;
And a second capacitor connected to the other end of the inductor at a connection point of, and the energy is supplied to a load via at least one of the first connection point and the second connection point. .

According to the first aspect of the present invention, a closed system that does not substantially leak energy to the outside of the energy storage means by the inductor, the first capacitance, and the second capacitance included in the energy storage means. It is formed. Since energy does not substantially leak outside the energy storage means, there is almost no energy loss in the power supply device. Thus, a low power consumption type power supply device can be provided.

Further, according to the first aspect of the present invention, the first capacitance and the second capacitance are set to predetermined values, respectively, so that each of the first connection point and the second connection point can be changed. Various types of voltage waveforms can be provided to the load. For example, a DC voltage waveform can be supplied to the load from one of the first connection point and the second connection point. Alternatively, an AC voltage waveform can be supplied to the load from one of the first connection point and the second connection point. Alternatively, a DC voltage waveform is supplied to the load from one of the first connection point and the second connection point, and an AC voltage waveform is supplied to the load from the other of the first connection point and the second connection point. can do. Alternatively, the AC voltage waveform can be supplied to the load from both the first connection point and the second connection point.

In one embodiment, the load is a semiconductor circuit having a structure providing a rectifying action. The power supply device of the present invention according to claim 1 is suitable for supplying power to such a load. This is because the power supply device of the present invention according to claim 1 has a structure in which current does not intensively flow in the load.

In another embodiment, the load is supplied with a DC voltage waveform from one of the first connection point and the second connection point.

In another embodiment, the load is supplied with an AC voltage waveform from one of the first connection point and the second connection point.

In another embodiment, a DC voltage waveform is supplied to the load from one of the first connection point and the second connection point, and the first connection point is connected to the second connection point. An AC voltage waveform is supplied from the other of the points.

In another embodiment, an AC voltage waveform is supplied to the load from one of the first connection point and the second connection point, and the first connection point is connected to the second connection point. An AC voltage waveform is supplied from the other of the points.

In another embodiment, the power supply and the load are formed on a single semiconductor chip.

In another embodiment, at least a portion of the energy provided to the load from the power supply is returned to the power supply for reuse.

In another embodiment, at least a part of the energy supplied to the load from the power supply device supplies the energy to the load among the first connection point and the second connection point. Then, it is returned to the power supply device through the same connection point as that used at the time of connection.

[0027] In another embodiment, at least a part of the energy supplied to the load from the power supply device supplies the energy to the load among the first connection point and the second connection point. Is returned to the power supply device via a connection point different from the connection point used at the time of connection.

A voltage converter according to the present invention converts a first voltage supplied from a power supply to a second voltage, and supplies the second voltage to a voltage supply circuit; A control unit that controls the voltage conversion unit so as to supply power substantially equal to the power consumed by the voltage supply circuit from the power supply to the voltage conversion unit, thereby achieving the above object. You.

In one embodiment, the control section includes a first detector for detecting that the second voltage output from the voltage conversion section has dropped below a desired voltage,
The control unit controls the voltage conversion unit when the first detector detects that the second voltage output from the voltage conversion unit has dropped below the desired voltage.

Another voltage converter of the present invention converts a first voltage supplied from a power supply into a second voltage, and supplies the second voltage to a voltage supply circuit; A voltage converter comprising: a controller configured to control the voltage converter, wherein the voltage converter includes: an inductor; a first capacitor connected to one end of the inductor at a first connection point; A switch having a resonance circuit including a second capacitor connected to the other end of the inductor at a connection point of the first and second terminals, and a first terminal and a second terminal; And the second terminal includes a switch connected to the first connection point of the resonance circuit, and the control unit controls opening and closing of the switch. This achieves the above object.

In one embodiment, the control unit includes a first detector for detecting that the second voltage output from the voltage conversion unit has dropped below a desired voltage,
The control unit controls opening and closing of the switch when the first detector detects that the second voltage output from the voltage conversion unit has dropped below the desired voltage.

In another embodiment, the control unit opens and closes the switch during a period in which the voltage at the first connection point is lower than the first voltage supplied from the power supply and higher than the desired voltage. Control.

[0033] In another embodiment, the control section includes a second detector for detecting that the voltage of the first connection point has reached a predetermined first reference voltage, and the first connection point. And a third detector that detects that the voltage of the first reference voltage has reached a predetermined second reference voltage that is higher than the predetermined first reference voltage. When it is detected that the voltage at the connection point has reached the predetermined first reference voltage, the control unit controls the switch so that the state of the switch changes from an open state to a closed state. When the third detector detects that the voltage of the first connection point has reached the predetermined second reference voltage, the control unit changes the state of the switch from the closed state to the closed state. The switch is controlled to change to an open state.

In another embodiment, the first detector comprises:
The operation starts in synchronization with the operation timing of the voltage supply circuit.

In another embodiment, the control section includes a fourth detector for detecting that the second voltage output from the voltage conversion section has reached a predetermined reference voltage, and a reset section. In response to the signal, the control unit controls the switch so that a state of the switch changes from an open state to a closed state, and the second detector output from the voltage conversion unit by the fourth detector. When it is detected that the voltage has reached the predetermined reference voltage, the control unit controls the switch so that the state of the switch changes from the closed state to the open state.

In another embodiment, the control unit includes a clock signal generator that generates a clock signal in response to a voltage change at the first connection point, wherein the clock signal has a cycle different from a predetermined cycle. And a circuit for outputting the reset signal when detecting the reset signal.

In another embodiment, the control unit further includes a circuit that outputs the reset signal when detecting that the maximum value of the voltage change at the first connection point is smaller than a predetermined reference voltage. ing.

[0038] In another embodiment, the control section further includes a first reference voltage generator for generating the desired voltage, wherein the first reference voltage generator includes the first detector. It operates only during the period during which it operates.

In another embodiment, the control unit further includes a first reference voltage generator for generating the desired voltage, wherein the first reference voltage generator is provided from the voltage supply circuit. The desired voltage is varied according to the transmitted signal.

In another embodiment, the control unit further includes a second detector for detecting that the voltage at the first connection point has reached a predetermined first reference voltage, and
When it is detected by the detector that the voltage at the first connection point has reached the predetermined first reference voltage,
The control unit controls the switch so that a state of the switch changes from an open state to a closed state, and the control unit performs a predetermined time after the state of the switch changes from an open state to a closed state. The switch is controlled so that the state of the switch changes from the closed state to the open state after a lapse of time.

In another embodiment, the control unit controls opening and closing of the switch during a period when the voltage of the first connection point is rising.

In another embodiment, the control unit controls opening and closing of the switch during a period when the voltage of the first connection point is falling.

[0043] In another embodiment, the voltage conversion unit further includes storage means for temporarily storing a return current flowing from the inductor to the power supply through the switch.

Another voltage converter of the present invention is a voltage converter for converting a voltage supplied from a power supply into a desired voltage and supplying the desired voltage to a voltage supply circuit. A voltage converter having a first conversion efficiency; and a second voltage converter having a first conversion efficiency larger than the first conversion efficiency when a current smaller than a predetermined current flows from the voltage converter to the voltage supply circuit. A second voltage converter having a conversion efficiency; and a current detector for detecting a current flowing from the voltage converter to the voltage-supplied circuit, wherein the current detected by the current detector is the predetermined voltage. When the current is larger than the current, the first voltage converter operates, and when the current detected by the current detector is smaller than the predetermined current, the second voltage converter operates. This achieves the above object.

Another voltage converter of the present invention converts a first voltage supplied from a power supply to a second voltage, and supplies the second voltage to a voltage supply circuit; A voltage converter including a controller configured to control the voltage converter, wherein the voltage converter is connected to a first inductor and a first connection point connected to one end of the first inductor at a first connection point. A first resonance circuit including a first capacitor, a second capacitor connected to the other end of the first inductor at a second connection point, and a first terminal having a first terminal and a second terminal. A switch, wherein the first terminal is connected to the power supply;
The second terminal is connected to a first switch connected to the first connection point of the first resonance circuit, a second inductor, and one end of the second inductor at a third connection point. A second resonance circuit including a third capacitor to be connected, a fourth capacitor connected to the other end of the second inductor at a fourth connection point, and a third terminal and a fourth terminal. Wherein the third terminal is connected to the first switch.
A second switch connected to the second connection point of the resonance circuit, and the fourth terminal includes a second switch connected to the third connection point of the second resonance circuit; Controls opening and closing of the first switch and the second switch. Thereby, the above object can be achieved.

Another voltage converter of the present invention converts a first voltage supplied from a power supply to a second voltage and supplies the second voltage to a voltage supply circuit. A voltage converter including a controller configured to control the voltage converter, wherein the voltage converter is connected to a first inductor and a first connection point connected to one end of the first inductor at a first connection point. A first switch having a resonance circuit including a first capacitor, a second capacitor connected to the other end of the first inductor at a second connection point, and a first terminal and a second terminal Wherein the first terminal is connected to the power supply, and the second terminal is a first switch connected to the first connection point of the resonance circuit; a second inductor; And a second switch having a third terminal and a fourth terminal. One end of the second inductor is connected to the second capacitor at a third connection point, and the other end of the second inductor is connected to the second connection point; A modulation resonance circuit, wherein the third terminal of the switch is connected to the power supply, and the fourth terminal of the second switch is connected to the third connection point; Controls opening and closing of the first switch and the second switch. Thereby, the above object can be achieved.

Another voltage converter of the present invention converts a first voltage supplied from a power supply to a second voltage, and supplies the second voltage to a voltage supply circuit; A voltage converter including a controller configured to control the voltage converter, wherein the voltage converter is connected to a first inductor and a first connection point connected to one end of the first inductor at a first connection point. A first switch having a resonance circuit including a first capacitor, a second capacitor connected to the other end of the first inductor at a second connection point, and a first terminal and a second terminal Wherein the first terminal is connected to the power supply, and the second terminal is a first switch connected to the first connection point of the resonance circuit; a second inductor; And a second switch having a third terminal and a fourth terminal. One end of the second inductor is connected to the first connection point, and the other end of the second inductor is connected to the third capacitance at a third connection point; A modulation resonance circuit, wherein the third terminal of the switch is connected to the power supply, and the fourth terminal of the second switch is connected to the third connection point; Controls opening and closing of the first switch and the second switch. Thereby, the above object can be achieved.

A semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit comprising a power supply device including an LC resonance circuit, and at least one circuit block supplied with a power supply voltage from the power supply device, wherein the LC resonance circuit Is set such that in a frequency band used by the at least one circuit block, the intensity of noise determined based on the resonance frequency is equal to or lower than a predetermined value. Thereby, the above object is achieved.

[0049] The power supply device and the at least one circuit block may be formed on a single semiconductor chip.

[0050] The power supply device and the at least one circuit block may be formed on different semiconductor chips.

[0051] The power supply may supply a DC voltage to the at least one circuit block.

[0052] (BEST MODE FOR CARRYING OUT THE INVENTION) 1. The basic principle view 1 of a power supply device according to the invention, showing a configuration of a power supply device 200 according to the present invention. The power supply device 200 includes an energy supply circuit 210 and an energy storage circuit 220.

The energy supply circuit 210 supplies energy to the energy storage circuit 220 at a predetermined timing. The energy supplied from the energy supply circuit 210 can be any type of energy. For example,
The energy supplied from the energy supply circuit 210 is electric energy (electric power), light energy, magnetic energy, and radiation energy.

The energy storage circuit 220 receives the energy supplied from the energy supply circuit 210,
Conserve that energy. Energy storage circuit 220
Is a capacitor 223 connected to one end of the inductor 221 at the connection point 222,
24 includes a capacitor 225 connected to the other end of the inductor 221. Here, L is the inductor 221
, C ₁ indicates the capacitance value of the capacitance 225, and C ₂ indicates the capacitance value of the capacitance 223.

The energy stored in the energy storage circuit 220 is supplied to a load (not shown in FIG. 1) via at least one of the connection points 222 and 224.

The power supply device 200 and the load may be formed on a single semiconductor chip. As will be described later, a relatively small value is sufficient for the inductor used in the power supply device 200. For example, the value of such an inductor is 10
It is about 0 nH. Therefore, it is easy to form the power supply device 200 on the silicon substrate.

The power supply device 200 has the following (1) to (3)
It has the following characteristics. (1) There is almost no energy loss in the power supply device 200. (2) The power supply device 200 can generate various types of voltage waveforms. (3) The power supply device 200 is suitable as a power supply for an LSI. Feature 1: As shown in FIG. 1 with almost no energy loss , the capacitor 223 is provided with an electrode plate 223-1.
And an electrode plate 223-2. The pole plate 223-1 and the pole plate 223-2 are electrically insulated from each other. The electrode plate 223-1 is connected to the connection point 222, and the electrode plate 222-2
Is connected to the ground. Similarly, the capacity 225 is
It has an electrode plate 225-1 and an electrode plate 225-2. Electrode 225-1 and electrode 225-2 are electrically insulated from each other. The electrode plate 225-1 is connected to the connection point 224,
The electrode plate 225-2 is connected to the ground.

The energy supplied from the energy supply circuit 210 generates charges in a closed system from the electrode 223-1 of the capacitor 223 to the electrode 225-1 of the capacitor 225 via the inductor 221. The charges generated in this way cannot move out of the closed system. The electrode plate 223-1 and the electrode plate 223-2 are electrically insulated from each other.
-2 has no path for the charge to move, and the electrode plate 225-1 and the electrode plate 225-2 are electrically insulated from each other.
This is because there is no path for the charge to move from the electrode plate 225-1 to the electrode plate 225-2.

Thus, the amount of charge in a closed system is kept constant. This means that the energy storage circuit 22
At 0 means that the amount of static energy is kept constant. Static energy is represented by the amount of charge in the closed system. The amount of static energy stored in the energy storage circuit 220 is ・ ·
It is represented by (q ₁ + q ₂ ) ² / (C ₁ + C ₂ ). Here, q ₁ represents the amount of charge stored in the capacitor 225, and q ₂ represents the amount of charge stored in the capacitor 223. In other words,
The static energy can be said to be the energy of the closed system when the terminal included in the closed system does not change in voltage and becomes constant.

FIGS. 2A to 2E show the energy storage circuit 2.
At 20 the dynamic energy is reduced to capacity 223 and capacity 225.
And is kept constant while circulating through the inductor 221. The state of the dynamic energy in the energy storage circuit 220 is shown in FIG.
The state shown in FIG. 2A changes to the state shown in FIG.
The state shown in FIG. 2E transitions to the state shown in FIG. 2A. Thereafter, such a state change is repeated.

The dynamic energy is classified into energy stored in the inductor 221 and energy based on a difference in electric charge (potential difference) between the capacitors 223 and 225. 2A to 2E, E _M1 is an inductor 22
1 indicates energy stored therein, and E _M2 indicates energy based on a difference in electric charge (potential difference) between the capacitors 223 and 225. (E _M1 + E _M2 ) is kept constant. E
_M1 is a ^{_{= 1/2 · Li 1 2}} . Here, i ₁ represents a current flowing through the inductor 221. E _M2 = | 1/2 · q ₁ ² / C
^{_{1 -1/2 · q 2 2 / C}} 2 | is. Here, q ₁ is capacity 2
25 represents the amount of charge stored in the storage device 25, and q ₂ represents the amount of charge stored in the capacitor 223. In other words, the dynamic energy is energy that can vibrate, or move, the voltage of the terminals included in a closed system.

The energy E _M1 stored in the inductor 221 acts to move charges from the capacitor 223 to the capacitor 225 (or from the capacitor 225 to the capacitor 223). Therefore, the capacitance 223 is maintained until the energy E _M1 stored in the inductor 221 becomes zero.
From the capacitor 225 (or from the capacitor 225 to the capacitor 223).

When the energy E _M1 stored in the inductor 221 is zero, the energy E _M2 based on the difference (potential difference) in the amount of charge between the capacitors 223 and 225 becomes maximum. Therefore, the movement of the charge is started in a direction to eliminate the difference (potential difference) in the charge amount between the capacitor 223 and the capacitor 225. As the electric charges pass through the inductor 221, energy E _M1 is stored in the inductor 221.
Hereinafter, such a process is repeated.

As described above, the energy storage circuit 220
Keeps static and kinetic energy substantially constant. In other words, static energy and dynamic energy do not substantially leak out of the energy storage circuit 220. Here, “substantially” means the capacity 2
In the sense that there is no energy leakage, except for unintended energy leakage such as leakage of static energy due to leakage current flowing between the plates 23 and 225 and dynamic energy leakage due to attenuation based on the resistance of the inductor 221. is there. This means that there is almost no energy loss in the power supply device 200. This makes it possible to provide a low power consumption type power supply device. Feature 2: Various types of voltage waveforms can be generated
C ₁ by setting the capacitance values of the capacitance 225 of the capacitance 223 so as to satisfy the relationship >> C ₂ that, to produce a DC voltage waveform at the node 222 alternating-current voltage waveform at the connection point 224 Can be. Such a voltage waveform is obtained based on resonance in the energy storage circuit 220. The mathematical basis for the voltage waveform will be described later with reference to (Equation 1) to (Equation 17).

By setting the capacitance value of the capacitor 223 and the capacitance value of the capacitor 225 so as to satisfy the relationship of C ₁ ≒ C ₂ , the AC voltage waveform can be changed at any of the connection points 222 and 224. Can be generated.

Further, of the energy supplied from the energy supply circuit 210, the ratio between the energy stored in the energy storage circuit 220 as static energy and the energy stored in the energy storage circuit 220 as dynamic energy is adjusted. This makes it possible to arbitrarily set the amplitude center of the AC voltage waveform and the amplitude of the AC voltage waveform. This is because the static energy determines the oscillation center of the AC voltage waveform, and the dynamic energy determines the amplitude of the AC voltage waveform.

FIG. 3 shows an example of the AC voltage waveform at the node 222 in the case of C ₁ >> C ₂ . Thus, by providing the dynamic energy E _M static energy E _S appropriately, the oscillation center is voltage V _P, and can be amplitude obtaining an AC voltage waveform is 1 / 2V _DD . Note that the voltage at node 222 is always higher or equal to the ground voltage.

If C ₁ >> C ₂ , the connection point 222
Can be approximated to a sine wave that oscillates at a period T ₀ = 2π (√LC ₂₎ . Therefore, the product (LC ₂ ) of the inductance L of the inductor 221 and the capacitance value C ₂ of the capacitor 223 is made variable. Thus, the period T ₀ of the voltage waveform at the connection point 222 can be adjusted to an arbitrary value.LC ₂ is adjusted to a predetermined value before the operation of the power supply device 200, and during the operation of the power supply device 200, Alternatively, the LC ₂ may be dynamically controlled by a control circuit during the operation of the power supply 200. For example, the control circuit may switch from the energy supply circuit 210 to the energy storage circuit. The LC ₂ is controlled such that the period T ₀ becomes longer as the energy supplied to the energy supply 220 decreases, and the energy supplied from the energy supply circuit 210 to the energy storage circuit 220 is controlled. The LC ₂ is controlled so that the period T ₀ becomes shorter as the energy becomes larger.By controlling the period T _{0 in} this manner, as the energy supplied from the energy supply circuit 210 to the energy storage circuit 220 increases, It is possible to increase the number of times that the voltage at the node 222 approaches the power supply voltage V _DD per unit time, so that the period when the voltage at the node 222 approaches the power supply voltage V _DD (period T _{A in} FIG. 3). By controlling the timing of the energy supply so that the energy is supplied from the energy supply circuit 210 to the energy storage circuit 220, the energy loss generated when the energy is supplied from the energy supply circuit 210 to the energy storage circuit 220 is reduced. Connection point 2 can be minimized
This is because supplying energy from the energy supply circuit 210 to the energy storage circuit 220 is the most efficient energy supply during a period when the voltage of the power supply 22 is close to the power supply voltage V _DD (period T _{A in} FIG. 3).

Further, by making L and C ₂ variable under the condition that LC ₂ is kept constant, the static energy included in the energy supplied from the energy supply circuit 210 can be maintained without changing the period T _0. The ratio between the dynamic energy E _S and the dynamic energy E _M can be adjusted. By increasing the capacitance C ₂ of the capacitor 223 and decreasing the inductance L of the inductor 221,
In addition, the energy (static energy) stored in the capacitor 225 can be increased, and the energy (dynamic energy) stored in the inductor 221 can be reduced.
Conversely, by decreasing the capacitance value C ₂ of the capacitance 223 and increasing the inductance L of the inductor 221, the energy (static energy) stored in the capacitance 223 and the capacitance 225 is reduced, and is stored in the inductor 221. Energy (dynamic energy) can be increased.

The example of adjusting the capacitance value C ₂ and the inductance L has been described above. Further, the capacitance value C ₁ and the capacitance value C ₂
And by adjusting the inductance L, it can be further adjusted in detail the ratio between the static energy E _S and the dynamic energy E _M.

For example, it is assumed that the current i ₀ flows from the connection point 222 by the energy supply circuit 210.
The current flowing into the capacitor 223 of the current i ₀ is defined as a current i ₁ , and the current flowing into the capacitor 225 of the current i ₀ is defined as a current i ₂
And The ratio between the current i ₁ and the current i ₂ can be set to an arbitrary value by adjusting the capacitance value C ₁ , the capacitance value C ₂ and the inductance L. Energy stored in the capacitors 223 and 225 (static energy)
Is represented by _{1/2 · (q 1 +} q 2) 2 / (C 1 + C 2), the energy stored in the inductor 221 (dynamic energy) is represented by ^_1/2 · Li 1 2. Here, q ₁ represents the amount of charge stored in the capacitor 225, and q ₂
Represents the amount of charge stored in the capacitor 223. Therefore, by adjusting the ratio between the current i ₁ and the current i ₂ , the capacitance 22
3 and the energy (static energy) stored in the capacitor 225 and the energy (dynamic energy) stored in the inductor 221 can be adjusted.

As described above, the ability to freely control the oscillation center and amplitude of the AC voltage waveform is suitable for charging a capacitive load utilizing the "adiabatic charging principle". "Principle of adiabatic charging" is a principle relating to charging a capacitive load using an AC voltage waveform. According to the principle of adiabatic charging, it is known that charging the capacitive load over a longer period of time can reduce the energy loss associated with the charging.

FIG. 4A shows an AC voltage waveform (A) oscillating between the power supply voltage V _DD and the ground voltage GND in the period T ₀ .
And an AC voltage waveform (B) that oscillates between the power supply voltage V _DD and the voltage −V _DD in the cycle T ₀ . Power supply voltage V
When performing adiabatic charging from _DD up to the ground voltage GND, the length of the adiabatic charging period T _A of the AC voltage waveform (A) is adiabatic charging period T 2 the length of _B of the alternating-current voltage waveform (B)
It is twice. Therefore, it is understood that performing adiabatic charging using the AC voltage waveform (A) is advantageous in that energy loss is small. The same applies to the case where adiabatic charging is performed from the ground voltage GND to the power supply voltage _VDD .

[0074] Figure 4B is an AC voltage waveform which oscillates between the power supply voltage V _DD and the voltage 1 / 2V _DD in the cycle T ₀ (A), in the period T ₀ of the power supply voltage V _DD and the voltage -V _DD The AC voltage waveform (B) that oscillates between them is shown in comparison. When the power supply voltage V _DD performing adiabatic charging up to the voltage 1 / 2V _DD, the length of the adiabatic charging period T _A of the AC voltage waveform (A) is adiabatic charging period T _E of the AC voltage waveform (B) About four times the length of Therefore, it is understood that performing adiabatic charging using the AC voltage waveform (A) is advantageous in that energy loss is small. The same applies to the case where adiabatic charging is performed from the voltage 電源_VDD to the power supply voltage _VDD .

Further, comparing FIG. 4A and FIG. 4B,
It can be seen that a smaller amplitude of the AC voltage waveform is more effective in performing adiabatic charging. Feature 3: Consider a case where an LSI is connected as a load to a connection point 222 of a power supply device 200 suitable as a power supply for the LSI . LSI always includes a parasitic diode. In this specification, a parasitic diode is defined as a semiconductor circuit having a structure that provides a rectifying action. For example, the inrush current generated outside the LSI
The protection diode provided to protect the inside of I is a parasitic diode. When the LSI uses a bipolar transistor, for example, a parasitic diode is formed between the base and the emitter and between the base and the collector. When the LSI uses MOS transistors,
For example, a parasitic diode is formed between the source and the well and between the drain and the well.

FIG. 5 shows an LS including a parasitic diode 250.
4 shows an equivalent circuit when I is connected to the connection point 222 of the power supply device 200. The voltage at the connection point 222 is the ground voltage GN
When it becomes lower than D, a forward current flows through the parasitic diode 250. Thereby, power is consumed in parasitic diode 250. As a result, energy loss occurs. Further, when a forward current flows through the parasitic diode 250, the parasitic diode 250 may be destroyed. This is because the energy stored in the inductor 221 may be intensively consumed by the parasitic diode 250.

On the other hand, the power supply device 200 according to the present invention
According to the above, as described in the feature 2, the AC voltage waveform can be controlled such that the voltage at the connection point 222 is always higher or equal to the ground voltage GND. Under such control, no forward current flows through the parasitic diode 250. Therefore, no energy loss occurs due to the parasitic diode 250 included in the LSI.

Further, even if a forward current flows through the parasitic diode 250, the parasitic diode 25
No destruction of zero. This is because the dynamic energy stored in the inductor 221 is converted into static energy and stored in the energy storage circuit 220.

Conventionally, LSIs are integrated by integrating digital circuits, SRAMs (static random access memories) and ROMs (read only memories).
Was usually formed. In recent years, flash
There is a tendency to form an LSI by integrating a memory, a DRAM (Dynamic Random Access Memory), and analog circuits ranging from high frequency to low frequency.
It is expected that such trends will become even stronger in the future, and that in ten years it will enter the era of new integrated circuits. In order for each circuit block of such an integrated circuit to operate in a higher control region, a power supply that generates various voltages required by each circuit block with high efficiency is required. This is because a higher system operation of the integrated circuit can be realized by reducing the power consumption of various types of circuit blocks. In addition, low noise characteristics can be obtained in a predetermined frequency range.

The power supply device of the present invention realizes, as a single power supply, conversion of dynamic energy to static energy with high efficiency, and supply of AC power and DC power to a load with high efficiency. By combining a plurality of such single power supply power supplies, a multi-power supply power supply can be obtained. A multiple power supply generates a plurality of power supply voltages. The multiple power supply may be a combination of a plurality of power supplies of the same type, or may be a combination of a plurality of power supplies of different types.

FIG. 6A shows the configuration of the energy supply circuit 210. The energy supply circuit 210 supplies electric energy (electric power) to a connection point 222 of the energy storage circuit 220.
Supply. The energy supply circuit 210 is connected to the connection point 22.
2 is connected to the energy storage circuit 220.

Energy supply circuit 210 shown in FIG. 6A
Are a DC power supply 211 and a connection point 222 with the DC power supply 211.
And a switch 212 provided between them.

When the switch 212 is turned on, the electric charge from the DC power supply 211 is supplied to the energy storage circuit 220 via the switch 212. By controlling the timing at which the switch 212 is turned on, the charge from the DC power supply 211 is stored at a predetermined timing.
0 can be supplied.

An AC power supply may be used in place of the DC power supply 211. By switching the power from the AC power supply at a predetermined timing, the AC power supply can be regarded as a DC power supply.

Further, a power supply for supplying a voltage having a pulse-like waveform may be used instead of the DC power supply 211. The magnitude of the power supplied from such a power source is, for example,
It can be controlled by pulse width modulation. If such a power supply is used, the switch 212 becomes unnecessary.

FIG. 6B shows another configuration of the energy supply circuit 210. The energy supply circuit 210 supplies magnetic energy to the inductor 221 of the energy storage circuit 220. The energy supply circuit 210 and the energy storage circuit 220 are non-contact.

The energy supply circuit 210 shown in FIG. 6B
Includes an inductor 214 and an AC power supply 215. When a current flows through the inductor 214 of the energy supply circuit 210, a magnetic field is generated, and the magnetic field causes a current to flow through the inductor 221 of the energy storage circuit 220. The dynamic energy is accumulated in the inductor 221 by the current flowing through the inductor 221. As described above, the magnetic energy supplied from the energy supply circuit 210 is received by the inductor 221 of the energy storage circuit 220 and stored in the energy storage circuit 220 as dynamic energy.

FIG. 6C shows another configuration of the energy supply circuit 210. The energy supply circuit 210 supplies light energy to at least one of the capacitors 223 and 225 of the energy storage circuit 220. The energy supply circuit 210 and the energy storage circuit 220 are non-contact.

The energy supply circuit 210 shown in FIG. 6C
Includes a light emitting circuit 216 that emits light. Capacity 2
At least one of the capacitor 23 and the capacitor 225 has a function of converting received light into electricity. As described above, the light energy supplied from the energy supply circuit 210 is received by the capacitor 223 (or the capacitor 225) of the energy storage circuit 220 and stored in the energy storage circuit 220 as static energy. For example, the capacitor 223 (or the capacitor 225) may be a photodiode or a solar cell.

FIG. 6D shows another configuration of the energy supply circuit 210.

Energy supply circuit 210 shown in FIG. 6D
Is a power supply 211, a switch 212, and a switch 212.
a, an inverter 212b, and a capacitor 212c.

In the energy storage circuit 220, generally, when the voltage at the node 222 rises, a current flows from the capacitor 225 to the capacitor 223 through the inductor 221. When the switch 212 is turned on while such a current is flowing, a current flows temporarily from the inductor 221 to the power supply 211 through the switch 212. Here, this current is called "return current"
I will call it. The return current is stored in the power supply 211. However, the power supply 211 is not an energy storage type power supply (for example, a power supply in which an output stage generally absorbs current and passes it to ground) or a power supply having a large parasitic internal resistance as represented by a battery or the like. (For example, lithium ion battery), the energy loss is large. This is because in a power supply that is not an energy storage type, the return current is discarded to the ground through the power supply 211, and in a battery, energy is lost due to parasitic internal resistance.

The switch 212a and the capacitor 212c are provided to prevent a return current from flowing into the power supply 211. The switch 212a includes a power supply 211 and a switch 2
12 is provided. The capacitor 212c is connected to a connection point 212 between the switch 212a and the switch 212.
d. Capacity 212c has a capacitance value C _0.

When the switch 212 is on, the switch 212a is off. in this case,
The return current is stored in the capacitor 212c. In this way, energy is stored in the capacitor 212c. Capacity 21
2c is stored in the energy storage circuit 2
20.

When the switch 212 is off, the switch 212a is turned on. as a result,
A current flows from the power supply 211 to the capacitor 212c,
The voltage of c becomes equal to the power supply voltage V _DD .

The inverter 212b is used to turn on and off the switch 212 and the switch 212a alternately. By turning on and off the switch 212 and the switch 212a alternately, the above-described operation is repeated.

FIG. 58A shows another configuration of the energy supply circuit 210.

Energy supply circuit 210 shown in FIG. 58A
Is a power supply 211, a switch 212, and a switch 212.
a and a capacitor 212c. The capacity 212c is
The return current is temporarily stored.

FIG. 58B shows a voltage change (waveform (A)) at node 222 and a voltage change (waveform (B)) at node 224.

At time t ₁ , the comparator 272a
Detects that the voltage at the node 222 has reached the power supply voltage V _DD , and outputs a detection signal to the control circuit 271a. The control circuit 271a responds to the detection signal by
2a is changed from the off state to the on state.

When a return current exists, the voltage at the node 222 increases toward a voltage higher than the power supply voltage V _DD during the period from time t ₁ to time t ₂ . Such a change in voltage indicates that a return current flows from the connection point 222 to the capacitor 212c, and the return current is temporarily stored in the capacitor 212c.

At time t ₂ , the voltage at the node 222 reaches the highest point, and thereafter, the voltage at the node 222 starts to drop.

In the period from time t ₂ to time t ₃ , the capacitance 21
From 2c, current starts to flow to the energy storage circuit 220.

At time t ₃ , comparator 272a
Detects that the voltage at the node 222 has reached the power supply voltage V _DD again, and outputs a detection signal to the control circuit 271a. The control circuit 271a changes the switch 212a from the on state to the off state in response to the detection signal.

At time t ₃ , control circuit 27
1 changes the switch 212 from the off state to the on state. Thereafter, the switch 212 is kept on until time t _4. Energy is supplied from the power supply 211 to the energy storage circuit 220 via the switch 212 while the switch 212 is on.

As described above, the return current is temporarily stored in the capacitor 212c without returning to the power supply 211. 2. Adjusting the Ratio of Dynamic Energy to Static Energy When the energy supply circuit 210 has the configuration shown in FIG. 6A, it is supplied to the energy storage circuit 220 by controlling the timing at which the switch 212 is turned on. The ratio of dynamic energy to static energy can be adjusted.

The period during which the switch 212 is turned on is classified into the following four periods in consideration of the magnitude of the voltage v at the connection point 222 and the direction of the current i ₁ flowing through the inductor 221. Here, the current i ₁ in the case where the connection point 224 current i ₁ flows in a direction towards the connection point 222 has a positive value, when the current i ₁ flows in a direction towards the connection point 224 from the node 222 It is assumed that the current i ₁ has a negative value.

Period I: A period in which the difference between the power supply voltage V _DD and the voltage v is smaller than a predetermined voltage V _TH and the current i ₁ has a positive value.

Period II: A period in which the difference between the power supply voltage V _DD and the voltage v is smaller than a predetermined voltage V _TH and the current i ₁ has a negative value.

Period III: A period in which the difference between the power supply voltage V _DD and the voltage v is larger than the predetermined voltage V _TH and the current i ₁ has a positive value.

Period IV: A period in which the difference between the power supply voltage V _DD and the voltage v is larger than a predetermined voltage V _TH and the current i ₁ has a negative value.

FIG. 7A shows a relationship between the periods I to IV, the waveform of the voltage v, and the waveform of the current i ₁ . The waveform of the voltage v is a sine waveform that oscillates around a predetermined voltage _VTH . Current i ₁
Is a sine waveform that oscillates around zero.

In order to minimize the energy loss that occurs when supplying energy from the energy supply circuit 210 to the energy storage circuit 220, it is necessary to turn on the switch 212 when the voltage between the terminals of the switch 212 is as small as possible. It is said. This is the principle of adiabatic charging, which minimizes the voltage applied to the resistor between the power supply and the capacitor when charging the capacitor, thereby minimizing the energy loss due to the resistance. based on. Therefore, in order to minimize energy loss, it is preferable that the switch 212 be turned on in the period I or the period II in which the difference between the power supply voltage V _DD and the voltage v is small.

The ratio between the dynamic energy and the static energy supplied to the energy storage circuit 220 in the period I and the period II will be described below.

FIG. 7B shows that the inductor 22
1 shows the current i ₂ flowing through the current i ₁ and a switch 212 flows, Figure 7C shows the timing for turning on the switch 212 in the period I.

As shown in FIG. 7B, in period I, current i ₁ flows in the direction opposite to the direction of current i ₂ . As a result, the current i ₂ is larger than the inductor 221 by the capacitance 223.
A lot flows toward. This means that during period I,
This means that more static energy is supplied to the energy storage circuit 220 than dynamic energy. This is because kinetic energy is mainly generated by the current flowing through the inductor 221.

FIG. 7D shows the state of inductor 2 in period II.
Current i ₂ flowing through the current i ₁ and the switch 212 through the 21
FIG. 7E shows the switch 212 in the period II.
Shows the timing at which is turned on.

As shown in FIG. 7D, in period II, current i ₁ flows in the same direction as current i ₂ .
As a result, the current i ₂ is more than the capacity 223 of the inductor 22.
It flows a lot toward 1. This means that the energy storage circuit 220 is supplied with more dynamic energy than static energy in the period II. This is because kinetic energy is mainly generated by the current flowing through the inductor 221.

As described above, by selecting one of the periods I and II as the timing for turning on the switch 212, the dynamic energy and the static energy supplied from the energy supply circuit 210 to the energy storage circuit 220 are selected. The ratio can be adjusted. 3. The detected energy storage circuit 220 for the dynamic energy and the static energy stores the dynamic energy and the static energy. Depending on the nature of the load connected to the energy storage circuit 220 (ie, strong capacitive or strong resistive), the amount of dynamic energy consumed by the load and the static energy consumed by the load The amount of strategic energy fluctuates.

In order to keep the amount of dynamic energy and static energy stored in the energy storage circuit 220 constant, the amount of decrease in dynamic energy and the amount of decrease in static energy are detected separately, From the energy supply circuit 210 to the energy storage circuit 2 according to the amount of energy reduction
It is necessary to supply energy to the energy storage circuit 20 and supply energy from the energy supply circuit 210 to the energy storage circuit 220 in accordance with the amount of decrease in static energy.

Hereinafter, detection of dynamic energy and static energy and supply of dynamic energy and static energy based on the detection will be described. Here, it is assumed that the energy supply circuit 210 has a configuration shown in FIG. 6A. However, the method of detecting and supplying dynamic energy and static energy described below
The energy supply circuit 210 has another configuration (for example, FIG. 6B
Or the configuration shown in FIG. 6C).

FIG. 8 shows a configuration of a power supply device 1301 having a function of detecting dynamic energy and static energy. The load 370 is connected to the power supply 1
301. Load 370 includes at least one of a capacitance component and a resistance component.

The power supply device 1301 comprises an energy supply circuit 210 and an energy storage circuit 220 which are basic components.
In addition, the control circuit 271 and the reference voltage generation circuit 371
To 374, comparators 375 to 379, and a clock signal generation circuit 380.

The capacitance value C ₁ and the capacitance value C ₂ are set so as to satisfy the relationship of C ₁ >> C ₂ . As a result, an AC voltage waveform is obtained at the connection point 222 and the connection point 224 is obtained.
A DC voltage waveform is obtained.

FIG. 9A shows an AC voltage waveform (A ′) in comparison with the AC voltage waveform (A). Here, the AC voltage waveform (A) represents a change with respect to time of the voltage of the connection point 222 when the dynamic energy stored in the energy storage circuit 220 is kept constant, and the AC voltage waveform (A ′). ) Indicates the connection point 2 when the dynamic energy stored in the energy storage circuit 220 decreases.
22 shows the change of the voltage 22 with respect to time. As shown in FIG. 9A, when the dynamic energy stored in the energy storage circuit 220 decreases, the vibration center of the AC voltage waveform at the connection point 222 does not change, and the vibration amplitude decreases.

FIG. 9B shows an AC voltage waveform (A ′) in comparison with the AC voltage waveform (A). Here, the AC voltage waveform (A) represents a change with time of the voltage of the node 222 when the static energy stored in the energy storage circuit 220 is kept constant, and the AC voltage waveform (A ′). ) Indicates the connection point 2 when the static energy stored in the energy storage circuit 220 decreases.
22 shows the change of the voltage 22 with respect to time. As shown in FIG. 9B, when the static energy stored in the energy storage circuit 220 decreases, the oscillation center of the AC voltage waveform at the connection point 222 shifts.

FIG. 10A shows a procedure of processing for detecting dynamic energy. This process is executed by the control circuit 271 (see FIG. 8) at predetermined time intervals. Where V _A
Represents the voltage at the connection point 222, V _P , V _r1 , V _r2
And V _r3 represent reference voltages output from the reference voltage generation circuits 371 to 374, respectively, and V _DD represents a power supply voltage. These voltages satisfy the relationship of V _P <V _r3 <V _r2 <V _r1 <V _DD . Further, a clock signal having the same cycle as the AC voltage waveforms (A) and (A ′) is generated by the clock signal generation circuit 380 (see FIG. 8).
The waveform of the clock signal is shown in FIG. 9A.

In step S11, it is determined whether or not the voltage _VA has _{exceeded the} voltage _Vr3 while the voltage _VA is increasing. That the voltage V _A is the voltage V _A has exceeded the voltage V _r3 while rising, the output signal of the comparator 379 is detected by changes from L level to H level. If the voltage V _A voltage V _A during the ascent exceeds the voltage V _r3, the processing step S
Proceed to 12.

In step S12, it is determined whether or not the voltage _VA has _{exceeded the} voltage _Vr1 while the voltage _VA is increasing. That the voltage V _A is the voltage V _A has exceeded the voltage V _r1 while rising, the output signal of the comparator 376 is detected by changes from L level to H level. If the voltage V _A is the voltage V _A during the ascent exceeds the voltage V _r1, the process terminates without supplying dynamic energy from the energy supplying circuit 210 to the energy preserving circuit 220. Energy storage circuit 22 so that dynamic energy must be supplied
This is because it is determined that the dynamic energy stored at 0 has not decreased.

On the other hand, while the voltage _VA is increasing, the voltage _VA is
_{If the} falling edge of the clock signal is detected without exceeding _r1 (step S13), it is determined that dynamic energy needs to be supplied from the energy supply circuit 210 to the energy storage circuit 220. This is because the voltage _VA cannot reach the voltage _Vr1 until the next cycle of the AC voltage waveform (A ′). Therefore, in this case, the process proceeds to step S14.

In step S14, it is determined whether or not the voltage _VA has dropped below the voltage _Vr2 while the voltage _VA has fallen. The fact that the voltage _VA has dropped below the voltage _Vr2 while the voltage _VA has fallen means that:
It is detected when the output signal of the comparator 378 changes from H level to L level. If the voltage V _A is the voltage V _A falls below the voltage V _r2 while descending, the control circuit 2
71 turns on the switch 212 (step S1)
5).

In step S16, it is determined whether or not the voltage _VA has dropped below the voltage _Vr3 while the voltage _VA has fallen. The fact that the voltage _VA has dropped below the voltage _Vr3 while the voltage _VA has fallen means that:
It is detected when the output signal of the comparator 379 changes from H level to L level. If the voltage V _A is the voltage V _A falls below the voltage V _r3 while descending, the control circuit 2
71 turns off the switch 212 (step S1).
7).

As described above, when the dynamic energy stored in the energy storage circuit 220 decreases, the switch is turned on during the period T ₁ near the power supply voltage V _DD and the voltage _VA is falling. 212 is turned on. Thus, dynamic energy can be supplied from the energy supply circuit 210 to the energy storage circuit 220.

FIG. 10B shows a procedure of processing for detecting static energy. This process is executed by the control circuit 271 (see FIG. 8) at predetermined time intervals. Where V _A
Represents the voltage at the connection point 222, V _P , V _r1 , V _r2
And V _r3 represent reference voltages output from the reference voltage generation circuits 371 to 374, respectively, and V _DD represents a power supply voltage. These voltages satisfy the relationship of V _P <V _r3 <V _r2 <V _r1 <V _DD .

[0135] In the step S21, the period than the period T ₁ T ₂
Is determined to be small. Here, the period T ₁ is defined as the time required from the time when the voltage V _A along the AC voltage waveform (A) exceeds the voltage V _P to the next below voltage V _P. Period T ₂ are defined as the time required from the time when the voltage V _A along the AC voltage waveform (A ') exceeds the voltage V _P to the next below voltage V _P. The period T ₁ and the period T ₂ are obtained by the control circuit 271 by measuring the time from the time when the output signal of the comparator 375 changes from the L level to the H level to the time when the output signal changes from the H level to the L level.

[0136] If it is determined that the period T ₂ from the time T ₁ is small, it is determined that it is necessary to supply the static energy to the energy preserving circuit 220 from the energy supplying circuit 210. Therefore, in this case, the processing is performed in step S
Proceed to 22.

In step S22, it is determined whether or not the voltage _VA has _{exceeded the} voltage _Vr3 while the voltage _VA is increasing. That the voltage V _A is the voltage V _A has exceeded the voltage V _r3 while rising, the output signal of the comparator 379 is detected by changes from L level to H level. If the voltage V _A is the voltage V _A has exceeded the voltage V _r3 while rising, the control circuit 271
Turns on the switch 212 (step S23).

In step S24, it is determined whether or not the voltage _VA has _{exceeded the} voltage _Vr2 while the voltage _VA is increasing. That the voltage V _A is the voltage V _A has exceeded the voltage V _r2 to the rise, the output signal of the comparator 378 is detected by changes from L level to H level. If the voltage V _A is the voltage V _A has exceeded the voltage V _r2 while rising, the control circuit 271
Turns off the switch 212 (step S25).

As described above, the energy storage circuit 220
If the stored static energy decreases,
Source voltage V_DDAnd the voltage V_AIs rising
Interval T_ThreeIn, the switch 212 is turned on. this
Saves energy from the energy supply circuit 210
Circuit 220 can be supplied with static energy. 4. Adjustment of dynamic energy FIG. 11A shows the operation stored in the energy storage circuit 220.
Power supply 13 having a function of adjusting the amount of static energy
02 shows the configuration of the second embodiment. The load 390 is located at the connection point 224.
Connected to the power supply 1302. The load 390 is
At least one of a capacitance component and a resistance component is included.

The power supply device 1302 includes an energy supply circuit 210 and an energy storage circuit 220 which are basic components.
, A control circuit 271, a comparator 272,
Reference voltage generation circuit 273 is further included.

When the dynamic energy is excessively supplied to the energy storage circuit 220, the oscillation amplitude of the AC voltage waveform at the connection point 222 increases. The power supply device 1302 aims to reduce the oscillation amplitude of the AC voltage waveform at the connection point 222 when the voltage at the connection point 222 becomes equal to or lower than the ground voltage GND.

The energy storage circuit 220 includes the element 39
1 is provided. The element 391 is connected to the connection point 222. The element 391 is, for example, a diode having a cathode as a terminal a and an anode as a terminal b (see FIG. 11B). The diode may be a Schottky barrier diode. Alternatively, element 391
Is a PMO in which a gate is connected to a source with a drain as a terminal a, a source as a terminal b, a well as a power supply V _DD ,
It may be an S transistor (see FIG. 11C). Threshold V _T of such a PMOS transistor, may be lower or higher.

FIG. 11D shows an AC voltage waveform (A) at the connection point 222.

In the case where the diode shown in FIG. 11B is used as the element 391, when the voltage at the node 222 becomes lower than the ground voltage GND, the diode is forward biased. As a result, the ground voltage GND by the forward voltage V _T of the diode lowered voltage to the connection point 22
2 voltage is fixed (e.g., the period of FIG. 11D t ₃ ~
see t _4). Since the diode is forward biased, a forward current flows. The forward current of the diode is
It is caused by the dynamic energy stored in the inductor. Therefore, the dynamic energy stored in the inductor is consumed by the diode. As a result, the connection point 22
The oscillation amplitude of the AC voltage waveform at 2 decreases. on the other hand,
Charge is supplied to the energy storage circuit 220 by the forward current of the diode. This increases the static energy.

The element 391 shown in FIG.
When using an OS transistor when the voltage of the drain is made from the ground voltage GND only lowered voltage threshold voltage V _T, PMOS transistor is turned on. As a result, a drain current flows from the terminal b (source) of the PMOS transistor to the terminal a (drain). This drain current is caused by the dynamic energy stored in the inductor. Therefore, the dynamic energy stored in the inductor is consumed by the PMOS transistor. As a result, the oscillation amplitude of the AC voltage waveform at the connection point 222 decreases. On the other hand, electric charges are supplied to the energy storage circuit 220 by the drain current.
This increases the static energy.

FIG. 12 shows the configuration of a power supply device 1303 having a function of adjusting the amount of dynamic energy stored in the energy storage circuit 220. The power supply device 1303 supplies energy from the energy supply circuit 210 to the energy storage circuit using magnetic coupling.

The energy storage circuit 220 includes the element 39
1 is provided. The element 391 is connected to the connection point 222. The configuration of the element 391 is as described above.

When the dynamic energy is excessively supplied to the energy storage circuit 220, the dynamic energy stored in the inductor is consumed by the element 391. As a result, the oscillation amplitude of the AC voltage waveform at the connection point 222 decreases. On the other hand, charge is supplied to the energy storage circuit 220 by the element 391. This increases the static energy.

As described above, the excessive amplitude of the dynamic energy is consumed by the element 391, so that the oscillation amplitude of the AC voltage waveform at the connection point 222 is attenuated. As a result, the amount of dynamic energy stored in the energy storage circuit 220 is kept constant.

FIG. 13A shows a configuration of a power supply device 1304 having a function of adjusting the amount of dynamic energy stored in the energy storage circuit 220. The load 400 is connected to the power supply 1304 at a connection point 224. The load 400 includes at least one of a capacitance component and a resistance component.

The power supply device 1304 includes an energy supply circuit 210 and an energy storage circuit 220 which are basic components.
, A control circuit 271, a comparator 272,
Reference voltage generation circuit 273, control circuit 402, comparators 403 to 404, and reference voltage generation circuits 405 to 4
06 is further included.

When the dynamic energy is excessively supplied to the energy storage circuit 220, the oscillation amplitude of the AC voltage waveform at the connection point 222 increases. The power supply device 1304 has an object to reduce the oscillation amplitude of the AC voltage waveform at the connection point 222 when the voltage at the connection point 222 becomes equal to or lower than the ground voltage GND.

A switch 401 is provided in the energy storage circuit 220. Switch 401 is connected to connection point 2
22. The switch 401 is, for example, N
It can be a MOS transistor. The opening / closing timing of the switch 401 is controlled by the control circuit 402.

The capacitance value C ₁ and the capacitance value C ₂ are set so as to satisfy the relationship of C ₁ >> C ₂ . As a result, an AC voltage waveform is obtained at the connection point 222 and the connection point 224 is obtained.
A DC voltage waveform is obtained.

FIG. 13B shows an AC voltage waveform (A) at node 222 and a DC voltage waveform (B) at node 224.

[0156] When the voltage at the node 224 falls below the target voltage V _P, the control circuit 271 turns on the switch 212. For example, the control circuit 271 turns on the switch 212 in the period of time t ₃ ~t _4. Alternatively, the period to turn on the switch 212 may be a period of time t ₁ ~t _2, may be a period of time t ₁ ~t _4. As a result, energy is supplied from the energy supply circuit 210 to the energy storage circuit 220. As a result, the oscillation amplitude of the AC voltage waveform at the connection point 222 increases.

When dynamic energy is excessively supplied to the energy storage circuit 220, the voltage at the node 222 becomes equal to or lower than the ground voltage GND. Energy conservation circuit 2
The same applies to the case where the static energy stored at 20 decreases and the oscillation center of the AC voltage waveform at the connection point 222 becomes smaller than 1/2 _VDD .

The voltage at the node 222 is equal to the ground voltage GND.
In the following period, the control circuit 402
Turn on 01. For example, the control circuit 402
To turn on the switch 401 in the _fifth period of ~t _6. Alternatively, the period during which the switch 401 is turned on is at time t ₇
May be a period of ~t _8, it may be a period of time t ₅ ~t _8. As a result, a current flows from the ground voltage GND toward the connection point 222. This current is caused by the dynamic energy stored in the inductor. Therefore, the dynamic energy stored in the inductor is consumed by the switch 401. As a result, the oscillation amplitude of the AC voltage waveform at the connection point 222 decreases. On the other hand, electric charge is supplied to the energy storage circuit 220 via the switch 401. This increases the static energy.

As described above, when the switch 401 is turned on when the voltage at the node 222 is lower than the ground voltage GND, a part of the dynamic energy stored in the energy storage It is converted into heat energy by resistance and consumed,
Some of the other kinetic energy is converted to static energy and stored in energy storage circuit 220.

On the other hand, when the switch 401 is turned on when the voltage at the node 222 is higher than the ground voltage GND, the static energy stored in the energy storage circuit 220 is released toward the ground voltage GND. A part of the static energy released from the energy storage circuit 220 is converted into heat energy by the parasitic resistance of the switch 401 and consumed, and another part of the static energy is dynamic by the electric charge passing through the inductor 221. Converted to energy.

That is, by turning on the switch 401 at a voltage lower than the ground voltage GND, the dynamic energy stored in the energy storage circuit 220 can be reduced, and the static energy can be increased. By turning on the switch 401 at a voltage higher than the ground voltage GND, the dynamic energy stored in the energy storage circuit 220 can be increased and the static energy can be reduced.

As described above, the dynamic energy and the static energy stored in the energy storage circuit 220 can be adjusted by adjusting the timing at which the switch 401 is turned on. The timing at which the switch 401 is turned on can be arbitrarily adjusted by adjusting the reference voltages V _r3 and V _r4 output from the reference voltage generation circuit 406.

FIG. 14 shows a procedure of processing for adjusting dynamic energy. This processing is performed by the control circuit 271 (FIG. 13A).
) Is executed at predetermined time intervals. Where V
_A represents the voltage at node 222, and V _B represents the voltage at node 22.
4, and V _P is a reference voltage generation circuit 273.
, V _r1 and V _r2 represent reference voltages selectively output from the reference voltage generation circuit 405, and V _r3 and V _r4 are selectively output from the reference voltage generation circuit 406. Represents a reference voltage, V _DD represents a power supply voltage, and GND represents a ground voltage. These voltages are V
_r4 satisfy the relationship of _{<V r3 <GND <V P} <V r2 <V r1 <V DD.

[0164] At step S31, the voltage V _B is whether below the voltage V _P is determined. That the voltage V _B falls below the voltage V _P, the output signal of the comparator 272 is detected by changes from H level to L level. If the voltage V _B falls below the voltage V _P, the process step S3
Proceed to 2.

[0165] At step S32, the voltage V _A is the voltage V _A is whether below the voltage V _r1 is determined in the descending. The fact that the voltage _VA has dropped below the voltage _Vr1 while the voltage _VA has fallen means that
It is detected when the output signal of the comparator 403 changes from L level to H level. If the voltage V _A is the voltage V _A falls below the voltage V _r1 while descending, the control circuit 2
71 turns on the switch 212 (step S3
3).

[0166] At step S34, the voltage V _A is the voltage V _A is whether below the voltage V _r2 is determined during descent. The fact that the voltage _VA has dropped below the voltage _Vr2 while the voltage _VA has fallen means that:
It is detected when the output signal of the comparator 403 changes from L level to H level. If the voltage V _A is the voltage V _A falls below the voltage V _r2 while descending, the control circuit 2
71 turns off the switch 212 (step S3).
5).

[0167] At step S36, the voltage V _A is the voltage V _A is whether below the voltage V _r3 is determined during descent. The fact that the voltage _VA has dropped below the voltage _Vr3 while the voltage _VA has fallen means that:
It is detected when the output signal of the comparator 404 changes from L level to H level. If the voltage V _A is the voltage V _A falls below the voltage V _r3 while descending, the control circuit 4
02 turns on the switch 401 (step S3
7).

In step S38, it is determined whether or not the voltage _VA has dropped below the voltage _Vr4 while the voltage _VA has fallen. The fact that the voltage _VA has dropped below the voltage _Vr4 while the voltage _VA has fallen means that
It is detected when the output signal of the comparator 404 changes from L level to H level. If the voltage V _A is the voltage V _A falls below the voltage V _r4 while descending, the control circuit 4
02 turns off the switch 401 (step S3
9).

As described above, during the period when the voltage at the connection point 222 is equal to or lower than the ground voltage GND, the switch 401
Is turned on. Excess kinetic energy can cause switch 40
By being consumed by 1, the amplitude of the vibration of the AC voltage waveform at the connection point 222 is attenuated. As a result, the amount of dynamic energy stored in the energy storage circuit 220 is kept constant. 5. As shown in FIG. 6A, when energy is supplied from the energy supply circuit 210 to the energy storage circuit 220 via the switch 212, the noise is activated according to the length of time during which the switch 212 is on. The total supply of dynamic energy and static energy (or the conversion of dynamic energy to static energy) is determined. When the dynamic energy and the static energy supplied from the energy storage circuit 220 to the load increase, the control is performed such that the period during which the switch 212 is in the ON state is lengthened. When the dynamic energy and the static energy supplied from the energy storage circuit 220 to the load decrease, the control is performed such that the period during which the switch 212 is in the ON state is shortened.

As described above, when the length of the period during which the switch 212 is in the on state changes, the distortion of the sine wave vibration at the connection point 222 also changes. As a result, the frequency spectrum of the distortion changes.

The sinusoidal oscillation at the connection point 222 causes a current to flow through the inductor 221. The current flowing through the inductor 221 generates an electromagnetic wave. The frequency of the electromagnetic wave is uniquely associated with the frequency of the sinusoidal vibration. Inductor 22
The electromagnetic wave generated by the flow of current through 1 is coupled to another inductor and affects a circuit to which the other inductor is connected. This is so-called noise.

[0172] Noise can be removed by a filter.
In order to facilitate the removal of noise by the filter, it is preferable that the frequency spectrum of the noise is substantially constant and does not change. By keeping the length of the period during which the switch 212 is in the ON state constant, the frequency spectrum of noise can be kept constant. When the length of time during which the switch 212 is in the on state is constant, the switch 212
The amount of energy supply and the amount of conversion may be adjusted by changing the parasitic resistance of the power supply.

To change the parasitic resistance of the switch 212, for example, a plurality of switches connected in parallel to each other between the power supply 211 and the connection point 222 are provided, and a switch that is turned on simultaneously among the plurality of switches is provided. Is achieved by changing the number of.

FIG. 15 shows a configuration example of the switch section 212e. The switch unit 212e includes four switches 212-1 to 212-4 connected in parallel with each other.
In a certain period, only the switch 212-1 is turned on. In another period, switches 212-1 and 22-1
12-2 is turned on. In another certain period, the switches 212-1 to 212-3 are turned on. In still another certain period, the switches 212-1 to 212-2
12-4 is turned on. As the number of switches turned on at the same time increases, the amount of energy supplied and converted increases.

As described above, the length of the period in which the switch 212 is on is constant, and the amount of energy supply and the amount of conversion are adjusted by changing the parasitic resistance of the switch 212. Can be constant. This makes it easier to remove noise by the filter. 6. Regarding the resonance operation, the frequency f of the sine wave vibration at the connection point 222 of the energy storage circuit 220 is expressed by f = 1 / {2π · {(LC ₂ )} when the condition of C ₁ >> C ₂ is satisfied. Is done. Here, L is the inductance of the inductor 221, C ₁ is the capacitance value of the capacitance 225, and C ₂ is the capacitance value of the capacitance 223.

When the capacitance value C ₂ is increased, the frequency f decreases. When the inductance L is increased, the frequency f is decreased.

A low frequency f means that the speed of change of a signal input to a comparator used in various types of power supply circuits is low. Thus, the comparator can detect the voltage without error. This is because the comparator has such a characteristic that the slower the signal to be detected, the more accurately the voltage can be detected. Further, when the comparator has a capability of detecting a voltage sufficiently accurately, the power consumption of the comparator can be reduced by lowering the detection accuracy of the comparator. In addition, energy can be supplied from the energy supply circuit 210 to the energy storage circuit 220 by watching when the voltage difference between the two terminals of the switch 212 is small. When a voltage difference is generated, noise caused by the incoming current can be avoided.

As described above, the energy storage circuit 220
Has a feature that the frequency f of the sine wave vibration at the connection point 222 can be increased or decreased by changing the capacitance value and / or the inductance. Therefore, the frequency of the noise in the resonance operation can be raised or lowered.

If the capacitance value C ₂ is increased under the condition that the amplitude of the sine wave vibration at the connection point 222 is kept constant, the amount of charge to be charged in the capacitance 223 increases. As a result, the current flowing into the capacitor 223 increases.

In the case where electric charges are supplied to the load using the sinusoidal vibration or the electric charges are collected from the load, the amount of the electric charges varies depending on the load. Therefore, the circuit design of the energy storage circuit 220 must be designed in consideration of the frequency f and the amount of charge supplied to the load (and / or the amount of charge recovered from the load). 7. It is expected that memory circuits, digital circuits, and analog circuits typified by DRAMs and the like will be formed on a single chip as LSIs become more highly integrated with respect to noise reduction based on LC resonance operation . . If these various circuits are mixed on a single chip, the effect on the characteristics of the analog circuit due to noise entering the operating frequency band of the intermediate frequency analog circuit will gradually become a problem in the future. Conceivable.

FIG. 75 shows an embodiment of a system LSI. The system LSI 1801, for example, has a function of receiving and demodulating a transmitted high-frequency radio wave like a mobile phone.

The system LSI 1801 has an intermediate frequency and high frequency analog circuit block 1802 having a function of receiving a high frequency signal and demodulating it to an intermediate frequency, and a DRAM block 180 storing a program required for demodulation.
And a low-frequency analog circuit block 1 including an A / D converter for controlling a demodulation operation and converting a demodulated signal into a digital signal
804, a digital circuit block 1805 that performs signal processing such as noise removal of the digital demodulated signal, and a power supply device 1806 including an LC resonance circuit. The circuit blocks 1802 to 1805 and the power supply 1806 are formed on a single silicon chip. Power supply 18
06 supplies a power supply voltage to at least one of the circuit blocks 1802 to 1805.

As shown in FIG. 75, the intermediate frequency and high frequency analog circuit block 1802 and the power supply 180
6, the noise generated by the inductor of the LC resonance circuit is mixed into the intermediate frequency and high frequency analog circuit block 1802. On the other hand, since the characteristics of the intermediate frequency and high frequency analog circuit block 1802 are remarkably deteriorated due to noise, the allowable noise strength is determined by a standard for each application mode such as signal transmission. For example, one standard is 10
It is prohibited to mix noise of -60 dBm or more into the frequency band of ２０20 MHz.

In order to prevent noise from being mixed, there is a method of using a power supply device that does not include an inductor, for example, a power supply device using an operational amplifier. However, a power supply device that does not include an inductor is disadvantageous in reducing the power consumption and heat generation of an LSI due to large energy loss. When a power supply device including an inductor is used, radiation noise is generated by a current flowing through the inductor. Therefore, it is necessary to prevent noise higher than the allowable strength from being mixed into the frequency band that affects the characteristics of the intermediate frequency and high frequency analog circuit blocks.

In the conventional DC / DC converter 61 having the voltage converter 54 shown in FIG. 51A, when the supply of the current from the switch 50 ends, the switch 50 changes from the open state to the closed state. Since the current flowing through the inductor 52 changes abruptly when the switch 50 changes from the open state to the closed state, the voltage of the signal input terminal A instantaneously reaches the ground voltage according to the characteristics of the inductor 52. As a result, the noise generated from the inductor 52 has a noise distribution that reaches a high frequency in accordance with a sudden change in the voltage of the signal input terminal A. This causes noise higher than the allowable strength to be mixed in a frequency band that affects the characteristics of the intermediate frequency and high frequency analog circuit blocks.

On the other hand, power supply device 180 including an LC resonance circuit
In 6, the change in current flowing through the inductor can be limited by appropriately setting the resonance frequency of the LC resonance circuit. Thereby, the frequency of the noise can be reduced.

FIG. 77 shows the distribution of noise intensity with respect to the resonance frequency of the LC resonance circuit. In FIG. 77, curves a, b, and c respectively represent the resonance frequency f of the LC resonance circuit.
_La , f _Lb , and f _Lc . Here, f _La <f _Lb <f _Lc
There is a relationship. The resonance frequencies f _La and f of the LC resonance circuit
Each of _Lb and f _Lc is a capacitance C (for example, C ₂ in FIG. 1).
And inductor L (for example, L in FIG. 1) are appropriately set at the time of design. Thereby, L and C can be appropriately selected and designed at the time of design. The resonance frequency f is represented by f = 1 / 2π√LC.
It can be seen that the frequency band in which the noise is distributed becomes narrower as the resonance frequency of the LC resonance circuit decreases. In addition,
A curve d indicates a noise distribution by the above-described conventional DC / DC converter 61.

Intermediate frequency and high frequency analog circuit block
1802, a specific frequency band (frequency f₁Less than
Upper frequency f_TwoPredetermined noise intensity in the following bands)
Value of P _TwoSuppose you have to: This place
In this case, the resonance frequency of the LC resonance circuit is f_LaOr f_LbTo
By setting, in that particular frequency band
The noise intensity is set to a predetermined value P_TwoIt can be:
This allows the intermediate frequency and high frequency
Prevents the characteristics of the log circuit block 1802 from deteriorating
can do. Frequency f₁Is, for example, 10 MHz
And the frequency f_TwoIs, for example, 20 MHz. Place
Constant value P_TwoIs, for example, −60 dBm.

[0189] Not only when various circuit blocks are mixedly mounted on a single silicon chip, but also when the mounting density of an LSI becomes high, such as in a multi-chip module or a high-density mounting on a substrate, It is necessary to prevent noise higher than the allowable strength from being mixed into the frequency band that affects the characteristics of the intermediate frequency and high frequency analog circuit blocks.

FIG. 76 shows a power supply device 1 including an LC resonance circuit.
806 and intermediate frequency and high frequency analog circuit block 1
802 is formed on a different chip.
The system LSI 1807 includes a digital circuit block 18
05 and a power supply 1806. System LS
The I1807 and the intermediate frequency and high frequency analog circuit block 1802 are formed on different silicon chips. The power supply device 1806 includes a circuit block 1802,
A power supply voltage is supplied to at least one of the power supply circuits 1805.

FIG. 78 shows the distribution of noise intensity with respect to the distance D between the system LSI 1807 and the intermediate frequency and high frequency analog circuit block 1802. In FIG. 78, curves e, f, and g respectively represent the system LSI 18
07 and intermediate frequency and high frequency analog circuit block 18
Distance D _e between 02, D _f, corresponding to the D _g. Where _De >
Relationship that D _f> D _g. It can be seen that the frequency band in which the noise is distributed increases as the distance D between the system LSI 1807 and the intermediate frequency and high frequency analog circuit block 1802 decreases.

As described above, by setting the resonance frequency of the LC resonance circuit to be sufficiently small, the noise intensity in a specific frequency band can be reduced to a predetermined value or less. Thus, it is possible to prevent the characteristics of the intermediate frequency and high frequency analog circuit block 1802 from deteriorating due to noise.

As the power supply 1806 including the LC resonance circuit, any type of power supply described in Chapters 8 and 9 of this specification can be used. However, it is essential that the LC resonance circuit includes a configuration in which a first capacitance is connected to one end of the inductor and a second capacitance is connected to the other end of the inductor (hereinafter, referred to as a CLC configuration). do not do. The LC resonance circuit of the power supply device 1806 has a configuration in which a capacitance is connected to only one end of an inductor (hereinafter, L-type).
C configuration).

FIG. 79 shows a configuration of a power supply device 1806 including an LC resonance circuit having an LC configuration. Power supply 1806
Supplies a DC power supply voltage to at least one of the plurality of circuit blocks. The power supply device 1806 and the plurality of circuit blocks may be formed on a single semiconductor chip, or may be formed on different semiconductor chips.

An LC resonance circuit is constituted by the inductor 1820 and the capacitor 1821. The current adjustment circuit 1811 is connected to the LC resonance circuit. The voltage of the terminal of the inductor 1820 to which the current adjustment circuit 1811 is connected is set to V _DD / 2. Here, the power supply voltage is assumed to be V _DD .

When the current flowing through inductor 1820 flows from current adjustment circuit 1811 toward capacitor 1821, the voltage at node 1818 increases. Inductor 1
The current flowing through the capacitor 820 is transferred from the capacitor 1821 to the current adjusting circuit 1.
When flowing toward 811, the voltage at node 1818 falls.

The current adjustment circuit 1811 adjusts the input / output of the current while monitoring the voltage at the connection point 1818 so that the voltage at the connection point 1818 performs LC resonance with a predetermined voltage amplitude. In order to convert the resonance voltage at the connection point 1818 into a DC voltage, comparators 1813 and 1819, a reference voltage generation circuit 1814, and a control circuit 1812 are provided. By opening and closing the switch 1815 by the control circuit 1812, the voltage at the connection point 1816 of the load 1817 is converted to a DC voltage. Such a conversion method is shown in FIG.
This is the same as the conversion method in the power supply device described later with reference to FIG. The control circuit 1812, comparators 1819 and 1813, switch 1815, and load 1 shown in FIG.
817 and the reference voltage generation circuit 1814 correspond to the control circuit 283 and the comparators 284 and 28 shown in FIG. 17A.
5, switch 282, load 280, and reference voltage generation circuit 286. 8. Types of Power Supply Device 200 The power supply device 200 is roughly classified into the following four types (1) to (4). (1) DC type: This type uses a DC voltage waveform supplied from one of the connection points 222 and 224 of the energy storage circuit 220. (2) AC type: This type uses an AC voltage waveform supplied from one of the connection points 222 and 224 of the energy storage circuit 220. (3) DC-AC type: A type using a DC voltage waveform supplied from one of the connection points 222 and 224 of the energy storage circuit 220 and using an AC voltage waveform supplied from the other. . (4) AC-AC type: This type uses an AC voltage waveform supplied from one of the connection points 222 and 224 of the energy storage circuit 220 and uses an AC voltage waveform supplied from the other. . 8.1 DC-Type Power Supply Device FIG. 16A shows a configuration of a DC-type power supply device 201 that supplies a DC voltage waveform to a load 270 connected to a connection point 224. Load 270 includes at least one of a capacitance component and a resistance component.

The power supply device 201 further includes a control circuit 271, a comparator 272, and a reference voltage generation circuit 273 in addition to the basic configuration of the energy supply circuit 210 and the energy storage circuit 220. In the example illustrated in FIG. 16A, the energy supply circuit 210 employs the configuration illustrated in FIG. 6A. However, as the configuration of the energy supply circuit 210, any of the configurations shown in FIGS. 6A to 6D and FIG. 58A may be adopted. 11A, 11B, and 1 as means for adjusting dynamic energy.
The configuration shown in FIG. 3A may be adopted.

The capacitance value C ₁ and the capacitance value C ₂ are set so as to satisfy the relationship of C ₁ >> C ₂ . As a result, an AC voltage waveform is obtained at the connection point 222 and the connection point 224 is obtained.
A DC voltage waveform is obtained.

FIG. 16B shows an AC voltage waveform (A) at connection point 222 (shown by a broken line) and a DC voltage waveform (B) at connection point 224 (shown by a solid line). Strictly speaking, the voltage waveform at the connection point 224 is also an AC voltage waveform. However, the voltage waveform at the connection point 224 can be regarded as a DC voltage waveform. This is because the voltage oscillation at the connection point 224 is sufficiently smaller than the voltage oscillation at the connection point 222.

As described above, the energy supply circuit 21
By appropriately adjusting the proportions of static energy and kinetic energy supplied from 0, the vibration center is voltage V _P, and the amplitude is obtained an AC voltage waveform (A) is 1 / 2V _DD Can be. Also, the DC voltage waveform (B)
Is substantially equal to the vibration center of the AC voltage waveform (A).

Hereinafter, the operation of the power supply device 201 will be described.

The comparator 272 compares the voltage at the connection point 224 with the voltage V _P output from the reference voltage generation circuit 273, and thereby the voltage at the connection point 224 becomes the voltage V _P.
Is detected. If the voltage at the node 224 is greater than or equal to voltage V _P, the output signal of the comparator 272 is at H level, when the voltage at the node 224 is lower than the voltage V _P, the output signal of the comparator 272 is L level It is.

[0204] At time t _1, the voltage at the node 224 falls below the voltage V _P, the output signal of the comparator 272 changes from H level to L level. Control circuit 271
Responds to a change in the output signal of the comparator 272,
The switch 212 is turned on. Thus, the supply of energy to the energy storage circuit 220 is started. As a result, the voltage at the node 224 increases.

[0205] In time t _2, the voltage at the node 224 becomes equal to or higher than the voltage V _P, the output signal of the comparator 272 changes from L level to H level. Control circuit 271
Responds to a change in the output signal of the comparator 272,
The switch 212 is turned off. Thus, the supply of energy to the energy storage circuit 220 ends.

[0206] In the same manner, at time t ₃ is started the supply of energy to the energy preserving circuit 220, the supply of energy to the energy preserving circuit 220 is terminated at time t _4.

As described above, the energy consumed by the load 270 is detected when the energy stored in the energy storage circuit 220 decreases.
Energy is provided to the energy storage circuit 220 so that the reduced energy is restored.

Thus, the DC type power supply 2
01 can provide a voltage lower than the power supply voltage V _DD to the load 270. 8.2 AC-Type Power Supply Device FIG. 17A shows a configuration of an AC-type power supply device 202 that charges a voltage at a connection point 281 in a load 280 connected to the connection point 222 to a desired voltage using an AC voltage waveform. Show. The load 280 includes at least one of a capacitance component and a resistance component, and a switch 282.

The power supply device 202 further includes a control circuit 283, a comparator 284, a comparator 285, and a reference voltage generation circuit 286 in addition to the structure of the power supply device 201 shown in FIG. 16A. The configuration shown in FIGS. 11A, 11B and 13A may be adopted as a means for adjusting the dynamic energy.

The capacitance value C ₁ and the capacitance value C ₂ are set so as to satisfy the relationship of C ₁ >> C ₂ . As a result, an AC voltage waveform is obtained at the connection point 222 and the connection point 224 is obtained.
A DC voltage waveform is obtained.

FIG. 17B shows an AC voltage waveform (A) at node 222, a DC voltage waveform (B) at node 224, and a voltage waveform (C) at node 281.

As described above, the energy supply circuit 21
By properly adjusting the proportion of the static energy and dynamic energy supplied from 0, the vibration center is voltage V _P, and the amplitude is obtained an AC voltage waveform (A) is 1 / 2V _DD Can be. Also, the DC voltage waveform (B)
Is substantially equal to the vibration center of the AC voltage waveform (A).

[0213] Hereinafter, an operation of the power supply device 202 in the case of setting the voltage at the node 281 from the voltages V ₁ to a voltage V _r1 than voltages V _1. At time t = 0, the connection point 281 is assumed to have been charged to the voltage V _1.

The comparator 284 compares the voltage at the node 222 with the voltage at the node 281 to determine whether the voltage at the node 222 has reached the voltage V ₁ while the AC voltage waveform (A) is falling. the voltage at the node 222 detects whether reached the voltages V ₁ in alternating-current voltage waveform (a) is a state of rising. When the voltage at the node 222 reaches the voltage V ₁ while the AC voltage waveform (A) is falling, the output signal of the comparator 284 changes from the L level to the H level. When the voltage at the node 222 reaches the voltage V ₁ while the AC voltage waveform (A) is rising, the output signal of the comparator 284 changes from the H level to the L level.

At time t ₁ , when the voltage at the node 222 reaches the voltage V ₁ while the AC voltage waveform (A) is falling, the output signal of the comparator 284 changes from the L level to the H level. The control circuit 283 responds to a change in the output signal of the comparator 284 by
2 is turned on. Thereby, the AC voltage waveform (A)
Along, the voltage at the connection point 281 changes.

The comparator 285 compares the voltage at the connection point 281 with the voltage V _r1 output from the reference voltage generation circuit 286, so that the voltage at the connection point 281 becomes the voltage V _r1.
Is detected.

At time t ₂ , when the voltage at node 281 reaches voltage V _r1 , the output signal of comparator 285 changes from L level to H level. Control circuit 283
Responds to a change in the output signal of the comparator 285,
The switch 282 is turned off. As a result, the voltage at the connection point 281 is maintained at the voltage _Vr1 .

[0218] Next, to set the voltage at the node 281 from the voltage V _r1 to the voltage higher V _r2 than the voltage V _r1 utilizes rising transition of the AC voltage waveform (A).

At time t ₃ , when the voltage at the node 222 reaches the voltage V _r1 while the AC voltage waveform (A) is rising, the output signal of the comparator 284 changes from the H level to the L level. The control circuit 283 responds to a change in the output signal of the comparator 284 by
2 is turned on. Thereby, the AC voltage waveform (A)
Along, the voltage at the connection point 281 changes.

The comparator 285 compares the voltage at the connection point 281 with the voltage V _r2 output from the reference voltage generation circuit 286, so that the voltage at the connection point 281 becomes the voltage V _r2.
Is detected. As described above, the reference voltage generation circuit 286 switches between the voltage V _r1 and the voltage V _r2 at a predetermined timing and outputs the switched voltage.

At time t ₄ , when the voltage at node 281 reaches voltage V _r2 , the output signal of comparator 285 changes from H level to L level. Control circuit 283
Responds to a change in the output signal of the comparator 285,
The switch 282 is turned off. As a result, the voltage at the connection point 281 is maintained at the voltage _Vr2 .

The voltage at the node 281 of the load 280 can be charged to an arbitrary voltage by adjusting the voltage output from the reference voltage generation circuit 286.

Further, similarly to the DC type power supply 201, the energy consumed by the load 280 is
It is detected when the energy stored in the energy storage circuit 220 decreases. Energy is provided to the energy storage circuit 220 so that the reduced energy is restored.

Thus, the AC type power supply 2
No. 02 can charge the voltage of the connection point 281 in the load 280 connected to the connection point 222 to a desired voltage using the AC voltage waveform. Charging the load 280 including the capacitance component using the AC voltage waveform is based on the above-described “adiabatic charging principle”. Therefore, the energy consumed by the load 280 when charging the load 280 is extremely small. 8.3 DC-AC Type Power Supply Device FIG. 18A shows a configuration of a DC-AC type power supply device 203. The configuration of the power supply device 203 is the same as the configuration of the power supply device 202 shown in FIG. 17A except that the load 270 is connected to the connection point 224.

By connecting the load 270 to the connection point 224, a DC voltage waveform can be supplied to the load 270. Further, by connecting the load 280 to the connection point 222, the voltage at the connection point 281 in the load 280 can be charged to a desired voltage using an AC voltage waveform.

FIG. 18B shows an AC voltage waveform (A) at node 222, a DC voltage waveform (B) at node 224, and a voltage waveform (C) at node 281. 8.4 AC-AC Type Power Supply (Part 1) FIG. 19A shows a configuration of an AC-AC type power supply 204. The power supply device 204 uses the first AC voltage waveform to charge the voltage at the node 281 at the load 280 connected to the node 222 to a desired voltage, and is only 180 degrees from the first AC voltage waveform. The voltage at the node 291 in the load 290 connected to the node 224 is charged to a desired voltage using the second AC voltage waveforms having different phases. The load 290 includes at least one of a capacitance component and a resistance component and a switch 292.

Power supply device 204 further includes a control circuit 293, a comparator 294, and a comparator 295 in addition to the configuration of power supply device 202 shown in FIG. 17A. The function of control circuit 293 is the same as the function of control circuit 283. The function of the comparator 294 is the same as the function of the comparator 284. The function of the comparator 295 is the same as the function of the comparator 285. The configuration shown in FIGS. 11A, 11B and 13A may be adopted as a means for adjusting the dynamic energy.

The reference voltage generation circuit 286 switches between the voltage V _r1 and the voltage V _r2 at a predetermined timing and outputs the same. The reference voltage generation circuit 286 supplies the comparator 285 with the voltage V
While outputting _r1 , it outputs the voltage _Vr2 to the comparator 295. The reference voltage generation circuit 286 outputs the voltage V _r2 to the comparator 285, while
5 to output the voltage V _r1 .

The capacitance value C ₁ and the capacitance value C ₂ are set so as to satisfy the relationship of C ₁ ≒ C ₂ . As a result, an AC voltage waveform is obtained at the connection point 222, and an AC voltage waveform is obtained at the connection point 224.

FIG. 19B shows an AC voltage waveform (A) at node 222, an AC voltage waveform (B) at node 224, a voltage waveform (C) at node 281 and a voltage waveform (D) at node 291. Show. The AC voltage waveform (A) and the AC voltage waveform (B) have substantially the same amplitude as the vibration center, but differ in phase by 180 degrees.

AC voltage waveform (A) and AC voltage waveform (B)
By using both, the falling AC voltage waveform
The voltage at the node 281 is changed to the voltage V₁From the voltage
V₁Lower voltage V_r1In parallel with setting to
Using the alternating voltage waveform (B) in the
Voltage V_TwoFrom the voltage V_TwoHigher voltage V_r2Can be set to
it can. Similarly, the rising AC voltage waveform (A) is used.
And the voltage at the node 281 is_r1From the voltage V_r1Higher
Voltage V_r2In parallel with the setting,
The voltage at the node 291 is changed to the voltage V using the voltage waveform (B)._r2Or
Voltage V_r2Lower voltage V_r1Can be set to
Note that the capacitance value C₁And capacitance value C_TwoIs related to C ₁> C_TwoIn
May be, C₁<C_TwoIt may be.8.5 AC-AC Type Power Supply (Part 2) FIG. 20A shows a configuration of an AC-AC type power supply device 205.
Is shown. The power supply 205 includes a first AC voltage waveform and a first AC voltage waveform.
Of the second AC voltage having a phase difference of 180 degrees from the AC voltage waveform of the second AC voltage waveform.
The connection point 222 and the
Connection point 3 in load 300 connected to connection point 224
01 is charged to a desired voltage. The load 300 is
At least one of the quantity component and the resistance component and the switch 30
2 and a switch 303.

The power supply device 205 includes a control circuit 304, a comparator 305, a comparator 306, and a comparator 3 in addition to the configuration of the power supply device 201 shown in FIG. 16A.
07 and a reference voltage generation circuit 308. The configuration shown in FIGS. 11A, 11B and 13A may be adopted as a means for adjusting the dynamic energy.

The capacitance value C ₁ and the capacitance value C ₂ are set so as to satisfy the relationship of C ₁ ≒ C ₂ . As a result, an AC voltage waveform is obtained at the connection point 222, and an AC voltage waveform is obtained at the connection point 224.

FIG. 20B shows an AC voltage waveform (A) at node 222, an AC voltage waveform (B) at node 224, and voltage waveforms (C) and (C ') at node 301. The AC voltage waveform (A) and the AC voltage waveform (B) have substantially the same amplitude as the vibration center, but differ in phase by 180 degrees.

[0235] Hereinafter, an operation of the power supply device 205 in case of setting the voltage at the node 301 from the voltages V ₁ to a high voltage V _r2 than voltages V _1. At time t = 0, it is assumed that the connection point 301 is charged to the voltage V _1.

The comparator 305 compares the voltage at the node 222 with the voltage at the node 301 to determine whether the voltage at the node 222 has reached the voltage V ₁ while the AC voltage waveform (A) is falling. the voltage at the node 222 detects whether reached the voltages V ₁ in alternating-current voltage waveform (a) is a state of rising. When the voltage at the node 222 reaches the voltage V ₁ while the AC voltage waveform (A) is falling, the output signal of the comparator 305 changes from the L level to the H level. When the alternating-current voltage waveform (A) is the voltage at the node 222 in a state of rising reaches the voltages V _1, the output signal of the comparator 305 changes from H level to L level.

The comparator 307 compares the voltage at the node 224 with the voltage at the node 301 to determine whether the voltage at the node 224 has reached the voltage V ₁ while the AC voltage waveform (B) is falling. It is detected whether or not the voltage at the node 224 has reached the voltage V ₁ while the AC voltage waveform (B) is rising. When the voltage at the node 224 reaches the voltage V ₁ while the AC voltage waveform (B) is falling, the output signal of the comparator 307 changes from the L level to the H level. When the voltage at the node 224 reaches the voltage V ₁ while the AC voltage waveform (B) is rising, the output signal of the comparator 307 changes from the H level to the L level.

At time t ₂ , when the voltage at node 224 reaches voltage V ₁ while AC voltage waveform (B) is rising, the output signal of comparator 307 changes from H level to L level. The control circuit 304 responds to a change in the output signal of the comparator 307 and
3 is turned on. Thereby, the AC voltage waveform (B)
Along, the voltage at the connection point 301 changes.

The comparator 306 compares the voltage at the connection point 301 with the voltage V _r2 output from the reference voltage generation circuit 308, so that the voltage at the connection point 301 becomes the voltage V _r2.
Is detected.

At time t ₃ , when the voltage at node 301 reaches voltage V _r2 , the output signal of comparator 306 changes from L level to H level. Control circuit 304
Responds to a change in the output signal of the comparator 306,
The switch 303 is turned off. Thus, the voltage at the connection point 301 is maintained at the voltage _Vr2 .

[0241] Next, the operation of the power supply device 205 in case of setting the voltage at the node 301 from the voltages V ₁ to a voltage V _r1 than voltages V _1. At time t = 0, it is assumed that the connection point 301 is charged to the voltage V _1.

At time t ₁ , when the voltage at node 222 reaches voltage V ₁ while AC voltage waveform (A) is falling, the output signal of comparator 305 changes from L level to H level. The control circuit 304 responds to a change in the output signal of the comparator 305 by
2 is turned on. Thereby, the AC voltage waveform (A)
Along, the voltage at the connection point 301 changes.

The comparator 306 compares the voltage at the connection point 301 with the voltage V _r1 output from the reference voltage generation circuit 308, so that the voltage at the connection point 301 becomes the voltage V _r1.
Is detected. As described above, the reference voltage generation circuit 308 switches and outputs the voltage V _r1 and the voltage V _r2 at a predetermined timing.

At time t ₃ , when it is detected that the voltage at node 301 has reached voltage V _r1 , the output signal of comparator 306 changes from L level to H level.
The control circuit 304 turns off the switch 302 in response to a change in the output signal of the comparator 306. Thus, the voltage at the connection point 301 is maintained at the voltage _Vr1 .

The voltage at the connection point 301 of the load 300 can be charged to an arbitrary voltage by adjusting the voltage output from the reference voltage generation circuit 308.

Further, similarly to the DC type power supply 201, the energy consumed by the load 300 is
It is detected when the energy stored in the energy storage circuit 220 decreases. Energy is provided to the energy storage circuit 220 so that the reduced energy is restored.

As described above, the load 300 is charged to a desired voltage by selectively using a voltage waveform that quickly reaches a desired voltage from the AC voltage waveform (A) and the AC voltage waveform (B). Can be shortened. Note that the relationship between the capacitance value C ₁ and the capacitance value C ₂ is C ₁ >
C ₂ may be satisfied, or C ₁ <C ₂ may be satisfied. 8.6 AC-AC Type Power Supply Unit (Part 3) FIG. 21 shows a configuration of an AC-AC type power supply unit 206. The load 410 includes a connection point 1222 and a connection point 1224.
And a connection point 1226 are connected to the power supply 206. The load 410 includes at least one of a capacitance component and a resistance component and switches 412 to 414.

The power supply device 206 includes the energy supply circuit 2
10 and an energy storage circuit 1220. 11A, 11B, and 1 as means for adjusting dynamic energy.
The configuration shown in FIG. 3A may be adopted.

The energy storage circuit 1220 has a configuration in which LC resonance circuits are cascaded. More specifically, the energy storage circuit 1220 includes the inductor 12
21, an inductor 1228, a capacitor 1223, a capacitor 1225, and a capacitor 1227. The inductor 1221 and the inductor 1228 are connected in series via a connection point 1224. The capacitor 1223 is connected to the connection point 1
At 222, it is connected to the inductor 1221.
The capacitor 1225 is connected to the inductor 1
221 and 1228. Capacity 1227
Is connected to an inductor 1228 at a connection point 1226. Here, L ₁ and L ₂ are inductors 1221,
1228 represents the inductance, and C _{1 to} C ₃ represent the capacitance values of the capacitors 1223, 1225, and 1227, respectively.

The power supply 206 further includes a control circuit 271, a comparator 272, a reference voltage generation circuit 273, a control circuit 415, comparators 416 to 419, and a reference voltage generation circuit 420.

[0251] The capacitance value C ₁ and the capacitance value C ₂ and the capacitance value C _3,
It is set so as to satisfy the relationship of C ₁ ≒ C ₂ ≒ C ₃ .
Thereby, an AC voltage waveform is obtained at the connection point 1222, and an AC voltage waveform is obtained at the connection point 1224.
At connection point 1226, an AC voltage waveform is obtained.

FIG. 22 shows the AC voltage waveform (A) at the connection point 1222, the AC voltage waveform (B) at the connection point 1224, the AC voltage waveform (C) at the connection point 1226, and the voltage waveform at the connection point 411 of the load 410 ( D). The AC voltage waveforms (A) to (C) have substantially the same vibration center and amplitude. The AC voltage waveform (A) and the AC voltage waveform (C) differ in phase by 180 degrees.

FIGS. 23A to 23D show the movement of charges in each of the periods T _{1 to} T ₄ shown in FIG. Here, V _A represents the voltage at the connection point 1222, V _B denotes the voltage at the connection point 1224, V _C is defined to identify the voltage at node 1226.

[0254] In the period T _1, the charge accumulated in the capacitor 1223 is moved to the capacitor 1225 and the capacitance 1227 (Figure 23A). Thus, the voltage V _A lowered voltage V _B
And the voltage V _C increases.

In the period T ₂ , the charge stored in the capacitor 1223 and the charge stored in the
27 (FIG. 23B). Thus, it lowered the voltage V _A and the voltage V _B, the voltage V _C increases.

In the period T ₃ , the charge stored in the capacitor 1225 and the charge stored in the
23 (FIG. 23C). Thus, the voltage V _A increases, the voltage V _B and the voltage V _C decreases.

In the period T ₄ , the charges accumulated in the capacitor 1227 move to the capacitors 1223 and 1225 (FIG. 23D). Thus, it increases the voltage V _A and the voltage V _B, the voltage V _C drops.

[0258] Hereinafter, an operation of the power supply device 206 in the case of setting the voltage at the node 411 from the voltages V ₁ to a voltage V _r1 than voltages V _1. At time t = 0, the connection point 411 is assumed to be charged to the voltage V _1.

[0259] At time t _1, the voltage V _C voltage of the voltage V _C is the connection point 411 in descending (i.e., the voltage V ₁₎ is reached, the control circuit 415 turns on the switch 414. As a result, the voltage at the connection point 411 falls along the AC voltage waveform (C).

[0260] In time t _2, the when the voltage V _C is the voltage V _C reaches the reference voltage V _r2 output from the reference voltage generating circuit 420 in descending, the control circuit 415 turns off the switch 414. As a result, the voltage at the connection point 411 becomes the voltage V
_It is kept at _r2 .

[0261] Next, the operation of the power supply device 206 in the case of setting the voltage at the node 411 from the voltage V _r2 to the voltage higher V _r1 than the voltage V _r2.

[0262] At time t _3, when the voltage V _C is the voltage V _C reaches the reference voltage V _r2 output from the reference voltage generation circuit 420 during the ascent, the control circuit 415 turns on the switch 414. As a result, the voltage at the connection point 411 rises along the AC voltage waveform (C).

[0263] At time t _4, when the voltage V _C is the voltage V _C reaches the reference voltage V _r1 output from the reference voltage generation circuit 420 during the ascent, the control circuit 415 turns off the switch 414. In this way, the capacitance component in the load 410 is charged adiabatically. The operation up to this point is the same as that of A
The operation is the same as that of the power supplies 204 and 205 of the C-AC type.

At time t ₄ , when setting the voltage at node 411 from voltage V _r1 to voltage V _r2 , it is efficient to use AC voltage waveform (B) instead of AC voltage waveform (C). It is. Connection point 4 along the AC voltage waveform (C)
In order to lower the 11 voltage must wait to turn on the switch 414 to the time t _5. In contrast, the use of AC voltage waveform (B), at an early time t ₄ to time t ₅ is because it is possible to turn on the switch 413. As described above, the use of the AC voltage waveform (B) makes it possible to increase the operating frequency.

Generally, when a plurality of AC voltage waveforms respectively generated by different circuits are used, it is necessary to adjust the phase between the AC voltage waveforms. On the other hand, according to the power supply device 206, the AC voltage waveforms (A) to
There is no need to adjust the phase between (C). This is because the phase of the AC voltage waveform (B) is set between the AC voltage waveform (A) and the AC voltage waveform (C) due to the nature of the cascade connection of the LC resonance circuit.

FIG. 24A shows voltage waveforms obtained at each connection point when capacitance values C _{1 to} C ₃ are set so as to satisfy the relationship of C ₁ , C ₂ << C ₃ . Connection point 1222
, An AC voltage waveform (A) is obtained.
, An AC voltage waveform (B) is obtained at connection point 1226
A DC voltage waveform (C) is obtained.

FIG. 24B shows voltage waveforms obtained at each connection point when capacitance values C _{1 to} C ₃ are set so as to satisfy the relationship of C ₁ , C ₃ << C ₂ . Connection point 1222
, An AC voltage waveform (A) is obtained.
A DC voltage waveform (B) is obtained at connection point 1226
, An AC voltage waveform (C) is obtained.

As described above, by appropriately combining the capacitance values C _{1 to} C ₃ , various types of voltage waveforms can be generated.

Table 1 summarizes combinations of voltage waveforms obtained at connection points 1222, 1224, and 1226, respectively.

Table 1

[0271]

[Table 1] 9. The energy reuse type power supply device 200 of the power supply device 200 is roughly classified into the following five types (1) to (5) from the viewpoint of energy reuse. (1) Energy recycling AC type: At least a part of the energy of the AC voltage supplied from one of the connection points 222 and 224 of the energy storage circuit 220 is supplied to the energy storage circuit 220 via the same connection point. It is a type that reuses energy by returning it. (2) Energy recycling DC type: At least a part of the energy of the DC voltage supplied from one of the connection points 222 and 224 of the energy storage circuit 220 is supplied to the energy storage circuit 220 via the same connection point. It is a type that reuses energy by returning it. (3) Energy reuse AC-AC type: At least a part of the energy of the AC voltage supplied from one of the connection point 222 and the connection point 224 of the energy storage circuit 220 is transferred to the energy storage circuit via the other connection point. 22
This is a type in which energy is reused by returning the energy of the AC voltage to 0. (4) Energy reuse AC-DC type: At least a part of the energy of the AC voltage supplied from one of the connection point 222 and the connection point 224 of the energy storage circuit 220 is transferred to the energy storage circuit via the other connection point. 22
This is a type in which energy is reused by returning the energy of the DC voltage to zero. (5) Energy reuse DC-AC type: At least a part of the energy of the DC voltage supplied from one of the connection point 222 and the connection point 224 of the energy storage circuit 220 is transferred to the energy storage circuit via the other connection point. 22
This is a type in which energy is reused by returning the energy of the AC voltage to 0. 9.1 Energy Recycling AC Type Power Supply Power supply 204 of the AC-AC type shown in FIG. 19A
Corresponds to an energy-reuse AC type power supply device 1201. When the AC voltage waveform (A) (see FIG. 19B) supplied from the connection point 222 of the energy storage circuit 220 is rising, energy is supplied from the energy storage circuit 220 to the load 280, and the AC voltage waveform (A) If the load 280 is descending,
This is because energy is returned to the energy storage circuit 220 from. Connection point 224 of energy storage circuit 220
The same applies to the AC voltage waveform (B) supplied from the power supply.

As described above, the loads 280 and 290
Charge stored in the capacitance component of the energy storage circuit 22
By returning to zero, energy is reused.
This makes it possible to charge and discharge the load 280 and the load 290 with a small energy loss. 9.2 Energy Reuse DC Type Power Supply FIG. 25A shows an energy reuse DC type power supply 1
2 shows a configuration of the embodiment 202. The load 310 is connected to the power supply device 1202 at a connection point 224. Load 310
Includes a capacitance component C ₃ and switch 312 and the switch 313.

The power supply 1202 supplies a DC voltage waveform to the load 310 via the connection point 224. Power supply 12
The energy supplied from 02 through the connection point 224 is stored in the capacitive component C ₃ of the load 310. Load 31
At least a part of the energy stored in the zero capacitance component C ₃ is returned to the power supply device 1202 via the connection point 224. Thereby, energy is reused.

The power supply device 1202 comprises an energy supply circuit 210 and an energy storage circuit 220 which are basic components.
, A control circuit 271, a comparator 272,
It further includes a reference voltage generation circuit 273 and a control circuit 314. In the example shown in FIG. 25A, the energy supply circuit 210 employs the configuration shown in FIG. 6A.
However, as the configuration of the energy supply circuit 210, any of the configurations shown in FIGS. 6A to 6D and FIG. 58A may be adopted. Figure 1 as a means to adjust dynamic energy
The configuration shown in FIGS. 1A, 11B, and 13A may be adopted.

The capacitance value C ₁ and the capacitance value C ₂ are set so as to satisfy the relationship of C ₁ >> C ₂ . As a result, an AC voltage waveform is obtained at the connection point 222 and the connection point 224 is obtained.
A DC voltage waveform is obtained.

FIG. 25B shows an AC voltage waveform (A) at node 222, a DC voltage waveform (B) at node 224, and a voltage waveform (C) at node 311.

Hereinafter, the operation of power supply device 1202 will be described.

The comparator 272 compares the voltage at the connection point 224 with the voltage V _P output from the reference voltage generation circuit 273, so that the voltage at the connection point 224 becomes the voltage V _P.
Is detected. If the voltage at the node 224 is greater than or equal to voltage V _P, the output signal of the comparator 272 is at H level, when the voltage at the node 224 is lower than the voltage V _P, the output signal of the comparator 272 is L level It is.

At time t = 0, switch 312 is off and switch 313 is on. Therefore, the voltage at the connection point 311 of the load 310 is set to the ground voltage GND.

At time t ₁ , control circuit 314 turns on switch 312 and turns off switch 313. As a result, the voltage at the node 311 is charged toward the power supply voltage V _DD . In the period from time t ₁ to time t ₂ , the voltage at the connection point 311 increases, and the charge stored in the capacitance component C ₃ of the load 310 is returned to the energy storage circuit 220 via the connection point 224.

At time t ₃ , control circuit 314 turns off switch 312 and turns on switch 313. As a result, the voltage at the connection point 311 is charged toward the ground voltage GND. In the period from time t ₃ to time t ₄ , the voltage at the node 311 falls, so that the charge supplied from the energy storage circuit 220 via the node 224 is accumulated in the capacitance component C ₃ of the load 310.

By supplying energy to the load 310, the voltage at the node 224 of the energy storage circuit 220 decreases.

[0283] At time t _4, the voltage at the node 224 falls below the voltage V _P, the output signal of the comparator 272 changes from H level to L level. Control circuit 271
Responds to a change in the output signal of the comparator 272,
The switch 212 is turned on. Thus, the supply of energy to the energy storage circuit 220 is started. As a result, the voltage at the node 224 increases.

[0284] At time t _5, the voltage at the node 224 becomes equal to or higher than the voltage V _P, the output signal of the comparator 272 changes from L level to H level. Control circuit 271
Responds to a change in the output signal of the comparator 272,
The switch 212 is turned off. Thus, the supply of energy to the energy storage circuit 220 ends.

The voltage at the connection point 311 of the load 310 is controlled so as to increase from the ground voltage GND to the power supply voltage V _DD or to decrease from the power supply voltage V _DD to the ground voltage GND. When the voltage at the node 311 of the load 310 increases, the electric charge stored in the capacitance component C ₃ of the load 310 is returned to the energy storage circuit 220 via the node 224. When the voltage at the node 311 of the load 310 decreases, the electric charge supplied from the energy storage circuit 220 via the node 224 is accumulated in the capacitance component C ₃ of the load 310.

As described above, the charge stored in the capacitance component C ₃ of the load 310 is returned to the energy storage circuit 220, so that the energy is reused. This allows
The load 310 can be charged and discharged with a small energy loss. 9.3 Energy Recycling AC-AC Type Power Supply FIG. 26A shows a configuration of an energy recycling AC-AC type power supply 1203. The configuration of the power supply 1203 is the same as that of the AC-AC type power supply 2 shown in FIG. 20A.
05 is the same as that of FIG. The load 300 is connected to the connection point 222.
And a connection point 224 are connected to the power supply device 1203. The load 300 is composed of the capacitance component C ₃ and the switch 302.
And a switch 303. The configuration shown in FIGS. 11A, 11B and 13A may be adopted as a means for adjusting the dynamic energy.

The power supply device 1203 supplies an AC voltage waveform to the load 300 via the connection point 222, and supplies an AC voltage waveform to the load 300 via the connection point 224. Energy from the power supply device 1203 is supplied through the connection point 224 is stored in the capacitance component C ₃ of the load 300. Load 3
At least a part of the energy stored in the capacity component C ₃ of the power supply device
Is returned to. Thereby, energy is reused.

FIG. 26B shows an AC voltage waveform (A) at node 222, an AC voltage waveform (B) at node 224, and a voltage waveform (C) at node 301. The AC voltage waveform (A) and the AC voltage waveform (B) have substantially the same amplitude as the vibration center, but differ in phase by 180 degrees.

Hereinafter, the operation of power supply device 1203 will be described.

[0290] At time t = 0, the connection point 301 of the load 300 is assumed to be charged to the voltage V _1. The switch 302 is off and the switch 303 is off.

At time t ₁ , while the AC voltage waveform (B) is rising, the voltage at node 224 is
When the voltage reaches ₁ (that is, the voltage V ₁ ), the output signal of the comparator 307 changes from H level to L level. The control circuit 304 turns on the switch 303 in response to a change in the output signal of the comparator 307. Thereby, the connection point 3 along the AC voltage waveform (B)
01 voltage changes.

The comparator 306 compares the voltage at the connection point 301 with the voltage V _r2 output from the reference voltage generation circuit 308, so that the voltage at the connection point 301 becomes the voltage V _r2.
Is detected.

At time t ₂ , when the voltage at node 301 reaches voltage V _r2 , the output signal of comparator 306 changes from L level to H level. Control circuit 304
Responds to a change in the output signal of the comparator 306,
The switch 303 is turned off. Thus, the voltage at the connection point 301 is maintained at the voltage _Vr2 .

At time t ₃ , while the AC voltage waveform (A) is falling, the voltage at node 222 is
When the voltage reaches 1 (that is, V _r2 ), the output signal of the comparator 305 changes from L level to H level. The control circuit 304 turns on the switch 302 in response to a change in the output signal of the comparator 305.
Thus, the connection point 301 along the AC voltage waveform (A)
Voltage changes.

The comparator 306 compares the voltage at the connection point 301 with the voltage V _r1 output from the reference voltage generation circuit 308 to make the voltage at the connection point 301 equal to the voltage V _r1.
Is detected. As described above, the reference voltage generation circuit 308 switches and outputs the voltage V _r1 and the voltage V _r2 at a predetermined timing.

At time t ₄ , when it is detected that the voltage at node 301 has reached voltage V _r1 , the output signal of comparator 306 changes from H level to L level.
The control circuit 304 turns off the switch 302 in response to a change in the output signal of the comparator 306. Thus, the voltage at the connection point 301 is maintained at the voltage _Vr1 .

In the period from time t = 0 to time t ₁ , there is no energy transfer between energy storage circuit 220 and load 300. During this period, the switch 302 and the switch 303 are both in the off state, and the energy storage circuit 220 and the load 300 are electrically separated.

In the period from time t ₁ to time t ₂ , load 300 is connected from energy storage circuit 220 through connection point 224.
Is supplied with energy. During this period, switch 30
2 is in the OFF state and the switch 303 is in the ON state. As a result, the connection point 30 of the load 300
1 rises.

In the period from time t ₂ to time t ₃ , there is no energy transfer between energy storage circuit 220 and load 300. During this period, the switch 302 and the switch 303 are both in the off state, and the energy storage circuit 220 and the load 300 are electrically separated.

In the period from time t ₃ to time t ₄ , load 30
0 to the energy storage circuit 220 via the connection point 222
Energy is returned to During this period, switch 302
Is in the ON state, and the switch 303 is in the OFF state. As a result, the connection point 301 of the load 300
Voltage drops.

Thus, the energy storage circuit 22
At least a part of the energy supplied from 0 to the load 300 via the connection point 224 is returned from the load 300 to the energy storage circuit 220 via the connection point 222, whereby the energy is reused. This makes it possible to charge and discharge the load 300 with a small energy loss. Note that the relationship between the capacitance value C ₁ and the capacitance value C ₂ is as follows:
C ₁ > C ₂ may be satisfied, and C ₁ <C ₂ may be satisfied. 9.4 Energy Reuse AC-DC Type Power Supply FIG. 27A shows the configuration of an energy reuse AC-DC type power supply 1204. The load 320 is connected to the connection point 22
2 and a connection point 224 are connected to the power supply device 1204. The load 320 is composed of the capacitance component C ₃ and the switch 32.
3-326. The configuration shown in FIGS. 11A, 11B and 13A may be adopted as a means for adjusting the dynamic energy.

The power supply device 1204 supplies an AC voltage waveform to the load 320 via the connection point 222, and supplies a DC voltage waveform to the load 320 via the connection point 224. Energy supplied from the power supply 1204 via the node 222 is stored in the capacitance component C ₃ of the load 320. Load 3
At least a part of the energy stored in the capacitance component C ₃ of the power supply device 1204 via the connection point 224
Is returned to. Thereby, energy is reused.

The power supply device 1204 includes an energy supply circuit 210 and an energy storage circuit 220 which are basic components.
, A control circuit 271, a comparator 272,
It further includes a reference voltage generation circuit 273, a control circuit 327, a comparator 328, a comparator 329, and a reference voltage generation circuit 330. In the example illustrated in FIG. 27A, the energy supply circuit 210 employs the configuration illustrated in FIG. 6A. However, the energy supply circuit 21
As the configuration of 0, any configuration shown in FIGS. 6A to 6C may be adopted.

The capacitance value C ₁ and the capacitance value C ₂ are set so as to satisfy the relationship of C ₁ >> C ₂ . As a result, an AC voltage waveform is obtained at the connection point 222 and the connection point 224 is obtained.
A DC voltage waveform is obtained.

FIG. 27B shows the AC voltage waveform (A) at node 222, the DC voltage waveform (B) at node 224, the voltage waveform (C) at node 321 and the voltage waveform (D) at node 322. Show.

Hereinafter, the operation of power supply device 1204 will be described.

[0307] At time t = 0, the connection point 321 of the load 320 is assumed to be charged to the voltage V _1. Switches 323 to 325 are off, and switch 326 is on.

At time t ₁ , while the AC voltage waveform (A) is rising, the voltage at the node 222
When the voltage reaches ₁ (that is, the voltage V ₁ ), the output signal of the comparator 328 changes from H level to L level. The control circuit 327 turns on the switch 323 in response to a change in the output signal of the comparator 328. Thereby, the connection point 3 along the AC voltage waveform (A)
The voltage at 21 changes.

The comparator 329 calculates the voltage of the connection point 321 and the power supply voltage V output from the reference voltage generation circuit 330.
By comparing the _DD, the voltage at the node 321 detects whether the host vehicle has reached the power supply voltage V _DD.

At time t ₂ , when the voltage at node 321 reaches power supply voltage V _DD , the output signal of comparator 329 changes from L level to H level. Control circuit 32
7 turns off the switch 323 in response to a change in the output signal of the comparator 329, and
24 is turned on. As a result, the voltage at the node 321 changes toward the voltage at the node 224 (that is, the voltage _VP ).

[0311] At time t _3, the voltage at the node 321 reaches the voltage V _P.

During the period from time t ₁ to time t ₂ , the load 320
Is supplied with energy. Energy storage circuit 220
Supplied from the load 320 is the capacitance component C of the load 320.
Stored in ₃ . During the period of time t ₃ from the time t _2, the energy storage circuit 2 from the load 320 via the node 224
Energy is returned to 20.

As described above, at least a part of the energy supplied from the energy storage circuit 220 to the load 320 via the connection point 222 is transferred from the load 320 to the connection point 22.
The energy is reused by returning to the energy storage circuit 220 via 4. This makes it possible to charge and discharge the load 320 with a small energy loss.

At time t ₄ , while the AC voltage waveform (A) is falling, the voltage at node 222 changes to node 32
When the voltage reaches 1 (that is, the voltage _VP ), the output signal of the comparator 328 changes from the L level to the H level. The control circuit 327 turns on the switch 323 in response to a change in the output signal of the comparator 328,
At the same time, the switch 324 is turned off. This allows
The voltage at the connection point 321 changes along the AC voltage waveform (A).

[0315] At time t _5, the voltage at the node 321 when it has reached the voltage V _r1 is detected, the output signal of the comparator 329 changes from H level to L level.
The control circuit 327 turns off the switch 323 in response to a change in the output signal of the comparator 329, and
The switch 324 is turned on. The control circuit 32
7 turns on the switch 325 in response to a change in the output signal of the comparator 329, and
26 is turned off. As a result, the voltage at the node 321 changes toward the voltage at the node 224 (that is, the voltage _VP ).

[0316] At time t _6, the voltage at the node 321 reaches the voltage V _P.

In the period from time t ₄ to time t ₅ , load 32
0 to the energy storage circuit 220 via the connection point 222
Energy is returned to During the period of time t ₆ from the time t _5, the energy is supplied to the load 320 from the energy preserving circuit 220 via the node 224. The energy supplied from the energy storage circuit 220
It is stored in the capacitance component C _3.

As described above, at least part of the energy supplied from the energy storage circuit 220 to the load 320 via the connection point 224 is transferred from the load 320 to the connection point 22.
The energy is reused by being returned to the energy storage circuit 220 via 2. This makes it possible to charge and discharge the load 320 with a small energy loss.

By supplying energy to the load 320, the connection point 224 of the energy storage circuit 220 is supplied.
Voltage decreases. In the example shown in FIG. 27B, the voltage at the node 224 is below the voltage V _P at time t _2.
When the voltage at the node 224 falls below the voltage V _P, the output signal of the comparator 272 changes from H level to L level. The control circuit 271 turns on the switch 212 for a predetermined period in response to a change in the output signal of the comparator 272. As a result, the voltage at the connection point 224 increases. 9.5 Energy Reuse DC-AC Type Power Supply FIG. 28A shows a configuration of an energy reuse DC-AC type power supply 1205. The load 350 is connected to the power supply 1
205 is provided between the connection point 224 and the connection point 351. The load 360 is provided between the connection point 351 and the ground. The connection point 351, the capacitance component C ₃ is connected.

The power supply 1205 supplies a DC voltage waveform to the load 350 via the connection point 224. Power supply 12
Energy supplied via the node 224 from the 05 is accumulated in the capacitance component C _3. At least some of the energy stored in the capacitance component C ₃ is returned to the power supply 1205 via the node 222. Thereby, energy is reused.

The power supply device 1205 comprises an energy supply circuit 210 and an energy storage circuit 220 which are basic components.
, A control circuit 271, a comparator 272,
Reference voltage generation circuit 273, switch 352, control circuit 353, comparator 354, comparator 35
5 and a reference voltage generation circuit 356.
In the example shown in FIG. 28A, the energy supply circuit 21
0 adopts the configuration shown in FIG. 6A. However, as a configuration of the energy supply circuit 210, FIGS.
58A may be adopted.
11A and 11 as means for adjusting dynamic energy.
B, the configuration shown in FIG. 13A may be adopted.

The capacitance value C ₁ and the capacitance value C ₂ are set so as to satisfy the relationship of C ₁ >> C ₂ . As a result, an AC voltage waveform is obtained at the connection point 222 and the connection point 224 is obtained.
A DC voltage waveform is obtained.

FIG. 28B shows an AC voltage waveform (A) at node 222, a DC voltage waveform (B) at node 224, and a voltage waveform (C) at node 351.

The operation of power supply device 1205 will be described below.

In the period from time t = 0 to time t ₁ , the load 3 is supplied from the energy storage circuit 220 via the connection point 224.
Charge is supplied to 50. As a result, the voltage at the node 224 gradually decreases. Some of the charge that has passed through the load 350 reaches the ground through the load 360. The remaining charge is accumulated in the capacitance component C _3. As a result, the voltage of the connection point 351 gradually increases.

[0326] At time t _1, the voltage at the node 224 falls below the voltage V _P, the output signal of the comparator 272 changes from H level to L level. Control circuit 271
Responds to a change in the output signal of the comparator 272,
During from time t ₁ of time t _2, the the switch 212 to the ON state. As a result, energy is supplied from the energy supply circuit 210 to the energy storage circuit 220.
As a result, the voltage at the connection point 224 increases.

In the period from time t ₂ to time t ₃ , no energy is supplied from energy supply circuit 210 to energy storage circuit 220. As a result, the voltage at the node 224 gradually decreases.

At time t ₃ , while the AC voltage waveform (A) is falling, the voltage at the node 222 is
When the voltage reaches 1, the output signal of the comparator 354 changes from L level to H level. Control circuit 353
Responds to a change in the output signal of the comparator 354,
The switch 352 is turned on. Thereby, the voltage at the connection point 351 changes along the AC voltage waveform (A).

In the period from time t ₃ to time t ₄ , the electric charge accumulated in the capacitance component C ₃ is transferred to the switch 352 and the node 2
It is returned to the energy storage circuit 220 via 22.

[0330] At time t _4, the voltage at the node 351 reaches a voltage V _r, the output signal of the comparator 355 changes from H level to L level. Here, the reference voltage generation circuit uses the voltage _Vr as a reference voltage to set the comparator 35
5 is output. The control circuit 353 includes the comparator 3
The switch 352 is turned off in response to the change of the output signal at 55.

In the period from time t ₄ to time t ₅ , energy is not supplied from the energy supply circuit 210 to the energy storage circuit 220, so that the voltage at the connection point 224 gradually decreases, and the electric charge accumulated in the capacitance component C ₃ is reduced. Since the voltage is not returned to the energy storage circuit 220, the voltage at the node 351 gradually increases. The decrease in the voltage at the connection point 224 starts to increase when energy is supplied from the energy supply circuit 210 to the energy storage circuit 220. The rise of the voltage at the connection point 351 starts to fall when the electric charge accumulated in the capacitance component C ₃ is returned to the energy storage circuit 220. In this manner, both the voltage at node 224 and the voltage at node 351 are maintained near the desired voltage.

In the example shown in FIG. 28A, the connection point 22
A load 350 is provided between the connection point 4 and the connection point 351, and a load 360 is provided between the connection point 351 and the ground. In addition to the load 350 and the load 360, the connection point 22
Another load may be provided between the ground 4 and the ground.
Alternatively, the load 3 is connected between the connection point 224 and the connection point 351.
50, and a load 360 may be provided between the connection point 224 and the ground. Alternatively, only the load 350 may be provided without providing the load 360. 10. Application of the present invention to a voltage converter Hereinafter, a case where the present invention is applied to a voltage converter (DC / DC converter) will be described. (Embodiment 1) FIG. 29 shows a voltage converter 2 according to the present invention.
0 is shown. The voltage converter 20 converts a voltage supplied from the power supply 1 into another voltage, and supplies the other voltage to the voltage supply circuit (load) 2, and a load 2.
Power 1 substantially equal to the power consumed by
And a control unit 130 for controlling the voltage conversion unit 3 so as to supply the voltage to the voltage conversion unit 3. Power supply 1 is connected to terminal 2
1 is connected to the voltage converter 20. Load 2
Are connected to the voltage converter 20 at a terminal 22.

The control unit 130 outputs the signals from the drive circuit 4 for opening and closing the switch 26 (not shown in FIG. 29; see FIG. 30) included in the voltage conversion unit 3 and the detectors 8, 15 and 18. And a synchronous circuit 5 that determines the open / closed state of the switch 26 based on the signal.

The control unit 130 includes a clock generator 6 for generating a clock pulse defining an operation cycle of the voltage conversion unit 3 and a clock detector 7 for detecting a clock pulse output from the clock generator 6. In addition.

The control unit 130 is connected to the terminal 3e of the voltage conversion unit 3.
Detector 8 for comparing the voltage output from the device with the target voltage
A reference voltage generator 9 for generating a target voltage; a detector 8 and a reference voltage generator 9 based on a control clock pulse and a clock pulse output from the clock generator 6.
And a synchronizing circuit 10 for controlling the operation timing. The control clock pulse is supplied to the synchronization circuit 10 via the terminal 23. Further, a signal indicating the target voltage is supplied to the reference voltage generator 9 via the terminal 25.

The control unit 130 is connected to the terminal 3e of the voltage conversion unit 3.
11 for comparing the voltage output from the sensor with the initial voltage
A reference voltage generator 12 for generating an initial voltage; a detector 11 and a reference voltage based on a start signal, a control clock pulse, a signal output from the synchronization circuit 5, and a signal output from the clock detector 7. And a synchronization circuit for controlling the operation timing of the generator. The start signal is supplied to the synchronization circuit 13 via the terminal 24. The control clock pulse is supplied to the synchronization circuit 13 via the terminal 23.

The control unit 130 generates a voltage defining the timing at which the state of the switch 26 (not shown in FIG. 29; see FIG. 30) included in the voltage conversion unit 3 changes from the open state to the closed state. A reference voltage generator 14, a detector 15 for comparing a voltage output from the reference voltage generator 14 with a voltage output from a terminal 3c of the voltage converter 3, a control clock pulse and an output from the clock generator 6, It further includes a synchronization circuit 16 for controlling the operation timing of the reference voltage generator 14 and the detector 15 based on the clock pulse to be generated. The control clock pulse is applied to terminal 23
Is supplied to the synchronizing circuit 16.

The control unit 130 generates a voltage that defines the timing at which the state of the switch 26 (not shown in FIG. 29; see FIG. 30) included in the voltage conversion unit 3 changes from the closed state to the open state. A reference voltage generator 17, a detector 18 for comparing a voltage output from the reference voltage generator 17 with a voltage output from a terminal 3c of the voltage converter 3, a control clock pulse and an output from the clock generator 6, It further includes a synchronization circuit 19 for controlling the operation timing of the reference voltage generator 17 and the detector 18 based on the clock pulse to be generated. The control clock pulse is applied to terminal 23
Is supplied to the synchronizing circuit 19.

FIG. 30 shows the structure of the voltage converter 3. The voltage converter 3 has terminals 3a to 3e. Terminal 3a
Is connected to the power supply 1 via the terminal 21. Terminal 3b
Are connected to the drive circuit 4. The terminal 3c is connected to the detector 15
, Detector 18 and clock generator 6. The terminal 3d is connected to the load 2 via the terminal 22. Terminal 3
e is connected to the detector 8 and the detector 11.

The voltage conversion section 3 includes a resonance circuit 140 and a switch 26 for electrically connecting the power supply 1 and the resonance circuit 140.
And

The switch 26 can be, for example, a PMOS transistor.

The resonance circuit 140 includes an inductor 28 and capacitors 27 and 29.

One end of the inductor 28 and the capacitor 27 are connected at a connection point 3f. The connection point 3f is connected to the terminal 3c. In the following description, the connection point 3f and the terminal 3c are treated as the same. The switch 26 is connected to the resonance circuit 14
0 is connected to the connection point 3f.

The other end of the inductor 28 and the capacitor 29 are connected at a connection point 3g. The connection point 3g is connected to the terminals 3d and 3e. In the following description, the connection point 3g, the terminal 3d, and the terminal 3e are treated as the same.

A signal for controlling the open / close state of the switch 26 is input to the terminal 3b.

Hereinafter, the operation of the voltage conversion unit 3 will be described. This
Here, the capacitance values of the capacitors 29 and 27 are represented by C ₁, C_TwoAnd in
The inductance value of the ductor 28 is represented by L.

In the resonance circuit 140, part of the electric charge stored in the capacitor 29 is transmitted to the capacitor 27 via the inductor. Further, the electric charge transmitted to the capacitance 27 is transmitted again to the capacitance 29 via the inductor 28. As described above, the electric charge is transferred between the capacitance 27 and the capacitance 29 by the inductor 28.
Is exchanged via

FIG. 31 shows a state in which the switch 26 is open.
5 shows an equivalent circuit of the resonance circuit 140 when the load 2 is not connected to the terminal 3d. When the switch 26 is open and the load 2 is not connected to the terminal 3d, the currents flowing through the capacitors 27 and 29 are in opposite directions and have the same magnitude. From this, (Equation 1) holds.

C ₁ · (dv _g (t)) / (dt) + C ₂ · (dv _f (t)) / (dt) = 0 (Equation 1) where v _f (t), v _g (t) represents the voltages of the terminals 3f and 3g at time t, respectively.

The terminal voltage of the inductor 28 is represented by (Equation 2).

V _g (t) −v _f (t) = L · (di) / (dt) (Expression 2) Here, i represents a current flowing through the inductor 28, and the current flows from the terminal 3g to the terminal 3f. The flowing current was defined as a positive sign. Further, the current i flowing through the inductor 28 is equal to the current flowing through the capacitor 27. From this, (Equation 3) holds.

I = C ₂ · (dv _f (t)) / (dt) (Equation 3) By calculating (Equations 1) to (Equation 3), the voltages v _f (t) and v
_By rearranging _g (t), (Equation 4) and (Equation 5) are obtained.

[0353]

(Equation 1) In order to make (Equation 4) and (Equation 5) easy to understand, conditions of (Equation 6) to (Equation 8) are introduced in consideration of actual design values.

[0354] C ₁ >> C ₂ ··· (Equation _{6) C 2 / C 1 ·} v f (0) ≒ 0 ··· ( Equation _{7) C 2 / C 1 ·} (v g (0) -v _f (0)) ≒ 0 (Equation 8) When the conditions of (Equation 6) to (Equation 8) are applied to (Equation 4) and (Equation 5), (Equation 4) and (Equation 5) become Equations 9) and 10 are simplified.

[0355]

(Equation 2) Here, v _f (0) and v _g (0) represent voltages at terminals 3f and 3g at time t = 0. i (0) represents the inductance current i at time t = 0. Further, α is (Equation 1
1).

[0356]

(Equation 3) When the conditions of (Equation 6) to (Equation 8) are applied to (Equation 11),
(Equation 11) is simplified as shown in (Equation 12).

[0357]

(Equation 4) It is understood from (Equation 9) that the voltage v _f (t) at the terminal 3f is represented by an AC component of the first term and a DC component of the second term represented by a cosine function. The frequency f _{R of the} AC component is obtained from the coefficient (angular velocity) of the cosine function at time t. That is, the frequency f _{R of the} AC component is represented by (Equation 13).

F _R = 1 / (2π√ (LC ₂ )) (Expression 13) The amplitude A _{f of the} AC component is a coefficient of a cosine function. That is, the amplitude A _{f of the} AC component is represented by (Equation 14).

[0359] From _{A f = v f (0)} -v g (0) + i (0) / C 2 ··· ( Equation 14) (Equation 10), at a voltage v _g (t) is a cosine function of the terminal 3g It is understood that the AC power is represented by the AC component of the first term and the DC component of the second term. Voltage v at terminal 3g
The frequency of the AC component of _g (t) is the voltage v _f (t) of terminal 3f.
Equal to the frequency of the AC component.

The amplitude A _{g of the} AC component is a coefficient of the cosine function. That is, the amplitude A _g of the alternating-current component is represented by (Equation 15).

A _g = (i (0) / C ₁ ) √ (LC ₂ ) (Equation 15) In an actual design, the condition of (Equation 16) can be applied.

[0362] v from _{f (0) -v g (0} ), i (0) / C 2 >> i (0) / C 1 ··· ( Equation 1 6) (Equation 16), the terminal 3f, 3g of It can be seen that the following relationship exists between the amplitudes of the AC components of the voltage.

A _f >> A _g (Equation 17) In an actual design, the amplitude of the terminal 3g is one of the amplitude of the terminal 3f.
/ 50 to 1/100.

For example, assume that the voltage supplied from the power supply to be converted is 3 V, and the voltage output from voltage converter 20 is 1.5 V. C ₁ = 50 [μF], C ₂ = 5 [μF], L =
According to the simulation result at 100 [nH], the voltage amplitude at the terminal 3f is 1.5 V, and the voltage amplitude at the terminal 3g is 20 mV. The frequency was 500 [kHz]. Therefore, the amplitude of the voltage at terminal 3g is
1/75 of the amplitude of the voltage.

Thus, the AC component of the voltage v _f (t) at the terminal 3f has a large amplitude. On the other hand, the AC component of the voltage v _g (t) of the terminal 3g is found to have a small amplitude enough to be almost negligible when compared with the terminal 3f of the voltage v _f (t).

The DC component of the voltage v _f (t) at the terminal 3f is approximately equal to the DC component of the voltage v _g (t) at the terminal 3g.
As an example, if the voltage (voltage of the terminal _g v g (t)) and 1.5V output from the voltage converter 20, the DC component of the voltage v _f (t) of the terminal 3f is 1.5V. Therefore, the voltage v _f (t) of the terminal 3f is 3V around 1.5V.
It turns out that it vibrates from 0 to 0V.

In FIG. 34, a curve a indicates a change in the voltage of the terminal 3f. The curve a has a cosine wave oscillation after the time tss. Here, the cosine wave is attenuated with time because the load 2 is connected to the output terminal 22 of the voltage converter 20.

In the discussion already made with reference to FIG. 31, since it is assumed that the load 2 is not connected to the output terminal 22 of the voltage converter 20, (Equation 4) and (Equation 5) No terms appeared. Actually, since the load 2 is connected to the output terminal 22 of the voltage converter 20, (Equation 4)
An attenuation term occurs in (Equation 5). This is because a current starts flowing from the voltage converter 20 through the load 2.

As shown in FIG. 34, the cosine wave is attenuated. In Figure 34, V _DD denotes the voltage of the conversion source 1, V _P represents the output voltage of interest.

Next, the control of the opening / closing operation of the switch (PMOS transistor) 26 of the voltage converter 3 will be described in detail with reference to FIGS.

First, the operation of the voltage converter 20 will be described with reference to FIG.

The start signal is input to the voltage converter 20 via the terminal 24. The start signal is the voltage converter 20
Before input to the reference voltage generator 12 and the detector 1
1 does not consume current. Thus, the reference voltage generator 1
2 and the operation in which the detector 11 does not consume current is called sleep.

In response to the start signal, the operation of reference voltage generator 12 shifts from sleep to reference voltage output.
The reference voltage output period, the reference voltage generator 12 starts operating and outputs the reference voltage V _S (the voltage V _S in FIG. 34) to the detector 11.

In response to the start signal, the operation of the detector 11 shifts from sleep to set. The set period, the detector 11, the reference voltage V _S output from the reference voltage generator 12 and the sampling hold.

In response to the start signal, the state of the switch 26 changes from the open state (OFF) to the closed state (ON).

After outputting the reference voltage V _S to the detector 11,
The operation of the reference voltage generator 12 returns to sleep from the reference voltage output.

After sampling and holding the reference voltage V _S , the operation of the detector 11 shifts from set to detection. In the detection period, the detector 11 by comparing the voltage with the reference voltage V _S of the terminal 3e of the voltage conversion section 3 (the terminal d, the same as g), or the voltage at the terminal 3e is higher than the reference voltage V _S Detect whether or not.

When the detector 11 detects that the voltage at the terminal 3e is higher than the reference voltage V _S , the detector 11 outputs a pulse signal (the output signal in FIG. 32). After outputting the output signal, the operation of the detector 11 returns from detection to sleep.

In response to the output signal, the state of the switch 26 changes from the closed state (ON) to the open state (OFF).

Next, referring to FIG. 34, voltage converter 20
Will be described. In FIG. 34, a waveform a indicates a voltage change at the terminal 3c of the voltage conversion unit 3, and a waveform b indicates a voltage change at the terminal 3e of the voltage conversion unit 3.

A start signal is input to voltage converter 20. Thereby, the operation of the voltage converter 20 is started.
At time t _s, the state is in the open state of the switch 26 (OF
The state changes from F) to the closed state (ON).

During the period from time t _s to time t _e , the voltages at terminals 3c and 3e of voltage converter 3 rise to reference voltage V _S (initial voltage of voltage converter 20). This period is called a setup period. In the set-up period, the voltage of the terminal 3c (shown by a waveform a in FIG. 34) and the voltage of the terminal 3e (shown by a waveform b in FIG. 34) increase according to the condition of (Equation 6). The voltage at the terminal 3c rises more rapidly than the voltage at the terminal 3e.

It is assumed that the load 2 is not connected to the terminal 3d of the voltage converter 3 during the period from time t _e to time t _SL . This period is called a hold period. This assumption can be made because the LSI connected to the output terminal 22 of the voltage converter 20 (the terminal 3d of the voltage conversion unit 3) is set immediately after the setup period of the voltage converter 20 ends. This is because it is common to start the operation after a certain period of time has elapsed after the end of the set-up period of the voltage converter 20.

In FIG. 29, the load 2 is represented by using a symbol of a resistor. This is because the operating speed of the LSI connected to the output terminal 22 is sufficiently faster than the operating speed of the voltage converter 20, so that the load of the LSI can be approximately replaced by the load of the resistor. The operation of the voltage converter 20 is about 500 kHz, while the operation of the LSI is generally 20 MHz or more.

In the hold period, the terminal 3 of the voltage converter 3
The voltage of d is maintained. This is because the load 2 is not connected to the output terminal 22 of the voltage converter 3. The holding of the voltage of the terminal 3d during the hold period is indicated by the waveform b shown in FIG. 34 being parallel to the horizontal axis during the hold period.

According to (Equation 4) and (Equation 5), the terminal 3
Both the voltage at c (waveform a) and the voltage at terminal 3e (waveform b) start sinusoidal oscillation. Here, the voltage (waveform b) of the terminal 3e also has a sine wave oscillation, but FIG.
The state in which the voltage of e (waveform b) oscillates in a sine wave is not shown. As can be seen from (Equation 17), the amplitude of the voltage (waveform b) at the terminal 3e is sufficiently smaller than the amplitude of the voltage (waveform a) at the terminal 3c.

The amplitude of the voltage at the terminal 3c of the voltage conversion unit 3 during the hold period is larger than in other periods. This voltage is the power supply voltage terminal 3c at time t _e the voltage change in the set-up period V _DD
Because it descends more than As a result, the diode formed by the drain region and the well region on the terminal 3f side of the PMOS switch 26 is biased in the forward direction. As a result, the sine wave a is clamped.

After time t _SS , terminal 3f of voltage converter 3
Is not clamped. This corresponds to the transition period (time t
When the voltage at the terminal 3f in the period) from _SL to time t _SS (waveform a) is once clamped, because the amplitude of the voltage (waveform a) of the terminal 3f becomes small thereby to attenuate the vibration energy.

The period after time t _{SS is} called the steady operation period. In the steady operation period, the terminals 3f, 3g of the voltage conversion unit 3
Has a sinusoidal oscillation. However, in the steady operation period, the LSI connected to the output terminal 22 starts operating (because the load 2 is connected), so that the LSI becomes a damped sine wave vibration. As described above, the sine wave vibration is actually attenuated, but if the period is about one cycle of the sine wave vibration, the terminal 3f,
The voltage of 3 g can be regarded as oscillating according to (Equation 4) and (Equation 5). This is because the amount of attenuation is sufficiently small.

[0390] Figure 35 shows a time t ₁ after the waveform a and the waveform b shown in FIG. 34. When the waveforms a and b are observed over one or more periods of the sine wave oscillation in the steady operation period, the amplitudes and the DC components of the sine waves of the waveforms a and b are attenuated. This is because a current flows through the load 2.

FIG. 33 shows the operation of voltage converter 20 during the normal operation period.

FIG. 33 shows the waveform of the resonance clock. The resonance clock is obtained by shaping the sinusoidal oscillation of the terminal 3f of the voltage converter 3 into a clock pulse by the clock generator 6.

In response to the change in the level of the resonance clock from the H level to the L level, the operation of the detector 8 shifts from sleep to sample. In the sampling period, the detector 8
Performs a so-called sampling operation of following and holding the voltage of the terminal 3g of the voltage conversion unit 3. Alternatively, the detector 8
May be started in synchronization with the timing at which the voltage supply circuit (load) 2 operates.

After the end of the sample period, the operation of the detector 8 shifts from the sample to the comparison. In comparison period, the detector 8 compares the desired voltage V _P and the sampled voltage output from the reference voltage generator 9. As a result, when the desired voltage V _P is greater than the voltage that is sampled (i.e., voltage that is sampled is less than the desired voltage V _P), the level of the signal output from the detector 8 L The level changes from the level to the H level. After the end of the comparison period, the operation of the detector 8 returns to sleep.

In synchronization with the operation of the detector 8 shifting from the sample to the comparison, the operation of the reference voltage generator 9 shifts from sleep to voltage output. In the voltage output period, the reference voltage generator 9 outputs a desired voltage _VP to the detector 8. After the end of the power output period, the operation of the reference voltage generator 9 returns to sleep.

When the level of the signal output from detector 8 is H
If so, the operation of the reference voltage generator 14 shifts from sleep to voltage output in response to the change of the level of the resonance clock from L level to H level.
During the voltage output period, the reference voltage generator 14 outputs the reference voltage V
_S is output to the detector 15. The reference voltage V _S is equal to the value of the switch 2
6 is used to determine when to close. After the end of the voltage output period, the operation of the reference voltage generator returns to sleep.

[0397] In synchronization with the operation of the reference voltage generator 14 shifting from sleep to voltage output, the operation of the detector 15 shifts from sleep to set. During the set period,
Detector 15, the reference voltage V _S output from the reference voltage generator 14 and the sampling hold. Thereafter, the operation of the detector 15 shifts from setting to detection. In the detection period, the detector 15 by comparing the voltage at the terminal 3f of the voltage conversion section 3 (waveform of Fig. 35 a) and a reference voltage V _S, the terminal 3
It is detected whether or not the voltage f (waveform a in FIG. 35) has reached the reference voltage V _S. Voltage at terminal 3f (waveform a in FIG. 35)
Reaches the reference voltage V _S (point 1 in FIG. 35),
The level of the signal output from the detector 15 changes from L level to H level. The change in the level of the signal output from the detector 15 is transmitted to the synchronization circuit 5. The synchronous circuit 5 changes the state of the switch 26 from the open state to the closed state in response to the level change of this signal. After the end of the detection period, the operation of the detector 15 returns to sleep.

The level of the signal output from detector 8 is H
If the level is the level, the operation of the reference voltage generator 17 shifts from sleep to voltage output in response to the level of the resonance clock changing from L level to H level.
In the voltage output period, the reference voltage generator 17 outputs the reference voltage V
_C is output to the detector 15. Reference voltage V _C, the switch 2
6 is used to determine when to open. After the end of the voltage output period, the operation of the reference voltage generator 17 returns to sleep.

In synchronization with the operation of the reference voltage generator 17 shifting from sleep to the voltage output, the operation of the detector 18 shifts from sleep to set. During the set period,
The detector 18 samples and holds the reference voltage V _C output from the reference voltage generator 17. Thereafter, the operation of the detector 18 shifts from set to detection. In the detection period, the detector 18 compares the voltage at the terminal 3f of the voltage conversion unit 3 (waveform a in FIG. 35) with the reference voltage V _C to detect the voltage at the terminal 3f.
It is detected whether or not the voltage f (waveform a in FIG. 35) has reached the reference voltage V _C. Voltage at terminal 3f (waveform a in FIG. 35)
Reaches the reference voltage V _C (point 2 in FIG. 35),
The level of the signal output from the detector 18 changes from L level to H level. The change in the level of the signal output from the detector 18 is transmitted to the synchronization circuit 5. The synchronization circuit 5 changes the state of the switch 26 from the closed state to the open state in response to the level change of this signal. After the end of the detection period, the operation of the detector 18 returns to sleep.

[0400] The switch 26 switches the signal level of the detector 1 after the signal output from the detector 15 changes from L level to H level.
8 is closed (ON) until the signal output from L changes from L level to H level, and is open (OFF) in other periods. Thus, the switch 26 is smaller than the voltage V _DD to the voltage at the terminal 3f is supplied from the power source 1, the voltage V _P is greater than the period of interest, it is opened and closed.

The operation of the voltage converter 3 during the above-mentioned steady operation period is summarized as follows.

[0402] When the voltage at the terminal 3g of the voltage conversion section 3 is below a desired voltage V _P is detected by the detecting unit 8, the detector from the detector 8 operation start signal via the synchronization circuit 5 15 and the detector 18. In response to the operation start signal, the operation of injecting charges from the power supply 1 into the voltage conversion unit 3 is started.

The detecting section 15 and the detecting section 18 start their respective operations in response to the operation start signal from the detecting section 8. When the detection unit 15 detects that the voltage at the terminal 3f has reached the reference voltage V _S , the switch 26 is controlled to change from the open state to the closed state. Thereafter, when the detection unit 18 detects that the voltage of the terminal 3f has reached the reference voltage V _C (> reference voltage V _S ), the switch 26
Is controlled to change from the closed state to the open state.

Alternatively, after the switch 26 is controlled to change from the open state to the closed state, the switch 26 may be controlled to change from the closed state to the open state after a predetermined period has elapsed. Alternatively, after the switch 26 is controlled to change from the open state to the closed state, the detection unit 18 detects that the voltage at the terminal 3f has reached the reference voltage V _C (> the reference voltage V _S ), May be controlled so that the switch 26 changes from the closed state to the open state after the elapse of the period.

While the switch 26 is closed, the power supply 1 to be converted and the voltage conversion unit 3 are connected. As a result, electric charges are injected from the power supply to be converted 1 into the voltage conversion unit 3, and power is supplied.

The voltage converter 20 according to the present invention has an advantage that power consumption is extremely small. The reason is described below.

During the period when the switch 26 is in the closed state, a current flows from the power supply 1 to be converted to the voltage conversion unit 3. The current flowing from the converted power supply 1 to the voltage converter 3 flows from the source terminal (the terminal connected to the converted power supply 1) of the PMOS switch 26 to the drain terminal (the terminal connected to the terminal 3f). . A resistor exists between the source terminal and the drain terminal of the PMOS switch 26. Therefore, PM
A voltage is generated between the terminals of the OS switch 26 (between the source terminal and the drain terminal), and power is consumed by a current flowing between the terminals. Such power consumption is conversion energy loss that occurs during voltage conversion. The conversion energy loss rate η _c is defined by (Equation 18).

Η _c = (power consumed between source terminal and drain terminal of PMOS switch 26) / (power consumed by load 2) (Equation 18) A voltage converter with poor conversion efficiency A voltage converter having a large conversion energy loss rate η _c . Conversely, a voltage converter with good conversion efficiency refers to a voltage converter with a small conversion energy loss rate η _c . The denominator of (Equation 18) is constant according to Ohm's law when the resistance value of the load 2 and the converted voltage are constant. Therefore, in order to reduce the conversion energy loss rate η _c , it is necessary to reduce the numerator. PMOS
The voltage generated between the source terminal and the drain terminal of the switch 26 is V _ds , and the current flowing between the terminals is I _d (the direction of the current flowing from the source terminal to the drain terminal is positive).
Then, the power consumption _Pt is expressed by the following equation.

[0409] When the converted voltage between _{P t = V ds · I d} ··· ( 19) the resistance of the load 2 is constant, must current I _d (supply must be supplied (Total charge) is constant. Thus, reducing the power consumption P _t can be achieved by reducing the inter-terminal voltage V _ds.

[0410] The voltage converter 20 oscillates the voltage at the terminal 3f of the voltage converter 3 as shown in FIG.
The PMOS switch 26 is closed by bringing the voltage _VDD of the power supply voltage 1 connected to the source terminal of the MOS switch 26 close to the voltage (waveform a) of the terminal 3f. Power supply voltage 1
Is close to the voltage of the voltage V _DD and the terminal 3f of by closing the PMOS switch 26, it is possible to reduce the power consumption P _t. At such timing PMO
By closing the S switch 26, under the assumption current I _d flowing between the source terminal and the drain terminal of the same,
This is because the voltage V _ds generated between the source terminal and the drain terminal can be reduced.

Furthermore, since the resistance component in the voltage conversion unit 3 is the resistance between the source terminal and the drain terminal of the PMOS switch 26, the power consumption in this part is small as described above. From this point, there is almost no heat generation in the voltage conversion unit 3.

Further, the detector 8 detects the reference voltage V _P (desired voltage) output from the reference voltage generator 9 and the voltage converter 3
When the reference voltage _VP (desired voltage) is lower than the voltage of the terminal 3d as a result of comparison with the voltage of the terminal 3d, the detector 15, the reference voltage generator 14, the synchronization circuit 16,
The detector 18, the reference voltage generator 17, and the synchronization circuit 19 do not operate. For example, the operation in the second cycle shown in FIG. 33 corresponds to this. As described above, the control unit 130 performs a conditional operation, thereby reducing power consumption. Furthermore, in order to reduce power consumption, the operation cycle of the detector 8 and the reference voltage generator 9 may be lengthened when the output current output from the voltage converter 20 is small.

[0413] Further, the voltage converter 20 according to the present invention has the following advantages. Detector 8, reference voltage generator 9, detector 11, reference voltage generator 12, detector 15, reference voltage generator 14, detector 18, and reference voltage generator 1
7 occupies most of the power consumed by the control unit 130 as a whole. In general, the main factors of power consumption in the control circuit system are high precision and / or
Alternatively, high-speed operation is required. For example, in a reference voltage generator, power consumption increases as a more accurate voltage output is required. In the detector, the power consumption increases as the accuracy and speed of the detection are required.
Therefore, in order to reduce power consumption, it is preferable that the control circuit system performs low-accuracy voltage output and low-accuracy and low-speed detection.
Since the resonance frequency of the voltage converter 3 in the voltage converter 20 according to the present invention is about 1 MHz to 500 kHz as described above, the voltage at the terminal 3f of the voltage converter 3 changes very slowly. Therefore, the control unit 130 that controls the voltage conversion unit 3 does not require a high-accuracy and high-speed operation. For example, in the detection of points 1 and 2 in FIG. 35, low speed is sufficient and low-precision detection is sufficient (high-speed operation requires high-precision and high-speed detection).

[0414] In this manner, the power consumption of the control unit 130 can be extremely reduced. In an actual design, it was confirmed that the power consumption of the control unit 130 can be suppressed to 1 mW or less. This means that even if the power consumption of the load 2 becomes 10 mW or less, the control unit 1
This means that the power consumption of the load 30 is only about 10% of the power consumption of the load 2. Since the resonance frequency can be set low, the noise frequency due to the resonance operation can be reduced.

[0415] Figure 53A shows the relationship between the power consumption P _L and the conversion loss P _t of the load in the conventional DC / DC converter.
Figure 53B shows the relationship between the power consumption P _L and the conversion loss P _t of the load in the voltage converter 20 according to the present invention. here,
The conversion loss _Pt is obtained by adding the power consumption P _C of the control system circuit and the power consumption P _S of the voltage converter. That is, _{P t = P C + P S} .

[0416] Figure 54A shows the relationship between the power consumption P _L of the load in the conventional DC / DC converter and the total loss rate eta _Ct. Figure 54B shows the relationship between the power consumption P _L of the load in the voltage converter 20 according to the present invention the total loss rate eta _Ct.
Here, the overall loss rate eta _Ct is obtained by dividing the conversion loss P _t in the power consumption P _L of the load. That is, η _Ct = P _t / P _L = (P _C + P _S ) / P _L.

[0417] Table 2 summarizes the characteristics of the conventional DC / DC converter 61 and the voltage converter 20 according to the present invention.

Table 2

[0419]

[Table 2] Further, the voltage converter 20 according to the present invention has an advantage that on-chip conversion is easy. The reason will be described below.

The value of the inductor 28 of the resonance circuit 140 is 1
About 00nH is sufficient. As described above, since the value of the inductor 28 is sufficiently small, it is easy to form the voltage converter 20 on a silicon substrate. The inductor 28
Is sufficiently small, so that radiated electromagnetic wave noise hardly occurs. In addition, since a large voltage difference does not occur between the two terminals of the switch 26, if a large voltage difference occurs between the two terminals of the switch 26, noise due to the incoming current does not occur.

When a PMOS switch is used as the switch 26, the on-resistance of the switch 26 is reduced by 50%.
It can be about 0 mΩ. As described above, since the ON resistance of the switch 26 is sufficiently large, it is easy to form the voltage converter 20 on a silicon substrate. 500m
Even when a switch having an ON resistance of about Ω is used, a conversion efficiency of 90% or more can be secured.

[0422] Hereinafter, the unsteady operation of the voltage converter 20 will be described. The oscillating voltage of the sine wave at the terminal 3f of the voltage converter 3 is converted into a square wave clock pulse by the clock generator 6. The clock pulse output from the clock generator 6 is supplied to the synchronization circuits 10, 16 and 19. Therefore, the incorrect output of the clock pulse causes the voltage converter 20 to malfunction. This is because the detectors 8, 15 and 18 and the reference voltage generators 9, 14 and 17 operate in synchronization with the clock pulses supplied from the synchronization circuits 10, 16 and 19.

The clock detector 7 is provided to return the operation of the voltage converter 20 to a normal operation when a clock pulse is not correctly output from the clock generator 6. If the clock pulse is not output correctly,
For example, this may occur when an abnormality occurs in the voltage fluctuation of the terminal 3f of the voltage conversion unit 3. When detecting that the clock pulse is not correctly output from the clock generator 6, the clock detector 7 outputs a reset signal to the synchronization circuit 13.

Synchronous circuit 13 restarts the operation of voltage converter 20 in response to the reset signal. Synchronous circuit 13
The operation of the voltage converter 20 after receiving the reset signal is the same as the operation of the voltage converter 20 after the synchronization circuit 13 receives the start signal via the terminal 24. Thus, the resonance operation in the voltage conversion unit 3 is reproduced, and the clock pulse output from the clock generator 6 is reproduced. As a result, the operation of the voltage converter 20 returns to the normal operation.

Hereinafter, another unsteady operation of voltage converter 20 will be described.

When the vibration amplitude of the terminal 3f decreases, the voltage of the terminal 3f reaches the reference voltage V _S , but the reference voltage V _C
May not be reached. In this case, P
The state of the MOS switch 26 changes from the open state to the closed state, and then remains in the closed state, and cannot be changed from the closed state to the open state.

[0427] Such an unsteady operation is detected by the synchronization circuit 5. The synchronization circuit 5 includes a capacitor 2 of the voltage conversion unit 3.
When it is detected that any one of the following three signals is not generated within a predetermined period (oscillation cycle of the resonance circuit) determined by the inductors 7 and 29 and the inductor 28, the reset signal is output. Output to the synchronization circuit 13.

An operation start signal output from the detector 8 to the detectors 15 and 18 via the synchronization circuit 5; a signal output from the detector 15 to the synchronization circuit 5; A signal defining a timing for changing the state from the open state to the closed state. A signal output from the detector 18 to the synchronization circuit 5, which defines a timing for changing the state of the PMOS switch 26 from the closed state to the open state. The signal synchronization circuit 13 restarts the operation of the voltage converter 20 in response to the reset signal. The operation of the voltage converter 20 after the synchronization circuit 13 receives the reset signal
3 is the same as the operation of the voltage converter 20 after receiving the start signal via the terminal 24. Thus, the resonance operation in the voltage conversion unit 3 is reproduced. as a result,
The operation of the voltage converter 20 returns to the normal operation.

Further, an operation different from the normal operation of the voltage converter 20 will be described.

The voltage output from voltage converter 20 (the voltage at terminal 22) matches the voltage at terminal 3e of voltage converter 20 with reference voltage V _P (desired voltage) output from reference voltage generator 9. To be varied. The desired voltage _VP is
It is specified by a signal input to the reference voltage generator 9 via the terminal 25. When a change of the desired voltage V _P is indicated by a signal input to the reference voltage generator 9, (the voltage at the terminal 22) a voltage output from the voltage converter 20 toward a desired voltage V _P of the changed Change.

[0431] When the voltage output from the voltage converter 20 decreases, the oscillation amplitude of the terminal 3f of the voltage converter 3 decreases, so that the voltage from the previous desired voltage to the next desired voltage is reduced. If the difference is large, the attenuation of the vibration amplitude of the terminal 3f also increases. In order to maintain the oscillation amplitude of the terminal 3f, an intermediate voltage is provided between the previous desired voltage and the next desired voltage, and when the voltage output from the voltage converter 20 falls below the intermediate voltage. , Operate the detectors 15 and 18,
The opening and closing operation of the PMOS switch 26 may be performed. As described above, by supplying electric charges (resonance energy) to the resonance circuit of the voltage conversion unit 3, it becomes possible to recover the vibration amplitude of the terminal 3f.

Next, another method for supplying electric charges to the voltage converter 3 will be described. According to the method described above with reference to FIG. 35, during the period in which the voltage of the terminal 3f rises, the state of the PMOS switch 26 changes from the open state to the closed state at the point 1, and the state of the PMOS switch 26 changes at the point 2 The timing of supplying electric charges to the voltage conversion unit 3 is controlled so that the state changes from the closed state to the open state.

[0433] Instead of the period during which the voltage at the terminal 3f rises, the charge may be supplied to the voltage converter 3 during the period when the voltage at the terminal 3f falls.

FIG. 36 shows the state of the terminal 3f in the normal operation state.
Voltage change (waveform a) and the voltage change at terminal 3e (waveform b)
And As shown in FIG. 36, when the voltage at the terminal 3f reaches the reference voltage V _S (point 3), the state of the PMOS switch 26 changes from the open state to the closed state, and the voltage at the terminal 3f becomes the reference voltage V _C. At the point (point 4)
The timing at which electric charges are supplied to the voltage conversion unit 3 may be controlled so that the state of the switch 26 changes from the closed state to the open state.

Of course, the operation of supplying charges to the voltage converter 3 during the period when the voltage of the terminal 3f rises (FIG. 35)
It is also possible to combine the operation (FIG. 36) with the operation of supplying electric charges to the voltage conversion unit 3 during the period in which the voltage of the terminal 3f is falling. By combining such two operations, it is possible to realize a voltage conversion operation with higher efficiency than a voltage conversion operation by one operation. Thus, combining the two operations is preferable in terms of the conversion efficiency.
It is not preferable because control of the MOS switch 26 becomes complicated. However, since the increase in the circuit scale is so small that it can be ignored, it can be considered that this is an excellent voltage conversion operation. However, since the power consumption of the control circuit for controlling the operation of the PMOS switch 26 increases, it is desirable to combine the two controls when the output current value from the voltage converter 20 is large. When the value is small, the operation by one control is suitable.

FIG. 37A and FIG. 37B show the configuration and operation of the detector 8. In Figure 37A, the input terminal I ₁ is connected to the terminal 3e of the voltage conversion section 3 (pin 3 g).
Voltage output from the reference voltage generator 9 is input to the input terminal I _2. The detector 8 includes transistors 30 to 35,
It includes a chopper comparator including 37, 38 and a capacitor 36, and logic gates 39, 40.

The chopper comparator operates according to the operation shown in FIG. 37B by connecting the terminals 3g (terminals 3e, 3d,
The voltage at the output terminal 22) is compared with the voltage output from the reference voltage generator 9. Clock pulse φ ₁ (φ _1B is φ ₁
During the period (the sampling period in FIG. 37B) in which the inverted clock pulse of FIG. 3 changes from the L level to the H level, the voltage of the terminal 3g (the terminals 3e, 3d, the output terminal 22) of the voltage conversion unit 3 is tracked and held. During a period in which the clock pulse φ ₁ changes from H level to L level (comparison period in FIG. 37B), the voltage output from the reference voltage generator 9 is input to the terminal I ₂ . When the voltage at the terminal 3g is lower than the voltage output from the reference voltage generator 9, an L-level signal is output from the output terminals of the inverters (transistors 37 and 38).

When the clock pulse φ ₄ (φ _4B is an inverted clock pulse of φ ₄ ) changes from the L level to the H level, the comparison result between the voltage at the terminal 3g and the voltage output from the reference voltage generator 9 is detected. The output terminal O changes from the L level to the H level (when the voltage of the terminal 3g is smaller than the voltage output from the reference voltage generator 9). The time when the clock pulse φ ₄ changes from the L level to the H level is delayed after the chopper comparator enters the comparison period (when the clock pulse φ ₂ changes to the H level). This is because the output value of the chopper comparator is unstable at the beginning of the comparison period, and an unstable signal is not output from the detector 8. After holding (after sampling) the voltage output from the voltage converter 3 (the voltage at the terminal 3 e), the detector 8 compares the sampled voltage with the voltage output from the reference voltage generator 9. I do. The reason for sampling the voltage of the terminal 3e in this way is to reduce the influence of noise when the load 2 is a digital LSI. By sampling the voltage of the terminal 3e, it is possible to prevent the detector 8 from detecting the voltage obtained by adding the noise superimposed on the terminal 22.

FIG. 38 shows a method for reducing the influence of noise when the load 2 is a digital LSI. Terminal 23
Is used as a clock pulse of the digital LSI connected to the terminal 22 (a synchronous clock pulse), so that the timing of noise generated from the digital LSI can be adjusted. It can be measured and avoided. In FIG. 38, the system clock is an operation clock pulse input to the digital LSI (load 2). In Figure 38, how the digital LSI at the point where the system clock changes is generating noise is represented by the noise is superimposed on the voltage V _P output from the voltage converter 20. Since the superimposed noise attenuates after a lapse of a certain time t _d from the change point of the system clock,
By detector 8 after time t _d has elapsed to hold the voltage at the terminal 3e of the voltage conversion section 3, it is possible to avoid noise. The clock pulse input to the terminal 23 does not have to have the same cycle as the clock pulse input to the digital LSI connected to the terminal 22, but must be synchronized.

With reference to FIG. 52, a description will be given of a noise generation mechanism of the LSI. The LSI incorporates a silicon chip in a package. The pins of the package and the silicon chip are connected by bonding wires. The bonding wire has an inductance L _p. A change in the system clock causes a current i (t) to flow through the silicon chip. When the current i (t) is changed, the voltage generated by the inductance L _p. This voltage becomes noise.

FIG. 39A shows the structure of the detector 15. Since the configuration of the detector 18 is the same as the configuration of the detector 15,
The detector 15 will be described in detail, and the description of the detector 18 will be omitted.

The difference from FIG. 37A is that the switches connected to the terminals I ₁ and I ₂ are PMOS switches 41 and 42. The reason why the PMOS switches 41 and 42 are used as the switches is as follows. When the voltage output from the voltage converter 20 is smaller than １ ／ of the voltage of the power supply 1 to be converted, the voltage of the terminal I ₂ (the terminal to which the voltage of the terminal 3f of the voltage converter 3 is input) is 0 V Vibrates below. In a configuration using an NMOS transistor as a switch or using a PMOS transistor connected in parallel,
The diode formed by the drain (source) and the well of the NMOS transistor is biased in the forward direction, and the charge is lost from the voltage converter 3 through the diode. This charge loss is a loss of the charge supplied to the resonance circuit, and lowers the voltage conversion efficiency.

To avoid such charge loss, P
MOS switches 41 and 42 are used.

The output terminal uses an AND gate because the signal output from the detector 15 when the voltage output from the reference voltage generator 14 exceeds the voltage output from the voltage converter 3 is used. This is for changing from the L level to the H level. The time when the clock pulse φ ₄ changes from the L level to the H level is delayed since the chopper comparator enters the comparison period (the clock pulse φ _2B changes to the L level). This is because the output value of the chopper comparator is unstable in the early part of the comparison period, and an unstable signal is not output from the detector 15.

FIG. 39B shows the operation of the detector 15. During the sampling period (the voltage of the reference voltage generator 14 is sampled), the clock pulse φ _1B becomes L level, and during the comparison period, the clock pulse φ _2B changes to L level.

The clock pulse converted by the clock generator 6 has the cycle of the oscillating voltage of the sine wave at the terminal 3f, but may be a multiple cycle, which is twice the oscillation cycle of the sine wave at the terminal 3f. Clock pulse
The detector 8 samples the output voltage (the voltage at the terminal 3g) of the voltage conversion unit 3 at a cycle twice as long as the operation cycle shown in FIG. The lower the operation cycle of the detector 8, the smaller the power consumed by the entire voltage converter 20. However, when the output voltage of the voltage converter 20 is increased, the PMO
Since the power consumed by the S switch 26 tends to increase, it is necessary to design the circuit appropriately according to the size of the load 2. (Embodiment 2) FIG. 40 shows another configuration of the voltage converter 20. The configuration of the voltage converter shown in FIG. 40 is the same as the configuration of voltage converter 20 shown in FIG. 29 except for monitor 661.

The monitor 661 has two input terminals and three output terminals. One input terminal of the monitor 661 is connected to a terminal 3 d of the voltage conversion unit 3. The other input terminal of the monitor 661 is connected to the synchronization circuit 10. The three output terminals of the monitor 661 are connected to the synchronization circuit 5 and the reference voltage generators 14 and 17, respectively.
The monitor 661 detects a current (a voltage that decreases per time) of the output terminal 3d of the voltage conversion unit 3. This is because the current (voltage falling per hour) flowing into the load 2 can be obtained from this current (voltage falling per hour). The monitor 661 outputs the power substantially equal to the power consumed by the load 2 from the power supply 1 to the voltage conversion unit 3.
To supply. For example, when the monitor 661 detects that the current consumed by the load 2 increases, the amount of charge supplied to the voltage conversion unit 3 is increased by increasing the period in which the PMOS switch 26 included in the voltage conversion unit 3 is in the closed state. Increase.

In order to increase the period during which the PMOS switch 26 is closed, for example, a voltage output from the reference voltage generator 14 (the timing at which the switch 26 changes from the open state to the closed state is determined by this voltage. ) May be decreased, and the voltage output from the reference voltage generator 17 (which determines the timing at which the switch 26 changes from the closed state to the open state) may be increased.

Incidentally, the following can be considered regarding the voltage conversion efficiency. The period during which the PMOS switch 26 is closed is short, and the period during which the switch 26 is closed is set where the oscillating voltage at the terminal 3f of the voltage converter 3 is close to the voltage of the power supply 1 to be converted. It is preferable for improving the efficiency. It is desirable to adjust the voltages output from the reference voltage generators 14 and 17 in order to realize better conversion efficiency.

In order to increase the period during which the PMOS switch 26 is closed, the voltages output from the reference voltage generators 14 and 17 may be adjusted according to the operation state of the detector 8. For example, when the comparison result of the voltage of the terminal 3e of the voltage conversion unit 3 and the voltage output from the reference voltage generator 9 continues twice, and the voltage of the terminal 3e falls below the voltage output from the reference voltage generator 9, Means that the amount of charge consumed by the load 2 is larger than the amount of charge supplied from the converted power supply 1 by closing the PMOS switch 26. In such a case, the PMOS switch 26
If the period during which the switch is closed is not increased, the voltage converter 20
Of the output terminal 22 cannot maintain a desired voltage. Therefore, the detector 8 sends a signal to the monitor 661 indicating that the voltage of the terminal 3e is lower than the voltage output from the reference voltage generator 9 continuously twice. Monitor 66
1 adjusts the voltage output from the reference voltage generators 14 and 17 in response to the signal from the detector 8 to increase the period during which the PMOS switch 26 is closed.

As described above, the monitor 661 is connected to the voltage converter 3
, The voltage at the terminal 3 e in the result of comparison between the voltage at the terminal 3 e of the voltage converter 3 and the voltage output from the reference voltage generator 9 is By detecting the frequency at which the voltage falls below the output voltage, the period during which the PMOS switch 26 is in the closed state can be increased.

Further, the PMOS included in the voltage conversion unit 3
The timing at which the state of the switch 26 changes from the closed state to the open state can be delayed not only by increasing the voltage output from the reference voltage generator 17, but also by the signal from the monitor 661. This can also be realized by delaying the operation signal of the PMOS switch 26 from the closed state to the open state.
By delaying the operation signal from the closed state to the open state of the PMOS switch 26 from the synchronization circuit 5, fine adjustment can be performed without increasing the circuit scale. Therefore, it can be said that the fine adjustment by coarsely adjusting the reference voltage generator 17 and delaying the operation signal from the closed state to the open state of the PMOS switch 26 from the synchronization circuit 5 is fine adjustment. .

FIG. 41 is a control flow chart showing the procedure of processing of the monitor 661.

In the control block C1, the end of the voltage converter 3
Voltage V of child 3d_dAnd the desired voltage (ie, the reference voltage generator)
Voltage output from the generator 9) V_pIs compared with Voltage
V_dIs the voltage V_pIf it is less, the process goes to the control block
Proceed to C2. Voltage V_dIs the voltage V _pIf greater than,
The processing of the control block C3 is repeated. Control block C
The voltage V at 1_dAnd voltage V_pThe result of comparing with
Stored in block C2. In control block C2
Means that the comparison result in the control block C1 is five times in a row
V_d<V_pIs detected. V_d<V_pIs 5 times in a row
Then, in the control block C3, the voltage V_sIs only ΔV
Can be lowered. Here, the voltage V_sIs a reference voltage generator 14
And the voltage ΔV is the voltage V_sChange
This is the minimum voltage width when operating. Of control block C3
After the processing ends, the processing returns to the control block C1.

In the control block C2, V_d<V_pIs 5 times
The detection of continuity means that the power supply 1
The power supplied to the unit 3 is smaller than the power consumed by the load 2.
Means. By the way, V_d<V_pIs repeated 5 times
The reason for waiting is to take a margin. Voltage V_dBut
Voltage V_pIf smaller, the power supply 1 switches to the voltage converter 3
Power is supplied, and this supplied power is consumed by load 2.
If the power is smaller than the power
Voltage V in the next comparison_dIs the voltage V_pSmaller
You. Therefore, V_d<V_pIs repeated twice when the power supply 1
That the power supplied to the voltage converter 3 is insufficient
means. However, the voltage V_dAnd voltage V_pComparison with
Susceptible to noise. In particular, the voltage V_dIs the voltage V_pTo
The closer, the more susceptible to noise. Neu
In order to reduce the effect of_d<V_pIs twice
Power supplied from the power supply 1 to the voltage conversion unit 3
Than V is determined to be insufficient_d<V_pIs 5 times in a row
The power supplied from the power supply 1 to the voltage converter 3
It is preferable to determine that there is a shortage. 3 merges
Eliminates comparison errors due to noise
This is because the determination is more reliable. Control block
The voltage V at C3_sIs reduced by ΔV, the power supply 1
Means to increase the power supplied to the voltage converter 3 from
I do. Voltage V _sLowers the switch 26 to the closed state.
This is because a longer period of time is required.

[0456] In the control blocks C4 to C6, the same processing as in the control blocks C1 to C3 is performed. That is,
In the control block C4, and the voltage V _d and the voltage V _p is compared. When it is detected in the control block C5 that V _d > V _p has been repeated five times, the voltage V _s is increased by ΔV in the control block C6. The fact that V _d > V _p is detected five consecutive times in the control block C5 means that
This means that the power supplied from the power supply 1 to the voltage converter 3 is larger than the power consumed by the load 2. Increasing in the control block C6 the voltage V _s by ΔV, the power supply 1
Means to reduce the power supplied to the voltage converter 3 from. Increasing the voltage V _s, it is because the period in which the switch 26 is closed is shortened.

FIG. 42 shows an example of a circuit configuration for realizing the control flow of FIG. The reference voltage generator 141 generates a voltage V _p. The detector 142 detects the voltage _Vd and the voltage _Vp
Compare with If V _d <V _p , detector 142
"0" is output to the shift register 143, and when _Vd > _Vp , "1" is output to the shift register 143. The shift register 143 outputs the output signal of "0""1" from the detector 142. Hold for 5 times Encoder 144
The case 5 times the data held in the shift register 143 are all "0" (i.e., "0" if the consecutive 5 times), the voltage V _s output from the reference voltage generator 14 When the data for five times held in the shift register 143 is “1” (that is, when “1” continues five times), the voltage V output from the reference voltage generator 14 is reduced by ΔV. Increase _s by ΔV. In this way, the control shown in FIG. 41 is realized.

[0458] Figure 43 illustrates how the voltage V _s output from the reference voltage generator 14 changes. If one voltage change is not enough, the voltage change is repeated until the power supplied from the power supply 1 to the voltage converter 3 becomes equal to the power consumed by the load 2.

[0459] Figure 44 is a control flow illustrating a procedure of a process for determining the voltage V _c.

[0460] In the control block C7, the voltage V _d and the object of the voltage at the terminal 3d of the voltage conversion section 3 (i.e., the voltage output from the reference voltage generator 9) and V _p are compared. When the voltage V _d is smaller than the voltage V _p, the process proceeds to the control block C8, otherwise, the process control block C7 is repeated. In the control block C8, V _d <V _p
Is determined five times in a row. If _Vd <Vp is _repeated five times, the process returns to the control block C7. Otherwise, processing proceeds to control block C9. In the control block C9, the voltage V _c increasing by [Delta] V. Thereafter, the process proceeds to the control block C10. Control block C
In 10, and the voltage V _d and the voltage V _p is compared. Voltage V _d
Is greater than the voltage V _p , the process proceeds to the control block C
11. If not, control block C10
Is repeated. In the control block C11, V _d
It is determined whether or not> _Vp has continued five times. If V _d > V _p is _repeated five times, the processing proceeds to control blocks C7 and C1.
Return to 4. If not, the process proceeds to control block C
Proceed to 12, C13, the voltage V _c falls only 2ΔV. Thereafter, the process returns to the control blocks C7 and C14. In the control block C14, and the voltage V _d voltage V _p is compared. When the voltage V _d is greater than the voltage V _p, the process proceeds to the control block C15, otherwise, the control block C
Step 14 is repeated. In control block C15,
It is determined whether V _d > V _p has been _repeated 5 times. V _d > V _p
Are repeated five times, the process returns to the control block C14. Otherwise, processing proceeds to control block C9.

The meaning of the control blocks C7 to C15 will be described below. The flow of the control blocks C7 and C8 corresponds to the voltage V _d
There since the voltage V _p of less than periods for five consecutive times, as described in the control flow shown in FIG. 41,
Means that in the process which determines the "width" (the potential difference between the voltage V _s and the voltage V _c). Control blocks C14, C1
The same applies to the flow of No. 5. Control block C8,
If the output of C15 is "No", it means that the width has been determined. Once the width is determined,
The “height” (voltage V _c ) is determined. Control block C9
In, the voltage V _c is raised by ΔV. This operation is performed by intentionally setting the voltage V _c from the appropriate width after control shown in FIG.
Means to fluctuate. Should widen the appropriate width is intentionally (Increasing the voltage V _c by [Delta] V), since the power supplied from the power supply 1 to the voltage conversion unit 3 increases, the voltage V _d and the voltage V _p in the control block C10 The comparison is V
_d > _Vp is expected to be 5 consecutive times. If V _d > V _p continues five times, the control flow in FIG. 44 is completed. However, if V _d > V _p does not continue five times, it means that the voltage V _c is too high. This is because the power supply 1 by raising the voltage V _c, by originally width increases
, The power supplied to the voltage converter 3 should increase, but the increase in the power is small (V _d > V _p is 5
The reason for this is that the switch 26 is closed during a period in which the voltage at the terminal 3f of the voltage conversion unit 3 is higher than the voltage of the power supply 1, so that the power supplied to the voltage conversion unit 3 is
Because it flows backward. In this case, the lower voltage V
_The switch 26 must be shifted from the closed state to the open state at _c . Therefore, the voltage V _c at the control block C12, C13 considering that raised only once ΔV the voltage V _c at the control block C9 in this case 2
That is, it is decreased by ΔV. The above is an example of a procedure of adjusting the height of the voltage V _c.

Table 3 summarizes the determination of the width, the determination of the height, and the intermittent operation.

Table 3

[0464]

[Table 3] (Embodiment 3) FIG. 45 shows another configuration of the voltage converter according to the present invention. 61 is a conventional DC / DC converter. 62 is a power supply to be converted, 63 is a clock pulse generator connected to the terminal 23 of the voltage converter 20,
Reference numeral 64 denotes a start signal generator connected to the terminal 24. Reference numeral 65 denotes an LSI serving as a load to which the converted voltage is supplied. The optimum supply voltage value is sent from the LSI 65 to the terminal 25 of the voltage converter 20. The voltage converter 20 is LS
When the current supplied to I65 is small, high-efficiency voltage conversion is performed. On the other hand, when the supply current increases, the conversion efficiency decreases and becomes lower than the voltage conversion efficiency of the conventional DC / DC converter 61.

The configuration of voltage converter 20 shown in FIG. 45 is the same as the configuration of voltage converter 20 shown in FIG. The voltage converter 20 includes a current detector that detects a current flowing from the terminal 22 to the LSI 65. Or,
This current detector may be provided outside the voltage converter 20.

When the current detected by the current detector is smaller than the predetermined current, voltage converter 20 operates. When the current detected by the current detector is larger than the predetermined current, the DC / DC converter 61 operates.

Alternatively, if the voltage output from the terminal 22 to the LSI 65 is larger than the predetermined time integral of the voltage, the voltage converter 20 operates and the terminal
When the voltage output to the DC / DC converter is smaller than the time integral value of the predetermined voltage, the DC / DC converter 61 may operate.

As described above, when the voltage conversion efficiency of the DC / DC converter 61 is higher than that of the voltage converter 20, the supply from the voltage converter 20 is stopped, and the DC / DC converter 61
To supply current.

Further, the DC / DC converter 61 executes not only the change in the current consumption of the LSI 65 but also the change to the desired voltage when the desired voltage largely changes. After reaching the desired voltage, the voltage converter 2
0 starts current supply. This speeds up the transition to the desired voltage (settling). Not only the switching of the DC / DC converter 61 during the transition period between the desired voltages, but also the startup and reset of the voltage
It can also be executed by the / DC converter 61.

FIG. 46 shows a voltage converter 20 and a conventional DC / DC converter.
A state in which the speed of the voltage change is increased by combining with the DC converter 61 is shown.

In FIG. 46, in periods I and III, only voltage converter 20 operates. Therefore, during these periods, power is supplied to the load 2 with high conversion efficiency. In the period II, the voltage converter 20 and the DC / DC converter 61 operate at the same time, so that the output voltage rapidly rises from 1V to 2V as compared with the case where only the voltage converter 20 operates.
However, the conversion efficiency decreases during this period.

FIG. 47 shows that there is a circuit portion that can be shared between the voltage converter 54 of the DC / DC converter 61 and the voltage converter 3 of the voltage converter 20. DC / D
The switches 26 and 66, the capacitors 27 and 29, and the inductor 28 most influence the circuit scale of the C converter 61 and the voltage converter 20. Therefore, by sharing these circuit portions, the DC / DC converter 61 can be taken into the voltage converter 20 without increasing the circuit scale. That is, by connecting the NMOS switch 66 to the terminal 3f of the voltage conversion unit 3 as shown in FIG.
The voltage converter 54 of the C / DC converter 61 can be configured. Since the circuit portion can be shared between the voltage conversion unit 54 and the voltage conversion unit 3, if the configuration of FIG. 47 is adopted, the DC / DC converter 61 and the voltage converter 20 can be connected with almost no increase in circuit scale. Can be realized. (Embodiment 4) FIGS. 48A and 48B show another configuration of the voltage converter 3. FIG.

The configuration of the voltage conversion unit 3 shown in FIG. 48A is different from the configuration of the voltage conversion unit 3 shown in FIG. 30 in that a diode 67 and a capacitor 66 are connected to the switch 26. The diode 67 can be, for example, a Schottky barrier diode.

The configuration of the voltage converter 3 shown in FIG. 48B is different from the configuration of the voltage converter 3 shown in FIG. 30 in that a Zener diode 68 is connected to the switch 26.

Terminal 3 shown in FIGS. 48A and 48B
a to 3e are the same as the terminals 3a to 3e shown in FIG. As shown in FIG. 33, the voltage at the terminal 3f (the voltage of the waveform a) becomes higher than the converted voltage V _DD during the transition period due to the operation characteristics of the voltage conversion unit 3 during the set-up period, and the PMOS transistor 26 When a diode (parasitic) formed between the drain and the well connected to the terminal 3f is biased in the forward direction, a current flows from the drain toward the well. This current has a capacity of 27,
Depending on the value of the inductor 29 and the value of the inductor 28, it has a large current value, exceeding the forward withstand current value of the diode between the drain and the well, and destroying the PMOS transistor.
Therefore, a diode 67 is connected between the terminal 3f and the terminal 3a, and a capacitor 66 is connected between the terminal 3a and the ground. When the voltage at the terminal 3f becomes higher than the voltage of the power supply 1 to be converted (the voltage at the terminal 3a) and the diode 67 is biased in the forward direction, the current flows from the terminal 3f toward the terminal 3a,
The current flowing into the terminal 3a flows into the capacitor 66. Here, in the diode 67, the forward current starts to flow at a voltage smaller than the voltage value at which the current starts flowing in the forward direction in the diode formed between the drain of the PMOS transistor 26 and the well. Since no large current flows through the PMOS transistor 26, no destruction occurs. However, since the diode 67 needs to have a large withstand current value, it is generally used as an external component rather than formed on a semiconductor integrated circuit. The capacitor 66 reduces the reverse flow of the forward current of the diode 67 to the power supply 1 to be converted.

FIG. 48B shows that a current flows from the terminal 3f to the ground terminal by the Zener diode 68 and the PM
A configuration for preventing a large current from flowing to the OS transistor 26 is shown. Here, the Zener diode 68 is PM
The voltage is lower than the voltage at which a current starts to flow between the drain and the well of the OS transistor 26 and higher than the voltage of the power supply 1 to be converted. (Embodiment 5) FIGS. 49A and 49B show another configuration of the voltage converter 3. FIG.

The configuration of voltage converter 3 shown in FIG. 49A is different from voltage converter 3 shown in FIG. 30 in that diode 69 is connected between terminal 3f and the ground terminal. Diode 69 may be, for example, a Schottky barrier diode.

The configuration of voltage converter 3 shown in FIG. 49B differs from voltage converter 3 shown in FIG. 30 in that Zener diode 70 is connected between terminal 3f and the ground terminal.

In the configuration shown in FIG. 49A, the voltage at the terminal 3f becomes lower than the ground voltage GND,
9 is biased in the forward direction and the terminal 3
A current flows toward f. The voltage at which the forward current starts flowing through the diode 69 is set to a voltage smaller than the reverse breakdown voltage of the diode formed between the drain connected to the terminal 3f of the PMOS transistor 26 and the well.
The destruction of the PMOS transistor 26 can be prevented.

The structure of FIG. 49B is obtained by replacing the diode 69 of FIG. 49A with a Zener diode 70. The voltage at which the current starts to flow through the Zener diode 70 is smaller than the reverse breakdown voltage of the diode formed between the drain connected to the terminal 3f of the PMOS transistor 26 and the well, so that the destruction of the PMOS transistor 26 can be prevented. Can be prevented. Generally, the diode 69 and the Zener diode 70 are external components rather than formed on a semiconductor integrated circuit. (Embodiment 6) FIG. 50 shows another operation procedure of the voltage converter 20. The operation procedure of the voltage converter 20 shown in FIG. 50 is based on the detection periods of the detectors 15 and 18, the detectors 15 and 18,
33 and the operation procedure of the voltage converter 20 shown in FIG.

[0481] When the detector 15 enters the detection period, the detector 15 compares the voltage V _S output from the voltage and the reference voltage generator 14 of the terminal 3f of the voltage conversion section 3, the voltage at the terminal 3f There outputs the H pulse as an output signal when it exceeds the voltage V _S. Thereafter, when the voltage at the terminal 3f starts to decrease beyond the peak, the voltage at the terminal 3f approaches the voltage V _S again. Detector 15 again outputs the H pulse as an output signal when the voltage at the terminal 3f fell below the voltage V _S.

[0482] When the detector 18 enters the detection period, the detector 18 compares the voltage V _C output from the voltage and the reference voltage generator 17 of the terminal 3f of the voltage conversion section 3, the voltage at the terminal 3f There outputs the H pulse as an output signal when it exceeds the voltage V _C. When the voltage at the terminal 3f starts to rise after dropping to the voltage V _S , the voltage at the terminal 3f becomes the voltage V _C
Approach again. Detector 18 outputs the H pulse as an output signal when it exceeds the voltage V _C.

[0483] Switch 26 in response to the beginning of the H pulse (signal when the voltage at the terminal 3f exceeds the voltage V _S) of the detector 15 transitions from the open state to the closed state. Thereafter, the switch 26 in response to the beginning of the H pulse (signal when the voltage at the terminal 3f exceeds the voltage V _C) of the detector 17 transitions from the closed state to the open state.

Further, the switch 26 shifts from the open state to the closed state in response to the next H pulse of the detector 15 (a signal when the voltage of the terminal 3f falls below the voltage V _S ). Finally, the switch 26 in response to the next H pulse of the detector 17 (signal when the voltage at the terminal 3f exceeds the voltage V _C) transitions from the closed state to the open state.

In this way, the PMOS switch 26 is closed between the points 1 and 2 shown in FIG.
The PMOS switch 26 is closed again between the point 3 and the point 4 shown in FIG.

As described above, in the operation of one cycle, the PMOS switch 26 is closed twice so that the voltage V _S defining the positions of the points 1 and 3 for supplying the electric charge to the voltage converter 3 is received. It is possible to approach the voltage of the conversion power supply 1. Thereby, the voltage conversion efficiency is improved.

In the above-described embodiment, the PMOS
The timing when the switch 26 shifts from the open state to the closed state and the timing when the PMOS switch 26 shifts from the closed state to the open state are independently controlled. Alternatively, the timing at which the PMOS switch 26 shifts from the closed state to the open state may be controlled depending on the timing at which the PMOS switch 26 shifts from the open state to the closed state. For example, the timing at which the PMOS switch 26 shifts from the closed state to the open state is determined by the PMOS switch 26.
Can be created by delaying the timing of transition from the open state to the closed state. (Embodiment 7) FIG. 59 shows a configuration of a voltage converter 1500. The voltage converter 1500 converts the power supply voltage supplied from the power supply 1516 into a desired voltage.
01 and a controller 1518 for controlling the voltage converter 1501
And

The voltage conversion section 1501 has terminals 1501a to 1501a to
1501f. Terminal 1501a is connected to power supply 15
16 are connected. The terminal 1501f is connected to the load 151
7 is connected. The load 1517 includes at least one of a resistance component and a capacitance component. Voltage converter 150
The desired voltage output from 1 is supplied to the load 1517 via the terminal 1501f.

The control unit 1518 includes detection units 1510 and 1510
12, 1513 and 1515, and synchronizers 1511 and 1514.

FIG. 60A shows the configuration of voltage conversion section 1501. The voltage converter 1501 includes a switch 1502, a resonance circuit LC1, a switch 1506, and a resonance circuit LC2.
And

The resonance circuit LC1 includes an inductor 1504
A capacitor 1503 connected to one end of the inductor 1504 at a connection point 1504-1;
, The capacitance 1 connected to the other end of the inductor 1504
505.

[0492] switch 1502, and a terminal S ₁ and the terminal S _2. The switch 1502 electrically connects the terminal S ₁ to the terminal S ₂ or electrically separates the terminal S ₁ from the terminal S ₂ according to a control signal. The control signal is supplied from the synchronization unit 1511 via the terminal 1501b. Terminal S ₁ of the switch 1502, the terminal 1501a
Is connected to the power supply 1516 via the. Switch 15
Terminal S ₂ of 02, the connection point of the resonance circuit LC1 1504-
1 connected.

The resonance circuit LC2 includes an inductor 1508
A capacitor 1507 connected to one end of the inductor 1508 at a connection point 1508-1, and a connection point 1508-2.
, The capacitance 1 connected to the other end of the inductor 1508
509.

The switch 1506 has a terminal S ₁ and a terminal S ₂ . The switch 1506 electrically connects the terminal S ₁ to the terminal S ₂ or electrically separates the terminal S ₁ from the terminal S ₂ according to a control signal. The control signal is supplied from the synchronization unit 1514 via the terminal 1501e. The terminal S _{1 of the} switch 1506 is connected to the resonance circuit LC ₁
Is connected to the connection point 1504-2 of the. Switch 15
Terminal S ₂ 06, the connection point of the resonance circuit LC2 1508-
1 connected.

Here, when the switch and the resonance circuit connected to the switch are referred to as a “basic resonance circuit”, the voltage conversion section 1501 has a configuration in which two basic resonance circuits are connected in series. Of course, the number of basic resonance circuits is not limited to two. Voltage conversion section 1501 may include N basic resonance circuits. Here, N is an arbitrary integer of 2 or more.

The voltage converter 1501 having the configuration in which the basic resonance circuits are connected in series is suitable for efficiently lowering the power supply voltage V _DD supplied from the power supply 1516. The reason is that the voltage _VP ( _VP < _VDD ) output from the first-stage basic resonance circuit can be used as the power supply voltage of the second-stage basic resonance circuit.

As a method of lowering the power supply voltage V _DD using only one basic resonance circuit, a method of shifting the oscillation center of the AC waveform downward and a method of reducing the amplitude of the AC waveform can be considered.

FIG. 61A shows how the power supply voltage V _DD is reduced by shifting the oscillation center of the AC waveform (A) downward by using only one basic resonance circuit. The waveform (A ′) is a waveform obtained by shifting the vibration center of the AC waveform (A) downward. A part of the waveform (A ′) obtained in this way falls below the ground GND. This is not preferable for protection of the LSI.

FIG. 61B shows how the power supply voltage V _DD is reduced by reducing the amplitude of the AC waveform (A) using only one basic resonance circuit. The waveform (A ′) is a waveform obtained by reducing the amplitude of the AC waveform (A). The potential difference ΔV between the voltage V _P and the waveform (A ') is at a minimum (V _DD -V _P). Therefore, energy loss due to turning on the switch is large.

FIG. 61C shows how the power supply voltage V _DD is stepped down by the voltage converter 1501 in which two basic resonance circuits are connected in series. The configuration in which the basic resonance circuits are connected in series uses the power supply voltage V _DD using only one basic resonance circuit.
The above-mentioned problem that occurs when stepping down the voltage is solved.

In FIG. 61C, a waveform (A) shows a change in the voltage at the connection point 1504-1 of the resonance circuit LC1. Waveform (A) is an AC waveform which oscillates between the power supply voltage V _DD and the ground GND around the voltage V _P. The waveform (B) shows a change in the voltage at the connection point 1504-2 of the resonance circuit LC1. Waveform (B) is a DC waveform of the voltage V _P. A waveform (C) shows a change in the voltage at the connection point 1508-1 of the resonance circuit LC2. The waveform (C) shows the voltage V around the voltage V _PP.
This is an AC waveform that oscillates between _P and ground GND.
The waveform (D) shows a change in the voltage at the connection point 1508-2 of the resonance circuit LC2. Waveform (D) is a DC waveform of voltage V _PP . Here, V _DD > V _P > V _PP > GND.

[0502] resonance circuit LC2 can utilize the voltage V _P output from the resonance circuit LC1 as a power supply voltage. Therefore, the potential difference between the voltage V _P and the waveform (C) [Delta] V
The switch 1502 can be turned on during a period when the value is small. By controlling the ON period of the switch 1502 in this manner, energy loss due to turning on the switch 1502 can be minimized. FIG. 61
In C, T ₁ <T ₂ . This indicates that the waveform (C) is more suitable for adiabatic charging than the waveform (A).

FIG. 60B shows the configuration of voltage conversion section 1501 revised from the viewpoint of “energy supply circuit 210” and “energy storage circuit 220”. FIG. 60B
As shown in the figure, the switch 1502 and the resonance circuit LC1
And the switch 1506 are connected to the “energy supply circuit 210”.
And the resonance circuit LC2 can be understood as the “energy storage circuit 220”. In this case, the resonance circuit LC1 is connected to the resonance circuit LC1 through the switch 1506.
2 has a function as a capacitor for temporarily storing a return current flowing from the power supply 2 to the power supply 1516. In this sense, the voltage converter 1501 has a configuration similar to the configuration shown in FIG. 6D. When storing the current from the power supply 1516 in the resonance circuit LC1, the voltage conversion unit 1501
It has the advantage of lower power compared to the configuration shown in FIG. 6D. This is because the switch 1502 can be turned on during a period in which the potential difference between both ends of the switch 1502 is small.

FIG. 62A is a control flowchart showing the timing at which control unit 1518 turns on / off switch 1502 of voltage conversion unit 1501.

[0505] Step S51: detection unit 1510 compares the voltage V _d of the terminal 1501d and the target voltage V _{p 1.} When the voltage V _d is smaller than the target voltage V _p1, the process proceeds to step S52. In this case, the detection unit 1510 outputs a detection signal indicating that the voltage V _d is smaller than the target voltage V _p1 in the detection unit 1512.

[0506] Step S52: detection unit 1512, a voltage is voltage V _c is voltage V _c of a predetermined in elevation of the terminal 1501c V
_It is determined whether or not _s1 has been reached. The predetermined voltage V _s1 is
It is used to determine the timing of turning on the switch 1502 from off. If the voltage V _c is voltage V _c reaches a predetermined voltage V _s1 or during the ascent, the process proceeds to step S53. In this case, the detection unit 1512 outputs the voltage V _c
There outputs a detection signal indicating that the voltage V _c reaches a predetermined voltage V _s1 or more on increasing the synchronization section 1511.

Step S53: The synchronization section 1511 turns on the switch 1502.

[0508] Step S54: detection unit 1512, a voltage is voltage V _c is voltage V _c of a predetermined in elevation of the terminal 1501c V
_It is determined whether or not _sp1 or more has been reached. Predetermined voltage V
_sp1 is used to determine the timing of turning the switch 1502 from on to off. If the voltage V _c is voltage V _c reaches a predetermined voltage V _sp1 or more on increasing, the process proceeds to step S55. In this case, the detection unit 1512
Outputs a detection signal indicating that the voltage V _c is voltage V _c reaches a predetermined voltage V _sp1 or more on increasing the synchronization section 1511.

[0509] Step S55: The synchronization section 1511 turns off the switch 1502.

Here, the predetermined voltage V _sp1 is equal to the predetermined voltage V _sp
Greater than _s1 . The larger the potential difference between the predetermined voltage _Vsp1 and the predetermined voltage _Vs1 , the longer the period during which the switch 1502 is turned on.

FIG. 62B is a control flowchart showing the timing at which control unit 1518 turns on / off switch 1506 of voltage conversion unit 1501. The control flow diagram shown in FIG. 62B is similar to that of FIG. 62A except that the voltage V _p2 is used as the target voltage and the voltages V _s2 and V _sp2 are used as the voltages that determine the ON period of the switch 1506. It is similar to the control flow diagram shown.

[0512] As described above, the on / off of the switch 1506 can be controlled independently of the on / off of the switch 1502.

[0513] When the voltage V _d of the terminal 1501d is a direct current does not affect the conversion efficiency of the voltage operating the sinusoidal oscillation and independently of one another in the sinusoidal oscillation and the resonance circuit LC2 in the resonance circuit LC1 . The resonance circuit LC2 is
This is because the operation is performed using the voltage _Vd as the power supply voltage.

[0514] On the other hand, if the voltage V _d of the terminal 1501 is an AC, the voltage at terminal 1501d V _d and the terminal 1501
Whether or not the voltage Vf of _f is synchronized affects the voltage conversion efficiency. In order to reduce energy loss when transferring energy from the resonance circuit LC1 to the resonance circuit LC2, a period during which the potential difference between both terminals of the switch 1506 (that is, the potential difference between the voltage _Vd and the voltage _Vf ) is small. It is necessary to control the amplitude and phase of the voltage _Vf so that the switch 1506 is turned on. Such control may be achieved, for example, by variably controlling the voltage V _s2 and the voltage V _sp2 to determine the on period of the switch 1506.

[0515] Figure 63A shows the timing of the on-off switch 1506 in the case where the voltage V _d and the voltage V _f are synchronized. Figure 63B shows the on-off timing of the switch 1506 when the synchronization of the voltage V _d and the voltage V _f is not sufficient.

[0516] In FIG 63A and FIG 63B, the waveform (A) shows the change in the voltage V _d, waveform (B) shows a change in voltage V _f. The switch 15 during the ON period of the switch 1506 is greater in the case of FIG. 63A than in the case of FIG. 63B.
06 (that is, the voltage _Vd and the voltage _Vf
Is small). Therefore, the energy loss due to the switch 1506 is smaller in the case of FIG. 63A than in the case of FIG. 63B. (Eighth Embodiment) FIG. 64 shows a configuration of a voltage converter 1600. The voltage converter 1600 includes a voltage converter 16 that converts a power supply voltage supplied from a power supply 1616 into a desired voltage.
01 and a control unit 1632 that controls the voltage conversion unit 1601
And

The voltage conversion section 1601 has terminals 1601a to 1601a to
1601 g. Terminal 1601a and terminal 160
1b is connected to the power supply 1616. Terminal 160
1 g is connected to the load 1617. Load 1617
Contains at least one of a resistance component and a capacitance component. The desired voltage output from voltage conversion section 1601 is
The power is supplied to the load 1617 via the terminal 1601g.

[0518] The control unit 1632 includes the detection units 1627 and 1627.
29 and 1631 and synchronizers 1628 and 1630
And

FIG. 65 shows the structure of the voltage conversion section 1601. Voltage conversion section 1601 includes a switch 1619, a resonance circuit LC, and a modulation resonance circuit MLC.

[0520] The resonance circuit LC includes an inductor 1623,
A capacitor 1621 connected to one end of the inductor 1623 at a connection point 1623-1, and a capacitor 162 connected to the other end of the inductor 1623 at a connection point 1623-2.
5 is included.

[0521] switch 1619, and a terminal S ₁ and the terminal S _2. The switch 1619 electrically connects the terminals S ₁ and S ₂ or electrically separates the terminals S ₁ and S ₂ according to a control signal. The control signal is supplied from the synchronization section 1628 via the terminal 1601c. Terminal S ₁ of the switch 1619, the terminal 1601a
Is connected to the power supply 1616 via the. Switch 16
The 19 terminal S ₂ is connected to the connection point 1623-1 of the resonance circuit LC.
It is connected to the.

The modulation resonance circuit MLC includes an inductor 162
4, a capacitor 1622, and a switch 1620. One end of the inductor 1624 is connected to a connection point 1624-1.
Is connected to the capacitor 1622 at Inductor 162
The other end of 4 is connected to a connection point 1623-2 of the resonance circuit LC.

The switch 1620 has a terminal S ₁ and a terminal S ₂ . The switch 1620 electrically connects the terminals S ₁ and S ₂ or electrically separates the terminals S ₁ and S ₂ according to a control signal. The control signal is supplied from the synchronization unit 1630 via the terminal 1601d. Terminal S ₁ of the switch 1620, the terminal 1601b
Is connected to the power supply 1616 via the. Switch 16
Terminal S ₂ of the 20 is connected to the connection point 1624-1.

[0524] The voltage conversion unit 1601 is provided with a switch 1619.
, An inductor 1623 and capacitances 1621 and 1625, and a second basic resonance circuit including a switch 1620, an inductor 1624, and capacitances 1622 and 1625. That is, the capacitor 1625 acts as a common capacitor for the first basic resonance circuit and the second basic resonance circuit.
The voltage converter 1601 provides an advantage of outputting a ripple-free DC voltage from the terminal 1601g.

[0525] The voltage at the terminal 1601g is equal to the voltage obtained by superimposing the voltage output from the first basic resonance circuit and the voltage output from the second basic resonance circuit. Therefore, the voltage output from the first basic resonance circuit and the voltage output from the second basic resonance circuit have the same amplitude and have opposite phases shifted by 180 degrees from each other. By controlling the converter 1601, a DC voltage from which ripple has been eliminated at the terminal 1601g can be obtained.

FIG. 66 shows the voltage converter 1 in the steady state.
601 shows a voltage change at each point. A curve E indicates a voltage change at the terminal 1601e. Curve F is terminal 160
1f shows a voltage change. A curve G ′ indicates a change in the voltage output from the second basic resonance circuit. A curve G "indicates a voltage change output from the first basic resonance circuit. A curve G indicates a voltage change at the terminal 1601g. The curve G is obtained by combining the curve G 'and the curve G" based on the principle of superposition. Obtained by overlapping.

[0527] The control unit 1632 controls the switch so that the voltage at the terminal 1601e (curve E) and the voltage at the terminal 1601f (curve F) have the same amplitude and opposite phases shifted by 180 degrees from each other. The opening / closing timing of 1620 is controlled. By such control, the voltage output from the first basic resonance circuit (curve G ″) and the voltage output from the second basic resonance circuit (curve G ′) have the same amplitude, and This results in having opposite phases shifted by 180 degrees from each other. As a result, the oscillation of the curve G ′ and the curve G ″
Are canceled each other, and a DC voltage (curve G) without vibration is obtained. Thus, ripples can be eliminated from the DC voltage output from the terminal 1601g.

If the voltage of the terminal 1601e and the voltage of the terminal 1601f are not in opposite phases, the control unit 1632 determines the timing of turning on and off the switch 1620 so that the voltage of the terminal 1601e and the voltage of the terminal 1601f are in opposite phases. Control. Specifically, the control unit 1632 determines that the terminal 1
The relationship between the phase of the voltage at the terminal 1601e and the phase of the voltage at the terminal 1601f is adjusted by advancing or delaying the phase of the voltage at the terminal 1601f based on the phase of the voltage at the terminal 601e.

FIG. 67 shows how the relationship between the phase of the voltage at the terminal 1601e and the phase of the voltage at the terminal 1601f is adjusted. In FIG. 67, a curve E indicates a voltage change at the terminal 1601e, and a curve F indicates a voltage change at the terminal 1601f.

Period Δt during which the voltage of terminal 1601f is rising
By turning on the switch 1620 in _oa , the voltage of the terminal 1601f is increased. Thereby, the curve F shifts to the curve F ′. This means that the phase of the curve F is advanced. Further, by adjusting the length of the period _Δtoa during which the switch 1620 is turned on, it is possible to adjust the degree of advance of the phase of the curve F.

During the period when the voltage of the terminal 1601f is falling Δt
By turning on the switch 1620 in _ob , the voltage of the terminal 1601f is increased. As a result, the curve F shifts to the curve F ″. This means that the phase of the curve F is delayed. Further, by adjusting the length of the period Δt _ob during which the switch 1620 is turned on, the curve F is changed. The degree of phase delay can be adjusted.

[0532] In this way, the phase of the voltage (curve F) at the terminal 1601f can be advanced or delayed.

FIG. 68A shows a state in which the voltage of the terminal 1601f (curve E) and the voltage of the terminal 1601f (curve F) have opposite phases by advancing the phase of the voltage of the terminal 1601f (curve F). In Figure 68A, by turning on the switch 1620 while the voltage increase of the terminal 1601F, the voltage at the terminal 1601e at time t ₅ and the terminal 16
The voltage of 01f is out of phase.

FIG. 68B shows a state in which the voltage of the terminal 1601f (curve E) and the voltage of the terminal 1601f (curve F) have opposite phases by delaying the phase of the voltage of the terminal 1601f (curve F). In FIG. 68B, the terminal 1601f
By turning on the switch 1620 during the descent of the voltage, the voltage at the terminal 1601e at time t ₅ and the terminal 16
The voltage of 01f is out of phase.

[0535] The operation of control unit 1632 will be described below.

FIG. 69 shows that the control unit 1632
FIG. 10 is a control flowchart showing timing for turning on and off a switch 1619 of the control unit 601.

[0537] Step S71: detection unit 1627 compares the voltage V _g and the target voltage V _p terminal 1601 g. The voltage V _g when the target voltage V _p smaller, the process proceeds to step S72. In this case, the detection unit 1627 outputs the voltage V _g
There outputs a detection signal indicating that less than the target voltage V _p to the detector 1629.

[0538] Step S72: detection unit 1629, a voltage is the voltage V _e of pin 1601e in increased V _e is the predetermined voltage V
_It is determined whether or not _s1 has been reached. The predetermined voltage V _s1 is
It is used to determine the timing of turning on the switch 1619 from off. When the voltage V _e is a voltage V _e becomes a predetermined voltage V _s1 or during the ascent, the process proceeds to step S73. In this case, the detecting unit 1629 outputs the voltage V _e
There outputs a detection signal indicating that the voltage V _e becomes a predetermined voltage V _s1 or more on increasing the synchronization section 1628.

Step S73: The synchronization section 1628 turns on the switch 1619.

[0540] Step S74: The detecting unit 1629 determines that the voltage V _e is equal to or lower than the predetermined voltage V _e while the voltage V _e of the terminal 1601e is rising.
_It is determined whether or not _sp1 or more has been reached. Predetermined voltage V
_sp1 is used to determine the timing at which the switch 1619 is turned off from on. When the voltage V _e is a voltage V _e becomes a predetermined voltage V _sp1 or more on increasing, the process proceeds to step S75. In this case, the detecting unit 1629
Outputs a detection signal indicating that the voltage V _e is a voltage V _e becomes a predetermined voltage V _sp1 or more on increasing the synchronization section 1628.

Step S75: The synchronization section 1628 turns off the switch 1619.

Here, the predetermined voltage V _sp1 is equal to the predetermined voltage V _sp
Greater than _s1 . The larger the potential difference between the predetermined voltage _Vsp1 and the predetermined voltage _Vs1 , the longer the period during which the switch 1619 is turned on.

FIG. 70 shows that the control unit 1632
FIG. 10 is a control flowchart showing the timing of turning on and off the switch 1620 of the control 601.

[0544] Step S81: The detecting unit 1629 determines that the voltage V _e is lower than the target voltage V _p while the voltage V _e of the terminal 1601e is falling.
To detect the time t ₁ that match. The detected time t ₁ is
The synchronization unit 1630 is notified.

[0545] Step S82: detecting unit 1631, the voltage V _f satisfies voltage V _f satisfies the target voltage V _p while increasing the terminal 1601f
To detect the time t ₂ that match. The detected time t ₂ is
The synchronization unit 1630 is notified.

Step S83: The synchronization section 1630 compares the time t ₁ with the time t ₂ . If t ₁ <t ₂ ,
The process proceeds to step S84. If t ₁ ≧ t ₂ , the process proceeds to step S88.

Step S84: The detecting unit 1631 determines whether or not the voltage _Vf has become equal to or higher than the predetermined voltage _Vsf while the voltage _Vf is increasing. The predetermined voltage V _sf is determined by the switch 1620
Is used to determine when to turn on from off. When the voltage V _f satisfies the voltage V _f becomes equal to or higher than the predetermined voltage V _sf while rising, processing proceeds to step S85. In this case, the detection unit 1631, the voltage V _f satisfies voltage V _f during the ascent
Is output to the synchronization section 1630 indicating that the voltage has become equal to or higher than the predetermined voltage _Vsf .

Step S85: The synchronization section 1630 turns on the switch 1620.

Step S86: The detecting unit 1631 determines whether or not the voltage _Vf has become equal to or higher than the predetermined voltage _Vspf while the voltage _Vf is increasing. The predetermined voltage V _spf is _supplied to the switch 16
It is used to determine when to turn 20 off. While the voltage _Vf is rising, the voltage _Vf becomes the predetermined voltage V
If it is equal to or greater than _spf , the process proceeds to step S87. In this case, the detection unit 1631 outputs a detection signal indicating that the voltage V _f satisfies the voltage V _f becomes equal to or higher than the predetermined voltage V _{sp f} during the ascent to the synchronization section 1630.

Step S87: The synchronization section 1630 turns off the switch 1620.

Here, the predetermined voltage V _spf is equal to the predetermined voltage V _spf.
Greater than _sf . The larger the potential difference between the predetermined voltage V _spf and the predetermined voltage V _sf , the longer the period during which the switch 1620 is turned on.

Step S88: The detecting section 1631 determines whether or not the voltage _Vf has become equal to or lower than the predetermined voltage _Vsd while the voltage _Vf is falling. The predetermined voltage V _sd is determined by the switch 1620
Is used to determine when to turn on from off. When the voltage V _f satisfies the voltage V _f has become less than the predetermined voltage V _sd while descending, the process proceeds to step S89. In this case, the detection unit 1631, the voltage V _f satisfies voltage V _f during descent
Is output to the synchronization unit 1630 indicating that the voltage has become equal to or lower than the predetermined voltage V _sd .

Step S89: The synchronization section 1630 turns on the switch 1620.

Step S90: The detecting unit 1631 determines whether or not the voltage _Vf has become equal to or lower than the predetermined voltage _Vspd while the voltage _Vf is falling. The predetermined voltage V _spd is
It is used to determine when to turn 20 off. While the voltage _Vf is falling, the voltage _Vf becomes the predetermined voltage V
If the value is equal to or _smaller than _spd , the process proceeds to step S91. In this case, the detection unit 1631 outputs a detection signal indicating that the voltage V _f satisfies the voltage V _f becomes equal to or lower than a predetermined voltage V _{sp d} in descending to the synchronization section 1630.

[0555] Step S91: The synchronization section 1630 turns off the switch 1620.

Here, the predetermined voltage V _spd is equal to the predetermined voltage V _spd.
smaller than _sd . The larger the potential difference between the predetermined voltage V _spd and the predetermined voltage V _sd , the longer the period during which the switch 1620 is turned on. (Embodiment 9) FIG. 71 shows a configuration of a voltage converter 1700. The voltage converter 1700 includes a voltage converter 17 that converts a power supply voltage supplied from a power supply 1716 into a desired voltage.
01 and a control unit 1758 that controls the voltage conversion unit 1701
And

The voltage conversion section 1701 has terminals 1701a to
1701 g. Terminal 1701a and terminal 170
1e is connected to the power supply 1716. Terminal 170
1c is connected to the load 1717. Load 1717
Contains at least one of a resistance component and a capacitance component. The desired voltage output from the voltage converter 1701 is
It is supplied to the load 1717 via the terminal 1701c.

The control unit 1758 includes detection units 1753 to 1753
55 and synchronizers 1756 and 1557.

FIG. 72 shows the structure of the voltage conversion section 1701. The voltage conversion section 1701 includes a switch 1747, a resonance circuit LC, and a modulation resonance circuit MLC.

The resonance circuit LC includes an inductor 1748,
A capacitance 1746 connected to one end of the inductor 1748 at the connection point 1748-1 and a capacitance 174 connected to the other end of the inductor 1748 at the connection point 1748-2.
9 is included.

The switch 1747 has a terminal S ₁ and a terminal S ₂ . The switch 1747 electrically connects the terminal S ₁ to the terminal S ₂ or electrically separates the terminal S ₁ from the terminal S ₂ according to a control signal. The control signal is supplied from the synchronization unit 1756 via the terminal 1701b. Terminal S ₁ of the switch 1747, the terminal 1701a
Is connected to the power supply 1716 via the. Switch 17
Terminal S ₂ of 47, the connection point of the resonance circuit LC 1748-1
It is connected to the.

The modulation resonance circuit MLC includes an inductor 175
0, a capacitor 1751, and a switch 1752. One end of the inductor 1750 is connected to a connection point 1750-1.
Are connected to the capacitor 1751 at Inductor 175
0 is connected to the connection point 1748-1 of the resonance circuit LC.

The switch 1752 has a terminal S ₁ and a terminal S ₂ . The switch 1752 electrically connects the terminal S ₁ and the terminal S ₂ or electrically separates the terminal S ₁ and the terminal S ₂ according to a control signal. The control signal is supplied from the synchronization section 1775 via the terminal 1701d. Terminal S ₁ of the switch 1752, the terminal 1701e
Is connected to the power supply 1716 via the. Switch 17
Terminal S ₂ of the 52 is connected to the connection point 1750-1.

[0564] The voltage conversion section 1701 includes a switch 1747.
A first basic resonance circuit (see FIG. 73A) including a capacitor, an inductor 1748, and capacitors 1746 and 1749;
752, inductor 1750, capacitance 1746, 1751
And a second basic resonance circuit (see FIG. 73B) including the following. That is, the capacitor 1746 acts as a common capacitor for the first basic resonance circuit and the second basic resonance circuit. Voltage converter 1701
Provides an advantage that the period during which the potential difference between the voltage of the terminal 1701g and the power supply voltage V _DD is small is long.

The voltage at the terminal 1701g is equal to the voltage obtained by superimposing the voltage at the connection point 1748-1 in the first basic resonance circuit and the voltage at the connection point 1748-1 in the second basic resonance circuit. .

FIG. 74 shows a voltage change at each point of the voltage-to-voltage converter 1701 in a steady state. A curve G indicates a voltage change of the terminal 1701g. Curve G 'is the first
5 shows a voltage change at a connection point 1748-1 in the basic resonance circuit of FIG. The curve G "indicates the voltage change at the connection point 1748-1 in the second basic resonance circuit. The curve G is obtained by superimposing the curve G 'and the curve G" based on the principle of superposition.

Note that the phase of the curve G ′ and the phase of the curve G ″ can be adjusted by a method similar to the method described in the eighth embodiment.

As shown in FIG. 74, a period Δt _c1 during which the potential difference between the potential of curve G and the potential of power supply voltage V _DD is small.
Is longer than the period Δt _{c2 in} which the potential difference between the normal sinusoidal curve A and the potential of the power supply voltage V _DD is small. Therefore, the period Δ
By turning on the switch 1747 at t _c1 , energy loss due to the switch 1747 can be reduced. As described above, by providing the modulation resonance circuit MLC, it is possible to obtain a voltage converter that is more efficient and can tolerate a larger output current than using ordinary sinusoidal oscillation. 11. The power supply device of the present invention as an LSI system power supply has a capability of supplying different power supply voltages to each of a plurality of loads as an LSI system power supply.

FIG. 55 shows a plurality of loads 280-1 to 280.
-4 indicates the configuration of the power supply device connected to the connection point 222 of the energy storage circuit 220. Load 280-1 ~ 2
80-4, each of which includes an energy supply unit 287-
The configuration of 1-287-4 is the same as that shown in FIG. 17A. However, the energy supply unit 287-
1～287-4, the reference voltage generation circuit 286-1 outputs a reference voltage V _r1, the reference voltage generation circuit 286-2 outputs a reference voltage V _r2, the reference voltage generating circuit 286-3 has a reference voltage V outputs _r3, the reference voltage generating circuit 286-4 is different in that outputs the reference voltage V _r4.

FIG. 56 shows the AC voltage waveform (A) at the connection point 222, the DC voltage waveform (B) at the connection point 224, the voltage waveform (C) at the connection point 281-1 of the load 280-1, and the load. 280-2 connection point 281-2
And the connection point 2 of the load 280-3
A voltage waveform (E) at 81-3 and a voltage waveform (F) at a connection point 281-4 of the load 280-4 are shown. Here, the voltage is V _r4 <V ₄ <GND <V ₃ <V _r3 <V _P <
The relationship of V ₂ <V _r2 <V _DD <V ₁ <V _r1 is satisfied. By increasing the dynamic energy stored in the energy storage circuit 220, the AC voltage waveform (A) is changed between a voltage higher than the power supply voltage _VDD and a voltage lower than the ground voltage GND, as shown in FIG. Can be vibrated. The oscillation center of the AC voltage waveform (A) is the voltage V
_P (= 1 / 2V _DD ). The oscillation center of the AC voltage waveform (A) can be set to an arbitrary voltage.

At time t ₁ , when the voltage at the node 222 reaches the voltage at the node 281-1 of the load 280-1 while the voltage at the node 222 rises, the control circuit 283-1
Changes the switch 282-1 from the off state to the on state in response to a change in the output value of the comparator 284-1. As a result, the voltage at the connection point 281-1 rises along the AC voltage waveform (A).

[0572] In time t _2, the when the voltage at the node 222 reaches the reference voltage V _r1, the control circuit 283-1 in response to the change in the output value of the comparator 285-1, turning on the switch 282-1 From OFF to OFF.
As a result, the voltage at the node 281-1 is set to the voltage V _r1. Thereafter, the voltage at the node 281 gradually descends toward the voltage V _1. This is because energy is consumed by the load 280-1.

When the voltage at the node 222 reaches the voltage at the node 281-1 of the load 280-1 again while the voltage at the node 222 rises, the control circuit 283-1 outputs the output value of the comparator 284-1. Switch 28 in response to the
2-1 is changed from the off state to the on state. As a result, the voltage at the connection point 281-1 rises along the AC voltage waveform (A).

As described above, the voltage at the connection point 281-1 is
Repeating the raising and lowering between the voltage V ₁ and the voltage V _r1.
It is possible to supply a voltage which can be regarded as DC by sufficiently reduce the difference between the voltages V ₁ and the voltage V _r1 to the load 280-1. Note that the voltage V _r1 can be set to an arbitrary value.

Similarly, the voltage at the connection point 281-2 is
Repeating the raising and lowering between the voltage V ₂ and the voltage V _r2.
It is possible to supply a voltage which can be regarded as DC by sufficiently reduce the difference between the voltage V ₂ and the voltage V _r2 to the load 280-2. The voltage at the node 281-3 repeats the raising and lowering between the voltage V ₃ and the voltage V _r3. Load voltage which can be regarded as DC by sufficiently reduce the difference between the voltage V ₃ and the voltage V _r3 280-
3 can be supplied.

The voltage V ₄ and the voltage V _r4 are equal to the ground voltage GN.
Lower than D. While the voltage at the node 222 is falling, the switch 2
By changing 82-4 from the off state to the on state, the voltage at the connection point 281-4 falls along the AC voltage waveform (A). As a result, the electric charge is stored in the energy storage circuit 2
Collected at 20.

[0577] Voltage at the connection point 281 - 4 repeats the raising and lowering between the voltage V ₄ and the voltage V _r4. It is possible to supply a voltage which can be regarded as DC by sufficiently reduce the difference between the voltage V ₄ and the voltage V _r4 to the load 280-4.

The voltages supplied to the loads 280-1 to 280-4 are different from each other. In this way, different power supply voltages can be supplied to a plurality of loads.

In the example shown in FIG. 55, the energy supply units 287-1 to 287-
4 have the same type of configuration. However, the energy supply units 287-1 to 287-4 may have different types of configurations. For example, the energy supply unit 287-
Each of the power supply units 1-287-4 is connected to the connection point 222 or the connection point 2 in any of the power supply units referred to in Chapter 8.
24 may be replaced with a configuration corresponding to the energy supply unit. In addition, the energy supply units 287-1 to 287-1
Each of the 287-4 may be replaced with a configuration corresponding to an energy supply unit connected to the connection point 222 or the connection point 224 in any of the energy reuse type power supply devices mentioned in Chapter 9. The same applies to the case where a plurality of energy supply units are connected to the connection point 224 in parallel.

[0580] The basic principle of injecting and storing energy in the energy storage circuit 220, a method of injecting dynamic energy and static energy into the energy storage circuit 220 with high efficiency, and the ratio of dynamic energy to static energy And a method of converting dynamic energy stored in the energy storage circuit 220 into static energy (or a method of converting static energy stored in the energy storage circuit 220 into dynamic energy). By properly combining the method of modulating the size of the switch and the method of keeping the frequency of the noise constant, the power supply device of the present invention can be applied as a power supply for various types of circuits. This is the same when the power supply device of the present invention is applied to the voltage converter (DC / DC converter) mentioned in Chapter 10.

Hereinafter, the role of the energy storage circuit 220 will be reconsidered by focusing on the flow of energy.

FIG. 57 shows flows of dynamic energy and static energy centered on the energy storage circuit 220. The energy storage circuit 220 realizes bidirectional exchange of dynamic energy and static energy between the energy supply circuit 210 and the energy storage circuit 220 while minimizing energy loss due to a resistance component in the circuit. I do. In addition, the energy storage circuit 220
Realizes bidirectional exchange of dynamic energy and static energy between the energy storage circuit 220 and the load while minimizing energy loss due to a resistance component in the circuit.

As described above, it can be seen that a low-loss flow of dynamic energy and static energy centering on the energy storage circuit 220 occurs in the electronic circuits and components such as the energy supply circuit 210 and the load. .

[0584] The dynamic energy and the static energy stored in the energy storage circuit 220 are converted into energy by exchanging control signals between the energy supply circuit 210, the energy storage circuit 220, and the load and the control circuit. It can be appropriately controlled according to the supply circuit 210 and the sum and ratio of the dynamic energy and the static energy required by the load. Alternatively, the amount of energy consumed by the energy supply circuit 210 and the load may need to be properly designed for the dynamic and static energy stored in the energy storage circuit 220.

In the embodiment described above, the dynamic energy and the static energy are converted into heat energy by the resistance component in the circuit, and the heat energy is dissipated outside the energy system of the electronic circuit system. A conversion circuit for converting heat energy into dynamic energy and static energy is provided, and the dynamic energy and the static energy obtained from the conversion circuit are efficiently returned to the energy supply circuit 210 and / or the energy storage circuit 220. Accordingly, the amount of energy dissipated outside the energy system of the electronic circuit system can be reduced.

The following is disclosed in the specification of the present application.

The voltage converter of the present invention converts a first voltage supplied from a power supply into a second voltage, and supplies the second voltage to a voltage supply circuit. And a control unit for controlling the conversion unit. The voltage converter includes an inductor, a first capacitor connected to one end of the inductor at a first connection point, and a second capacitor connected to the other end of the inductor at a second connection point. And a switch having a first terminal and a second terminal, wherein the first terminal is connected to the power supply, and the second terminal is the first connection point of the resonance circuit. And a switch connected to the control unit, wherein the control unit includes:
Opening and closing the switch is controlled.

[0588] The control unit has a first detector for detecting that the second voltage output from the voltage conversion unit has dropped below a desired voltage, and the control unit includes a first detector. When the detector detects that the second voltage output from the voltage conversion unit has fallen below the desired voltage, it controls opening and closing of the switch.

[0589] The control section includes a second detector for detecting that the voltage at the first connection point has reached a predetermined first reference voltage, and a control circuit for controlling whether the voltage at the first connection point is the predetermined voltage. A third detector that detects that a predetermined second reference voltage that is higher than the first reference voltage has been reached, and the second detector causes the voltage at the first connection point to be higher than the first reference voltage. When detecting that the predetermined first reference voltage has been reached, the control unit controls the switch so that the state of the switch changes from the open state to the closed state, and controls the third switch.
When it is detected by the detector that the voltage at the first connection point has reached the predetermined second reference voltage,
The control unit controls the switch so that a state of the switch changes from a closed state to an open state.

[0590] The control unit includes a clock signal generator for generating a clock signal in accordance with a voltage change at the first connection point.
If the first detector detects that the second voltage output from the voltage conversion unit has fallen below the desired voltage in a half cycle of the clock signal, The second detector and the third detector operate in a second half cycle following the first half cycle.

[0590] The control unit further includes a second reference voltage generator for generating the first reference voltage, and the second reference voltage generator operates during a period during which the second detector operates. Only works within.

[0593] The control unit further includes a third reference voltage generator for generating the second reference voltage, and the third reference voltage generator operates during a period during which the third detector operates. Only works within.

[0593] The control unit further includes a second reference voltage generator for generating the first reference voltage, and a monitor circuit for monitoring a time change of the second voltage output from the voltage conversion unit. And the second reference voltage generator varies the first reference voltage according to the output of the monitor circuit.

The control section further includes a third reference voltage generator for generating the second reference voltage, and a monitor circuit for monitoring a time change of the second voltage output from the voltage conversion section. And the third reference voltage generator varies the second reference voltage according to the output of the monitor circuit.

When the monitor circuit detects that the second voltage output from the voltage converter does not reach the desired voltage, the second reference voltage generator
The first reference voltage is reduced.

If the monitor circuit detects that the second voltage output from the voltage converter does not reach the desired voltage, the third reference voltage generator sets
The second reference voltage is increased.

When the monitor circuit detects that the second voltage output from the voltage converter has reached the desired voltage, the second reference voltage generator outputs the second reference voltage. 1 is increased.

When the monitor circuit detects that the second voltage output from the voltage conversion section has reached the desired voltage, the third reference voltage generator outputs the second reference voltage to the second reference voltage generator. 2 is lowered.

[0599] The control unit further includes a monitor circuit for monitoring a time change of the second voltage output from the voltage conversion unit, and the second voltage output from the voltage conversion unit is controlled by the control unit. When the monitor circuit detects that the voltage does not reach the desired voltage, the control unit determines that the voltage at the first connection point has reached the predetermined second voltage by the third detector. The switch is controlled such that the state of the switch changes from the closed state to the open state after a predetermined time has elapsed since the detection of the switch.

[0600] The control section operates the switch of the switch after a lapse of a predetermined time after the third detector detects that the voltage at the first connection point has reached the predetermined second voltage. The switch is controlled so that the state changes from the closed state to the open state.

(Industrial Applicability) According to the power supply device of the present invention, energy is substantially supplied to the outside of the energy storage means by the inductor, the first capacitance, and the second capacitance included in the energy storage means. A closed system is formed that does not leak. Since energy does not substantially leak outside the energy storage means, there is almost no energy loss in the power supply device. Thus, a low power consumption type power supply device can be provided.

[0602] By setting the first capacitance and the second capacitance to predetermined values, various types of voltage waveforms are supplied to the load from the first connection point and the second connection point, respectively. be able to. Further, the power supply device of the present invention is suitable as a power supply for LSI.

According to the voltage converter of the present invention, the voltage converter is controlled such that power substantially equal to the power consumed by the voltage supply circuit is supplied from the power supply to the voltage converter. This makes it possible to realize a high-efficiency (90% or more) voltage converter with little energy loss in voltage conversion.

According to another voltage converter of the present invention,
The power supply and the resonance circuit are connected via a switch, and the opening and closing operation of the switch is controlled by the control unit. The resonance circuit includes an inductor, a first capacitor connected to one end of the inductor at a first connection point, and a second capacitor connected to the other end of the inductor at a second connection point. I have. By performing the opening and closing operation of the switch at a predetermined timing, it is possible to realize a voltage converter with small energy loss in voltage conversion.

The switching operation of the switch is controlled by closing the switch when the voltage at the first connection point in the resonance circuit approaches the power supply voltage and allowing current to flow from the power supply to the resonance circuit, thereby connecting the two terminals of the switch. Can be made smaller to allow the current to flow into the resonance circuit. further,
By changing the state of the switch from the open state to the closed state and then changing the state of the switch from the closed state to the open state before the voltage at the first connection point in the resonance circuit becomes higher than the power supply voltage, the current flows from the resonance circuit to the power supply. To prevent backflow. When the current flowing from the power supply into the resonance circuit is constant (the current flowing from the power supply into the resonance circuit is constant if the power consumed by the load is constant), the smaller the voltage difference between the two terminals of the switch, the smaller the switch And the power consumption is reduced, and the voltage conversion efficiency is improved. Further, power consumption is reduced by preventing current from flowing back from the resonance circuit to the power supply.

According to another voltage converter of the present invention, a voltage converter having high conversion efficiency can be realized by combining two voltage converters having different conversion efficiencies.

According to the semiconductor integrated circuit of the present invention, the power supply device includes the LC resonance circuit, and the resonance frequency of the LC resonance circuit is within a frequency band used by the circuit block to which the power supply voltage is supplied from the power supply voltage. , The intensity of the noise determined based on the resonance frequency is set to a predetermined value or less. As a result, it is possible to prevent the characteristics of the circuit block from deteriorating due to noise generated by the LC resonance circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a power supply device 200 according to the present invention.

FIG. 2A is a diagram illustrating dynamic energy stored in an energy storage circuit 220 between a capacitor 223 and a capacitor 225;
It is a figure which shows typically being kept constant while circulating through 21.

FIG. 2B is a diagram illustrating dynamic energy stored in an energy storage circuit 220 between a capacitor 223 and a capacitor 225;
It is a figure which shows typically being kept constant while circulating through 21.

FIG. 2C is a diagram illustrating dynamic energy stored in an energy storage circuit 220 between a capacitor 223 and a capacitor 225;
It is a figure which shows typically being kept constant while circulating through 21.

FIG. 2D is a diagram illustrating dynamic energy stored in the energy storage circuit 220 between the capacitor 223 and the capacitor 225;
It is a figure which shows typically being kept constant while circulating through 21.

FIG. 2E is a diagram illustrating dynamic energy stored in an energy storage circuit 220 between a capacitor 223 and a capacitor 225;
It is a figure which shows typically being kept constant while circulating through 21.

FIG. 3 is a diagram showing an example of an AC voltage waveform at a connection point 222 in the case of C ₁ >> C ₂ .

FIG. 4A is a diagram showing an example of an AC voltage waveform.

FIG. 4B is a diagram showing an example of an AC voltage waveform.

FIG. 5 is a diagram showing an equivalent circuit when an LSI including a parasitic diode 250 is connected to a connection point 222 of the power supply device 200.

FIG. 6A is a diagram showing a configuration of an energy supply circuit 210.

FIG. 6B is a diagram showing a configuration of an energy supply circuit 210.

FIG. 6C is a diagram showing a configuration of the energy supply circuit 210.

FIG. 6D is a diagram showing a configuration of the energy supply circuit 210.

FIG. 7A is a diagram showing a waveform of a voltage v and a waveform of a current i ₁ .

FIG. 7B is a diagram showing a waveform of a voltage v and a waveform of a current i ₁ .

FIG. 7C is a diagram showing a waveform of a voltage v and a waveform of a current i ₁ .

FIG. 7D is a diagram showing a waveform of a voltage v and a waveform of a current i ₁ .

FIG. 7E is a diagram showing a waveform of a voltage v and a waveform of a current i ₁ .

FIG. 8 is a diagram showing a configuration of a power supply device 1301.

FIG. 9A is a diagram showing a voltage waveform at a connection point.

FIG. 9B is a diagram showing a voltage waveform at a connection point.

FIG. 10A is a flowchart illustrating a procedure of a process of detecting dynamic energy.

FIG. 10B is a flowchart illustrating a procedure of a process of detecting static energy.

11A is a diagram showing a configuration of a power supply device 1302. FIG.

FIG. 11B is a diagram showing a configuration of an element 391.

FIG. 11C is a diagram showing a configuration of an element 391.

FIG. 11D is a diagram showing a voltage waveform at a connection point.

FIG. 12 illustrates a configuration of a power supply device 1303.

13A is a diagram illustrating a configuration of a power supply device 1304. FIG.

FIG. 13B is a diagram showing a voltage waveform at a connection point.

FIG. 14 is a flowchart illustrating a procedure of a process of adjusting dynamic energy.

FIG. 15 is a diagram illustrating a configuration example of a switch unit 212e.

16A is a diagram showing a configuration of a DC type power supply device 201. FIG.

FIG. 16B is a diagram showing a voltage waveform at a connection point.

17A is a diagram showing a configuration of an AC type power supply device 202. FIG.

FIG. 17B is a diagram showing a voltage waveform at a connection point.

18A is a diagram showing a configuration of a DC-AC type power supply device 203. FIG.

FIG. 18B is a diagram showing a voltage waveform at a connection point.

19A is a diagram showing a configuration of an AC-AC type power supply device 204. FIG.

FIG. 19B is a diagram showing a voltage waveform at a connection point.

20A is a diagram showing a configuration of an AC-AC type power supply device 205. FIG.

FIG. 20B is a diagram showing a voltage waveform at a connection point.

21 is a diagram showing a configuration of an AC-AC type power supply device 206. FIG.

FIG. 22 is a diagram showing a voltage waveform at a connection point.

FIG. 23A is a diagram showing movement of charges in each of periods T _{1 to} T ₄ .

FIG. 23B is a diagram showing movement of charges in each of periods T _{1 to} T ₄ .

FIG. 23C is a diagram showing movement of electric charges in each of periods T _{1 to} T ₄ .

FIG. 23D is a diagram showing movement of electric charges in each of periods T _{1 to} T ₄ .

FIG. 24A is a diagram showing a voltage waveform at a connection point.

FIG. 24B is a diagram showing a voltage waveform at a connection point.

FIG. 25A is a power supply device 1 of the energy reuse DC type.
FIG. 2 is a diagram illustrating a configuration of a second embodiment.

FIG. 25B is a diagram showing a voltage waveform at a connection point.

26A is a diagram showing a configuration of an energy recycling AC-AC type power supply device 1203. FIG.

FIG. 26B is a diagram showing a voltage waveform at a connection point.

27A is a diagram showing a configuration of an energy-reuse AC-DC type power supply device 1204. FIG.

FIG. 27B is a diagram showing a voltage waveform at a connection point.

FIG. 28A is a diagram showing a configuration of an energy recycling DC-AC type power supply device 1205.

FIG. 28B is a diagram showing a voltage waveform at a connection point.

FIG. 29 is a diagram showing a configuration of a voltage converter 20 according to the present invention.

FIG. 30 is a diagram showing a configuration of a voltage conversion unit 3.

FIG. 31 is a diagram showing an equivalent circuit of the resonance circuit 140.

FIG. 32 is a diagram showing the operation of the voltage converter 20.

FIG. 33 is a diagram showing an operation of the voltage converter 20 during a steady operation period.

FIG. 34 shows a voltage change at terminal 3c of voltage converter 3 (waveform a) and a voltage change at terminal 3e of voltage converter 3 (waveform b).
FIG.

FIG. 35 is a diagram showing a waveform a and a waveform b in a steady operation state.

FIG. 36 is a diagram showing a waveform a and a waveform b in a steady operation state.

FIG. 37A is a diagram showing a configuration of a detector 8;

FIG. 37B is a diagram showing the operation of the detector 8;

FIG. 38 is a diagram illustrating a method of reducing the influence of noise when the load 2 is a digital LSI.

FIG. 39A is a diagram showing a configuration of a detector 15;

FIG. 39B is a diagram showing the operation of the detector 15;

FIG. 40 is a diagram showing another configuration of the voltage converter 20.

FIG. 41 is a control flow showing the procedure of processing of a monitor 661.

FIG. 42 is a diagram showing an example of a circuit configuration for realizing the control flow of FIG. 41.

FIG. 43 shows a voltage V _s output from a reference voltage generator 14.
FIG. 7 is a diagram showing a state in which changes.

FIG. 44 is a control flow illustrating a procedure of a process for determining the voltage V _c.

FIG. 45 is a diagram showing another configuration of the voltage converter according to the present invention.

FIG. 46 shows a voltage converter 20 and a conventional DC / DC converter 6
FIG. 4 is a diagram showing a state in which the speed of voltage change is increased by combining the first and second methods.

FIG. 47 is a diagram showing that there is a circuit portion that can be shared between the voltage converter 54 of the DC / DC converter 61 and the voltage converter 3 of the voltage converter 20.

FIG. 48A is a diagram showing another configuration of the voltage conversion unit 3;

FIG. 48B is a diagram showing another configuration of the voltage conversion unit 3.

FIG. 49A is a diagram showing another configuration of the voltage conversion unit 3;

FIG. 49B is a diagram showing another configuration of the voltage conversion unit 3;

FIG. 50 is a diagram showing another operation procedure of the voltage converter 20.

FIG. 51A is a diagram showing a configuration of a conventional DC / DC converter 61.

FIG. 51B is a diagram showing a configuration of a conventional DC / DC converter 61.

FIG. 52 is a diagram illustrating a noise generation mechanism of an LSI.

Figure 53A is a diagram showing a relationship between power consumption of the load in the conventional DC / DC converter 61 P _L and the conversion loss P _t.

FIG. 53B is a diagram showing the relationship between the power consumption P _L of the load and the conversion loss P _t in the voltage converter 20 according to the present invention.

Figure 54A is a graph showing the relationship between the power consumption P _L of the load in the conventional DC / DC converter 61 and the total loss rate eta _Ct.

Is a diagram showing the relationship between the power consumption P _L and total loss rate eta _Ct load in the voltage converter 20 according to FIG. 54B] present invention.

FIG. 55 is a diagram showing a configuration of a power supply device that supplies different power supply voltages to a plurality of loads.

FIG. 56 is a diagram showing a voltage waveform at a connection point.

FIG. 57 is a diagram showing flows of dynamic energy and static energy centering on the energy storage circuit 220.

FIG. 58A is a diagram showing another configuration of the energy supply circuit 210.

FIG. 58B is a diagram showing a voltage change at the connection point 222 (waveform (A)) and a voltage change at the connection point 224 (waveform (B)).

FIG. 59 is a diagram showing a configuration of a voltage converter 1500.

FIG. 60A is a diagram showing a configuration of a voltage conversion unit 1501.

FIG. 60B is a diagram showing a configuration of a voltage conversion unit 1501.

FIG. 61A is a diagram showing a state in which a power supply voltage V _DD is stepped down.

FIG. 61B is a diagram showing how the power supply voltage V _DD is stepped down.

FIG. 61C is a diagram showing how the power supply voltage V _DD is stepped down.

FIG. 62A is a control flowchart showing the timing at which control unit 1518 turns on / off switch 1502 of voltage conversion unit 1501.

FIG. 62B is a control flowchart showing the timing at which control unit 1518 turns on / off switch 1506 of voltage conversion unit 1501.

FIG. 63A is a diagram showing on / off timing of a switch 1506.

FIG. 63B is a diagram showing the on / off timing of the switch 1506.

FIG. 64 is a diagram showing a configuration of a voltage converter 1600.

FIG. 65 is a diagram showing a configuration of a voltage conversion unit 1601.

FIG. 66 is a diagram illustrating a voltage change at each point of the voltage conversion unit 1601 in a steady state.

FIG. 67 illustrates a phase of a voltage at a terminal 1601e and a terminal 1601.
FIG. 9 is a diagram showing how to adjust the relationship between the voltage f and the phase of the voltage f.

FIG. 68A shows the voltage at terminal 1601e (curve E) and terminal 1;
FIG. 13 is a diagram showing a state in which the voltage of 601f (curve F) has an opposite phase.

FIG. 68B shows the voltage at terminal 1601e (curve E) and terminal 1
FIG. 13 is a diagram showing a state in which the voltage of 601f (curve F) has an opposite phase.

FIG. 69 is a control flowchart showing the timing at which the control unit 1632 turns on and off the switch 1619 of the voltage conversion unit 1601.

FIG. 70 is a control flowchart showing the timing at which the control unit 1632 turns on and off the switch 1620 of the voltage conversion unit 1601.

FIG. 71 is a diagram showing a configuration of a voltage converter 1700.

72 is a diagram illustrating a configuration of a voltage conversion unit 1701. FIG.

FIG. 73A is a diagram showing a configuration of a first basic resonance circuit.

FIG. 73B is a diagram showing a configuration of a second basic resonance circuit.

FIG. 74 is a diagram showing a voltage change at each point of the voltage-voltage converter 1701 in a steady state.

FIG. 75 is a diagram showing one embodiment of a system LSI.

FIG. 76 is a diagram showing a distribution of noise intensity with respect to a resonance frequency of the LC resonance circuit.

FIG. 77 is a diagram showing an example in which a power supply device 1806 including an LC resonance circuit and an intermediate frequency and high frequency analog circuit block 1802 are formed on different chips.

FIG. 78 is a diagram showing a distribution of noise intensity with respect to a distance D between a system LSI 1807 and an intermediate frequency and high frequency analog circuit block 1802.

FIG. 79 is a power supply device 1 including an LC resonance circuit having an LC configuration.
FIG. 806 is a diagram illustrating a configuration of an 806.

Continued on front page F-term (reference)

Claims (4)

[Claims] 1. A semiconductor integrated circuit comprising: a power supply device including an LC resonance circuit; and at least one circuit block supplied with a power supply voltage from the power supply device, wherein the resonance frequency of the LC resonance circuit is A semiconductor integrated circuit, wherein a noise intensity determined based on the resonance frequency is set to be equal to or less than a predetermined value in a frequency band used by at least one circuit block. 2. The semiconductor integrated circuit according to claim 1, wherein said power supply device and said at least one circuit block are formed on a single semiconductor chip. 3. The semiconductor integrated circuit according to claim 1, wherein said power supply device and said at least one circuit block are formed on different semiconductor chips. 4. The semiconductor integrated circuit according to claim 1, wherein said power supply device supplies a DC voltage to said at least one circuit block.