JP2002300091A - Adjustment method for equalizing filter circuit for digital communication, and equalizing filter circuit for digital communication used for execution of the adjustment method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an adjustment method for an equalization filter circuit for digital communication with a compact circuit configuration able to be mounted on a small-sized LSI, that can efficiently adjust a plurality of adjustment points by means of a genetic algorithm. SOLUTION: The adjustment method is characterized by that first a plurality of objects each having a chromosome connecting optional digital initial values corresponding to each adjustment value of a plurality of adjustment points are selected to obtain an object group, two optional objects in the object group are selected as parents, two children are generated by applying a genetic operation including a cross processing and a mutation processing to the parents every repetitive input of an equalization signal, two objects, which have higher evaluation of adaptation of the signal after the equalization with respect to the equalizing signal, are selected among the two parents and the two children, and the processing of replacing the two parents with the selected objects and returning them to the object group, are repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital communication equalization filter circuit comprising an analog filter, an analog-to-digital converter, and a digital filter which are sequentially connected to each other. Is adjusted so that the evaluation of the fitness of the post-equalization signal output by the digital filter based on a predetermined equalization signal repeatedly input from the communication line to the analog filter before digital communication is increased. The present invention relates to a method for adjusting an equalization filter circuit for digital communication, which is suitable for adjustment by an algorithm, and an equalization filter circuit for digital communication used for implementing the adjustment method.

[0002]

2. Description of the Related Art As an equalizing filter circuit for digital communication as described above, IS
DS for Integrated Services Digital Network (DN)
There is an equalization filter circuit used for a U (Digital Service Unit), and in such an equalization filter circuit, it is necessary to perform online adjustment of a plurality of adjustment points for changing a filter coefficient. Further, such an equalizing filter circuit is an LSI
(A large-scale integrated circuit chip).

[0003] By using a genetic algorithm for on-line adjustment of an electronic circuit, good adjustment can be performed in a short time.
It is disclosed in 156627. However,
Generally, in the on-line adjustment of an electronic circuit, it is necessary to make the adjustment circuit compact in order to mount it on a smaller LSI. Therefore, in order to use a genetic algorithm (GA) for the adjustment circuit, G
It is necessary to realize each genetic operation of A with a compact circuit. Hereinafter, problems in realizing the GA with a compact circuit will be considered.

[0004] The research on the conventional GA hardware is basically aimed only at speeding up the genetic manipulation, and does not discuss the problem of more compact mounting. Therefore, first consider the problems when realizing each genetic operation of GA as a small-scale circuit, and based on this consideration,
The present invention proposes a genetic operation most suitable for hardware implementation.

[0005] As a problem when each processing of the GA is implemented as hardware, first, the size of a memory (chromosome memory) for storing chromosomes of each individual is described.
Consider each of the selection process and the crossover process.

[0006] GA is generally characterized in that the larger the number of genes, the more efficient the search. However, if you increase the population to search efficiently,
Accordingly, a large memory is required to store the chromosomes of each individual. Therefore, in order to make the circuit smaller, the smaller the number of individuals, the better. Therefore, in order to implement more compactly, a method that can efficiently perform a search even if the number of individuals is small is required.

[0007] In the GA, an individual having a higher evaluation value is selected, crossover processing and mutation processing are performed on those chromosomes, and an individual having a higher evaluation value is generated to perform a search. There are two methods of selecting the “generation model” and “non-generation model”. In the “generation model”, after calculating evaluation values of all individuals (N individuals), N individuals are selected therefrom according to the evaluation values. However, an individual having a large evaluation value may be selected a plurality of times. Therefore, extra memory is needed to store the chromosomes of the selected N individuals. In other words, in the generation model, a memory is required for storing a total of 2N chromosomes of N individuals before selection and N individuals after selection.

On the other hand, in the “non-generation model”, evaluation values of some individuals are calculated, and a selection process is performed only among the individuals for which the evaluation values have been calculated. For example, when the selection process is performed for each of four individuals, first, the evaluation values of the four individuals are calculated, and then the individual having the higher evaluation value is selected from the four individuals. Therefore, the chromosome of the selected individual can be stored in a small memory or register. For example, in the example shown above, it is sufficient if there is a register for storing four individuals and a memory for storing chromosomes of N individuals before selection. That is, when the “non-generation model” is used, only a memory for storing the chromosomes of N individuals and a small register are required, so that the implementation can be made smaller.

The crossover process is a process of recombining information of two chromosomes, in which a chromosome is cut at an arbitrary point (single point crossover) or at a plurality of points (multipoint crossover), and information is recombined before and after them. Yes, specifically, determine the point (crossover point) to be recombined according to the random number that maximizes the chromosome length,
The chromosomes are recombined before and after those crossover points. For this reason, in order to implement the crossover processing in hardware, a circuit that generates a random number having a maximum chromosome length is required. However, since a random number generator implemented in hardware can generate only a random bit string, its maximum value is limited to ^2M . Therefore, a circuit for normalization is required to generate a random number having an arbitrary maximum value. From the above considerations, in order to design a circuit for crossover processing to be small, a crossover method that does not require an arbitrary maximum random number is required.

[0010] From these considerations, the present inventors have reached the conclusion that it is desirable that genetic manipulation for hardware should satisfy at least one of the following three conditions. 1. 1. Efficient search method even for small populations Non-generation model 3. Crossover method that does not require random number of arbitrary maximum value

[0011]

Means for Solving the Problems and Action / Effect Thereof The method for adjusting the equalization filter circuit for digital communication of the present invention, which advantageously solves the above problems, comprises an analog filter, an analog-digital converter, and a digital filter. A plurality of adjustment points of the analog filter and the digital filter of the equalization filter circuit for digital communication, which are sequentially connected, and a predetermined equalization that is repeatedly input from the communication line to the analog filter before digital communication. In adjusting by the genetic algorithm so that the evaluation of the fitness of the equalized signal output by the digital filter based on the use signal is increased, first, the digital value corresponding to each adjustment value of the plurality of adjustment points A plurality of individuals having chromosomes linked to arbitrary initial values are prepared as a population, and thereafter, the population Each time the equalization signal is input repeatedly, two children are created from the parents by genetic manipulation including crossover processing and mutation processing, and the two parents are From the two offspring, select two individuals with high evaluation of the fitness of the post-equalization signal for the equalization signal, and replace the two parents with the selected individuals to return to the population. Is repeated.

According to such a method, the selection process is performed only between the parent and the child, as will be described later. Therefore, diversity can be maintained even with a small number of individuals, and since the "non-generation model" is used, the chromosome memory and the selection Since the processing registers are all small, the LSI can be made compact when online adjustment is performed by a circuit mounted on the LSI.

In the crossover process, a random bit string having the same length as the chromosome is created, and the two parents are used for 5 loci at each locus of the chromosome based on the bit string.
Gene information may be exchanged with a probability of 0%. In this case, it is sufficient to prepare a random bit string having the same length as the chromosome, and a random number having an arbitrary maximum value is not required. Therefore, a circuit for crossover processing can be designed to be small.

In the mutation processing, a predetermined mutation rate composed of a bit string is compared with one or more lower bits of a random bit string having the same number of bits as the bit string, and the mutation rate is larger. And 1 if the remaining upper bits of the random bit string do not have a 1
Is repeated, to produce two mutation masks consisting of a bit string of the same length as the chromosome, and for the two individuals subjected to the crossover process, the two mutation masks are used, respectively. A mutation may be generated so that the data of the chromosome locus corresponding to the bit where 1 is set is inverted. In this way, the circuit for mutation processing can be designed to be small.

An equalizing filter circuit for digital communication of the present invention used for carrying out the adjusting method is a digital communication equalizing filter circuit comprising an analog filter, an analog-digital converter, and a digital filter which are sequentially connected. In the conversion filter circuit, a mutation rate register that holds a mutation rate used for the mutation processing, a chromosome memory that stores chromosomes of a plurality of individuals of the population in association with the fitness of those chromosomes, Two parent registers that hold the two parent chromosomes in correspondence with the fitness of those chromosomes, and two child registers that hold the two child chromosomes in correspondence with the fitness of those chromosomes, A genetic manipulation circuit used for the genetic manipulation, and the fitness of the chromosomes of the two parents is obtained and held in the parent register. An evaluation circuit that obtains the fitness of the chromosomes of the two children and holds them in the child register, and selects two individuals with a high evaluation of fitness among the two parents and the two children, and selects them. A selection and selection circuit for replacing the two parents with an individual.

According to such an equalizing filter circuit for digital communication, the adjusting method of the present invention can be implemented with a compact circuit configuration, and the equalizing filter circuit for digital communication that performs adaptive adjustment by a genetic algorithm is mounted. LSI
Can be made compact.

The gene manipulation circuit includes a random number generator for generating the random bit string, a crossover circuit for performing the crossover process, a mask generation circuit for generating the mutation mask, and a sudden generation process for performing the mutation process. It may have a mutation circuit.

It is preferable that the digital communication equalizing filter circuit is mounted on an LSI used for an ISDN DSU, since a small LSI and an inexpensive DSU can be realized.

[0019]

Preferred embodiments of the present invention will be described below with reference to the drawings. In the present invention, as a genetic operation for satisfying the above three conditions, MMG (Minimal Gene
ratio gap model), UC (Uniform Crossover), and a combination thereof.

The MMG is a system that simplifies each processing of the GA and enables efficient search even with a small number of individuals.
The MMG is a non-generation model. As shown in FIG. 1, two individuals (parent 1 and parent 2) arbitrarily selected from the population in step S1 and the parent in step S2 are subjected to genetic manipulation. The selection process is performed only between the two created individuals (child 1, child 2). That is, after the fitness calculation (evaluation) of the children 1 and 2 is completed in step S3, the top two individuals having the higher fitness values among the four individuals of parent individuals 1 and 2 and child individuals 1 and 2 are determined in step S4. Then, in step S5, the parent individual is replaced with the selected two individuals. Note that all individuals in the initial population are evaluated first, and the fitness is determined.

Since the MMG performs selection processing only between the parent and the child, diversity can be maintained even with a small number of individuals, and since it is a non-generation model, one of the three conditions described above. "Efficient search method for small populations"
And 2. Of "non-generation model".

UC is 5 for each locus on the chromosome.
In this method, gene information is exchanged with a probability of 0%. In this method, it is not necessary to determine the crossover position, and it is sufficient to prepare a random bit string having the same length as the chromosome. It satisfies the condition "crossover method that does not require an arbitrary maximum random number".

Thus, by combining MMG and UC, all of the above three conditions can be satisfied.

Next, an example of a circuit that can execute the above MMG and UC at high speed is an FPGA (Field Programmable Gate Arrangement).
The result of evaluating the circuit scale and the operation speed by mounting on a (ray) is shown. As shown in FIG. 2, the circuit mounted on the FPGA has two registers (80 bits) R1 and R2 for the chromosome of the parent individual (parent and parent 2) R1 and R2, and two registers for the chromosome of the child individual. (80 bits) (child 1, child 2) R3
R4, one register R5 for the mutation rate, and a gene manipulation circuit GC described later.

According to the circuit mounted on the FPGA, the chromosome is written into the two registers R1 and R2 for the parent chromosome in 80-bit units, and genetic manipulation is performed on them to make the child chromosome (80 Bits) are output to two registers R3 and R4 for the child chromosome.

As shown in FIG. 3, the genetic operation circuit comprises four circuits: a crossover circuit CC, a mutation circuit MC, a mutation mask generation circuit MD, and a random number generator RG.

The crossover circuit CC receives an 80-bit random bit string from the random number generator RG, as shown in FIG. (C1, C2) is made. This bit string (C1, C2) is subjected to mutation processing by a mutation circuit MC. As the random number generator RG, a random number generator based on a cellular automaton, which is most often used in research on hardware implementation of a conventional GA, is used.

As shown in FIG. 5, the mutation circuit MC receives two 80-bit bit strings (mutation masks) (M1, M2) from the mutation mask generation circuit MD, and respectively receives the crossover circuits. Bit string made with CC (C
1, C2) and XOR for each bit. That is, M1,
Mutation is caused at a bit of M2 where 1 is set (data of a chromosome locus corresponding to a bit where 1 is set is inverted, and 0 is set to 1 and 1 is set to 0).

As shown in FIG. 6, the mutation mask generation circuit MD compares the random number with the mutation rate for each of the 80 bits to determine whether or not to perform mutation for each bit, and Create a mask for mutation (M1, M2). Generally, it is necessary to compare the mutation rate (8 bits) with the random number (8 bits) for each bit, so an 8-bit comparison circuit is required. However, since the 8-bit comparison circuit is large, taking into account the nature of the mutation rate, this embodiment uses the following method to reduce the size of the circuit.

If the value of the mutation rate is large, the search becomes close to a random search, so that a very large value is not adopted. That is, the upper bit of the mutation rate is always 0 in many cases. Therefore, here, the upper bits of the mutation rate are fixed to 0, and only the lower 2 bits are made valid. Specifically, as shown in FIG. 6, only the lower 2 bits of the random number are compared, and if there is 1 in the upper 6 bits, it is determined that the random number is larger than the mutation rate.

Since this method does not require an 8-bit comparison circuit and can be realized only by a 2-bit comparison circuit and a 6-bit logical sum, the circuit can be made smaller.

The mounted circuit (see FIG. 2) is an XC4
025 (equivalent to 25000 gates) CLB (Configurab
le Logic Block) 65% (668 out of a maximum of 1024)
Only). Although the exact number of gates cannot be calculated from the number of used CLBs, the size is about 16250 gates (65% of 25,000 gates) to about 25,000 gates.

Also, in the circuit mounted above, the parent 1 and the parent 2
The delay from the first register to the first and second registers is 4
6.3 [ns]. On the other hand, the same processing is performed by a so-called workstation type computer (trade name) Ultra Sparc II (CP) manufactured by Sun Microsystems.
Approximately 3750 [ns] is required for software execution at a U operation speed of 200 MHz), and thus it has been found that the implemented circuit can perform genetic manipulation approximately 80 times faster.

[0034]

Next, an ISDN as an embodiment of the present invention will be described.
A digital communication equalizing filter circuit mounted on an LSI used in a DSU for digital communication will be described with reference to the drawings.
FIG. 7 shows an equalizing filter circuit for digital communication according to the embodiment. The equalizing filter circuit includes an analog filter circuit AF and an analog-digital converter circuit ADC.
And a digital filter circuit DF, which are sequentially connected.
C and a digital filter circuit DF, and a phase locked loop (PLL) circuit PLC for synchronizing the digital filter circuit DF, and a genetic algorithm processing circuit G for simultaneously adjusting the analog filter circuit AF and the digital filter circuit DF.
AC equipped.

The genetic algorithm processing circuit GAC here has a digital filter circuit DF as shown in FIG.
And an adjusting portion for changing the filter coefficient for determining the filtering frequency characteristic for Δf equalization provided in the analog filter circuit AF constituting the normal analog filter based on the digital data. Three programmable gain amplifiers (P
GA), and supplies three adjustment values consisting of 8-bit digital values for adjusting their operation, respectively, and at the same time, the digital filter circuit DF of the above-mentioned digital filter circuit DF constituting an ordinary seven-stage FIR filter as shown in FIG. For bridge tap equalization, seven gain adjustment values a2 to a8 each consisting of an 8-bit digital value for operation adjustment of the adjustment unit of each stage as an adjustment part for changing the filter coefficient are supplied, and the two gain adjustment values are set. The filter circuits AF and DF are simultaneously adjusted. As a result, the genes in the genetic algorithm have 8 bits × 10 genes and have 80-bit chromosomes. Note that a1 in FIG. 8 is a constant gain value.

Specifically, in this embodiment, the IS
Using the first training sequence sent from the central office as a protocol to the DSU in the transmission method called ping-pong method, which is a feature of DN, the reflection component of the line of the equalizing filter circuit of the above embodiment is obtained by a genetic algorithm. Optimize the noise removal function.

FIG. 9 shows the burst pattern repeated in the training sequence, and FIG.
0 (a) and (b) are 2 bits of 377 bits (16 + 8 × 45 + 1 = 377) in the burst pattern.
3 shows different types of training patterns. “M” is 1
And 0 alternate, and “P” indicates a parity bit.

Since the start-up time of the system is usually specified to be within 250 ms and the worst case within 300 ms, it is desirable that the training sequence used for determining the parameters for line equalization (optimization of the equalization filter circuit) should be completed within 100 ms. . Thus, the burst pattern is 2.
Since the repetition is performed at 5 ms, the adjustment using the training pattern can be performed 40 times even at 100 ms. The adjustment may be performed 40 times using the entire 377 bits, or may be performed 40 × 45 = 1800 times using 8 bits × 45 times each time.

FIG. 11 is a diagram showing the configuration of the genetic algorithm processing circuit GAC. The genetic algorithm processing circuit GAC includes a digital filter circuit DF.
And a comparison circuit CPC that receives the equalized data of the above training pattern, compares it with predetermined training data held in advance, and outputs the number of correct answers (or the number of incorrect answers) as fitness. The system includes a chromosome memory GM for storing the individuals in association with the chromosomes of each individual and their fitness, and a normal random number generator (not shown).

In addition, similar to the circuit shown in FIG. 2, the genetic algorithm processing circuit GAC stores the mutation rate given in advance in the register R5 and the two parental circuits extracted from the chromosome memory GM. The chromosome of the individual and the genes of the two offsprings created by genetic manipulation are stored in four registers R1 to R4, and the fitness is compared between the two parents and the two offsprings. The two individuals with high fitness are returned as parent individuals to the chromosome memory GM, and after the training sequence, the 80-bit data of the chromosome is divided into 8 bits × 3 and 8 bits × 7, and the analog filter circuit AF and the digital filter circuit are divided. Selection selection circuit SC to be supplied to DF and DF, respectively
Similarly to the circuit shown in FIG. 3, two chromosomes of two parent individuals supplied from the selection and selection circuit SC are subjected to genetic manipulation processing based on the mutation rate also supplied from the selection and selection circuit SC to obtain two chromosomes. And a gene manipulation circuit GC for producing offspring individuals and supplying those genes to a selection and selection circuit SC.

FIG. 12 is a flowchart showing the operation of the genetic algorithm processing circuit GAC centering on the operation of the selection / selection circuit SC in the digital communication equalization filter circuit of this embodiment.
In step S1, the identification numbers of the two parents (parent individuals) 1 and 2 are arbitrarily determined based on the random numbers generated by the random number generator. In the next step S12, the two parents 1 and 2 corresponding to those identification numbers are determined.
2 is obtained from the chromosome memory GM and stored in the registers R1 and R2. In the subsequent step S13, the chromosome data of the two parents 1 and 2 are stored in the genetic operation circuit G.
Set to C.

Next, in step S14, the genetic manipulation circuit GC performs the crossover process and the mutation process as described above to convert the chromosome data of the two children (child individuals) created from the two parents 1 and 2 into the gene. It is taken out from the operation circuit GC, and in the next step S15, the chromosome data of the child 1 are first converted into analog and digital filter circuits A
F, DF, the training data is equalized (equalized) by the analog and digital filter circuits AF, DF, and the number of correct answers (or the number of incorrect answers) of the equalized digital data is obtained by the comparison circuit CPC. The fitness of 1 is determined and stored in the register R3. And the following step S
At 16, the fitness is determined for child 2 in the same manner as for child 1, and stored in register R4.

Next, in step S17, two individuals with higher fitness (high number of correct answers or small number of incorrect answers) are selected from the four individuals of two parents and two children, and the following step S18. Then, the chromosome data of the upper two individuals is written into the chromosome memory GM at the positions of the parents 1 and 2 of the identification numbers determined in step S11. Then, in the following step S19, the logic circuit makes an end determination to determine whether or not a predetermined end condition such as the fitness value exceeds a predetermined value or the training sequence has ended, and the end condition is satisfied. If not, step S20
And returns to step S11 to repeat the above-mentioned processing. On the other hand, when the termination condition is satisfied, the processing proceeds from step S20 to the termination processing (not shown), and the individual in the chromosome memory GM, which finally has the highest fitness, Is set in the analog and digital filter circuits AF and DF, and the optimization process is terminated.

Thus, according to the equalizing filter circuit for digital communication of this embodiment and the adjusting method executed by the same,
Since selection processing is performed only between the parent and the child, diversity can be maintained even with a small number of individuals, and since the "non-generation model" is used, both the chromosome memory and the selection processing register can be small. When mounted on an LSI, the LSI can be made compact.

Further, according to the equalizing filter circuit for digital communication of this embodiment and the adjusting method executed by the same, a random bit string having the same length as the chromosome is formed by the crossover process, and each gene of the chromosome is generated based on the bit string. Since two parents exchange gene information with a 50% probability for each locus, it is sufficient to prepare a random bit string of the same length as the chromosome, and it does not need an arbitrary maximum random number. The circuit for the crossover process can be designed to be small.

Further, according to the equalizing filter circuit for digital communication of the present embodiment and the adjusting method executed by the same, the mutation processing allows a predetermined mutation rate consisting of a bit string to be obtained,
One or a plurality of lower bits of the bit string and a random bit string of the same number of bits are compared with each other, and if the mutation rate is higher and there is no 1 in the remaining upper bits of the random bit string, 1 is set. By repeating the process of outputting, two mutation masks consisting of a bit string of the same length as the chromosome are created, and 1 is set for each of the two individuals subjected to the crossover process by the two mutation masks. Since the mutation is generated so as to invert the data of the chromosome locus corresponding to the bit, the circuit for the mutation processing can be designed small.

Since the digital communication equalization filter circuit of this embodiment is mounted on an LSI used for an ISDN DSU, it is possible to realize a small LSI and hence an inexpensive DSU.

As described above, the present invention has been described based on the illustrated examples. However, the present invention is not limited to the above-described examples.
It goes without saying that the present invention can be applied to uses other than U.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a preferred embodiment of a method for adjusting an equalization filter circuit for digital communication according to the present invention.

FIG. 2 is a configuration diagram showing an example of a digital communication equalization filter circuit used for implementing the adjustment method of the embodiment.

FIG. 3 is a configuration diagram showing an example of a gene manipulation circuit in the equalization filter circuit of the above example.

FIG. 4 is a configuration diagram showing an example of a cross-processing circuit in the gene manipulation circuit of the above example.

FIG. 5 is a configuration diagram illustrating an example of a mutation processing circuit in the gene manipulation circuit of the above example.

FIG. 6 is a configuration diagram showing an example of a mutation mask generation circuit in the gene manipulation circuit of the above example.

FIG. 7 is a digital communication equalization filter circuit mounted on an LSI used in an ISDN DSU as a specific example of a digital communication equalization filter circuit used for implementing the adjustment method of the embodiment. FIG.

FIG. 8 is an explanatory diagram showing a configuration of a digital filter circuit in the equalization filter circuit of the embodiment.

FIG. 9 is a time chart showing a burst pattern repeated in the first training sequence sent from the central office to the DSU.

FIGS. 10A and 10B are explanatory diagrams respectively showing two types of training patterns of 377 bits in the burst pattern.

FIG. 11 is a configuration diagram showing a genetic algorithm processing circuit in the equalization filter circuit of the embodiment.

FIG. 12 is a flowchart showing the operation of the genetic algorithm processing circuit centering on the operation of the selection and selection circuit in the digital communication equalization filter circuit of the embodiment.

[Explanation of symbols]

 a1 Constant gain value a2 to a8 Gain adjustment value R1 to R5 Register AF Analog filter circuit CC Crossover processing circuit DF Digital filter circuit GC Gene manipulation circuit GM Chromosome memory MC Mutation processing circuit MD Mutation mask generation circuit RG Random number generator SC Selection and selection circuit ADC Analog-digital converter circuit CPC comparison circuit GAC Genetic algorithm processing circuit PLC PLL circuit

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masahiro Murakawa 1-1-4 Umezono, Tsukuba, Ibaraki Pref., Ministry of Economy, Trade and Industry (AIST) (72) Inventor Isamu Kajitani, Umezono, Tsukuba, Ibaraki 1-4-1 In-house Research Institute of Electronics and Technology, Ministry of Economy, Trade and Industry (72) Inventor Tetsuya Higuchi 1-4-1 Umezono, Tsukuba-city, Ibaraki Pref. (72) Inventor Masahiko Kato 3-7-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo Asahi Kasei Microsystems Co., Ltd. F term (reference) 5K046 AA01 BA01 BA06 BB05 EE06 EE10 EF02 EF15 EF23 EF26

Claims (6)

[Claims] 1. A digital communication equalization filter circuit comprising an analog filter, an analog-to-digital converter, and a digital filter which are sequentially connected to each other. In adjusting by the genetic algorithm to increase the evaluation of the fitness of the post-equalization signal output by the digital filter based on a predetermined equalization signal repeatedly input to the analog filter from the communication line before communication, First, a plurality of individuals having chromosomes connected to arbitrary initial values of digital values corresponding to respective adjustment values of the plurality of adjustment points are prepared as an individual group, and then, any two individuals in the individual group As a parent,
Each time the equalization signal is repeatedly input, two children are created from their parents by genetic operations including crossover processing and mutation processing, and the two parents and two children are used for the equalization. Selecting two individuals with high evaluation of the fitness of the post-equalization signal for the signal, replacing the two parents with the selected individuals and returning to the population, repeating the process of How to adjust the equalization filter circuit for digital communication. 2. In the crossover process, a random bit string having the same length as the chromosome is created, and gene information is generated at a probability of 50% between the two parents at each locus of the chromosome based on the bit string. 2. The method for adjusting a digital communication equalization filter circuit according to claim 1, wherein the adjustment filter circuit is replaced. 3. In the mutation process, a predetermined mutation rate composed of a bit string is compared with one or more lower bits of a random bit string having the same number of bits as the bit string, and the mutation rate is determined to be higher. The process of outputting 1 when there is no 1 in the large and the remaining upper bits of the random bit string is repeated, and two mutation masks consisting of a bit string of the same length as the chromosome are created, Claims: Mutation is performed on two individuals that have been subjected to crossover processing so that data of a chromosome locus corresponding to a bit where 1 is set in each of the two mutation masks is inverted. Item 3. An adjustment method of the equalization filter circuit for digital communication according to Item 2. 4. A digital communication equalization filter circuit comprising an analog filter, an analog-to-digital converter, and a digital filter connected in sequence, wherein a mutation maintaining a mutation rate used in the mutation processing is provided. A rate register, a chromosome memory for storing chromosomes of a plurality of individuals in the population in association with the fitness of those chromosomes, and a chromosome memory for retaining the chromosomes of the two parents in association with the fitness of those chromosomes. Two parent registers; two child registers for holding the two child chromosomes in association with the fitness of those chromosomes; a gene manipulation circuit used for the genetic manipulation; and a fitness of the two parent chromosomes An evaluation circuit for determining the fitness of the chromosomes of the two children and for storing the fitness of the chromosomes of the two children in the child register. A selection and selection circuit for selecting two individuals with high evaluation of fitness among two parents and two children, and replacing the two parents with the selected individuals. An equalizing filter circuit for digital communication used for implementing the adjusting method according to claim 3. 5. A genetic operation circuit comprising: a random number generator for generating the random bit string; a crossover circuit for performing the crossover processing; a mask generation circuit for generating the mutation mask; The equalization filter circuit for digital communication according to claim 4, further comprising a mutation circuit. 6. The digital communication equalization filter circuit according to claim 4, wherein the digital communication equalization filter circuit is mounted on an LSI used for an ISDN DSU.