JP2002298587A - Programable memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device which can fully exhibit the functions of a volatile memory and a programmable non-volatile memory. SOLUTION: Programming voltage is applied to a DRAM memory cell consisting of word lines, bit lines, transistors, and capacitive storing devices to fully employ the functions of a non-volatile memory. Programming voltage varies permanently the voltage leak function of the capacitive storing device. Therefore, in this DRAM memory device, the voltage leak characteristics of a cell can be read out by measurements.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable memory device, and more particularly to a dynamic random access memory.
The present invention relates to a method for programming an access memory.

[0002]

2. Description of the Related Art In modern society, electronic devices capable of storing data are becoming more and more popular. Most data processing devices consist of two types of memory devices, so-called volatile memory or RAM, and non-volatile memory or ROM. Volatile memory loses stored data when power to the device is lost, while non-volatile memory can store data even after power to the device is lost. In many electronic devices, both types of memory devices are typically provided, with non-volatile memory being used for long-term storage of data that changes infrequently and volatile storage for data that is needed only for short periods Memory is used.

[0003] The most common types of volatile memory devices are dynamic random access memory,
That is, it is a DRAM. DRAM is preferably selected because of its relatively low manufacturing cost, large storage capacity, and small size. Advances in semiconductor manufacturing methods have allowed DRAMs to be made smaller and cheaper.

[0004] A DRAM array comprises a plurality of memory cells,
It is manufactured by duplicating several million identical memory circuits composed of word lines and bit lines. Bit lines and word lines are arranged orthogonally,
The memory cells are arranged adjacent to the intersection of a word line and a bit line. A conventional DRAM memory cell is a single transistor structure, where the memory cell has a storage capacitor, a first terminal of which is connected to a reference voltage such as V _REF and a second terminal of which is typically a field effect transistor. Are connected to the respective pass gate transistors.

Data is stored in each memory cell as a charge level on a storage capacitor. In the storage capacitor, a current leaks from either the storage capacitor or the pass gate transistor due to an excessive time. The leakage current due to the excess of the time lowers the voltage level of the storage capacitor, particularly, the high voltage level. Therefore, the voltage levels on the storage capacitors need to be refreshed periodically to prevent corruption of the data stored in the memory cells.

Conventional DRAMs typically use a current sense amplifier that senses whether the value in a selected memory cell is a logical one or zero. To read data, the sense amplifier detects a small differential voltage between the stored voltage and a reference voltage. The sense amplifier can further increase the voltage difference to a maximum logic level.

[0007]

When a non-volatile memory is required, most devices use a PROM type or a mask ROM type. However, these types of memory have the limitations of being physically larger and more expensive than modern DRAMs. In general, there is a great difference between the manufacturing methods of the ROM memory and the RAM memory, so that it is very difficult to manufacture them on a single device. Using another method, DR
The circuit of the AM memory cell is intentionally shorted and the mask RO
M function is provided to enable cell reading using a conventional sensing circuit. However, there is a limitation that these methods must be performed during the manufacturing process. Accordingly, there is a need for a memory device that can perform both functions of volatile memory and programmable non-volatile memory.

[0008]

According to the present invention, there is provided a memory device in which a dynamic random access memory (DRAM) can perform the functions of a volatile memory and a programmable non-volatile memory. Also,
Dynamic random access memory (DRA)
It is also an object of the present invention to provide a programming method of M). It is a further object of the present invention to provide a method for controlling and reading out a programmed dynamic random access memory (DRAM). Since the DRAM can realize the functions of the volatile memory and the nonvolatile memory, the present invention can capture all the advantages of the DRAM memory such as small size, low cost, and large storage capacity.

SUMMARY OF THE INVENTION The present invention is a dynamic random access memory in which individual memory cells are programmed by applying a programming voltage to the memory cells, thereby acting on the dielectric layer to change the capacitance storage characteristics. Is disclosed. The changed storage device then has a persistent current leakage characteristic indicating that the cell has been programmed. The ability to program the device after fabrication is a distinct advantage over conventional devices.

[0010] The device according to the present invention charges all memory cells and determines the cells to be programmed by giving the leakage cells time to discharge. Memory cells to which a programming voltage has been applied decrease in voltage at a greater rate than non-programming memory cells. Then the device reads the DRAM device and
Determine the program data sequence. The device periodically refreshes the memory cells to maintain the desired stored value.

[0011] These and other features which characterize the invention are set forth in the claims annexed hereto and forming a separate part. However, for a better understanding of the invention, its advantages, and the objects attained with it, refer to the drawings and the accompanying description.

[0012]

DETAILED DESCRIPTION OF THE INVENTION The present invention described below provides a method of manufacturing, reading, and controlling a programmable dynamic random access memory (DRAM). In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof. The accompanying drawings illustrate certain preferred embodiments in which the invention may be practiced. These preferred embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and other embodiments may be utilized and logical changes may be made without departing from the spirit and scope of the invention. It should be understood that it is possible to add Therefore, the following detailed description should not be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

FIG. 1 shows an M row × N column DRAM memory cell array 130, a controller 110, and a row decoder 1.
20, a plurality of sense amplifiers 140, a column decoder 150,
1 shows a memory 100 comprising a plurality of read amplifiers 160 and a plurality of write buffers 170. The controller 110 includes a clock generator, a command generator, a row / column address converter, and a power supply. DRAM array 130 comprises a plurality of identical memory cells arranged in M rows × N columns. As is well known to those skilled in the art, generally D
The RAM array is divided into a plurality of memory banks. Access to each bank is performed by the row decoder 120 and the column decoder 150. The circuit receives the control signal and sends the controller 11 from an external source such as a CPU.
Time to zero. Although not shown here, the principles of the present invention can be incorporated into many types of data manipulation devices known to those skilled in the art.

FIG. 2 illustrates a conventional DRAM memory cell 200 having a single transistor structure consistent with the present invention. This memory cell comprises a storage capacitor 25
And its first terminal is connected to a reference voltage, such as V _REF , and its second terminal is connected to a pass gate transistor, which is typically a field effect transistor 240. The reference voltage V _REF is usually specified to be one half of the power supply voltage V _DD . Pass gate transistor 2
40 carries charge to the storage capacitor 250 and serves to read the capacitor and measure its charge level. The gate electrode of pass gate transistor 240 is connected to word line decode signal 210 and the drain electrode is connected to bit line 230. Generally, pass gate transistor 240 is an N-channel field effect transistor. When a voltage indicating a high or low logic level is stored in the storage capacitor 250 of the memory cell, the voltage level is supplied to the selected word line 210 and the gate electrode of the pass gate transistor 240, and the corresponding memory cell Starts. The charge then travels between the storage capacitor 250 and the corresponding bit line 230 via the pass gate transistor 240. The operation and implementation of non-volatile memory devices are well known to those skilled in the art and will not be described in detail here.

The present invention discloses a methodology for programming DRAM cells by exposing selected cells to a programming voltage and changing the leakage characteristics of the cells. Thereby, the DRAM device can realize the volatile memory function and the nonvolatile memory function in the same device. The programming voltage _VP is a voltage high enough to apply stress to the dielectric layer to cause dielectric breakdown and permanently reduce the capacitive storage capability of the dielectric layer. Voltage _VP
Can be generated from various sources, including internal and external means. The exact value of V _P, the thickness of the dielectric layer, factors such as the type, and the skilled person will be determined by the structure of a known storage capacitor. Also applies the voltage to the cell at the maximum size, or may be gradually increasing voltage to a magnitude of V _P. For example, 5
Against ONO dielectric layer having a thickness of 0 Å, the programming voltage, i.e. _{V P} is approximately 6-7 volts. Certain time is applied to the plate electrode of the storage capacitor programming voltage V _P. This time depends on the thickness and type of the dielectric layer, the construction of the storage capacitor, and the degree of dielectric layer breakdown required. Note that the programming voltage is applied for a fixed or continuous time. Both this time and the value of the programming voltage applied to a particular device can be measured by a test procedure before the programming procedure. This testing procedure allows the programming procedure to take into account material and process differences,
Procedures can be individualized for a single device or a group of devices. In accordance with another embodiment of the present invention, there is provided a method of programming a DRAM memory cell having a variable storage capacity. Therefore, this DR
AM memory devices can store various logic values according to the voltage leakage characteristics of a particular memory cell.

The programming method will be described in detail below. FIG. 3 is a timing diagram illustrating a programming method according to the present invention. A programming voltage is applied to a first terminal of the storage capacitor 320. Then, the word line goes high, and the transistor on the word line 310 is activated. Each memory cell is connected to its corresponding bit line 330
Is activated, and the write enable signal 340 is activated to enable programming.
Note that the voltage on the bit line is typically ground, but a voltage can be applied to the bit line during the programming procedure. Then another word line is selected and the memory cells on that word line are programmed, and so on.

FIG. 4 illustrates the reading and operation of a programmable DRAM according to one preferred embodiment of the present invention. At step 405, power is supplied to the circuit. In step 410, the next programmed DRAM storage location is charged. In step 415, the circuit waits for a certain time, and the cell leaks. Storage locations where the programming voltage was applied leak current and lower the power level at a greater rate than storage locations where the programming voltage was not applied. At step 420, the storage location voltage level V
_LEVEL is measured. If memory locations voltage level _{V LEVE L} in step 425 matches the first predetermined voltage range _{(V 1),} the logical value 1 is assigned to memory location at step 430. Memory location voltage level V _LEVEL is second
, A logical value of 0 is assigned to the storage location in step 435. In the embodiment of the present invention, the sense amplifier 140 is connected to the voltage level (V _LEVEL ).
_Is detected, and a logical value 1 or 0 can be output by comparing _VLEVEL with the reference voltage _VREF . Step 44
0 and 445 refresh the storage location if necessary. In step 450, the circuit checks whether all programmed locations have been read. If all have been read, the program proceeds to step 455 to periodically refresh the storage location. If there is still a memory location to be read, the circuit proceeds to step 4
Return to 10. It should be noted that, according to the present invention, the test procedure can determine the drainage time of the memory cells required by an individual memory device to account for programming, material, or process differences.

In another embodiment, the conventional D
One can imagine the manufacture of a DRAM device with a region of volatile memory that matches the RAM device and a region that is programmed as disclosed in the present invention. Thus, a memory that can flexibly mix programmable non-volatile memory and ordinary DRAM on the same die.
The system is very attractive. Volatile DRAM and another type of memory device with associated circuitry, such as E
Mixtures with non-volatile DRAM with PROM are also
It is incorporated into a single device, as is well known to those skilled in the art. Various additional modifications can be made to the embodiments described above without departing from the spirit and scope of the invention. Accordingly, the invention is in the claims.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a general structure of a DRAM and associated circuits.

FIG. 2 is a circuit diagram of a DRAM memory cell according to the prior art.

FIG. 3 is a timing diagram illustrating a programming method according to a preferred embodiment.

FIG. 4 shows a programmable DRAM according to a preferred embodiment.
5 is a flowchart showing an operation method of the embodiment.

[Explanation of symbols]

 100: memory 110: controller 120: row decoder 130: DRAM array 140: sense amplifier 150: column decoder 160: read amplifier 170: write buffer 200: DRAM memory cell 210: word line 230: bit line 240: pass gate -Transistor 250: Storage capacitor 310: Word line 320: Storage capacitor 330: Bit line 340: Writable signal

Claims (23)

[Claims] An individual memory to be programmed.
Selecting a cell; and changing a voltage leakage characteristic of the memory cell.
Applying a programming voltage to the memory cell. 2. The method of claim 1, wherein said memory device is a DRAM. 3. The method of claim 1, wherein said programming voltage is a voltage of a magnitude suitable to stress a dielectric of a capacitive storage device of a DRAM memory cell. . 4. The method of claim 1, wherein said individual memory cells comprise a storage capacitor, a first bit line, a first word line, and a transistor. 5. The method according to claim 1, wherein the programming voltage is applied with increasing voltage. 6. A method for reading a DRAM device, the method comprising: charging a memory cell to a first voltage; allowing discharge from the memory cell for a certain time; and measuring a voltage level after a certain time. Assigning a value to a storage location based on the voltage level; and periodically refreshing the memory cell. 7. The method of claim 6, wherein a memory cell having a higher voltage level after a certain time is assigned a logical value of one, and a memory cell having a lower voltage level after a certain time is a logical value. A method characterized by assigning 0. 8. The method of claim 6, wherein said voltage level is compared to a reference voltage level. 9. A semiconductor device comprising: at least one memory cell having a first voltage drainage characteristic; and at least one memory cell having a second voltage drainage characteristic, wherein the second voltage drainage characteristic has a capacity storage capacity. A programmable DRAM characterized by being obtained by intentional alteration. 10. The programmable DR according to claim 9, wherein:
The programmable DRAM of claim 1, wherein the memory cell comprises a storage capacitor, a first bit line, a first word line, and a transistor. 11. Programmable DR according to claim 9,
In the AM, the change in the capacity storage capacity is caused by intentionally applying a programming voltage. 12. The programmable DR according to claim 9, wherein:
In the AM, the programming voltage is a voltage of a suitable magnitude to stress a dielectric of a capacitive storage device of a DRAM memory cell.
M. 13. A memory device, comprising: a volatile DRAM memory cell; an associated circuit for accessing said volatile memory cell; and an electrical device comprising a word line and a bit line, a transistor, and a storage capacitor. Programmable nonvolatile D
RAM memory cell, associated circuit for programming the nonvolatile DRAM memory cell, associated circuit for reading the nonvolatile DRAM memory cell, and associated circuit for refreshing the DRAM memory cell An adjunct circuit for programming the non-volatile DRAM memory cell programs the memory cell by applying a programming voltage to the storage capacitor to change the storage capacity of the storage capacitor. An associated circuit for reading the non-volatile DRAM memory cell charges the memory cell to a certain voltage, waits for a predetermined time, detects the voltage level of the storage capacitor, Assigning a level-based value to said memory cells. Memory characterized by
device. 14. The memory device according to claim 13, further comprising a sense amplifier for detecting a voltage level of the storage capacitor. 15. The memory device of claim 14, wherein the sense amplifier further comprises a reference voltage for assigning a value based on the voltage level to a memory cell. 16. The memory device according to claim 13, wherein said memory device further comprises a mask ROM memory cell and associated circuits. 17. The memory device according to claim 13, wherein said memory device further comprises an EPROM memory cell and associated circuits. 18. A memory device, comprising: at least one electrically programmable non-volatile DRAM memory cell comprising word and bit lines, a transistor, and a storage capacitor; and programming the DRAM memory cell. And an auxiliary circuit for reading the DRAM memory cell, wherein the auxiliary circuit for programming the DRAM memory cell includes a programming voltage for changing a storage capacity of the storage capacitor. By applying the following to the storage capacitor to program the memory cell and read out the DRAM memory cell:
Charging the memory cell to a certain voltage, waiting for a predetermined time, detecting a voltage level of the storage capacitor, and assigning a value based on the voltage level of the storage capacitor to the memory cell. Memory device. 19. The memory device according to claim 18, wherein said memory device is also a volatile DRAM memory device.
A memory device comprising a cell and an associated circuit. 20. The memory device according to claim 18, further comprising a sense amplifier for detecting a voltage level of the storage capacitor. 21. The memory device of claim 20, wherein the sense amplifier further comprises a reference voltage for assigning a value based on the voltage level to a memory cell. 22. The memory device according to claim 18, wherein said memory device further comprises a mask ROM memory cell and associated circuits. 23. The memory device according to claim 18, wherein said memory device also comprises EPROM memory cells and associated circuitry.