JP2002292935A - Image write apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely correct an image write position by a write head even when image data is transferred in units of a plurality of pixels. SOLUTION: For writing an image by a plurality of write heads 1-3, an image data DATA transferred in units of a plurality of pixels to an SRAM write control unit 102 of a first IC 10 is shifted in units of one pixels and then formed into a plurality of formats having pixel data in units of a plurality of pixels. One of the image data in the plurality of formats is selected in accordance with image position designation data for designating the image write position by each of write heads 1-3, and written to an SRAM 30 as a buffer memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image writing apparatus for writing an image with a plurality of writing heads, such as a wide-area copying machine (or plotter).

[0002]

2. Description of the Related Art There is an image forming apparatus for forming an image on a photoreceptor by a writing head using an LED array.
However, when forming a wide image, since a long write head corresponding to the width is expensive and low in reliability, it is necessary to form the image by sharing the write area with a plurality of small write heads. Is being done. In addition, the image reading and image processing unit and the image writing unit are relatively far apart, and it is necessary to perform high-speed data transfer. In many cases, image data is transferred in units of a plurality of pixels to reduce the transfer speed. The image data is distributed to a plurality of small write heads, and each write head is driven to form an image.

In order to form a clear image by this method, it is necessary to control each writing head so that the boundary of the area in charge is not shifted. This control is performed by changing a data transfer address to each write head. Further, as a method of making a shift which is difficult to correct by adjustment inconspicuous, Japanese Patent Application Laid-Open No. 8-2583 is disclosed.
No. 37 proposes an apparatus and a method for randomly setting the boundaries of the areas in charge of a plurality of write heads for each line of an image.

[0004]

As described above, in order to form a clear image with a plurality of small write heads, it is necessary to connect the write heads so that the boundaries of the shared areas are not shifted. Conventionally, however, image data sent in units of a plurality of pixels is directly distributed to a plurality of write heads, so that when joint correction of an image between write heads is performed by changing a data transfer address to the write head, a plurality of write heads are required. There has been a problem that only joint correction can be performed in pixel units. For example, when image data is sent in units of two pixels, only position correction can be performed in units of two pixels.

In general, once image data is distributed to a plurality of write heads in a unit of a plurality of pixels, the image data is
Position correction in dot units becomes impossible. Therefore, to perform position control in units of one dot, it is necessary to complete position correction in units of one dot (unit of one pixel) when distributing image data to a plurality of write heads. In the method disclosed in Japanese Patent Application Laid-Open No. 08-258337, a boundary is set regardless of the content of an image. Therefore, in a document having many thin lines, the boundary may not be set properly. there were.

SUMMARY OF THE INVENTION The present invention solves such a problem, and enables correction on a pixel-by-pixel basis when writing an image with a plurality of write heads. It is intended to be unobtrusive.

[0007]

In order to achieve the above object, the present invention distributes image data transferred in one main scanning unit to a plurality of write heads, and writes an image with the plurality of write heads. In the image writing device, an image data capturing unit that captures image data transferred in units of a plurality of pixels, and an input of the image data in units of a plurality of pixels is shifted by a unit of a pixel, and a format of a plurality of systems in a unit of a plurality of pixels is returned. A first data shift means, a buffer memory, and an address control means for controlling an address at which image data is written to the buffer memory in accordance with image position designation data for designating an image writing position of each of the plurality of write heads. When writing the image data into the buffer memory, the first data shift means Data writing means for selecting and writing any of the plurality of formats converted in accordance with the image position designation data, and reading the data written in the buffer memory to read and write the plurality of writing heads in the sub-scanning direction. Second data shift means for correcting the output timing of the data by the displacement of the arrangement position and outputting the corrected data to the write head.

Further, when the data writing means writes the image data in the buffer memory in a different series format for each image data corresponding to each write head, a time lag caused by format conversion is corrected in advance. And means for continuously writing image data corresponding to the respective write heads in the buffer memory so as not to overlap in time.

Further, the image forming areas of the plurality of write heads are arranged so as to partially overlap, and when the transferred data is taken in, the image forming areas in the overlapping image forming areas are
A white area detecting means for detecting an area without a write request;
A writing range control means for changing a writing range of the plurality of writing heads according to a detection signal from the white area detection means may be provided. In such an image writing device, when the white area detecting means detects an area without a write request in the overlapped image forming area, the write area control means sets the maximum of the areas without the write request. It is preferable that the center of the area is set as a boundary of the writing range of the head.

[0010]

Embodiments of the present invention will be specifically described below with reference to the drawings. [First Embodiment: FIGS. 1 to 10] A schematic configuration of an image writing apparatus according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the image writing device. The image writing apparatus shown in FIG.
D includes first to third write heads (hereinafter simply referred to as “heads”) 1 to 3 arranged in a row, and two control ICs of a first IC 10 and a second IC 20 as control circuits thereof;
It is composed of 12 SRAMs 30, a light amount correction ROM group 40 including three light amount correction ROMs, three field memories 50, and the like.

The first IC 10 includes a signal selection circuit 10
1. SRAM write control unit 102, SRAM read control unit 103, write pulse creation circuit 1
04, address selector 105, block switching control circuit 106, field memory write control circuit 10
7 and the register 108 and the like. Second I
C20 is a light amount correction ROM read control unit 20
1. Field memory read control unit 202, select circuit 203, format conversion circuits 204 and 20
5, test pattern generation circuit 206, three gamma correction circuits 207, selector 208, strobe output control circuit 2
09, a transfer control circuit 210, a register 211, and the like.

The effective signal PFGAT in the sub-scanning direction is
When E and the valid signal PLGATE in the main scanning direction are both valid, image data DATA is sent from the image processing unit to which the image writing device is connected in units of two pixels in synchronization with the transfer clock PCLK. This image data D
The ATA is converted into a write format by the SRAM write control unit 102 and the address selector 105
Is written to the specified address of the SRAM 30 specified by. This SRAM 30 is a buffer memory.

The SRAM 30 performs a read / write toggle operation for each main scan, and the written image data is read at the timing when the image data of the next line is transferred. The reading is performed by the SRAM read control unit 103 by the S
This is done from the RAM 30. That is, 12 SRAMs
30 constitutes a block A and a block B by 6 pieces each,
While the image data of a certain line is being written to the SRAM 30 of the block A, the image data of the previous line is read from the SRAM 30 of the block B, and the image data of the next line is being written to the SRAM 30 of the block B. The image data written in the SRAM 30 is read.

The image data read from the SRAM 30 is fetched into the second IC 20 and directly or via the select circuit 203, the format conversion circuit 204,
The format is converted from a two-pixel unit to a one-pixel unit by 205, gamma-corrected by three gamma correction circuits 207, and transferred to the heads 1, 2, 3 by the selector 208. After the transfer, the image data is latched in the head and LED is
Lights up. However, since the three heads 1 to 3 are arranged so as to partially overlap the image writing areas, they cannot be arranged at the same position in the sub-scanning direction. It is shifted from the reference position in the sub-scanning direction. Accordingly, the output timing is delayed by passing the image data read from the SRAM 30 through the field memory 50, and the displacement of the arrangement position in the sub-scanning direction is corrected.

As schematically shown in FIG. 2, in this embodiment, when the position of the first head 1 is set as a reference position, the position of the second head 2 is greatly shifted.
The cascade connection of the field memories 50 corrects the image data with a delay corresponding to the shift. Also,
Since the position of the third head 3 is not so much shifted, it is delayed by one field memory 50 to perform position correction in the sub-scanning direction. The write control to the field memory 50 is performed by the field memory write control circuit 107 on the first IC 10 side, and the read control is performed by the second IC 2.
This is performed from the 0-side field memory read control circuit 202.

By the way, as shown in FIG. 2, the image writing areas of the three heads 1 to 3 are partially overlapped, and the writing effective areas are left at both ends, leaving room for correction. Is set. The maximum image area is formed by combining the effective areas of the three heads 1 to 3, and the three heads 1
3 connect the images to be written to the respective write-enabled areas to form a final output image. Data representing "white" is written in advance in an area where no image is actually formed in the room for correction.

Since these three heads 1 to 3 are further divided into two and have two input terminals, a total of 3 (head) × 2 (division) × 2 (toggle) = 12 is obtained.
That is, two SRAMs 30 are required. Writing of image data for one main scan is performed to half of the six SRAMs as described above. 76 for each head 1-3
There are 80 LEDs, as shown in FIG.
Each LED corresponds to one pixel, and data for each pixel is input to two SRAMs assigned to one head. The SRAM has addresses from 0 to 2047, each of which can store data for two pixels. In this embodiment, however, since one SRAM stores data for half the pixels of each head, 3840 pixels are used. Minutes,
That is, data is stored only in 1920 addresses from 0 to 1919.

In FIG. 3, the SRAMs assigned to the first head 1 are SRAM0 and SRAM1, and the SRAMs assigned to the second head 2 are SRAM2 and SR.
AM3, SRAM assigned to the third head
We will call them AM4 and SRAM5. In addition, these six SRAMs are six in block A or six in block B.
However, unless otherwise specified, it is not distinguished between them. This image writing device writes image data to an address corresponding to the effective area of each head, delays the output of the image data by the field memory 50, and further performs format conversion and gamma correction to perform the respective heads 1 to 3. To form an image.

As shown in FIG. 3, the first head 3 and the third head 3 are arranged so that the physical positions on the heads are opposite to the directions in which the pixel numbers are assigned. Data is written to addresses in descending order. Conversely, the second head 2 is arranged such that the physical position on the head is the same as the direction in which the pixel numbers are assigned.
Data is written to addresses in ascending order. Therefore, the write address becomes irregular up and down. Further, data for two pixels is written into each address of each SRAM at a time.

The writing is performed in the ascending order of the pixel numbers, and the first head 1 moves to the left side (the smaller pixel number) in FIG.
Since there is room for eight pixels, writing to SRAM0 is not performed from the maximum address 1919 but at 1820.
(Because two pixels are written in one address), and writing is performed in descending order. When writing to address 0 is performed, writing is performed in descending order from the maximum address 1919 of the SRAM 1, and since there is room for 258 pixels on the right side in FIG. 2, the writing ends at address 129.

Next, the SRAM corresponding to the second head 2
2 and the SRAM 3 are written. As shown in FIG. 2, since the second head 2 has room for 258 pixels on the left side, writing starts from the address 129 of the SRAM 2. From here, writing is performed in ascending order, and when the address reaches the maximum value 1919, writing starts from address 0 of the SRAM 3, and since there is room for 258 pixels on the right side, writing is not performed up to the maximum value. The writing ends at the corresponding address 1790.

Finally, the SRA corresponding to the third head 3
Data is written to M4 and SRAM5. As shown in FIG. 2, since the third head has room for 258 pixels on the left side, writing to the SRAM 4 starts from 1790, not from the maximum address 1919, and writes in descending order. When writing to address 0, SR
Writing is performed in descending order from the maximum value 1919 of the address of AM5. Since there is room for 198 pixels on the right side in FIG. 2, the writing ends at address 99. Thus, the writing of the pixel data for one line into each of the SRAMs 0 to 5 is completed. Here, in the room where the image is not actually formed,
It is assumed that data representing white is written in advance.

The case where the position between the heads is not corrected has been described above. However, in practice, the effective area of each head may not be connected well due to a slight shift of the head position or the like. In this case, the position of the effective area is corrected. To correct the position of the effective area, first, there is a method of shifting the write position of the image data. In this embodiment, this is performed by shifting the write address of the image data for the first and third heads 1 and 3. Further, in this embodiment, since the data is stored in one address of the SRAM in units of two pixels, the shift of the address is controlled in units of two pixels.

This will be described with reference to FIG. As shown on the left side of “2 pixel data on SRAM” shown in FIG. 4, the normal storage position of data for the first head 1 is SR
Addresses 0 to 1820 of AM0 and addresses 129 to 1919 of SRAM1. FIG. 2 shows the first head 1
, The write start address is advanced (increased) by one, as shown in the center of “2 pixel data on SRAM” shown in FIG. That is, SRAM
0 starts at address 1821, writes to address 0 in descending order, and then writes address 1 of SRAM 1
When the data is written in descending order from 919, the data becomes pixel number 722
Since the number is up to three, the process ends at the address 130 just before the address 129 of the SRAM 1. As a result, the image data of the first head 1 is stored two pixels to the left of the normal position at the physical position of the head, and the shift of the first head 1 to the right is corrected to the left. be able to.

Conversely, when the first head 1 is shifted to the left in FIG. 2, the write start address is delayed by one as shown on the right side of "two pixel data on SRAM" shown in FIG. For example, the physical position of the head is stored two pixels to the right of the normal position, and the shift of the first head 1 to the left can be corrected to the right. Of course, if the deviation is large, it is also possible to perform the same correction by shifting a plurality of addresses. In this method, correction can be performed only in units of two pixels, but correction can be performed in units of one pixel by shifting image data. In the case of performing correction on a pixel-by-pixel basis, the format of the image data is shifted from the normal storage position on the left by one pixel as shown on the right side of FIG. 5 without changing the write start address. For example, if this data is written to a normal address, it is stored one pixel to the right of the normal position in the physical position of the head. However, in this method, since the number of write addresses is increased by one, the control of the write counter needs to be changed.

Next, an example of a circuit for performing data format conversion in the SRAM write control unit 102 in FIG. 1 will be described with reference to FIG. The circuit described here is the first data shift means. SRA of FIG.
Of the image data of two pixels stored in one address of M30, the data of the left pixel is E (even number) and the data of the right pixel is O (odd number) as shown in FIGS. is there. The circuit shown in FIG.
Format conversion is performed by latching image data and changing the combination.

The standard format (regular) image data for the first head 1 is output as it is without passing through a latch because there is no need for delay. To generate image data of a format delayed by one pixel (one dot delay) for the first head 1, the original data E is placed at a position delayed by one pixel as data O. And the original data O is the first
The data is delayed by one clock by the latch 61, and then is set to the data E, so that this also comes to a position delayed by one pixel.

The image data of the standard format (regular) for the second and third heads 2 and 3 may be obtained by delaying both the data E and O by one clock by the first latch 61. The image data in the format delayed by one pixel (delayed by one dot) for the third head 3 is converted to the data O by delaying the data E by one clock by the first latch 61 to a position further delayed by one pixel. Put on. Then, the first latch 6
The data O delayed by one clock by 1 is further delayed by one clock by the second latch 62 to be the data E, so that the data O comes to a position further delayed by one pixel.

FIGS. 6 and 7 show the data input timing. FIGS. 7 and 8 are diagrams to be described in one diagram, but are divided into two diagrams due to space limitations. Therefore, WRADRS (with write counter) state
The (stay) portion is described in both FIGS. 7 and 8 so that the two views correspond to each other for easy viewing. As shown in FIG. 7, the image data is in two pixel units (DATA-E and DATA-O) at the timing when the LGATE signal becomes LOW.
Will be transferred. Then, there is a delay of one clock in the latch of the input part and two clocks in the thinning processing, and a delay of three clocks in total is sent to the SRAM writing part.

Here, the image data for the second and third heads 2 and 3 is further delayed by one clock. Thus, extra writing timing necessary when the image data of the first head 1 is delayed by one pixel is prepared at the end of the writing of the image data of the first head 1. At this timing, the corresponding SRAM (FIG. 3)
Write to the address 128 of the SRAM 1). If the data for the third head 3 is also delayed by one pixel, writing of one more clock is required. However, since the data of the third head 3 is the last, the writing is simply added by one clock. And write to the address 98 of the corresponding SRAM (SRAM5 in FIG. 3). In order to simplify the operation control, this extra write timing is provided even when unnecessary.

When the image data for the first head 1 is written from the standard position, as in the example of the third row in FIG. 7, writing is performed at the timing provided by the delay of the image data of the second head 2. Although there is no data to be written, in this case, since the address to be written at this timing corresponds to a pixel outside the effective area, data representing "white" is written and masked. In the case of this example, since the third head 3 also writes from the standard position, there is no data to be written even at the extra write timing provided at the end, so that the mask is also performed here.

In the case where the image data for the first head 1 is written with a shift of one pixel as in the example of the fourth row in FIG. 7, the data of the pixel number 0 is set as DATA-O at the first write timing. Just writing, DATA-
E does not exist. Therefore, a mask is applied here. First
The writing of the image data for the head 1 is completed by writing the image data of the last pixel number 7223 at an extra writing timing provided by delaying the image data for the second head 2 and thereafter. DAT
Since there is no A-O, a mask is also applied here. The writing of the data for the second and third heads 2 and 3 is the same as in the above-described example, and the description is omitted.

In the example of the fifth row in FIG. 7, the image data for the first and third heads 1 and 3 are both shifted by one pixel. The writing of the image data for the first head 1 is the same as in the above-described example, and the description is omitted. After writing the image data for the second head 2, the third head 3
Image data is written, but at the first write timing, only the image data of the pixel number 14388 is written as DATA-O, and DATA-E does not exist. Therefore, a mask is applied here. The writing of the image data for the third head 3 is completed by writing the image data of the last pixel number 21611 at the extra writing timing provided at the end. At this time, since DATA-O does not exist, it is also used here. Perform a mask.

Here, the case of shifting (delaying) the writing by one pixel to the right has been described. However, when shifting (advancing) the writing by one pixel to the left, this operation is performed and then the write address is advanced by one. Good. By combining the change of the write address and the operation of shifting by one pixel, the write position of the image data can be shifted by an arbitrary integer pixel.
The size of the shift is confirmed by writing an image of the test pattern in advance, the size to be corrected is set as image position designation data, and the number of pixels to be shifted may be selected according to the data. Alternatively, the adjustment may be made while referring to the state of the image appropriately formed during the operation.
In this way, there is no time overlap when switching between the formats between the heads 1 to 3, and only one SRAM needs to be accessed at the same timing, and only one type of address output is required. The circuit configuration is simplified.

According to the write dot format of the heads 1 and 3, the value of the content written to the SRAM changes as shown in FIG. Then, each state (s
At the timing of (state), a load instruction LOAD and an up-count / down-count instruction U / D are issued to the write counter. In addition, a data mask is instructed by a signal MASKEN at a boundary between heads. Furthermore, a select signal SEL for outputting a write pulse
0 to SEL5 are output.

The selection of the write destination SRAM and the designation of the write address by these signals are performed by the write counter 82 shown in FIG. This write counter 82
Is an address control means. Therefore, this operation will be described with reference to FIG. FIG. 9 shows the SRA in FIG.
FIG. 3 is a block diagram showing a configuration of an M write control unit and its peripheral circuits. The WRSTART signal shown in FIG.
This is a signal indicating the timing of starting writing of image data for a line. This signal causes the write counter 8 in FIG.
2 starts the operation. The state machine 80 receives a start address, a break address, and an end address from the register 108, receives a write address from the write counter 82, and loads a load instruction LOAD, an up-count / down-count instruction U / D, and a select signal in each state. The output timing of SEL0 to SEL5 is managed.

When the load instruction LOAD becomes "H", the write counter 82 starts counting from the address indicated by the start address (HSTADRS) at the next timing. It should be noted that if the up-count / down-count instruction U / D is "H", the up-count is performed, and if it is "L", the down-count is performed. At each timing, image data is written to the address of the count value of the write counter 82. To shift the write address, the value of the start address signal (HSTADRS) may be changed.

On the other hand, the write destination SRAM 30 is designated as
This is performed by the select signals SEL0 to SEL5, and writing is performed to the SRAM 30 whose corresponding signal is “H”. A circuit equivalent to the circuit shown in FIG. 6 is constituted by the latches 61 and 62, and the image data delayed from the output image data at an appropriate timing is selected by the selector 84 into the signal BITSHIFT.
And select signals SEL0 to SEL5 to output SRAM write data. Further, the write pulse generating circuit 104 generates a write pulse based on the pixel clock PCLK and the select signals SEL0 to SEL5.

The address selector 1 shown in FIG.
In the SRAM 30 designated by 05, writing is performed by outputting a write address from a write counter, a write pulse from a write pulse creation circuit 83, and SRAM write data from a selector. These units are data writing means. In FIG. 9, L
The image data transferred in units of two pixels (DATA-E and DATA-O) at the timing when the GATE signal becomes LOW is delayed by one clock in the input unit latch 85 and two clocks in the thinning processing latches 86 and 87. , These combinations are further delayed by the latch 88, and the latch 61
Alternatively, it is sent to the selector 84.

The toggle operation of the SRAM 30 is performed by the circuit having the configuration shown in FIG. 10 in accordance with the block switching signal from the block switching control circuit 106 also shown in FIG. Switching of addresses and switching of write pulses generated by the write pulse generation circuit 104 are performed. Read counter 92
Are provided in the SRAM read control unit shown in FIG. Address selector 105 shown in FIG.
Comprises a block A selector 105A and a block B selector block 105B shown in FIG. 10, and activates either the block A selector 105A or the block B selector 105B according to the output signal of the block switching control circuit 106. Block A selector 105A
Addresses any of the six SRAMs 30 in block A shown in FIG.
B addresses any of the six SRAMs 30 in block B shown in FIG.

The write pulses output by the write pulse generating circuit 104 corresponding to the select signals SEL0 to SEL5 are also transmitted to WR0 to WR5 corresponding to the six SRAMs 30 in the block A and to six SRAMs 30 in the block B in FIG. Switching between the corresponding WRs 6 to 11 is performed. The data read from the SRAM undergoes a necessary delay in the sub-scanning direction by the combination of the three field memories 50 shown in FIG. In this embodiment, one field memory can delay up to 104 lines. 600d
When writing an image with pi, 104 lines are 4.4
mm. In this embodiment, the first head 1 and the second head 1
Of the head 2 in the sub-scanning direction is set to 8 mm ≒ 192 lines. As described above, in order to delay 192 lines, two field memories 50 are connected and delayed.

FIG. 11 shows a circuit for this delay. This circuit is the second data shift means. here,
The three field memories 50 are first, second, and third field memories FM1, FM2, and FM3. Then, the first field memory FM1 and the second field memory FM2 are used for delaying the image data for the second head 2. Here, the delay amount of the first field memory FM1 is fixed to 100 lines, and the delay after that is performed by the second field memory FM2. The third field memory FM3 is used for delaying image data for the third head 3.

Each of these field memories FM1, FM
2 and FM3, the field memory write control circuit 107 in the first IC 10 shown in FIG.
1 is controlled by the field read control circuit 202 shown in FIG. All delays are controlled by the delay of the RRST signal relative to the WRST signal. In FIG. 11, input lines and output lines for image data are not shown.
As described above, it is possible to configure an image writing apparatus including a plurality of writing heads, which can adjust an image writing position in units of one pixel, even though image data for a plurality of pixels is simultaneously transferred.

[Second Embodiment: FIGS. 1, 2, 11 to 18] Next, an image writing apparatus according to a second embodiment of the present invention will be described with reference to FIGS. 18 will be described. As shown in FIG. 2, when the image formation areas are partially overlapped by the three heads and the effective areas are joined to create an image, the data writing positions of the first head 1 and the third head 3 are changed. As described in the description of the first embodiment, it is possible to correct the image shift in the main scanning direction by controlling.

However, since this correction control is performed in units of one pixel, a deviation of one pixel or less will inevitably occur. When the boundary of the effective area of each head is at a fixed position, the deviations are arranged in the sub-scanning direction. For example, when an image as shown in FIG. 12 is to be output, the actual output image is as shown in FIG. 13, and even a slight shift becomes significantly noticeable in appearance (arrow portion).

In this embodiment, the image seam is set as shown in FIG.
As shown in (1), a method is adopted in which the shift in the main scanning direction is made difficult to see by performing the writing in a portion (white pixel portion) where writing is not actually performed. As shown in the lower six lines in FIG. 14, when all of the image overlapping portions are black, random numbers are generated to control the joints irregularly so that the joints are difficult to see. In such a case, the output result is as shown in FIG. 15, and as compared with FIG.
The joints are almost inconspicuous. The image writing apparatus of this embodiment is the same as the image writing apparatus of the first embodiment except that the circuit shown in FIG. Descriptions other than the above operation are omitted.

The circuit shown in FIG. 16 corresponds to the first IC 1 shown in FIG.
0, a circuit for input to the SRAM write control circuit 102, a main scanning counter 111 for counting the position of each pixel in the main scanning direction, a latch 112 for storing the value, and a white pixel count for counting continuous white pixels A circuit 113, a maximum value storage buffer 114 for storing the maximum number of continuous white pixels, a white pixel count circuit 113
115 for comparing the count value of the image data with the maximum value stored in the maximum value storage buffer 114, a line buffer 116 for storing one line of image data, a random number generator 117, and a storage for setting a storage destination of the image data RA
An M switching control circuit 118 is provided. White pixel count circuit 113, maximum number storage buffer 114, and comparison circuit 115
The storage RAM switching control circuit 118 is a writing range control means.

When the main scanning synchronization signal PLSYNC is input to this circuit, image data is input in order. When a white pixel is input in the overlapping portion of the image formable area of each of the heads 1 to 3, the white pixel counting circuit 113 counts the continuous number and stores it in the maximum value storage buffer 114. When the white pixel is interrupted, the value of the main scanning counter 111 at that time is stored by the latch 112. Once the white pixel is interrupted and then the white pixel starts again, the white pixel counting circuit 113 starts counting again, and when it is larger than the number of consecutive pixels at the end, the contents of the maximum value storage buffer 114 are replaced. The value of the main scanning counter 111 at that time is stored by the latch 112.

When the data input for the overlapping portion of the first head 1 and the second head 2 is completed, the value of the main scanning counter 111 at the stage when the maximum continuous white pixel ends for the overlapping portion, and the maximum continuous value Will be stored. From these data, the midpoint of the maximum continuous white pixel area is calculated until the next overlapping portion of the second head 2 and the third head 3 is reached, and is stored as a main scanning count value at the seam of the image. It is stored in the switching control circuit 118. If no white pixel exists in the overlapped portion, the main scan count value at the joint of the images is determined by the random number generated by the random number generator 117.

After that, the storage of the maximum value storage register 114 and the latch 112 is cleared, and the main scanning count value at the joint of the image is similarly calculated for the overlapping portion of the second head 3 and the third head 3 and stored. The data is stored in the RAM switching control circuit 118. Here, an example has been shown in which the seam of the image is determined after the data of one overlapping portion is completed and before the data of the next overlapping portion is sent. May be provided, and after all the data for one line is read, the joint of the images may be determined.

On the other hand, the read image data is sequentially stored in the line buffer 116. When reading of one line of image data is completed, one line of data is stored in the line buffer 116. Then, data is read from the line buffer 116 at the timing of the next line. At this time, the storage RAM switching control circuit 118
An SRAM write control circuit 1 shown in FIG. 1 is controlled so that the seam of the image between the heads becomes a stored value.
02 and written to each SRAM 30.

The flow of the above-described processing is shown in the flowchart of FIG. That is, when the image data of the overlapping portion of the image formable regions of the heads 1 to 3 is read, the processing of this flow is started, and the number of continuous white pixels is counted in step S1. If the count value is larger than the maximum value stored in the maximum value storage register 204 in step S2, the maximum value is updated in step S3 and the latch 2
2 stores the value of the main scanning counter 21 at that time.

If it is determined in step S4 that the overlapping area has not been completed, the process returns to step S1.
Proceed to. If the maximum value stored in the maximum value storage register 204 is not 0 in step S5, the process proceeds to step S7, where 0
If it is determined that there is no white pixel, the position of the joint is set by a random number in step S6. In step S7, switching control of the write address to the SRAM is set so that the joint of the effective areas of the respective heads is located at the center of the maximum continuous area of white pixels (at a random position when there is no white pixel). finish.

FIGS. 18 and 19 show an example in which the image forming effective area of the head is changed according to this control. In the description of this example, it is assumed that the image position correction by changing the data writing position is not considered. Of course, even if this position correction is performed, each head which does not have any problem in operation only by shifting the data writing address. When the boundaries of the effective areas 1 to 3 are at the standard positions, the heads 1 to 3 respectively connect the images with a margin of 258 pixels as shown in FIG.

When the joint of the effective areas of the first and second heads 1 and 2 is shifted to the right by 248 pixels, the effective areas of the heads 1 to 3 are as shown in FIG. Therefore,
To the first head 1, the lower half physical position 10 shown in FIG.
The image data is applied until the address 5 of the SRAM 1 is written. Since the image data is applied to the second head 2 from the upper half physical position 506 shown in FIG. 3, the SRAM 2 writes the image data from the address 253.

Conversely, when the joint of the effective areas of the first and second heads 1 and 2 is shifted to the left by 238 dots, the effective areas of the heads 1 to 3 are as shown in FIG. In this case, the image data is applied to the first head 1 up to the lower half physical position 496 shown in FIG. 3, and the image data is written up to the address 248 of the SRAM 1. Since the image data is applied to the second head from the upper half physical position 20 shown in FIG. 3, the SRAM 2 writes the image data from the address 10.

The storage RAM switching control circuit 108 shown in FIG. 16 controls the SRAM write control unit 102 in accordance with the set data of the boundary of the assigned area of the first and second heads 1 and 2. A data write destination is controlled by sending a signal specifying a write address. Then, by appropriately determining the boundaries of the effective areas of the respective heads for each line, it is possible to make a shift that is difficult to correct in the pixel-by-pixel adjustment inconspicuous.

Here, only an example in which the boundary between the effective areas of the first head 1 and the second head 2 is shifted has been described.
The boundary between the effective areas of the second head 2 and the third head 3 can be similarly changed. Further, even when the number of heads is two or four or more, similar control is possible, and image quality can be improved.

[0059]

As described above, the image writing apparatus according to the present invention selects image data transferred in units of a plurality of pixels from a plurality of formats shifted in units of a single pixel and transfers the data to a buffer. By performing the writing control, for example, even if data is sent in units of two pixels, the image writing position can be controlled in units of one pixel. Therefore,
The image position can be precisely corrected, and the image quality of the written image can be improved.

Further, according to the image writing position control of the image writing apparatus according to the present invention, a time delay is generated in advance for each format of the shifted image data, and the writing timing at the switching point of the format is changed. Since no overlap occurs, the buffer memory (S
The control of writing data to the RAM (RAM) can be simplified. Further, when writing an image with a plurality of heads, by setting the boundaries of the effective areas of each head as much as possible in an area where there is no actual write request, positional deviation between heads that cannot be corrected by pixel-by-pixel adjustment is not noticeable. To improve the image quality.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an image writing device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an effective area of each writing head in an image forming area in the image writing apparatus.

FIG. 3 is an SRA of image data in the image writing device.
FIG. 3 is an explanatory diagram for explaining a write address to M.

FIG. 4 is an explanatory diagram of an operation of shifting an image by controlling a write address in the image writing device.

FIG. 5 is an explanatory diagram of a write address when the image is shifted by one pixel by changing the pixel format in the image writing device.

FIG. 6 is a block diagram showing an example of a circuit for converting a pixel format in the image writing device.

FIG. 7 is a diagram illustrating an upper half of a timing chart showing a timing of inputting image data in the image writing device.

FIG. 8 is a diagram showing the lower half of the timing chart.

FIG. 9 is a block diagram showing a configuration of a data writing circuit in the image writing device.

FIG. 10 is a block diagram showing a configuration of a circuit for performing a toggle operation of an SRAM in the image writing device.

FIG. 11 is a block diagram showing a configuration of a circuit for performing a data delay operation in the image writing device.

FIG. 12 is a diagram illustrating an example of an image to be written by the image writing device.

FIG. 13 is a diagram illustrating an output example of an image in a case where the position of a joint of an effective area of each writing head is fixed.

FIG. 14 is a diagram illustrating, on an image, an example of a change in the joint of the effective areas of the write heads determined by the image writing apparatus according to the second embodiment of the present invention.

FIG. 15 is a diagram showing an example of image output by the image writing device.

FIG. 16 is a block diagram showing a configuration of a circuit for determining a joint between effective areas of each write head in the image writing apparatus.

FIG. 17 is a flowchart showing a flow of the control.

18 is a diagram illustrating an example of an effective area of each head when a joint of the effective areas of the first and second heads illustrated in FIG. 2 is shifted to the right.

FIG. 19 is a diagram illustrating an example of an effective area of each head when a joint of the effective areas of the first and second heads illustrated in FIG. 2 is shifted to the left.

[Explanation of symbols]

1: First write head 2: Second write head 3: Third write head 10: First IC 20: Second IC 30: SRAM (buffer memory) 40: Light amount correction ROM group 50: Field memory 61, 62, 85-88: Latch 80: State machine 82: Write counter 84: Selector 92: Read counter 101: Signal select circuit 102: SRAM write control unit 103: SRAM read control unit 104: Write pulse generation circuit 105: Address Selector 105A: Block A selector 105B: Block B selector 106: Block switching control circuit 107: Field memory write control circuit 108: Register 111: Main scanning counter 112: Latch 113: White pixel count circuit 114: Value storage buffer 115: comparison circuit 116: line buffer 117: random number generator 118: storage RAM switching control circuit 201: light amount correction ROM read control circuit 202: field memory read control circuit 203: select circuit 204, 205: format conversion circuit 206 : Test pattern generation circuit 207: gamma correction circuit 208: selector 209: strobe output control circuit 210: transfer control circuit

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[Procedure amendment]

[Submission date] April 2, 2001 (2001.4.2)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

[0010]

Embodiments of the present invention will be specifically described below with reference to the drawings. [First Embodiment: FIGS. 1 to 11 ] A schematic configuration of an image writing apparatus according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of the image writing device. The image writing apparatus shown in FIG.
D includes first to third write heads (hereinafter simply referred to as “heads”) 1 to 3 arranged in a row, and two control ICs of a first IC 10 and a second IC 20 as control circuits thereof;
It is composed of 12 SRAMs 30, a light amount correction ROM group 40 including three light amount correction ROMs, three field memories 50, and the like.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction contents]

Next, an example of a circuit for performing data format conversion in the SRAM write control unit 102 in FIG. 1 will be described with reference to FIG. The circuit described here is the first data shift means. SRA of FIG.
Of the image data of two pixels stored in one address of M30, the data of the left pixel is E (even number) and the data of the right pixel is O (odd number) as shown in FIGS. is there. Circuit shown in FIG. 6 will come transferred 2
Format conversion is performed by latching image data for pixels and changing the combination.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0029

[Correction method] Change

[Correction contents]

[0029] shows the timing of data input to FIGS. FIGS. 7 and 8 are diagrams to be described in one diagram, but are divided into two diagrams due to space limitations. Therefore, WRADRS (write counter ) and state
The ( state ) portion is described in both FIGS. 7 and 8 so that the two figures correspond to each other for easy viewing. As shown in FIG. 7, the image data is in two pixel units (DATA-E and DATA-O) at the timing when the LGATE signal becomes LOW.
Will be transferred. Then, there is a delay of one clock in the latch of the input part and two clocks in the thinning processing, and a delay of three clocks in total is sent to the SRAM writing part.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0039

[Correction method] Change

[Correction contents]

The address selector 1 shown in FIG.
In the SRAM 30 designated by 05, writing is performed by outputting a write address from the write counter 82 , a write pulse from the write pulse creation circuit 104 , and SRAM write data from the selector 84 . These units are data writing means. In FIG. 9, at the timing when the LGATE signal becomes LOW, 2
Image data transferred in pixel units (DATA-E and DATA-O) is delayed by one clock at the input unit latch 85 and two clocks at the thinning latches 86 and 87, and further combined by the latch 88 with these combinations. The signal is sent to the latch 61 or the selector 84 after being delayed.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0040

[Correction method] Change

[Correction contents]

The toggle operation of the SRAM 30 is performed by the circuit having the configuration shown in FIG. 10 in accordance with the block switching signal from the block switching control circuit 106 also shown in FIG. Switching of addresses and switching of write pulses generated by the write pulse generation circuit 104 are performed. Read counter 92
Is the SRAM read control unit 103 shown in FIG.
It is provided within. Address selector 1 shown in FIG.
Reference numeral 05 denotes a block A selector 105A and a block B selector block 105B shown in FIG.
Activate either the selector 105A or the block B selector 105B. Block A selector 105
A is an example of the six SRAMs 30 in the block A shown in FIG.
Address one of them, block B selector block 1
05B indicates the six SRAMs 3 in the block B shown in FIG.
Address any one of 0.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0042

[Correction method] Change

[Correction contents]

FIG. 11 shows a circuit for this delay. This circuit is the second data shift means. here,
The three field memories 50 are first , second , and third field memories FM1, FM2, and FM3. Then, the first field memory FM1 and the second field memory FM2 are used for delaying the image data for the second head 2. Here, the delay amount of the first field memory FM1 is fixed to 100 lines, and the delay after that is performed by the second field memory FM2. The third field memory FM3 is used for delaying image data for the third head 3.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0044

[Correction method] Change

[Correction contents]

[0044] Second Embodiment: FIG. 1, FIG. 2, FIGS. 12 to 19] Next, the image writing device of the second embodiment of the present invention, FIGS. 1, 2 and 12 through 19 will be described. As shown in FIG. 2, when the image formation areas are partially overlapped by the three heads and the effective areas are joined to create an image, the data writing positions of the first head 1 and the third head 3 are changed. As described in the description of the first embodiment, it is possible to correct the image shift in the main scanning direction by controlling.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0047

[Correction method] Change

[Correction contents]

The circuit shown in FIG. 16 corresponds to the first IC 1 shown in FIG.
0, a circuit for input to the SRAM write control circuit 102, a main scanning counter 111 for counting the position of each pixel in the main scanning direction, a latch 112 for storing the value, and a white pixel count for counting continuous white pixels A circuit 113, a maximum value storage buffer 114 for storing the maximum number of continuous white pixels, a white pixel count circuit 113
115 for comparing the count value of the image data with the maximum value stored in the maximum value storage buffer 114, a line buffer 116 for storing one line of image data, a random number generator 117, and a storage for setting a storage destination of the image data RA
An M switching control circuit 118 is provided. White pixel count circuit 113, maximum number storage buffer 114, and comparison circuit 11
5 constitutes a white area detection means, and the storage RAM switching control circuit 118 is a writing range control means.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0049

[Correction method] Change

[Correction contents]

When the data input for the overlapping portion of the first head 1 and the second head 2 is completed, the value of the main scanning counter 111 at the stage when the maximum continuous white pixel ends for the overlapping portion, and the maximum continuous value Will be stored. From these data, the middle point of the maximum continuous white pixel area is calculated until the next overlapping portion of the second head 2 and the third head 3 is reached, and stored as the main scanning count value at the joint of the image. It is stored in the switching control circuit 118. If no white pixel exists in the overlapping portion, the main scan count value at the joint of the images is determined by the random number generated by the random number generator 117.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0050

[Correction method] Change

[Correction contents]

After that, the storage of the maximum value storage register 114 and the latch 112 is cleared, and the main scanning count value at the joint of the image is similarly calculated for the overlapping portion of the second head 3 and the third head 3 and stored. The data is stored in the RAM switching control circuit 118. Here, an example has been shown in which the seam of the image is determined after the data of one overlapping portion is completed and before the data of the next overlapping portion is sent. May be provided, and after all the data for one line is read, the joint of the images may be determined.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0051

[Correction method] Change

[Correction contents]

On the other hand, the read image data is sequentially stored in the line buffer 116. When reading of one line of image data is completed, one line of data is stored in the line buffer 116. Then, the data from the line buffer 116 at the timing of the next line is read, the time stored RAM switching control circuit 118 that controls so that the value joint image are stored between the heads, in FIG. 1 The data is output to the shown SRAM write control circuit 102 and written to each SRAM 30.

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0052

[Correction method] Change

[Correction contents]

The flow of the above-described processing is shown in the flowchart of FIG. That is, when the image data of the overlapping portion of the image formable regions of the heads 1 to 3 is read, the processing of this flow is started, and the number of continuous white pixels is counted in step S1. If the count value is larger than the maximum value stored in the maximum value storage register 114 in step S2, the maximum value is updated in step S3 and the latch 1
12 stores the value of the main scanning counter 111 at that time.

[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0053

[Correction method] Change

[Correction contents]

If it is determined in step S4 that the overlapping area has not been completed, the process returns to step S1.
Proceed to. If the maximum value stored in the maximum value storage register 114 is not 0 in step S5, the process proceeds to step S7, where 0
If it is determined that there is no white pixel, the position of the joint is set by a random number in step S6. In step S7, switching control of the write address to the SRAM is set so that the joint of the effective areas of the respective heads is located at the center of the maximum continuous area of white pixels (at a random position when there is no white pixel). finish.

[Procedure amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0054

[Correction method] Change

[Correction contents]

According to this control, the image formation of the head is effective.
Examples in which the area is changed are shown in FIGS. In the description of this example, it is assumed that image position correction by changing the data writing position is not considered. However, even if this position correction is performed, there is no problem in the operation, as only the address where data is written is shifted . When the boundaries of the effective areas of the heads 1 to 3 are at the standard positions, as shown in FIG. 2, the heads 1 to 3 respectively connect the images with a margin of 258 pixels.

[Procedure amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0057

[Correction method] Change

[Correction contents]

The storage RAM switching control circuit shown in FIG.
The path 118 transmits a signal designating such a write address to the SRAM write control unit 102 in accordance with the set data of the boundary of the area in charge of the first and second heads 1 and 2, Control the write destination of Then, by appropriately determining the boundaries of the effective areas of the respective heads for each line, it is possible to make a shift that is difficult to correct in the pixel-by-pixel adjustment inconspicuous.

[Procedure amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0060

[Correction method] Change

[Correction contents]

Further, the image of the image writing apparatus according to the present invention
According to the writing position control, a time delay is generated in advance for each format of the shifted image data so that overlapping of the writing timing does not occur even at the switching point of the format. Therefore, the buffer memory (SRAM) The control of writing data to the memory can be simplified. Further, when writing an image with a plurality of heads, by setting the boundaries of the effective areas of each head as much as possible in an area where there is no actual write request, positional deviation between heads that cannot be corrected by pixel-by-pixel adjustment is not noticeable. To improve the image quality.

[Procedure amendment 17]

[Document name to be amended] Statement

[Correction target item name] Explanation of sign

[Correction method] Change

[Correction contents]

[Description of Signs] 1: First write head 2: Second write head 3: Third write head 10: First IC 20: Second IC 30: SRAM (buffer memory) 40: Light amount correction ROM Group 50: Field memories 61, 62, 85-88: Latch 80: State machine 82: Write counter 84: Selector 92: Read counter 101: Signal select circuit 102: SRAM write control unit 103: SRAM read control unit 104: Write pulse Creation circuit 105: Address selector 105A: Block A selector 105B: Block B selector 106: Block switching control circuit 107: Field memory write control circuit 108: Register 111: Main scanning counter 112: Latch 113: White pixel count Road 114: Maximum value storage buffer 115: Comparison circuit 116: a line buffer 117: random number generator 118: storage RAM switch control circuit 201: light intensity correction ROM read control circuit 202: a field memory read control circuit 203: select circuit 204 and 205: Format conversion circuit 206: Test pattern generation circuit 207: Gamma correction circuit 208: Selector 209: Strobe output control circuit 210: Transfer control circuit

[Procedure amendment 18]

[Document name to be amended] Drawing

[Correction target item name] Fig. 1

[Correction method] Change

[Correction contents]

FIG.

[Procedure amendment 19]

[Document name to be amended] Drawing

[Correction target item name] Figure 3

[Correction method] Change

[Correction contents]

FIG. 3

[Procedure amendment 20]

[Document name to be amended] Drawing

[Correction target item name] Fig. 4

[Correction method] Change

[Correction contents]

FIG. 4

[Procedure amendment 21]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 10

[Procedure amendment 22]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG. 11

[Procedure amendment 23]

[Document name to be amended] Drawing

[Correction target item name] FIG.

[Correction method] Change

[Correction contents]

FIG.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2C087 AA09 AC02 BA02 BC03 2C162 AE04 AE28 AF07 AF19 AF53 AF59 FA04 FA17 2C187 AC02 5C077 LL02 PP58 PQ22 TT02

Claims (5)

[Claims] An image writing apparatus for distributing image data transferred in one main scanning unit to a plurality of write heads and writing an image with the plurality of write heads, wherein the image data transferred in a plurality of pixel units is provided. Means for capturing image data, a first data shift means for shifting the input of the image data in a plurality of pixels by the means in units of one pixel, and again forming a format of a plurality of series in a plurality of pixels, and a buffer memory Address control means for controlling an address at which image data is written to the buffer memory according to image position designation data for designating an image writing position by each of the plurality of write heads; A plurality of streams converted by the first data shift means; Data writing means for selecting and writing any one of the data in accordance with the image position designation data, reading out the image data written in the buffer memory, and reading the image data by an amount corresponding to the displacement of the plurality of write heads in the sub-scanning direction. By correcting the output timing of the image data,
An image writing apparatus, comprising: a second data shift unit that outputs the data to the writing head. 2. The image writing device according to claim 1, wherein
Means for correcting in advance a time lag caused by format conversion when the data writing means writes the image data in the buffer memory in a different series format for each of the image data corresponding to the plurality of write heads. An image writing apparatus for continuously writing image data corresponding to each writing head in the buffer memory so as not to overlap with time. 3. An image writing apparatus which distributes image data transferred in one main scanning unit to a plurality of writing heads and creates an image with the plurality of writing heads. Image data capturing means for capturing data is provided, and the plurality of write heads are arranged so as to partially overlap the respective image forming areas. When the image data capturing means captures the image data, White area detecting means for detecting an area in which no write request is made in the formed image forming area, and writing range control means for changing a writing range of each of the plurality of write heads according to a detection signal from the means. Image writing device. 4. The image forming apparatus according to claim 1, wherein the plurality of write heads are arranged so as to partially overlap the respective image forming areas, and the transferred data is stored in the image data. A white area detecting means for detecting an area without a write request in the overlapped image forming area when the capturing means takes in the image data; and a writing area for changing a writing area of each of the plurality of write heads according to a detection signal from the means. An image writing device comprising a control unit. 5. The image writing device according to claim 3, wherein the writing range control unit detects, when the white region detection unit detects an area without a writing request in the overlapping image forming area, An image writing apparatus characterized in that the center of the largest area among the areas not requiring a write is defined as the boundary of the writing range of the plurality of heads.