JP2002289797A - Ferroelectric substance memory and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To microminiaturize a cell and manufacture the same with a stable characteristic. SOLUTION: A ferroelectric substance memory comprises a cell including a MIS transistor formed on the semiconductor substrate, an oxide diffusion barrier film formed on the upper part of the MIS transistor via an interlayer insulation film, a ferroelectric capacitor arranged so that a direction connecting both electrode is in line with a channel length direction of the transistor formed on the oxide diffusion barrier film via the interlayer insulation film, a metal interconnection connecting one electrode of the ferroelectric substance capacitor to a source of the transistor and the other electrode of that to a drain of the transistor, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a ferroelectric memory, and more particularly, to a ferroelectric memory using a TC parallel unit serial connection type ferroelectric memory architecture and a method of manufacturing the same. Here, in the TC parallel unit serial connection type ferroelectric memory, both ends of the capacitor (C) are respectively connected between the source and the drain of the cell transistor (T), and this is used as a unit cell, and a plurality of the unit cells are connected in series. A thing.

[0002]

2. Description of the Related Art A ferroelectric memory is non-volatile, but can rewrite stored data, and has been widely used for various purposes. In order to further expand the applications, it is an essential requirement that the storage capacity be increased and the size be reduced. Conventional methods for reducing the cell size of a ferroelectric memory include a COP (Capacitor On Plug) structure and a T
C. Parallel unit series connection type ferroelectric memory structure is D. Tak
Proposed at ISSC in February 1999 by ashima et al.

Certainly, in the FeRAM having the conventional structure, which is not the TC parallel unit series connection type ferroelectric memory according to the prior art without using the COP structure, the contact region to the upper and lower electrodes and the connection region to the diffusion layer Is necessary, and there is a lot of room for holes and wiring, and there are many spaces for wiring and wiring.
The area required for cell layout is inevitably increased. Under the same rule, TC
Estimating the chip area of the parallel unit serial connection type ferroelectric memory and the conventional chip area shows that using the TC parallel unit series connection type ferroelectric memory architecture, 4MFer
In AM class, it can be reduced to about 60% of the conventional level. However, with this method, the limit of realistic miniaturization is becoming apparent.

[0004] This will be described in detail below.

In general, for example, as shown in FIG. 11 (a), in a conventional FeRAM which does not use a COP structure and is not a TC parallel unit serial connection type ferroelectric memory, the upper electrode 101 of the ferroelectric capacitor and The contact region 103 to the lower electrode 102 and the connection wiring 105 to the diffusion layer 104 are required, and a margin between the contact hole for the contact region 103 and the connection wiring 105 is required to some extent. Because of the large number of spaces, the area required for one cell layout is inevitably large. For example, if the minimum dimension used in the FeRAM design and F, the cells of FIG. 11 (a) it comes to 8F ² cells.

One method of reducing the area required for the layout of one cell is a TC parallel unit serial connection type ferroelectric memory structure, for example, a structure shown in FIG. 11B. This cell becomes 6F ² cells, provided in common to the two cells ferroelectric upper electrode 111 of the capacitor are adjacent to each other, similarly common to two cells of the lower electrode 112 adjacent to each other And are connected to the diffusion layers 114 via the contacts 113, respectively. The diffusion layer 114 is commonly used between the transistors Tr of adjacent cells.

[0007] Comparing the chip areas of the cells having the structure shown in FIGS. 11A and 11B with the same dimensional rule, the TC parallel unit series connection type ferroelectric shown in FIG. By using the body memory architecture, the size can be reduced to about 60% in the 4M FeRAM class. However, in this method, the limit of practical miniaturization is becoming visible.

As described above, since miniaturization is practically difficult, in order to overcome this limitation and realize further miniaturization, a TC parallel unit series connection having a structure as shown in FIG. Type ferroelectric memories have been proposed. The TC parallel unit serial connection type ferroelectric memory of this structure can be represented as an equivalent circuit as shown in FIG.
In FIG. 11C, diffusion layers 124 and 124 used as a source and a drain with the gate electrode G of one memory cell transistor Tr interposed therebetween are contact plugs respectively with the upper electrode 121 and the lower electrode 122 of the ferroelectric capacitor Cf. They are connected via 123, 123.

[0009] One diffusion layer 124 is commonly used as a source or a drain of transistors of two cells adjacent to each other, and constitutes an architecture that is connected continuously. Here the top of the COP structure, by applying at the bottom of the electrodes 121 and 122, in the ideal state, may become minimum 4F ² cells as shown in FIG. 11 (c) is shown.

[0010] However, its realization involves many difficulties. For example, when the contact plug 123 is made of tungsten (W) that is easily oxidized, the contact plug 12
It is necessary to develop a barrier film capable of ensuring sufficient conduction between 3 (W) and the lower electrode 122 and preventing oxidation of W as a constituent material after forming the contact plug 123. Another problem is that the barrier film sets the upper limit of the process temperature. Therefore, at present, it can be said that it is extremely difficult to combine with an SBT that requires a film forming temperature of 700 ° C. or more.

Further, even when the lower electrode 122 side can have a COP structure, the number of steps must be increased in order to make the ideal upper electrode 121 as shown in FIG. The process becomes very complicated due to an increase in the number of times of embedding, and it is particularly difficult to secure the characteristics of the ferroelectric capacitor Cf. For these reasons, the price paid for proceeding with process integration is large.

[0012]

As described above, FIG.
The realization of the TC unit parallel-connected ferroelectric cell miniaturization possible 4F ² structure of the memory shown (c), the lower of the upper electrode 121 also COP structures lower electrode 122, i.e., a ferroelectric capacitor Cf It is necessary to adopt a structure that takes the electrode from Naturally, a conductive barrier film is required for both the upper and lower electrodes 121 and 122, but at present, an excellent barrier film that can withstand recovery annealing with a sufficient margin has not yet been found.

That is, it is necessary to further develop a low-damage processing process, a low-damage insulating film forming technology, a low-temperature, short-time damage recovery technology, a damage protection electrode, and a cover. However, its realization involves many difficulties. For example,
In particular, in the case of W in which the plug material of the underlying contact is easily oxidized, it is necessary to develop a barrier film that has sufficient conduction with W and the lower electrode and can prevent oxidation of W after the plug is formed. There is also a problem that the barrier property determines the upper limit of the process temperature. It can be said that it is extremely difficult to combine with SBT which requires a film formation temperature of 700 ° C. or more at present. In addition, even if the lower electrode side can have a COP structure, even if the ideal upper electrode also has a COP structure,
The process becomes very complicated due to an increase in the number of steps and the number of times of embedding, and it is difficult to secure characteristics. The price paid for advancing process integration is significant.

Therefore, the present invention has been made in view of such circumstances, and a ferroelectric memory which realizes miniaturization of a cell, can be manufactured by a simple manufacturing process, and has stable characteristics, and a manufacturing method thereof. The aim is to provide a method that is more practical.

[0015]

According to the present invention, there is provided a ferroelectric memory comprising: a MIS transistor formed on a semiconductor substrate;
An oxide diffusion barrier film formed above the MIS transistor with an interlayer insulating film interposed between the two electrodes in the channel length direction of the transistor formed above the oxide diffusion barrier layer with an interlayer insulating film interposed therebetween; A ferroelectric capacitor, one of the electrodes of the ferroelectric capacitor is connected to the source of the transistor, and the other electrode is connected to the drain of the transistor, and a metal wiring for connecting the other electrode to the drain of the transistor, It is configured as having a cell portion composed of

According to the method of manufacturing a ferroelectric memory of the present invention, a step of forming an MIS transistor in a cell portion on a semiconductor substrate and a step of forming an oxide diffusion barrier film above the MIS transistor via an interlayer insulating film Forming a ferroelectric capacitor over the oxidation diffusion barrier film via an interlayer insulating film such that a direction between the two electrodes is along the direction of the channel; and one of the ferroelectric capacitors. Forming a metal wiring in which the electrode is connected to the source of the MIS transistor and the other electrode is connected to the drain.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the present invention will be schematically described.

In the present invention, the size of the cell is reduced by making the capacitors "horizontal stacking (horizontal type)" instead of "vertical stacking (vertical type)". Further, in the present invention,
First, as a barrier film on the contact plug, use an insulating barrier film instead of a conductive barrier film with a wide margin in the thermal process. After forming a ferroelectric capacitor and performing recovery annealing, And a wiring layer that also serves as a connection with the plug on the diffusion layer. By adopting such manufacturing, in the present invention, the upper and lower electrodes can be simultaneously formed, and the number of steps can be reduced. The yield and reliability are improved by introducing an etching stopper and a second oxidation diffusion barrier film. Further, in the present invention, the connection between the upper (right) electrode and the lower (left) electrode and the source / drain is made after the formation (damage recovery) of the ferroelectric capacitor. The capacitors are placed horizontally. The entire surface up to and including the opening is covered with an insulating oxide barrier film.

Further, two etching stoppers,
Is introduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a structure of a TC parallel unit serial connection type ferroelectric memory according to a first embodiment of the present invention. (A) of the figure is a plan view, (b) is AB of the figure (a)
FIG. 3C is a cross-sectional view taken along a line, and FIG. 3C is a cross-sectional view taken along a CD line in FIG.

A plurality of buried element isolation regions 2, 2,... Are formed on the surface of the semiconductor substrate 30 in stripes, and a plurality of element regions 1, 1,. ing.

In the element region 1, a diffusion layer 4 is formed in a self-aligned manner with respect to the gate electrode 3 of each transistor Tr formed on the gate insulating film 21, which is a first insulating film, to form one conductivity type. A plurality of MOS transistors Tr are configured. The MOS transistor Tr is covered with a second insulating film 22 whose surface is smoothed by a CMP method or the like.
On this second insulating film 22, a laminated film diffusion barrier film (oxide diffusion barrier film) 22 of a nitride film and an oxide film described in detail later is formed.

A contact plug 8 is buried in the second insulating film 22 and is connected to the diffusion layer 4. Note that a contact plug is buried in the gate 3 as a gate contact 8G above the element isolation region 2, for example. For these contact plugs, for example, polycrystalline silicon or W (tungsten) doped with impurities at a high concentration is used. That is, a silicon or silicide film or a contact plug containing W as a main component is used.

Immediately above each MOS transistor Tr via the smoothed second insulating film 22, the ferroelectric capacitor electrode 9 extends laterally in the direction of the gate length of the transistor Tr.
a, a ferroelectric capacitor Cf in which a ferroelectric film 10 as a third insulating film and another capacitor electrode 9b are sequentially arranged. A fourth insulating film 11 is formed above the capacitor Cf. Above the contact plug 8 connected to the diffusion layer 4 of the transistor Tr, a tapered metal wiring 14 made of a metal mainly composed of aluminum, copper, and silver is arranged, and both side surfaces thereof are adjacent to each other. It is electrically connected to the left and right electrodes 9a and 9b of the ferroelectric capacitor Cf. Ferroelectric capacitor electrode 9
a, 9b include Pt, Ir, IrO ₂ , Ru, Ru
O ₂ , an SRO film, a stacked film thereof, or the like can be used. Further, as the ferroelectric film 10, PZT, S
A film having ferroelectricity such as a BT film can be used. An insulating film 13 is further formed on the ferroelectric capacitor Cf and the metal wiring (barrier metal + metal) 14, and a bit line BL is formed on the insulating film 13 along the element region 1 in the lateral direction of FIG. Is formed. One of the metal wirings 14 on both sides of the transistor Tr is electrically connected to the source, and the other is electrically connected to the drain.

Although not shown, the bit line BL
A passivation film is formed on the upper portion to complete a ferroelectric memory.

In the memory cell having the lateral ferroelectric capacitor Cf thus formed, the distance between the contact plugs 8 in the direction along the element region 1 is 2F, as shown in FIG. since dimension across the device region 1 also 2F, the area of one memory cell is 4F ^2, and the ultimate miniaturization is achieved.

Here, the ferroelectric capacitor Cf is formed between a pair of adjacent metal wirings 14, and the distance between the metal wirings 14 is, for example, 1.5F. , 9b and the ferroelectric film 10 are formed. The dimension of the ferroelectric film 10 in the thickness direction of the substrate 30 is desirably, for example, 2F or more, but it is needless to say that the dimension can be freely set depending on the design capacity of the ferroelectric capacitor Cf.

Next, the above-described oxidation diffusion barrier film 25 will be described.

Oxidation of the plug 8 and diffusion of impurities into the transistor region when the ferroelectric film capacitor is formed can be more reliably suppressed by the oxidation diffusion barrier film 25.
For example, the present inventors have confirmed that when the nitride film and the oxide film each have a thickness of 150 nm, sufficient barrier properties can be secured even in a furnace heat treatment at 700 ° C. Note that an oxynitride film may be used as the oxidation diffusion barrier film 25. That is, a single layer or a stacked film including a silicon nitride film and a silicon oxynitride film can be used. In this embodiment, a process of removing the oxidation diffusion barrier film 27 on the plug 8 after forming the capacitor and forming the metal wiring 14 is employed. Since the upper surface of the plug 8 is protected by the barrier film, the recovery annealing in a sufficiently high temperature O ₂ atmosphere can be performed to improve the characteristics.

Next, the metal wiring 14 will be described.

In this embodiment, the tapered metal wiring 14 is used as described above. Further, the metal wiring 14 is formed by embedding one type of metal wiring.

The metal wiring 14 is usually formed as a double structure from an outer barrier metal and a metal serving as an inner main wiring. As this barrier metal, N
It is possible to use b or Ti or a nitride thereof, and a low-resistance metal such as aluminum, copper, or silver for the main wiring. For example, in the case of Al, the present inventors have confirmed that holes having an aspect of about 5 are completely buried at a temperature of about 400 ° C., and these can be used.

Next, a method of manufacturing the above-described device will be described.

As will be described in detail later, in the structure of the embodiment shown in FIG. 1, both electrodes 9a and 9b of the ferroelectric film capacitor Cf conventionally formed separately can be processed at the same time. And the variation in the characteristics of the electrodes 9a and 9b can be suppressed.

FIG. 2 (a)-(c) and FIG. 3 (a)-
The manufacturing process of the ferroelectric memory having the structure shown in FIG. 1 will be described with reference to FIG. The following explanation is
This is performed with reference to a cross-sectional view of the element region 1 cut in the longitudinal direction along the line AB in FIG.

As can be seen from FIG. 2A, first, for example, the element isolation regions 2 and 2 are formed on the surface of an n-type semiconductor substrate 30.
Are formed, and an element region 1 is formed therebetween. Then, a gate 3 is formed on the surface of the element region 1 via a gate oxide film 21.
To form For example, the interval between adjacent gates 3 at this time is 1.5F, and the gate length of the gate 3 is set to F. The gate width is formed slightly smaller than the width of the element region 1 as shown in FIG. Next, a p-type diffusion layer 4 is formed in a self-aligned manner using the gate 3 as a mask, an interlayer insulating film 22 is deposited, and the surface thereof is planarized by a CMP method. Next, a resist is applied on the interlayer insulating film 22 by lithography, and a resist mask is formed by exposure and development. Using this mask, a contact hole 8a reaching the diffusion layer 4 is opened in the middle part of the gate 3; Tungsten W is deposited as a contact plug material in the contact hole 8a, and the interlayer insulating film 22 and the contact plug material W are shaped by CMP to form the contact plug 8. In addition to W, for example, doped polycrystalline silicon may be used as the contact plug material. Next, a contact barrier film 26 and a diffusion barrier film 27 are formed.

Next, as can be seen from FIG. 2B, a capacitor electrode film 9A is formed by a sputtering method or a coating method.

Next, as can be seen from FIG. 2C, the capacitor electrode film 9A in the region where the ferroelectric capacitor is to be formed is removed by etching to form an opening 9B.

Next, as can be seen from FIG. 3A, the ferroelectric film 10 is buried only in the opening 9B. An insulating film 11 is deposited thereon.

Next, as can be seen from FIG. 3B, the capacitor electrode film 9A on the plug 8 and the insulating film 11 are removed by etching in a tapered shape. This etching is stopped at the diffusion barrier film 27. Thereafter, annealing for recovering the processing damage is performed, for example, at 700 ° C. for about 1 hour.

Next, as can be seen from FIG. 3C, the plug 8 is exposed by etching the diffusion barrier film 27 and the contact barrier film 26. Thereafter, the metal wiring 14 is buried in the opening. As the metal wiring 14, T
It is desirable to use a film containing Al or Cu as a main component and using i or Nb as a liner material. After that, the insulating film 13 and the bit line BL are formed.

FIGS. 4 (a), (b) and (c) correspond to FIG.
It is a figure which shows each different modification of 1st Example shown to (b). In FIG. 4A, a columnar wiring 14 (1) is used instead of the tapered metal wiring 14 of FIG. 1B. The wiring 14 (1) is made of the same material as the contact plug 8 thereunder, for example, polycrystalline silicon or W (tungsten) doped with impurities at a high concentration. FIG.
4B, the diffusion layer 4 is directly contacted by the wiring 14 (2) without using the contact plug 8 in FIG. 4A. FIG. 4C uses a wiring 14 (3) obtained by tapering the wiring 14 (2) of FIG. 4B.

FIG. 5 is a sectional view showing a second embodiment of the present invention, showing a memory section MP and a peripheral circuit section PCP. In the case of adopting the structure of the series connection type ferroelectric, it is sufficient to connect the capacitor Cf and the diffusion layer 4 as described above, and the wiring (not shown) inside the cell may be provided only for the gate. In the peripheral circuit portion PCP of FIG. 5, a plug 30 of silicon or W (tungsten) formed in the interlayer insulating film 22 is formed in a contact with the diffusion layer 4. The plug 30 is connected to the fourth insulating film 11
It is connected to embedded wirings 31 and 32 formed therein. That is, when the embedded wiring is formed after the capacitor is formed, the connection between the diffusion layer 4 and the capacitor electrodes 9a and 9b in the cell portion CP is simultaneously made with the diffusion layer 4 in the peripheral circuit portion FCP.

According to the embodiment shown in FIG. 5, there is an effect that it is easy to easily match with an existing library when performing mixed mounting with logic.

Incidentally, an etching stopper film as described later may be formed below the barrier film 25.

FIGS. 6A and 6B show different third embodiments of the present invention. 6A and 6B show examples in which the connection between the capacitor electrodes 9a and 9b and the wiring (diffusion layer 4) is performed not only on the side surface but also on the upper surface. That is, in FIGS. 6A and 6B, the wirings 14 (2) and 14 (2)
In (1), in addition to being electrically connected to the side surfaces of the capacitor electrodes 9a and 9b, the lower surface of the wiring 35 in the insulating film 13 and the upper surfaces of the capacitor electrodes 9a and 9b are electrically connected. As can be seen from the figure, the difference between FIGS. 6A and 6B is that the wiring 14 (2) in FIG. 4, and the wiring 14 (1) of FIG. 6B contacts the diffusion layer 4 via the contact plug 8. In this manner, the structure in which the lower surface of the wiring 35 is connected to the capacitor electrodes 9a and 9b is, for example, as shown in FIG. This is useful when the area of contact with 9a and 9b may be reduced.

FIG. 7 shows a fourth embodiment of the present invention. One of the differences between the embodiment of FIG. 7 and the embodiment of FIG. 5 is that an etching stopper film 37 is formed below the barrier film 26. This etching stopper film is an insulating film composed of a metal oxide or nitride or a silicon nitride film. This etching stopper film 37 prevents the etching of the etching hole for embedding the wiring 14 (1). This prevents the contact plug 8 from being scraped, or prevents the interlayer insulating film 22 from being etched even when misalignment occurs in lithography. This further improves the yield. In FIG. 7, the wiring 14 (1) includes an outer barrier metal layer 14 (1) a and an inner metal layer 14 (1) b. This barrier metal layer is composed of a single layer of a nitride of titanium, niobium, or oxide, or a laminated film containing them.

FIGS. 8A and 8B are cross-sectional views of different examples of the fifth embodiment of the present invention.

The fifth embodiment shown in FIGS. 8A and 8B is different from the fourth embodiment shown in FIG. 7 in that a second oxide diffusion barrier film 39 is additionally formed on the capacitor Cf. is there. That is, the second diffusion barrier film 39 is formed directly in FIG. 8A and indirectly through the oxide film 41 such as O ₃ -TEOS in FIG. 8B. The second
As the oxidation diffusion barrier film 39, a single-layer film or a stacked film including a silicon nitride film, a silicon oxynitride film,
Alternatively, a film having a small diffusion coefficient of hydrogen, such as an oxide or a nitride of Al or Ti, can be used. That is, it can include a plasma nitride film and a silicon nitride film. Further, it may be an oxide or nitride of Al or Ti. Note that the wiring 14 (1)
Although it has a single-layer structure, it may have two layers as shown in FIG.

FIGS. 9 and 10 show a sixth embodiment of the present invention. 9 (a) and 10 (a) show only the cell part, and FIGS. 9 (b) and 10 (b) show the cell part CP and the peripheral circuit part PC.
P is shown. FIGS. 9A and 9B show two insulating films 1.
The second upper surface of the lower insulating film 11 between
Is formed to a desired depth. Due to the presence of the second etching stopper film 43, there is obtained an effect that variations are eliminated when the upper insulating film 13 is subjected to etching (RIE) processing, and the depth becomes uniform. As the second etching stopper,
It is possible to use an insulating film including a single layer of a metal oxide or nitride, a silicon nitride film, and a stacked film. For example, when the depth of the trench wiring is 500 nm, it is effective to use a stopper film having a selectivity of about 20, preferably about 50. In this case, the second etching stopper film 43 is a thin film of about 200 Å.

FIGS. 10 (a) and (b) correspond to FIGS.
(B), respectively, and FIG.
In the device shown in FIG. 2B, a second oxidation diffusion barrier film 39 is further formed on the upper surface of the capacitor cf.
Other configurations in FIGS. 10A and 10B are the same as those in FIG.
(A) and (b) are the same.

As described above, FIGS. 9A and 9B and FIG.
One of the features of O (a) and (b) is that the second etching stopper film 43 exists in both the cell portion and the peripheral circuit portion.

In each of the embodiments described above, an example in which a so-called side wall is used as a transistor structure is not described. However, an embodiment of an LDD type structure may be used. Further, there is no problem even if the silicide layer is formed above the gate and the source / drain. When using silicide, it is desirable to use a diffusion barrier film also from the problem of heat resistance. Also, when forming a contact plug of polycrystalline silicon, it is necessary to take care to obtain a sufficiently low contact resistance. The present invention can also be implemented with a SAC structure using a nitride film as a sidewall material of a transistor. In addition, various modifications can be used without departing from the original spirit.

According to the embodiment of the present invention, the following various effects can be obtained.

In the present invention, the entire surface of the wafer is covered with an insulating barrier film except for an opening through which a plug for making contact with the diffusion layer is passed. That is,
No conductive barrier film with a narrow margin was used. Therefore, the process temperature can be kept high, and the margin is increased. Actually, the damage given during the formation, processing, and formation of the insulating film of the ferroelectric capacitor can be suppressed by performing sufficient annealing, and good characteristics can be obtained. For example, since a barrier property of about 700 ° C. has been confirmed, high-temperature film formation is possible. Therefore, for example, the present invention can be applied to an SBT requiring high-temperature film formation.

According to the present invention, not COP but COT
(Capacitor Over Tr) structure, the ultimate size (4F
Miniaturization up to 2) is possible. As a result, it is possible to achieve both a capacitor exhibiting good characteristics and miniaturization.

More specifically, the following effects can be expected in each of the above embodiments. For example, as can be seen from the embodiment of FIG. 4, since the structure of the capacitor is not vertical but horizontal, a pair of electrodes can be formed simultaneously, and the number of steps can be reduced. Further, with such a structure, the degree of integration is improved and the chip size can be reduced. Furthermore, in the present invention, a film having a sufficient barrier property even at least at 700 ° C., such as a SiN film, is used as the barrier film on the contact plug, instead of the conductive barrier film having a wide margin in the thermal process. Therefore, in addition to the above-described effects, an effect can be expected by covering the entire surface of the wafer with the insulating barrier film before the step of opening the plug contact.
That is, processing damage and the like can be recovered by a high-temperature heat treatment in an oxygen atmosphere before opening a contact. After this recovery, a contact opening will be formed. Further, for example, in the embodiment of FIG. 6, since the contact to the capacitor electrode is made on both the side surface and the upper surface of the capacitor electrode, it is possible to increase the degree of freedom in how to take the contact. For example, in the embodiment of FIG. 7, since an etching stopper film is additionally formed,
Wiring can be more reliably connected to the contact plug, and the yield is improved. For example, in the embodiment of FIG. 8, since the second diffusion barrier film is formed,
It is possible to suppress the diffusion of hydrogen under a reducing atmosphere during the formation of a sinter or passivation after the formation of the capacitor, and to prevent the deterioration of the polarization amount. Further, according to the example of FIG. 9, since the second etching stopper film is formed, the processing of the buried wiring (groove) is facilitated and the over-etching can be sufficiently performed, so that the wiring yield is improved. The speed can be increased, the taper can be suppressed, the chip size can be further reduced, and the film thickness on the capacitor can be suppressed. In addition, since CMP is used to form the capacitor electrode, taper can be reduced and miniaturization can be achieved. Further, damage to the capacitor can be reduced.

[0059]

According to the present invention, miniaturization of a cell can be realized by a simple manufacturing process, and a ferroelectric memory can be stably manufactured.

[Brief description of the drawings]

FIG. 1 is a plan view, a sectional view taken along line AB, and a sectional view taken along line CD of a ferroelectric memory according to a first embodiment of the present invention;

FIG. 2 is a process chart for explaining a first ferroelectric memory manufacturing method.

FIG. 3 is a process chart for explaining a method of manufacturing the ferroelectric memory in FIG. 1;

FIG. 4 is a cross-sectional view showing different modifications of the ferroelectric memory according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a second embodiment of the ferroelectric memory according to the present invention.

FIG. 6 is a cross-sectional view showing different examples of the third embodiment of the ferroelectric memory according to the present invention.

FIG. 7 is a sectional view showing a fourth embodiment of the ferroelectric memory according to the present invention.

FIG. 8 is a cross-sectional view of a different example showing the fifth embodiment of the ferroelectric memory according to the present invention.

FIG. 9 is a sectional view showing a sixth embodiment of the ferroelectric memory according to the present invention;

FIG. 10 is a sectional view showing a sixth embodiment of the ferroelectric memory according to the present invention;

FIG. 11 is a view showing various examples of a cross-sectional structure of a conventional ferroelectric memory.

FIG. 12 is a diagram showing a circuit configuration of a conventional TC parallel unit serial connection type ferroelectric memory.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Element region 2 Element isolation region 3 Gate electrode 4 Diffusion layer 8 Contact plug 9a, 9b Ferroelectric capacitor electrode 10 Ferroelectric film 13 Insulating film 14 Metal wiring 15a, 15b Conductive oxide film 26 Contact barrier film 27 Oxidation diffusion barrier Film 37 etching stopper film 39 second oxidation diffusion barrier film 43 second etching stopper film

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) JA35 JA36 JA37 JA38 JA39 JA43 JA56 MA06 MA17 PR06 PR40 PR42 PR43 PR44 PR52 PR53 PR54 ZA12

Claims (28)

[Claims] A MIS transistor formed on a semiconductor substrate; an oxide diffusion barrier film formed above the MIS transistor via an interlayer insulating film; and an oxide diffusion barrier film formed above the oxide diffusion barrier layer via an interlayer insulating film. A ferroelectric capacitor formed so that the direction between the two electrodes extends along the channel length direction of the transistor, and one electrode of the ferroelectric capacitor is used as the source of the transistor and the other is used as the other. And a metal wiring for connecting the electrode to the drain of the transistor, respectively. 2. The semiconductor device according to claim 1, further comprising a peripheral circuit portion having a transistor, wherein an electrode lead from a diffusion layer in the transistor is connected to a contact plug mainly composed of silicon, a silicide film, or tungsten, and the contact plug. 2. The method according to claim 1, wherein the extraction of the electrode from the diffusion layer in the transistor in the cell portion is directly performed by the metal wiring without using a contact plug. 3. Ferroelectric memory. 3. The ferroelectric memory according to claim 1, wherein said oxidation diffusion barrier film is a single layer or a laminated film formed of a silicon nitride film or a silicon oxynitride film. 4. In the cell portion, the oxide diffusion barrier film is formed between the pair of interlayers except for a contact region for making contact between an electrode of the ferroelectric capacitor and a source and a drain of the transistor. 4. The ferroelectric memory according to claim 1, wherein the ferroelectric memory is formed between insulating films. 5. A connection between at least one electrode of both electrodes of the ferroelectric capacitor and the metal wiring connected to a source or a drain of the transistor is performed through a side surface of the one electrode. The ferroelectric memory according to claim 1, wherein: 6. An electrode drawing from a diffusion layer in a transistor in the cell portion is performed by a contact plug contacting the diffusion layer and a metal wiring connected to the contact plug. 6. The ferroelectric device according to claim 1, wherein an etching stopper film functioning as a stopper when etching a hole for embedding the metal wiring is formed between the ferroelectric and a capacitor. Body memory. 7. The ferroelectric memory according to claim 6, wherein said etching stopper film is an insulating film made of an oxide or nitride of a metal such as Al or a silicon nitride film. 8. The metal wiring has a two-layer structure of an outer barrier metal layer and an inner metal layer, wherein the barrier metal layer is a titanium or niobium nitride or oxide single layer; The ferroelectric memory according to claim 1, wherein the ferroelectric memory is made of a laminated film including them. 9. The metal wiring connecting the electrode of the capacitor with the source and the drain is made of aluminum, copper,
9. The ferroelectric memory according to claim 1, wherein the ferroelectric memory is made of a metal containing silver as a main component. 10. Both electrodes of said ferroelectric capacitor are P
The ferroelectric memory according to claim 1, wherein the ferroelectric memory is configured as t, Ir, IrO ₂ , Ru, RuO ₂ , an SRO film, and a stacked film thereof. 11. The semiconductor device according to claim 1, wherein a second oxidation diffusion barrier film is formed above said ferroelectric capacitor.
11. The ferroelectric memory according to any one of items 1 to 10. 12. The ferroelectric memory according to claim 11, wherein said second oxidation diffusion barrier film includes a plasma nitride film and a silicon oxynitride film. 13. A method according to claim 12, wherein said second oxidation diffusion barrier film is made of Al,
The ferroelectric memory according to claim 11, wherein the ferroelectric memory is made of an oxide or a nitride of Ti. 14. A second etching stopper film serving as a stopper for etching when forming a groove for burying a wiring connected to the metal wiring, above the ferroelectric in the cell portion. The ferroelectric memory according to any one of claims 6 to 13, wherein: 15. The method according to claim 14, wherein the second etching stopper film is an insulating film composed of a single layer of a metal oxide or nitride, a silicon nitride film, and a laminated film. Ferroelectric memory. 16. A step of forming an MIS transistor in a cell portion on a semiconductor substrate, a step of forming an oxide diffusion barrier film above the MIS transistor via an interlayer insulating film, and a step of forming an oxide diffusion barrier film above the MIS transistor. , Through an interlayer insulating film,
Forming a ferroelectric capacitor so that the direction between the two electrodes is along the direction of the channel; one electrode of the ferroelectric capacitor is connected to the source of the MIS transistor, and the other electrode is connected to the drain. Forming a metal wiring. 17. A semiconductor device comprising: a step of forming a direct contact hole to both diffusion layers of the transistor; and a step of forming the metal wiring connecting the two electrodes of the capacitor and the two diffusion layers, respectively. The method for manufacturing a ferroelectric memory according to claim 16, wherein: 18. A step of forming a contact hole on a diffusion layer of a peripheral transistor in a peripheral circuit portion, and forming a peripheral contact plug buried in the contact hole with a material containing silicon, a silicide film, or tungsten as a main component. Forming a direct contact hole opening in the diffusion layer of the MIS transistor in the cell portion after forming the capacitor; and burying the metal wiring in the direct contact hole simultaneously with forming the peripheral contact plug. 18. The method of manufacturing a ferroelectric memory according to claim 16, further comprising: 19. The method according to claim 19, wherein the oxidation diffusion barrier film comprises a step of forming a single layer or a laminated film including a silicon nitride film and a silicon oxynitride film.
19. A method for manufacturing a ferroelectric memory according to item 18. 20. The metal wiring for connecting both electrodes of the capacitor and the two diffusion layers in the cell portion is connected to a cell contact plug closer to the diffusion layer than the oxidation diffusion barrier film. And an opposite cell metal wiring. In forming the cell metal wiring, the oxidation diffusion barrier film formed on the contact region to the MIS transistor is etched to form the cell contact plug. 20. The method according to claim 16, further comprising the step of exposing.
3. The method for manufacturing a ferroelectric memory according to claim 1. 21. The method according to claim 16, further comprising a step of depositing an etching stopper layer between the step of forming the oxidation diffusion barrier and the step of forming the ferroelectric capacitor. 2. A method for manufacturing a ferroelectric memory according to claim 1. 22. The method for manufacturing a ferroelectric memory according to claim 21, wherein said etching stopper layer is formed of a film containing titanium or aluminum oxide or nitride. 23. The step of forming a metal wiring comprises a step of forming an outer barrier metal film and a step of depositing a metal inside the barrier metal film, wherein the barrier film is formed by nitriding titanium or niobium. 17. The method for manufacturing a ferroelectric memory according to claim 16, wherein the ferroelectric memory is formed of a material, an oxide single layer, or a laminated film including the same. 24. A second power supply, comprising:
24. The method of manufacturing a ferroelectric memory according to claim 16, further comprising the step of forming an oxidation diffusion barrier film of (1). 25. The method according to claim 24, further comprising a heat treatment step of forming a single layer or a laminated film including a silicon nitride film and a silicon oxynitride film as the second oxidation diffusion barrier film. A manufacturing method of the ferroelectric memory according to the above. 26. The method according to claim 26, wherein the second oxidation diffusion barrier film is made of A
25. The method of manufacturing a ferroelectric memory according to claim 24, further comprising a step of forming a film containing an oxide or a nitride of 1, Ti. 27. The method according to claim 16, further comprising the step of forming a second etching stopper layer above both the lead electrodes of the ferroelectric capacitor above the MIS transistor. 3. The method for manufacturing a ferroelectric memory according to 1. 28. The method according to claim 27, wherein an insulating film composed of a single layer of a metal oxide or nitride, a silicon nitride film, and a laminated film is used as the second etching stopper film. Manufacturing method of a ferroelectric memory.