JP2002289594A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a hard mask which has high reliability and simplifies the micronization. SOLUTION: On an interlayer insulating film 3, a hard mask 4a is made of a silicon oxide film containing organic matter. Using this as an etching mask, the above interlayer insulating film 3 is dry etched to form a via hole 7. In this etching process, Cu wiring 1 is protected with a protective film 2. Then, the extraneous matter made at the sidewall of the via hole 7 is completely removed by organic peeling chemicals (chemicals where the organic solvents of a variety of amide or a variety of alcohol constitute the composition) containing ammonium fluoride. Here, the etching resistance of the hard mask 4a in the organic peeling chemicals containing ammonium fluoride constituted of a silicon oxide film containing organic matter is high. Therefore, a fine via hole 7 can be made with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to an etching mask used in the manufacture of a semiconductor device and a cleaning method after the etching.

[0002]

2. Description of the Related Art Miniaturization and densification of semiconductor devices are still being vigorously pursued, and at present, logic devices or 1 gigabit dynamic random access memories (GbDRAMs) designed on the basis of dimensions of about 0.15 .mu.m have been developed. Ultra-highly integrated semiconductor devices, such as memory devices, have been developed and prototyped.

Usually, in the manufacture of a semiconductor device, patterns formed of various materials such as a metal film, a semiconductor film, and an insulator film are sequentially laminated on a semiconductor substrate to form a semiconductor device having a fine structure. In the case of laminating the pattern for the semiconductor element, in a photolithography step, a resist mask is formed by aligning (positioning) a mask with a lower layer pattern formed in a previous step. Then, the material film is processed using the resist mask as a mask for reactive ion etching (RIE) to form an upper layer pattern.

Recently, instead of a resist mask, an inorganic insulating material such as a silicon dioxide film (relative dielectric constant: about 3.9) or a silicon nitride film (relative dielectric constant: about 7.5) is used as an etching mask (hereinafter referred to as an etching mask). , Called a hard mask)
, And a method of processing the material to be etched by RIE has become essential. This is because the shape of a pattern used for a semiconductor element can be more easily controlled with a hard mask that has less deposits in RIE than with a resist mask. The use of such a hard mask
2. Description of the Related Art As semiconductor elements become finer, they are increasingly used.

In particular, when an organic insulating film is used as an interlayer insulating film in forming a trench wiring (damascene wiring), a hard mask having a small dielectric constant is required. Further, when forming a groove for groove wiring in the interlayer insulating film, an etching stopper layer is indispensable in dry etching of the interlayer insulating film.

Referring to FIG. 11 and FIG. 12, a case where a via hole for a multilayer wiring is formed in an interlayer insulating film using a hard mask will be described. FIG. 11 and FIG.
FIG. 6 is a schematic cross-sectional view in the order of steps for forming via holes in an interlayer insulating film which is an organic insulating film on a Cu wiring.

[0007] As shown in FIG.
A silicon carbide (SiC) film 102 is formed on 1. Then, an organic insulating film 103 is formed on the SiC film 102 by known coating and baking. Here, the organic insulating film 10
Reference numeral 3 denotes an organic insulating film having a low dielectric constant.

Then, a silicon dioxide film 104 is formed on the organic insulating film 103 by a plasma-excited CVD method.
A resist mask 105 is formed thereon by a known photolithography technique. Here, an opening 106 is formed in the resist mask 105. Then, the silicon dioxide film 104 is etched by known RIE using the resist mask 105 as an etching mask. This R
In the IE, CF ₄ , O ₂ and Ar are used as etching gases.
Is used. In this case, in the RIE apparatus, the etching gas is plasma-excited by two high frequencies (RF). Here, the RIE apparatus has a multi-chamber.

Next, the organic insulating film 103 is dry-etched in another reaction chamber of the multi-chamber. Here, a mixed gas of N ₂ and H ₂ or NH ₃ (ammonia) gas is used as an etching gas, and plasma excitation is performed at a high frequency. By the dry etching of the organic insulating film 103, as shown in FIG. 11 (b), at the same time as the via hole 107 is formed, the resist mask 105 made of the organic film is also etched and removed, exposing the silicon dioxide film 104. I do. In this RIE process, the SiC film 1
02 functions as an etching stopper, and the Cu wiring 10
Protect one surface from etching.

However, in the formation of the via hole 107, the deposit 1 containing silicon and oxygen is formed on the side wall.
08 is formed. Therefore, a cleaning treatment is performed using an organic stripping chemical solution containing ammonium fluoride (a chemical solution containing an organic solvent of amides and alcohols as a composition). As shown in FIG. 12 (a), the above-mentioned deposit
8 is removed. However, in this case, FIG.
As shown in FIG. 7, the surface region of the silicon dioxide film 104 is also etched to be like the silicon dioxide film 104a. For this reason, the organic insulating film 103 in the frontage region of the via hole 107 is exposed.

Next, the SiC film 102 at the bottom of the via hole 107 is dry-etched using the silicon dioxide film 104a as an etching mask. Here, the etching apparatus is an RI having the above-described multi-chamber.
E device. The etching gas for the SiC film 102 is obtained by adding N ₂ to a mixed gas of CH ₂ F ₂ , O ₂ , and Ar, and is subjected to plasma excitation to perform dry etching.

After the dry etching of the SiC film 102, a residue 109 containing copper, silicon and oxygen is formed as shown in FIG. In this RIE, the upper part of the organic insulating film 103 exposed by the etching of the silicon dioxide film 104 is etched to form a corroded portion 110.

Next, the above-mentioned treatment of the organic stripping solution is performed again. In this process, the residue 109 is removed. In this way, as shown in FIG.
Via holes 107 that penetrate the organic insulating film 103 on the substrate 1 and reach the surface of the Cu wiring 101 are formed. Although not shown, a contact plug is filled in the via hole 107 to connect an upper layer wiring.

[0014]

As described above, when the silicon dioxide film 104 is used as a hard mask, the silicon dioxide film 104 is removed in the step of processing an organic stripping chemical solution for removing the deposit 108 formed after dry etching. Membrane 10
The surface region of No. 4 is wet-etched, and its pattern shape is receded.

Then, in the dry etching step for forming the via hole 107, the corroded portion 110 is formed on the organic insulating film 103 as described above. The formation of the corroded portion 110 is a major factor that hinders the production of fine via holes, and makes it difficult to miniaturize the multilayer wiring structure.

A main object of the present invention is to solve the above-mentioned problems and to provide a hard mask which has high reliability and facilitates miniaturization. Another object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can facilitate fine processing of a semiconductor element, and to significantly reduce the manufacturing cost of the semiconductor device.

[0017]

To this end, in the semiconductor device of the present invention, a mask is formed on the semiconductor substrate on which the semiconductor device is mounted by using a silicon oxide film containing an organic substance.
The material to be etched is processed by dry etching using the mask as an etching mask. Here, the material to be etched is an organic insulating film, a metal oxide film or a conductor film.

Alternatively, in the semiconductor device according to the present invention, in the wiring structure forming the semiconductor device, the mask made of the silicon oxide film containing the organic substance is a part of the interlayer insulating film between the wirings.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a material film to be etched on a semiconductor substrate and a step of forming a mask with a silicon oxide film containing an organic substance on the surface of the material film to be etched. Dry etching the material film to be etched using the mask as an etching mask, and removing a residue formed after the dry etching with an organic stripping chemical solution containing ammonium fluoride (an organic solvent such as an amide or an alcohol). Removal with a chemical solution as a substance).

The above-mentioned material film to be etched is a metal oxide film which is an organic insulating film, a conductor film, a high dielectric constant film or a ferroelectric film.

The organic-containing silicon oxide film is composed of an organic SOG (spin-on-glass), a methylsilsesquioxane film or a methylated hydrogensilsesquioxane film.

Here, the organic substance contained in the silicon oxide film containing the organic substance is an alkyl group, and the concentration of the organic substance is 6 wt% or more.

The relative dielectric constant of the silicon oxide film containing the organic substance is about 2.8, which is relatively small compared to 3.9 of the silicon dioxide film. Further, the silicon oxide film containing an organic substance has a very high etching resistance in an organic stripping chemical solution containing ammonium fluoride, as compared with a normal silicon oxide film.

For this reason, in the case of forming a damascene wiring or forming a semiconductor element, fine processing can be performed with high precision and with ease. Then, the manufacturing cost of the semiconductor device can be significantly reduced.

[0025]

Next, a first embodiment of the present invention will be described with reference to FIGS. 1 to 3 are schematic cross-sectional views in the order of steps for forming via holes in an interlayer insulating film, which is an organic insulating film on a Cu wiring, as in the prior art.

As shown in FIG. 1A, a protective insulating film 2 is formed on a Cu wiring 1 by using a SiC film having a thickness of about 100 nm. The relative permittivity of this SiC film is about 4.6. Then, an interlayer insulating film 3 having a thickness of 600 nm is formed on the protective insulating film 2. Here, the interlayer insulating film 3 is an organic insulating film having a low dielectric constant. Examples of such an organic insulating film include organic polysilazane, BCB (benzocyclobutene), polyimide, plasma CF polymer, and plasma CF. C
H polymer, SiLK (registered trademark), Teflon AF (registered trademark), Parylene N (registered trademark), Parylene AF4
(Registered trademark) and polynaphthalene N. Here, the relative dielectric constant of these organic insulating films is about 2.

Next, a film thickness of 100 nm is formed on the interlayer insulating film 3.
An organic-containing silicon oxide film 4 is formed to a degree. As the organic-containing silicon oxide film, a known organic SOG film or a low dielectric constant film such as an MSQ film or an MHSQ film is used. The organic substance in this case is an alkyl group such as a methyl group and an ethyl group. Here, this MSQ film or MHS
When the porosity of these films is increased, the dielectric constant of the Q films is reduced to about 2 which is smaller than the above-mentioned 2.8.

Next, a resist mask 5 having an opening pattern is formed thereon by a known photolithography technique.

Next, as shown in FIG. 1B, the organic-containing silicon oxide film 4 is etched by RIE using the resist mask 5 as an etching mask, and the diameter of the organic-containing silicon oxide film 4 is reduced to 0.1.
A hard mask 4a having an opening 6 of 5 μm is formed. Here, R ₄ is used by using a mixed gas of CF ₄ , O ₂ and Ar.
In the IE apparatus, the etching gas is plasma-excited at two high frequencies. Also in this case, the RIE apparatus has a multi-chamber.

Next, the interlayer insulating film 3 is dry-etched in another reaction chamber of the RIE apparatus. Here, as an etching gas, a mixed gas of N ₂ and H ₂ or NH ₃
Plasma excitation is performed at a high frequency using gas. By the dry etching of the interlayer insulating film 3, as shown in FIG. 2A, the via holes 7 are formed, and at the same time, the resist mask 5 formed of the organic film is also etched away. Then, the surface of the hard mask 4a composed of the organic-containing silicon oxide film is exposed. In this RIE process, the protective insulating film 2 functions as an etching stopper, and the Cu wiring 1
Protect the surface from etching.

As described in the background art, the formation of the via hole 7 forms a deposit 8 containing silicon and oxygen on the side wall thereof. Therefore, a cleaning treatment is performed using an organic stripping chemical solution containing ammonium fluoride (a chemical solution containing an organic solvent of amides and alcohols as a composition).

As shown in FIG. 2B, the deposit 8 is completely removed by the treatment of the organic stripping solution. In the present invention, the hard mask 4a is not etched. This is because the organic-containing silicon oxide film has high etching resistance to the ammonium fluoride-containing organic stripping solution. Thus, the interlayer insulating film 3
A via hole 7 having a fine size can be formed.

The inventor has studied in detail the relationship between the amount of the alkyl group in the organic-containing silicon oxide film and the etching resistance of the ammonium fluoride-containing organic stripping solution. As a result, it was found that when the content of the methyl group or the ethyl group in the MSQ film or the MHSQ film was 6 wt% or more, the etching resistance was improved. Therefore, in the present invention, an organic SOG film, an MSQ film,
In the HSQ film, the content of an organic substance such as a methyl group or an ethyl group is preferably set to be 6 wt% or more. The upper limit of the content of these organic substances is 60 watts.
t%.

Next, as shown in FIG. 3A, the protective insulating film 2 at the bottom of the via hole 7 is dry-etched using the hard mask 4a as an etching mask.
Here, the etching apparatus is an RIE apparatus having the above-described multi-chamber. The etching gas for the protective insulating film 2 is N ₂ mixed gas of CH ₂ F ₂ , O ₂ , and Ar.
₂ is added, and this is plasma-excited and dry-etched.

After the dry etching of the protective insulating film 2,
As described in the related art, the residue 9 containing copper, silicon, and oxygen forms the via hole 7 on the Cu wiring 1.
Formed at the bottom.

Next, the above-described treatment of the organic stripping solution is performed again. In this process, the residue 9 is completely removed. In this way, as shown in FIG. 3B, a fine via hole 7 having a diameter of 0.2 μm or less penetrating through the interlayer insulating film 3 on the Cu wiring 1 and reaching the surface of the Cu wiring 1 is formed. After this step, hard mask 4a is hardly etched for the above-mentioned reason. In this way, a via hole 7 having a fine size can be formed in the interlayer insulating film 3. Although not shown later, the via hole 7 is filled with a contact plug to connect an upper layer wiring.

Next, a second embodiment of the present invention will be described with reference to FIGS. 4 and 5 are cross-sectional views in the order of steps in the case of forming a wiring pattern using an organic-containing silicon oxide film as a hard mask, which is a feature of the present invention. Here, the same components as those described in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 4A, a metal film 12 is formed on the insulating film 11. This metal film 12 is formed of tungsten or the like (W film or W and tungsten nitride (W
N) or tungsten silicide.

Next, an organic-containing silicon oxide film 4 having a thickness of about 200 nm is formed on the metal film 12. Subsequently, a resist mask 13 of a wiring pattern is formed on the organic-containing silicon oxide film 4 by using a known photolithography technique. Then, the organic-containing silicon oxide film 4 is processed by RIE using the resist mask 13 as an etching mask. Here, the RIE etching gas is obtained by plasma-exciting a mixed gas of CF ₄ gas and helium gas. Here, CH ₂ F ₂ , CHF instead of CF ₄ gas
Fluorocarbon gas such as ₃ , C ₄ F ₈ , CH ₃ F may be used.

In this way, as shown in FIG. 4B, a hard mask 4a of a wiring pattern is formed on the metal film 12. Here, the pattern width and pattern interval of the hard mask 4a are both 0.2 μm.

Next, after the resist mask 7 is removed, as shown in FIG. 4C, the hard mask 4a is used as an etching mask, and an ICP (Inductive Couple) is used.
The metal film 12 is dry-etched by a plasma etching apparatus using edPlasma or microwave excitation (ECR) to form the wiring 14. In this dry etching, a mixed gas of SF ₆ , N ₂ and Cl ₂ is used as a reaction gas.

After the dry etching, a residue 15 containing tungsten, silicon and oxygen is deposited on the wiring 1.
4 is formed on the side wall.

Next, a known oxygen plasma treatment (ashing) is performed, and thereafter, the same cleaning treatment of the organic stripping solution as described in the first embodiment is performed. In this process, the residue 15 is completely removed. Thus, FIG.
As shown in FIG. 3A, a width of 0.2 μm is formed on the insulating film 11.
The following fine wiring 14 is formed. And this wiring 1
The hard mask 4a is left on the substrate 4 as it is. After this cleaning step, hard mask 4a is hardly etched.

Next, as shown in FIG. 5B, a flat interlayer insulating film 16 is formed by depositing an insulating film on the entire surface by CVD and flattening the surface by chemical mechanical polishing (CMP). .

Also in the second embodiment, the size of the fine wiring is high. The relative permittivity of the hard mask 4a remaining as a part of the interlayer insulating film as it is is small. Therefore, the parasitic capacitance between the wirings is reduced.

Next, a third embodiment of the present invention will be described with reference to FIGS. In this embodiment, the present invention is applied to formation of a dual damascene wiring.
Here, the same components as those described in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 6A, a protective insulating film 2 of a SiC film having a thickness of about 100 nm is formed on a lower wiring 21 made of Cu. Then, a first interlayer insulating film 22 having a thickness of 500 nm is formed on the protective insulating film 2. Here, the first interlayer insulating film 22 is an organic insulating film having a low dielectric constant. Examples of such an organic insulating film include organic polysilazane, BCB (benzocyclobutene), polyimide, and plasma CF polymer. , Plasma CH polymer,
SiLK (registered trademark), Teflon AF (registered trademark), Parylene N (registered trademark), Parylene AF4 (registered trademark),
And polynaphthalene N.

Next, a film having a thickness of 10
A first organic-containing silicon oxide film 23 of about 0 nm is formed. As the first organic-containing silicon oxide film 23, a known organic SOG film or a low dielectric constant film such as an MSQ film or an MHSQ film is used.

Similarly, the first organic-containing silicon oxide film 23
A second interlayer insulating film 2 made of an organic insulating film having a low dielectric constant
The fourth and second organic-containing silicon oxide films 25 are formed by lamination. Here, the thickness of the second interlayer insulating film 24 is 1 μm, and the thickness of the second organic-containing silicon oxide film 25 is 100 nm.
m.

Then, the second organic-containing silicon oxide film 25
A silicon nitride film 26 having a thickness of about 50 nm is deposited thereon. Further, an antireflection film 27 and a resist mask 28 having an opening pattern are formed by a known photolithography technique.

Then, the silicon nitride film 26 is dry-etched by RIE using the resist mask 28 as an etching mask, and as shown in FIG.
An opening 29 is formed in 6a. Here, CHF ₃ , a mixed gas of Ar and O ₂ is used as an etching gas, and the second organic-containing silicon oxide film 25 is not etched.

Next, as shown in FIG. 7A, the anti-reflection film 30 is again formed on the second organic-containing silicon oxide film 25 and the silicon nitride film 26a by photolithography.
Then, a resist mask 31 is formed.

Next, as shown in FIG. 7B, using the resist mask 31 as an etching mask,
Then, the second organic-containing silicon oxide film 25 is dry-etched. Here, CF ₄ ,
A mixed gas of Ar, O ₂ and N ₂ is used. In this etching step, the second interlayer insulating film 24 is also partially etched.

Next, as shown in FIG. 8A, the second interlayer insulating film 24 is dry-etched in the reaction chamber of the RIE apparatus in the same manner as described in the first embodiment to form a second via. A hole 33 is formed. Here, a mixed gas of N ₂ and H ₂ or an NH ₃ gas is used as an etching gas, and plasma excitation is performed at a high frequency. This second interlayer insulating film 2
In the dry etching of No. 4, the second hard mask 32 and the silicon nitride film 26a serve as an etching mask,
The organic-containing silicon oxide film 23 has a role of an etching stopper layer. Then, the first interlayer insulating film 22 is protected from etching.

Although not shown, similar to the description of the first embodiment, the formation of the second via hole 33 forms a deposit containing silicon and oxygen on the side wall. Therefore, the adhered substance is removed by a cleaning process using an organic stripping chemical solution containing ammonium fluoride.

Next, the silicon nitride film 26a and the second layer
Using the inter-insulating film 24 as an etching mask,
Select the mask 32 and the first organic-containing silicon oxide film 23
Dry etching. Where the etching gas
Then, C_Four F₈ , CO, O _Two And a mixed gas of Ar and
You. In this way, as shown in FIG.
Forming a hard mask 34 and a second hard mask 32a.
You.

Next, as shown in FIG. 9A, the second interlayer insulating film 24 is dry-etched using the silicon nitride film 26a and the second hard mask 32a as an etching mask to form a wiring groove 35. . In this etching step, the first hard mask 34 serves as an etching stopper layer (mask), and the first interlayer insulating film 22 is also selectively etched to form the first via holes 36. Here, a mixed gas of N ₂ and H ₂ or an NH ₃ gas is used as an etching gas. Here, the lower wiring 21 is protected from etching by the protective insulating film 2.

After this etching step, although not shown,
As described in the first embodiment, the deposits formed are removed by a cleaning treatment with an organic stripping chemical solution containing ammonium fluoride.

Next, as shown in FIG. 9B, the protective insulating film 2 at the bottom of the first via hole 36 is dry-etched using the first hard mask 34 and the second hard mask 32a as an etching mask. . Here, the etching gas for the protective insulating film 2 is a mixed gas of CH ₂ F ₂ , O ₂ , and Ar to which N ₂ has been added.

As described in the first embodiment, after the dry etching of the protective insulating film 2, the residue 37 containing copper, silicon and oxygen remains on the bottom of the first via hole 36 on the lower wiring 21. Formed.

Therefore, the above-mentioned treatment of the organic stripping solution is performed again. In this process, the residue 37 is completely removed. In this manner, as shown in FIG. 10A, the first via hole 36 is formed in the protective insulating film 2, the first interlayer insulating film 22, and the first hard mask 34 so as to reach the surface of the lower wiring 21. . Further, the second interlayer insulating film 24 and the second
The wiring groove 35 is formed in the hard mask 32a.

Finally, as shown in FIG.
A barrier film 38 is formed on the side walls of the via hole 36 and the wiring groove 35, and Cu is filled therein to form an upper wiring 39. The upper wiring 39 is connected to the lower wiring 21. Further, the first hard mask 34 and the second hard mask 32a functioning as etching masks or etching stoppers are used as they are as interlayer insulating films.

In this embodiment, the same effects as described in the first embodiment are produced. That is, in the present invention, the first hard mask and the second hard mask are not etched when the deposits or residues after the dry etching are removed by the cleaning treatment with the organic stripping solution containing ammonium fluoride. This is because the organic-containing silicon oxide film has high etching resistance to the ammonium fluoride-containing organic stripping solution. In this way, a wiring structure having a highly accurate structure can be formed.

Further, in the third embodiment, since the relative permittivity of the hard mask to be left is small, the effect that the parasitic capacitance between the multilayer wirings is reduced also occurs.

As described above, a feature of the present invention resides in that a hard mask or an etching stopper layer is formed of an organic-containing silicon oxide film. Therefore, application of the present invention is not limited to the above embodiment. In addition, it should be noted that the above-described hard mask is also effective when patterning a high dielectric constant film or a ferroelectric film formed of a metal oxide used for a capacitor insulating film of a capacitor.

The present invention is not limited to the above embodiments, and the embodiments can be appropriately modified within the scope of the technical idea of the present invention.

[0067]

As described above, according to the present invention, a hard mask used in a dry etching process for manufacturing a semiconductor device can be formed by using an organic SOG film, a methylsilsesquioxane film, or a methylated hydrogensilsesquioxane film. It is formed of a silicon oxide film containing an organic substance such as a sun film. Here, the organic substance contained in the silicon oxide film containing the organic substance is an alkyl group, and the organic substance concentration is 6 wt%.
Set up as above.

The relative permittivity of the silicon oxide film containing an organic substance is relatively small, and the silicon oxide film containing an organic substance has an organic exfoliated film containing ammonium fluoride as compared with a normal silicon oxide film. Very high etching resistance in chemicals.

For this reason, in the case of forming a damascene wiring or forming a semiconductor element, fine processing can be performed with high precision and with ease. Then, the manufacturing cost of the semiconductor device can be significantly reduced.

If the silicon oxide film containing an organic substance used as the hard mask is left as it is and used as a part of an interlayer insulating film between wirings, the relative dielectric constant becomes small, so that the parasitic capacitance between the wirings becomes small. Is reduced. Further, the operation speed of the semiconductor device can be easily increased.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a via hole in a manufacturing process order for describing a first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating a via hole manufacturing process in the order of a process following the above process.

FIG. 3 is a cross-sectional view illustrating a via-hole manufacturing process in the order of the above-described subsequent process.

FIG. 4 is a cross-sectional view illustrating a wiring in order of a manufacturing process for explaining a second embodiment of the present invention;

FIG. 5 is a cross-sectional view in the order of the manufacturing steps of the wiring for explaining the following steps.

FIG. 6 is a cross-sectional view illustrating a damascene wiring in order of a manufacturing process for describing a third embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a damascene wiring in the order of a manufacturing process for explaining the following process.

FIG. 8 is a cross-sectional view of a damascene wiring in the order of the manufacturing process for explaining the following process.

FIG. 9 is a cross-sectional view illustrating a damascene wiring in the order of a manufacturing process for explaining the following process.

FIG. 10 is a cross-sectional view of a damascene wiring in the order of the manufacturing process for explaining the following process.

FIG. 11 is a cross-sectional view illustrating a via hole in a manufacturing process order for explaining a conventional technique.

FIG. 12 is a cross-sectional view illustrating a via hole manufacturing process in the order of the above-mentioned subsequent process.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Cu wiring 2 protective insulating film 3, 16 interlayer insulating film 4 organic-containing silicon oxide film 4 a hard mask 5, 13, 28, 31 resist mask 6, 29 opening 7 via hole 8 attached matter 9, 15, 37 residue 11 Insulating film 12 Metal film 14 Wiring 21 Lower wiring 22 First interlayer insulating film 23 First organic-containing silicon oxide film 24 Second interlayer insulating film 25 Second organic-containing silicon oxide film 26, 26a Silicon nitride film 27, 30 Antireflection film 32, 32a Second hard mask 33 Second via hole 34 First hard mask 35 Wiring groove 36 First via hole 38 Barrier film 39 Upper layer wiring

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference) QQ30 QQ37 QQ48 QQ91 QQ92 QQ94 RR01 RR06 RR21 RR22 RR23 RR24 RR25 RR29 TT04 VV10 VV16 WW04 XX01 XX03 XX21 XX24 5F043 BB27 DD15 DD21 FF06 GG03

Claims (13)

[Claims] 1. A semiconductor device, wherein a mask is formed of a silicon oxide film containing an organic substance, and a material to be etched is processed by dry etching using the mask as an etching mask. 2. The method according to claim 1, wherein the material to be etched is an organic insulating film,
2. The semiconductor device according to claim 1, wherein the semiconductor device is a metal oxide film or a conductor film. 3. The wiring structure of a semiconductor device, wherein the mask made of the organic-containing silicon oxide film is part of an interlayer insulating film between the wirings. The semiconductor device according to claim 2. 4. The semiconductor device according to claim 1, wherein the silicon oxide film containing an organic substance is made of organic SOG (spin-on-glass). 5. The organic-containing silicon oxide film is a methylsilsesquioxane film (Methyl Silsesquioxane: M).
SQ film) or Methylated Hydrogen Silsesquioxane film
4. The semiconductor device according to claim 1, wherein the semiconductor device comprises a xane: MHSQ film. 6. An organic substance contained in the organic substance-containing silicon oxide film is an alkyl group, and the concentration of the organic substance is 6 wt.
6. The semiconductor device according to claim 4, wherein the ratio is not less than%. 7. A step of forming a material film to be etched on a semiconductor substrate, a step of forming a mask with a silicon oxide film containing an organic substance on the surface of the material film to be etched, and using the mask as an etching mask. A step of dry-etching the material film to be etched, and a step of removing residues formed after the dry-etching with an organic stripping chemical solution containing ammonium fluoride (a chemical solution containing an organic solvent such as amides and alcohols as a composition). A method of manufacturing a semiconductor device, comprising: 8. The method according to claim 7, wherein the material film to be etched is an organic insulating film. 9. The method according to claim 7, wherein the material film to be etched is a conductor film. 10. The method according to claim 7, wherein the material film to be etched is a metal oxide film which is a high dielectric constant film or a ferroelectric film. 11. The silicon oxide film containing an organic substance,
The method of manufacturing a semiconductor device according to claim 7, wherein the method is configured by organic SOG (spin-on-glass). 12. The silicon oxide film containing an organic substance,
11. The method of manufacturing a semiconductor device according to claim 7, comprising an MSQ film or an MHSQ film. 13. The manufacturing of a semiconductor device according to claim 11, wherein the organic substance contained in the silicon oxide film containing the organic substance is an alkyl group, and the concentration of the organic substance is 6 wt% or more. Method.