JP2002281083A - Test cell generating circuit and test data generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that there is possibility that it is decided that a cell conduction test is normally ended when only a test cell clarifying bit is correctly received although any transmission error is generated in a bit other than the test cell clarifying bit. SOLUTION: A test cell generating circuit is provided with a header generating part for generating the header of a test cell, a data generating part constituted of an M system generating circuit for generating the payload test data of the test cell, a selector for inserting the test cell header generated by the header generating part and the test data generated by the data generating part into a cell signal, and a control part for controlling the generating timing of the test cell and the insert timing into the cell signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test cell and a test data generating circuit in a communication apparatus, and more particularly to an ATM circuit.
(Asynchronous Transfer Mode) This is suitable for a test cell for performing a cell continuity test between functional blocks in a communication device and a circuit for generating test data.

[0002]

2. Description of the Related Art A test cell generated by a conventional test cell generation circuit has one bit out of 5 bytes of an ATM cell header for specifying a test cell in an ATM communication apparatus. Was just what was assigned.

[0003] In a test in an ATM communication device using this test cell, a cell in which the test cell explicit bit is made valid on the transmitting side is generated, and within a certain period of time, the test cell explicit bit becomes valid on the receiving side. The conduction characteristic is determined based on whether or not a cell is received. The cells other than the test cell are distinguished from the test cell and the normal cell by not setting the test cell explicit bit to be valid. In the test, the 48 bytes of the payload did not have any particular meaning.

[0004]

The prior art has the following technical problems. In other words, the functional blocks constituting the ATM communication device are implemented in an LSI for each function, but the number of lines accommodated in the ATM communication device tends to increase, and the demand for functions and services also tends to increase. It is in. Therefore, the LS mounted on the device
The mainstream of I is a multi-pin LSI having 300 pins or more. Similarly, discrete general-purpose ICs also tend to have more pins, and the pitch between pins tends to be narrower. Therefore, the probability of occurrence of a solder defect in the manufacture of the device is high, and it is difficult to find it.

When debugging a prototype device, especially when debugging firmware or software mounted on the device, it is essential that functional connections of hardware are guaranteed. In particular, the verification of the transmission system of the ATM communication apparatus, that is, the path transmitted by the cell which is the main information, is a test item to be prioritized.

[0006] Further, when the apparatus is operated, a method of setting the upper layer and the like after ending the conduction check of the cells of the transmission system at the time of starting the apparatus is effective from the viewpoint of operation.

[0007] However, the conventional conduction confirmation is a reception confirmation using only one test cell explicit bit. Therefore, even if there is a transmission error in bits other than the test cell explicit bit, if only the test cell explicit bit is correctly received, it may be determined that the cell continuity test has been completed normally. In order to avoid this, a complicated cell synchronization circuit is provided between the functional blocks to be tested, and the test has to be performed by a double mechanism such as detecting a bit error of a cell there.

[0008]

In order to solve the above problems, a test cell generation circuit according to the present invention includes a header generation section for generating a header of a test cell, and a data generation section for generating test data of a payload of the test cell. A selector that inserts the test cell header generated by the header generation unit and the test data generated by the data generation unit into a cell signal; and a control unit that controls the generation timing of the test cell and the insertion timing into the cell signal. I decided that.

The test data generation circuit is a test data generation circuit for generating test data in N-bit units from a parallel input of N bits (N: a positive integer), wherein each delay constituting the M-sequence generation circuit is provided. A first logic unit for obtaining an output N clocks after the initial state of the circuit;
And a second logic unit for obtaining the output of the last stage of the delay circuit for each clock until -1 clock.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention relates to a test cell generation circuit having a function of generating a payload of a random bit pattern using small-scale hardware.

An embodiment of the present invention applied to an ATM communication device will be described below.

(1) First Embodiment (1-1) Circuit Configuration FIG. 1 shows a block diagram for realizing test cell generation. The test cell generation circuit 100 includes a header generation unit 200,
It comprises functional blocks of a data generation unit 300, a control unit 400, and a SEL 500. The header generation unit 200 generates a 5-byte test cell header from a control signal input from the control unit 400, an input clock, and the like. The data generation unit 300 generates a 48-byte test cell payload from a code generation circuit corresponding to a primitive polynomial from a control signal input from the control unit 400, an input clock, and the like.
The control unit 400 controls the generation of test cells by the header generation unit 200 and the data generation unit 300 from a start signal for starting generation of a control signal, an input clock, and the like, and also controls the timing of inserting test cells into a transmission sequence. .

The cell signal 104 is a cell transmission path in the ATM device, and is composed of eight parallel signal lines.
The cell signal 104 is input to the SEL 500. CLK
Reference numeral 103 denotes a clock, which is input to the header generator 200, the data generator 300, and the controller 400, respectively.
The CLK 103 also serves as a transmission clock for the cell signal 104. CLK 102 is also a clock, and is input to the data generator 300 and the controller 400, respectively. The initial value 101 is input to the data generator 300. The start signal 105 is a start signal for notifying the test cell generation circuit 100 of the start of test cell generation, and is input to the control unit 400. Output 109 of header generation unit 200 and data generation unit 3
00 are respectively input to the SEL 500. An output 106 of the control unit 400 is a header generation unit.
200 and the data generator 300 . The control signals 107 and 108 are input to the data generator 300, respectively. The selector signal 111 is input to the SEL 500. The output of the SEL 500 is a cell signal 112, which is a signal line for inserting and outputting a test cell generated by the test cell generation circuit 100 to a transmission path of the cell.

The detailed configuration of the data generator 300 will be described with reference to FIG. The data generation unit 300 includes eight selectors 310 to 317 and eight D flip-flops (FF).
318-325, three exclusive OR gates (EXO
R) 326 to 328, and a serial / parallel conversion circuit (SP) 330. CLK102 is a common clock of the D flip-flops (FF) 318 to 325 and the serial / parallel conversion circuit (SP) 330. L
The OAD 108 is a control signal connected to each of the selectors 310 to 317. The initial value 101 is the D flip-flop (FF) 318 to 325 connected to
This is an 8-parallel signal that gives an initial value to the flip-flop. Initial values are given to the D flip-flops (FF) 318 to 325 in the order from the LSB bit of the initial value 101 to the MSB bit. CLK 103 is a clock and is input to the serial / parallel conversion circuit (SP) 330. ENB 107 is a control signal output from control unit 400 in FIG. 329 is the output of FF7, EX
The signals are input to ORs 326 to 328 and selector 310, respectively. 331 is an SP33 composed of 8 parallel signals.
0 output.

(1-2) Operation Next, the operation of the test cell generation circuit 100 having such a configuration will be described with reference to FIG. FIG. 2 shows how a test cell generated by the test cell generation circuit 100 is inserted into a cell transmission line (cell signal 104) in the ATM device.

The header generator 200, data generator 300, and controller 400 shown in FIG. 1 operate in synchronization with CLK103. CLK103 is, for example, 155.52 Mb.
When performing 8-parallel transmission in a device having a transmission rate of / s, the frequency is about 20 MHz. The activation signal 105 is
This is a start signal for starting test cell generation in the test cell generation circuit 100. The control unit 400 recognizes that the activation signal 105 is valid (L level), and makes the control signal to each block valid (L level). Control signals generated by the control unit 400 include ENB106, ENB107, L
OAD108, selector signal 111, ENB10
7, LOAD 108 will be described later. Start signal 10
The phase relationship between 5 and ENB 106 is the relationship shown in FIG.

When ENB 106 is enabled (L level), header generation unit 200 and data generation unit 30
0 generates a cell header of 5 bytes and a payload of 48 bytes, respectively. At this time, the cell header generated by the header generation unit 200 is a header for specifying a test cell in the ATM communication device. As mentioned in the previous example,
The specific bit may be assigned for test cell identification, or may be a bit pattern that can be specified as a test cell in the entire header. ENB106, 5 bytes of cell header (1
09), the phase relationship of the payload 48 bytes (110) is as shown in FIG.

The selector signal 111 is transmitted to the header generator 20
0, an output 110 of the data generation unit, and a signal for selecting the cell signal 104. As shown in FIG. 2, a cell signal selection period, a header generation unit output selection period, and a data generation unit There are three states of the output selection period.
The cell signal 104 is selected during the cell signal selection period, the cell header 5 bytes output via 109 is selected during the header generation unit output selection period, and the cell header 104 is output via 110 during the data generation unit output selection period. By selecting 48 bytes of payload, a test cell is inserted into the cell signal 104 and output from the cell signal 104. The phase relationship of each signal is shown in FIG.
It becomes like.

Next, the operation of the data generator 300 will be described with reference to FIGS.

FFs (318 to 325) in FIG. 3, EXOR
The circuit composed of (326 to 328) is a primitive polynomial X
⁸ + X ⁶ + X + 1 is known as an M-sequence generation circuit. In general, an output when a non-zero initial value is given to a linear feedback shift register connected according to a primitive polynomial is a bit string having the longest period that can be generated by shift registers of the same number of stages. This is converted into a maximum long-period sequence (max
imum lengthsequence), M for short
It is called a sequence (M-sequence). Primitive polynomial X ⁸
FIG. 5 shows an M-sequence generating circuit of + X ⁶ + X + 1. 10
Reference numeral 17 denotes a D flip-flop circuit. 18-20
Means an exclusive OR gate (EXOR) as shown in FIG. The output 21 of the D flip-flop 17 is used as the input of the D flip-flop 10, and the signal obtained by taking the exclusive OR of the output of the D flip-flop 14 and the output 21 is used as the input of the D flip-flop 15.
A signal obtained by performing an exclusive OR operation between the output of the flip-flop 15 and the output 21 is set as the input of the D flip-flop 16. At this time, if the initial values of the D flip-flops 10 to 17 are “all other than 0”, a shift operation is performed in the direction from the D flip-flop 10 to the D flip-flop 17 so that a random output is output to the output 21 of the D flip-flop 17. "
5 can be output. For example, the initial values of the D flip-flops 10 to 17 in FIG.
When 0 = "1" and C2-7 = "0", a data string as shown in FIG. 6 is obtained.

The circuit shown in FIG. 3 has selectors arranged at the inputs of the D flip-flops 10 to 17 in FIG. 5 so that an arbitrary initial value can be set. In FIG. 3, the number of D flip-flops is eight, and except for the case where the D flip-flops are “all 0”, 2 ⁸ −1 = 255 initial values can be set. This means that 255 bit strings can be generated. When the LOAD 108 is valid (L level), the initial value is an initial value 101 which is an 8-parallel signal.
Are set in the D flip-flops 318 to 325 one by one in order from the LSB bit to the MSB bit.

The shift operation of D flip-flops 318 to 325 is performed when ENB 107 is valid (L level).

LOAD 108 and ENB 107 are signals generated by the control unit 400 in FIG. 1 and are signals synchronized with CLK 102. The phase relationship is as shown in FIG.

When LOAD 108 is valid, the initial value signal 1
01, 1, 0, 0, 0, 0,
When 0, 0, 0 are set in the D flip-flops 318 to 325, and the output of the ENB 107 during the L level period is made valid, the output 329 of the FF 7 (325) in the valid period becomes
It is as shown in FIG. The cell payload is 48 bytes,
That is, it is composed of a total of 48 × 8 = 384 bit strings. Therefore, the D flip-flops 318 to 325
Performs the shift operation 384 times to obtain the output 32
9, it is possible to obtain a payload for one cell.
FIG. 4 shows FF7 (325). Note that E
The NB 107 becomes invalid (H level) when the shift operation for one cell is completed.

Since the bit width of the cell transmission path in the ATM communication device is 8 parallel, the output 3 of the FF 7 (325)
29 is 8 in the serial / parallel converter (SP) 330
Converted to parallel. Every eight clocks at CLK102, the data serving as the cell payload is converted into eight parallel data. FIG. 4 shows the output 329 of the FF7 (325).
Shows the internal state of the SP 330 when converting to 8 parallel.

The data converted to 8 parallel is SP33
At 0, it is latched by CLK103. This is because the cell in the ATM communication device is CL
This is because K103 is used as the transmission clock. FIG. 4 shows the output of SP 330, that is, data generation unit 300.
Shows the output 331 of the payload of the cell generated in.

Next, the present invention is applied to a PCB in an ATM communication device.
The operation when applied to functional blocks inside the board and the LSI will be described with reference to FIG.

The test system inputs a test cell by the test cell generator 602 to the cell transmission path 601 inside the LSI 600,
After passing through the function block 603 inside the LSI 600, the function block 801 on the PCB board, and the function block 701 inside the LSI 700, a test cell header detection unit 702 inside the LSI 700 detects a test cell.

Upon detecting a test cell, the test cell header detector 702 notifies the test cell generator 703 of the fact and starts generating test cells. At this time, the test cell generator 6
It is necessary to set the same initial value to the data generation unit 02 and the data generation unit of the test cell generation unit 703. The comparing section 706 compares the payload of the test cell transmitted on the cell transmission path with the payload of the cell generated by the test cell generating section 703.
To compare. If there is a mismatch in the cell ’s payload,
From 706, a failure is notified to a higher order.

On the other hand, if the test cell generated by the test cell generation unit 602 is determined to be normal by the coincidence determination of the comparison unit 706, the functional connection between the functional blocks and the PC
It can be determined that the mounting of the LSI on the B board is performed normally.

In the coincidence judgment of the test cells, not only the complete coincidence of the codes of the payload but also the bit error rate and the like are measured, and the coincidence judgment is made by setting a threshold value according to the communication quality required for the test section. It is also possible.

(1-3) Effects of the Embodiment As described above, according to the test cell generation circuit of the present embodiment, a test cell having a payload portion having a random bit pattern is generated, and cell transmission within the device is performed. Test cells can be inserted into the path. By mounting an M-sequence code in the payload of the test cell, failures other than errors in the test cell identification bits in the header can be detected, and even if the communication capacity or function of the device increases, a highly reliable continuity test Can be implemented. In addition, since a selector circuit is provided at a stage preceding the D flip-flop and an arbitrary initial value can be set, it is possible to generate several types of payload patterns.

(2) Second Embodiment (2-1) Circuit Configuration FIG. 10 shows the configuration of a data generator according to this embodiment.
In FIG. 10, the same and corresponding parts as those in FIGS. 1 and 3 are denoted by the same reference numerals and corresponding reference numerals.

The data generator in the first embodiment comprises:
The configuration requires eight clocks to obtain 1-byte data, and replaces the transmission clock of the cell. This means that data generation requires eight times the clock of the cell transmission clock.

Assuming that the transmission clock of the cell is 20 MHz, the clock of the data generation unit is 160 MHz, which requires a high-speed clock. On the other hand, when the serial / parallel conversion means is not provided and the serial data generation means is provided for each bit of the 8-parallel cell transmission line, data can be generated at the same speed as the transmission clock of the cell.
The amount of hardware is increased about eight times.

In the second embodiment, a description will be given of a data generator which operates at the same speed as the transmission clock of a cell and has a configuration in which an increase in hardware is minimized.

The data generation unit 300 includes eight selectors 3
50 to 357, 16 D flip-flops (FF0 to FF0)
15) It comprises 360 to 375, a logic unit 340, and a logic unit 380.

Reference numeral 103 denotes a clock common to the cell transmission clock. LOAD108 is FF0 to FF7 (3
60 to 367) to give an initial value.
It is input to selectors 350-357. FF0-FF
The initial value for 7 is given by the initial value 101. EN
B107 is a signal for permitting the data generation unit 300 to generate data. From 110-0 to 110-7, the data generation unit 30
The 8-parallel data generated by 0 is output. 110
−0 becomes the LSB bit, and 110-7 becomes the MSB bit.

In the second embodiment, the CLK 102 shown in FIG.
Does not require. The LO generated by the control unit in FIG.
AD108 and ENB107 are C which is a cell transmission clock.
This signal is synchronized with LK103.

(2-2) Operation Next, the operation of the test cell generation circuit having such a configuration will be described. The data generation unit shown in FIG. 3 has a configuration in which one byte of data is obtained every eight clocks. In the configuration of FIG. 10, one-byte data can be obtained in one clock. The principle will be described below.

It is assumed that the initial values of the D flip-flops of the M-sequence generation circuit used in the data generator of FIG. 3 are as shown in FIG. From this state, the state of each D flip-flop after 1 CLK is as shown in FIG. From this state, the state after one clock, that is, the state of the D flip-flop two clocks after the initial state is as shown in FIG. Similarly, the state of each D flip-flop from three clocks to seven clocks after the initial state is as shown in FIGS. Note that “＾” in FIGS. 11 to 18 means exclusive OR. Although the formula is simplified in the middle of calculation, it follows the rule as shown in FIG.

The circuit shown in FIG. 5 can take out one byte of data serially in 8-clock units from the MSB bit. Therefore, the state of the D flip-flop at the last stage (rightmost) from the initial state to after 7 clocks becomes the MSB bit in FIG. 5 and becomes 17 in FIG. 11 and 1 in FIG.
7, 17 of FIG. 13, 17 of FIG. 14, 17 of FIG. 15, FIG.
In the order of 17 in FIG. 6, finally, 17 in FIG. 17 becomes the LSB bit, and 8 bits are extracted.

The logic section 380 in FIG. 10 is a functional block for calculating these states. The state of the last stage of the D flip-flop from the initial state to after seven clocks is calculated, and the calculation result is used as eight D flip-flops 368 to 368.
375 respectively. The result is 110-0 to 7
Output.

According to the above procedure, the data of 8 bits in the initial state of FIG. 5, that is, the data of 1 byte of the cell can be processed in parallel. In order to process the next eight bits of data in parallel, it is necessary to find a state next to the initial state in FIG. The state may be obtained by the state after eight clocks of the D flip-flops 10 to 17 in FIG. The state after eight clocks of the D flip-flops 10 to 17 in FIG. 5 is as shown in 10 to 17 in FIG.

The logic section 340 in FIG. 10 is a block for obtaining the states 10 to 17 in FIG. 18 described above.
The result obtained by the logic unit 340 is set in each of the D flip-flops 360 to 367.

The state transition from the initial state of the D flip-flops 360 to 367 is obtained by the logic unit 1, and based on this, the logic unit 380 outputs the output 11 of the data generation unit 300.
0-0 to 7 can be obtained.

In the first embodiment, 8-parallel data is obtained by serial-to-parallel conversion of serial data. On the other hand, the second embodiment converts 8-parallel data in parallel by the above-described method. It is possible to ask for.

FIG. 19 is a time chart of the data generator 300 shown in FIG.

(2-3) Effects of the Embodiment By adopting the circuit configuration of FIG. 10 in the data generation unit 300 of FIG. 1, serial-parallel conversion means is not required, and
It is possible to generate parallel data. Also,
The clock of the data generator can be shared with the transmission clock of the cell. Compared with the first embodiment, it is possible to suppress an increase in the amount of hardware without requiring a serial-parallel conversion unit.

(3) Other Embodiments In the first and second embodiments, the bus width of the cell transmission path in the ATM device is set to 8 parallel, and the data generation unit is an M-sequence of primitive polynomial X ⁸ + X ⁶ + X + 1. It was constructed based on the generating circuit. This is because the circuit based on the above polynomial has a high affinity for the 8-parallel bus, particularly when performing 8-parallel parallel processing as in the second embodiment.
However, this is merely an example, and the configuration of the M-sequence generation circuit can be changed to X ⁴ + X + 1 or X ¹⁶ + X ⁵ + X ³ + X ² +1 depending on the bus width of the cell transmission line in the ATM device.

[0051]

According to the present invention, the random bit pattern generated by the M-sequence generation circuit is mounted on the payload of the test cell. Therefore, even if a transmission error occurs in bits other than the test cell explicit bit, The continuity of the device can be confirmed without providing a complicated synchronization circuit between the functional blocks to be tested. In addition, since the data generation unit has a parallel processing circuit configuration, the time required for generating test data can be significantly reduced. Furthermore, since the initial value of the input of the delay circuit constituting the M-sequence generation circuit can be arbitrarily selected, it is possible to easily generate different test data patterns.

[Brief description of the drawings]

FIG. 1 is a block diagram of a test cell generator of a first embodiment.

FIG. 2 is a time chart illustrating an operation of a test cell generation unit according to the first embodiment.

FIG. 3 is a block diagram of a data generation unit according to the first embodiment.

FIG. 4 is a time chart illustrating an operation of the data generation unit according to the first embodiment.

FIG. 5 is a block diagram of an M-sequence generation circuit of the data generation unit according to the first embodiment.

FIG. 6 is a diagram illustrating an output example of M-sequence data according to the first embodiment.

FIG. 7 is a diagram illustrating an exclusive OR gate according to the first embodiment;

FIG. 8 is a diagram illustrating an exclusive OR gate used in the operation of the M-sequence generation circuit according to the second embodiment.

FIG. 9 is a diagram showing a test form of a continuity test.

FIG. 10 is a block diagram of a data generation unit according to the second embodiment.

FIG. 11 is a diagram illustrating an operation state of the data generation unit according to the second embodiment after one clock.

FIG. 12 is a diagram illustrating an operation state of the data generation unit according to the second embodiment after two clocks.

FIG. 13 is a diagram illustrating an operation state of the data generation unit according to the second embodiment after three clocks.

FIG. 14 is a diagram illustrating an operation state of the data generation unit according to the second embodiment after four clocks.

FIG. 15 is a diagram illustrating an operation state of the data generation unit according to the second embodiment after five clocks.

FIG. 16 is a diagram illustrating an operation state of the data generation unit according to the second embodiment after six clocks.

FIG. 17 is a diagram illustrating an operation state after seven clocks of the data generation unit according to the second embodiment.

FIG. 18 is a diagram illustrating an operation state of the data generation unit according to the second embodiment after eight clocks.

FIG. 19 is a time chart illustrating the operation of the data generation unit according to the second embodiment.

[Explanation of symbols]

100: Test cell generator, 200: Header generator, 30
0: data generator, 400: controller, 500: SEL,
101: initial value, 102: CLK1, 103: CLK
1, 104: cell signal, 105: activation signal, 106: E
NB1, 107: ENB2, 108: LOAD, 112
... cell signal.

Claims (6)

[Claims] A header generation unit for generating a test cell header; a data generation unit for generating test data of a payload of the test cell; a test cell header generated by the header generation unit; and a data generation unit generating the test cell header. A test cell generation circuit, comprising: a selector that inserts the obtained test data into a cell signal; and a control unit that controls the generation timing of the test cell and the timing of insertion into the cell signal. 2. The test cell generation circuit according to claim 1, wherein said data generation section comprises an M-sequence generation circuit. 3. The test cell generation circuit according to claim 2, wherein a selector is provided at an input of the delay circuit of the M-sequence generation circuit to set an initial value. 4. A test data generation circuit for generating test data in N-bit units from a parallel input of N bits (N: a positive integer), wherein N is an integer from the initial state of each delay circuit constituting the M-sequence generation circuit.
A test comprising: a first logic unit for obtaining an output after a clock; and a second logic unit for obtaining an output of the last stage of the delay circuit for each clock from an initial state to after N-1 clocks. Data generation circuit. 5. A selector for switching between an output and an initial value of each delay circuit constituting the M-sequence generation circuit of the first logic section and inputting the output to the first and second logic sections. The test data generation circuit according to claim 4, wherein 6. The test data generation circuit according to claim 4, wherein an output of the selector and an output of the second logic unit are output in synchronization with a clock same as a transmission clock.