JP2002279007A - Method for synthesizing logic - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logic synthesizing method for improving area reduction and a signal value propagation speed by reducing the number of cells of a logic circuit that is subjected to cell mapping by logic synthesis. SOLUTION: An actual cell and a pseudo model cell are prepared in a cell library for mapping to be a cell mapping object, the logic circuit is subjected to logic optimization and cell mapping by using the cell library for mapping, and a pseudo model cell subjected to cell mapping is converted into an actual cell that is logically equivalent to the pseudo model cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit designed in a hardware description language or the like, using a mapping cell library composed of cell information to be mapped.
The present invention relates to logic synthesis that performs logic optimization to perform cell mapping, and more particularly to a logic synthesis method suitable for reducing the area of a circuit after logic synthesis and improving the signal value propagation speed in the circuit.

[0002]

2. Description of the Related Art In designing a logic circuit such as an integrated circuit,
Logic operations and data flows are described exclusively using a hardware description language. These descriptions are subjected to logic optimization by a logic synthesizer, and are mapped to technology cells to generate gate-level circuits. The cells for mapping are cells with basic operations such as product and sum, and functions combining basic operations so that logical operations expressed in a hardware description language are also realized in gate-level circuits. A composite cell to be realized is provided. Also, even for the same operation, cells with different electrical characteristics and cells with different areas are prepared. ing.

[0003]

The logic operation expressed in a hardware description language is optimized by a logic synthesizer to perform logic optimization and cell mapping. This mapping process conforms to the logical operation expression. Thus, the cell is selected from the mapping cell library. However, in the mapping cell library, not all of the logical operation expressions can be matched by cell-level functions,
Mapping is performed using a combination of a basic cell and a composite cell. A logic circuit mapped by such a combination or the like cannot satisfy the area restriction or the restriction on the signal value propagation speed in the circuit. To compensate for this, if cell design is performed so that all of the logical operation expressions match at the cell-level function, the number of cell types will increase, and a longer cell design period is expected.

An object of the present invention is to provide a logic synthesis method that reduces the area of a logic circuit obtained after logic synthesis without increasing the cell design period and improves the signal value propagation speed.

[0005]

In order to solve the above problem, a pseudo cell logically equivalent to a real cell is created and added to a mapping cell library to be subjected to cell mapping, and this pseudo cell is also subjected to optimization processing. The number of cells that match the logical operation expression is increased, and the number of cells after mapping is reduced.

[0006]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart in which processing for realizing the present invention is added to the processing flow of the logic synthesis apparatus. The flow of the logic synthesis process is performed by using a mapping cell library indicated by 102 for logic circuit data whose function is described in a hardware description language 101 or the like in FIG.
Logic optimization and cell mapping are performed by a logic synthesis process shown at 104, and a gate-level logic circuit shown at 106 is generated. The present invention adds a pseudo model cell indicated by 103 which is logically equivalent to an existing cell indicated by 102 to the mapping cell library indicated by 102 as a mapping cell, thereby optimizing the logic indicated by 104 and cell mapping. More cell selection menus and improve optimization.

However, at this time, since the pseudo model cell is also used in the circuit after the logic synthesis, the portion where the pseudo model cell is mapped as shown by 105 is converted into a logically equivalent real cell, and Is output as a logic circuit after the synthesis. FIG. 2 shows an example of a real cell model of the mapping cell library indicated by reference numeral 102 in FIG. FIG. 3 shows an example of a model of a pseudo model cell indicated by reference numeral 103 in FIG. FIG. 4 shows a circuit diagram before logic synthesis in which a logic design corresponding to 101 in FIG. 1 is made.

FIG. 5 is a circuit diagram showing the result of logical synthesis of only real cells when the present invention is not used. FIG. 6 is a circuit diagram showing the result of logic synthesis using both the real cell and the pseudo cell as mapping targets using the present invention.

FIG. 7 is a circuit diagram after the pseudo cell mapped by the logic synthesis shown by 105 in FIG. 1 is replaced with a real cell.

Next, according to the processing flow shown in FIG.
The details of the logic synthesis method according to one embodiment of the present invention will be described with reference to FIG.

First, as a preparation for logic synthesis, a library for mapping is prepared. In the present embodiment, a flip-flop will be described as an example of a cell to be mapped.
As the flip-flop cell to be mapped, FIG.
When the positive flip-flop 201 and the negative flip-flop 202 indicated by are prepared, a pseudo cell logically equivalent to these is created. A pseudo cell modeled as 301 in FIG. 3 is prepared as a cell equivalent to 201 in FIG. The pseudo cell 301 has a data input P1
And the D of the negative polarity flip-flop indicated by 303
This is a model in which an inverter indicated by 302 is inserted between the two. In addition, as the name of the pseudo model, a name obtained by adding “_N” to the name of a logically equivalent real cell is used. 201
In the case of “FF1” indicated by, “FF1_N” indicated by 301
It will be named.

Similarly, as a cell equivalent to 202 in FIG.
A pseudo cell indicated by 304 in FIG. 3 is prepared.

Next, in the logic synthesis processing, when a logic circuit as shown in FIG. 4 is designed and is subjected to logic synthesis, a logic cell is used as a mapping cell library only with the real cells shown in FIG. When combined, 401 and 40 in FIG.
2 and 403 combine the respective functions to form a logical aggregate and select cells corresponding to the logical aggregate. However, from the selection range in FIG. 2, 402 and 40 in FIG.
With the combination of 3, 202 in FIG. 2 is selected and 5 in FIG.
A mapping result represented by 02 is obtained. Also, 405 in FIG.
Is selected as 201 in FIG. 2 and becomes a mapping result represented by 504 in FIG. As a result of this logic synthesis, 40 in FIG.
The cell mapping for the logical expressions indicated by 1 and 404 simply results in the remaining inverters as indicated by 501 and 503 in FIG. The number of cells mapped as shown in FIG. 5 is 501/502/503/504, which means that a circuit composed of four cells has been generated.

Therefore, by adding the logic-equivalent pseudo cell shown in FIG. 3 to the real cell shown in FIG. 2 as a mapping target and logically synthesizing the logic design circuit shown in FIG.
When the combination of the functions 402, 403, and 403 is viewed as one logical aggregate, the pseudo cell 301 shown in FIG. 3 can be selected. Also, 404 and 405 in FIG.
3 can be selected as one logical aggregate. The result of the logic synthesis is the circuit shown in FIG.

However, since the circuit diagram shown in FIG. 6 is still mapped to the pseudo cell, it must be replaced with a real cell. Originally, when creating a pseudo cell, it is prepared with a name with “_N” added as a logical equivalent to a real cell, and this is mapped,
The circuit name after the synthesis is searched for a cell name with “_N” in the cell name, and “_N” is deleted. That is, FIG.
601 will be replaced with 201 in FIG. 2 which is logically equivalent. Similarly, 602 in FIG. 6 is replaced with 202 in FIG. 2, and the circuit shown in FIG. 7 can be obtained. As shown in FIG. 7, there are two cells, 701/702, and a circuit composed of two cells can be generated. Assuming that only the real cells are included in the mapping cell library, the number of cells can be reduced by two as compared with the circuit of FIG.

[0016]

As described above, according to the present invention, in mapping cells by logic synthesis, the number of cells after logic synthesis is reduced, the area of the generated logic circuit is reduced, and signal value propagation is performed. There is an effect that the speed can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing the overall processing of the present invention.

FIG. 2 is a model of a real cell used in cell mapping of logic synthesis.

FIG. 3 is a model of a pseudo cell which is logically equivalent to a real cell used in cell mapping of logic synthesis.

FIG. 4 is a circuit diagram of a logic designed as an input of the logic synthesis.

FIG. 5 is a circuit diagram showing a result of logic synthesis of a real cell as a mapping target;

FIG. 6 is a circuit diagram showing a result of logic synthesis of a pseudo cell added to a mapping target;

FIG. 7 is a circuit diagram after a circuit constituted by a pseudo cell is replaced with a real cell.

[Explanation of symbols]

102 Cell Library for Mapping (Real Cell) 103 Cell Library for Mapping (Pseudo Model Cell) 201 Real Cell 202 Real Cell 301 Pseudo Model Cell 304 Pseudo Model Cell 601 Pseudo Model Cell 602 Pseudo Model Cell

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuhiko Minohara 1 Horiyamashita, Hadano City, Kanagawa Prefecture Inside Nichi Information Technology Co., Ltd. (72) Inventor Yoichi Kumai 1 Horiyamashita, Hadano City, Kanagawa Prefecture Nichi Information Technology Co., Ltd. F-term (reference) 5B046 AA08 BA03 KA06

Claims (2)

[Claims] 1. A logic synthesis method for performing logic optimization of a logic circuit logically described by a hardware description language to map cells, wherein real cells and pseudo model cells are stored in a mapping cell library to be subjected to cell mapping. A logic synthesis method comprising preparing, performing logic optimization and cell mapping of a logic circuit using the mapping cell library, and converting the cell-mapped pseudo model cell into a logically equivalent real cell. 2. The logic synthesis method according to claim 1, wherein a cell name to which a code for distinguishing the pseudo model cell from a real cell is added is prepared.