JP2002271287A - Channel-multiplexing transmission system and transmission system and reception system thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable time division multiplexing transmission, without adding changes, as much as possible in an existent packet communication system. SOLUTION: An n-channel (n: an integer of 2 or more) input data string is multiplexed in time division by a time division multiplexing means 21, its multiplexed output is divided into blocks by a transmission interface conversion means 22, and each block is packed to a packet by a packet transmitter 23 and transmitted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital multiplex transmission system, and a transmission system and a reception system used therein.

[0002]

2. Description of the Related Art Japanese Patent Publication No. 268481 discloses a conventional example.
A multiplex transmission system assumed in No. 5 “Digital multiplex transmission system” is shown in FIGS. 1 and 2 and briefly described. Figure 1
Shows the configuration of a conventional time division multiplex transmission apparatus. FIG.
Are the interfaces IF21, IF22, IF3, IF4, IF5
1, the data stream flowing through IF52 is multiplexed as input data stream M
ID1, MID2, multiplexed output data sequence MOD, demultiplexed input data sequence DMID, and demultiplexed output data sequence DMOD1, DMOD2. In FIG. 2, each minimum unit square represents one bit, and 10
The bold rectangle surrounding the bits represents a 10-bit word. Each bit is transmitted sequentially from the left.

The transmitting node 10TN encodes the input data strings ID1 and ID2 of the two channels by 8B / 10B encoding by the 8B / 10B encoding means 111 and 112, converts them into multiplexed input data strings MID1 and MID2, and further multiplexes. Time-division multiplexing by means 12;
The multiplexed output data MOD is transmitted from the transmission device 13 as one serial data transmission signal. 8B / 10B is characterized by converting 8-bit data into a 10-bit code. Although the transmission speed is 1.25 (= 10/8) times, it has excellent code characteristics such as DC-free characteristics. The 8B / 10B code is described in detail in Japanese Patent Laid-Open Publication No. Sho 59-10056, "Code Generation Method", but will be briefly described in the embodiments. Note that each bold rectangle in FIG. 2 corresponds to one 8B / 10B code.

[0004] The receiving node 10RN receives one serial data reception signal by the receiving device 14, and generates a demultiplexed input data sequence.
Output as DMID to the demultiplexing input interface IF4. This demultiplexing input data sequence DMID is transmitted to the demultiplexing means 1
5, demultiplexed into 2 channels of 8B / 10B word strings,
Output to the desired demultiplexing output interfaces IF51 and IF52 as demultiplexing output data strings DMOD1 and DMOD2,
8B / 10B decoding means 161 and 162 provide two-channel data OD1,
It is decoded to OD2 and output to interfaces IF61 and IF62. A regenerative repeater (not shown) is inserted into the transmission path TL between the transmitting and receiving nodes according to the signal deterioration.

[0005]

In the case of multiplexing and transmitting n = 2 or more n-channel input data strings using the above-mentioned conventional technique, a high-speed transmission / reception device 13, 14 or a regenerative relay inserted between transmission / reception nodes. Need to redesign the vessel,
There is a problem that development costs increase. Further, there is a problem that the transmission speed before multiplexing and the transmission speed of the transmission signal transmitted from the transmission device 13 are restricted to an integral multiple of n. The present invention has been made to solve such a problem, and an object of the present invention is to reduce development costs and enable flexible setting of a transmission rate before multiplexing.

[0006]

According to the first aspect of the present invention, there is provided a multiplex transmission system for transmitting an input data sequence of n channels (n is an integer of 2 or more) from a transmission node to a reception node. A time-division multiplexing means 21 for time-division multiplexing the input data sequence of the above, and outputting the multiplexed output data sequence to the multiplex output interface IF3 as a multiplexed output data sequence; A transmission system is constituted by a transmission interface conversion unit 22 that outputs a packet transmission device interface data sequence to the transmission device interface IF4 and a packet transmission device 23 that transmits the packet transmission device interface data sequence.

According to a second aspect of the present invention, in the first aspect, each of the n-channel input data strings has a clock correction means for correcting a difference in clock frequency. According to a third aspect of the present invention, in the first or second aspect, the n-channel input data sequence is an 8B / 10B word sequence, and the 8B / 10B
Means for decoding the word string is provided. The invention of claim 4 is
4. The block according to claim 1, wherein the block has a size such that any word boundary of the input data string always exists at a specific bit position in the block.

According to a fifth aspect of the present invention, in any one of the first to fourth aspects, the block size is an integral multiple of a channel multiplexing period. The invention of claim 6 is the invention of claims 1 to 5
In any one of the above, the transmission interface conversion means 22, according to the difference between the multiplex output interface and the data transmission speed of the packet transmission device interface,
Means for inserting and removing idles between the packets. According to a seventh aspect of the present invention, in any one of the first to sixth aspects,
The packet transmission device interface is a 10 Gigabit Ethernet transmission device interface.

The invention according to claim 8 is the communication device according to any one of claims 1 to 6, wherein the packet transmission device interface IF
4 is a gigabit Ethernet transceiver interface. According to a ninth aspect of the present invention, there is provided a packet receiving device which receives a transmission data sequence of the multiplex transmission system according to the first aspect and outputs a packet receiving device interface data sequence to a packet receiving interface IF7; A receiving interface converting means for extracting a packet from the data sequence, combining respective blocks included in the packet sequentially obtained to generate a demultiplexed input data sequence, and converting the demultiplexed input data sequence to a desired channel; And a demultiplexing unit 26 for performing division and demultiplexing.

[0010] According to a tenth aspect of the present invention, in the ninth aspect,
The packet receiving interface IF7 is a 10 Gigabit Ethernet receiving device interface. Claim 11
In the ninth aspect of the present invention, in the ninth aspect, the packet receiving interface IF7 is a gigabit Ethernet receiving device interface. A multiplex transmission system according to a twelfth aspect of the present invention includes a transmission system according to the first aspect and a reception system according to the ninth aspect.

According to the action present invention, the input data string of n-channel when multiplexing and transmitting, by the use of the existing packet transceiver stores the multiplexed signal into packets, the reception apparatus and regenerator There is no need for new development, and development costs can be reduced. Furthermore, even if the transmission speeds of the multiplex channel and the packet transmission / reception device do not have a relationship of an integral multiple of each other, the difference in transmission speed can be absorbed by the presence or absence of a packet, so that a flexible multiplex transmission system can be constructed.

[0012]

FIG. 3 is a block diagram showing the principle of the present invention. According to the present invention, input data strings ID1 to IDn of n channels (n is an integer of 2 or more) are transmitted from the transmission node 20TN to the reception node.
In the multiplex transmission system for transmitting to the 20RN, the transmission system constituting the transmission node 20TN performs time division multiplexing of the n-channel input data strings ID1 to IDn and outputs the multiplexed output data stream MOD to the multiplex output interface IF3. The division multiplexing means 21 sequentially divides the multiplexed output data sequence MOD into blocks having a predetermined block length, and adds predetermined information to each of the blocks to form packet data PD. The transmission interface conversion means 22 outputs the packet PD to the packet transmission device interface IF4, and the packet transmission device 23 transmits the packet PD. Further, the receiving system constituting the receiving node 20RN receives a packet from the transmission line TL, outputs the packet to the interface IF7 as packet data PD, and deletes additional information from the packet data PD to form a block sequence, Receiving interface converting means 2 for further converting the data into a multiplexed data string MOD of one series
5 and multiplexing / demultiplexing means 26 for demultiplexing the multiplexed data string MOD to obtain n-channel output data strings OD1 to ODn.

An embodiment of the present invention will be described below with reference to FIGS. In the present specification, the channel multiplexing cycle is defined as an arbitrary bit included in a data sequence obtained by time-division multiplexing an n-channel input data sequence from a channel to which the bit belongs and a bit next to the bit. Starting from the natural number τ, the channel to which the bit belongs after is always the smallest τ among the natural numbers τ. First Embodiment FIGS. 4 and 5 relate to a first embodiment of the present invention. A feature of the present invention is to use an existing packet transmission device by storing a multiplexed signal in a packet when multiplexing and transmitting an n-channel input data sequence. FIG.
FIG. 1 is a configuration diagram of a communication system that multiplexes and transmits an input data sequence of two channels.

The transmitting system constituting the transmitting node 20TN is a multiplexing means for multiplexing the input data strings ID1 and ID2 of two channels.
1 to generate a series of data by bit multiplexing and transmit the multiplexed output data sequence MOD to the transmission interface converting means 2.
2, the packet PD is divided into blocks each having a predetermined length, and the packet PD is transmitted by the existing packet transmitting device 23 for each packet. In the first embodiment, since no information is given to each block, the contents of each packet and the corresponding block are the same. The receiving system that constitutes the receiving node 20RN includes a packet PD sequentially received by the packet receiving device 24.
Are combined by the receiving interface converting means 25 and demultiplexed by the demultiplexing means 26.
OD1 and OD2 are output to the respective channel interfaces IF91 and IF92.

Next, a detailed description will be given while showing the flow of a data string. FIG. 5 shows each interface IF11, IF in FIG.
12, IF3, IF4, IF7, IF8, IF91, IF92, multiplexed input data sequence ID1, ID2, multiplexed output data sequence MO
D, the packet transmitting device interface data sequence PD, the packet receiving device interface data sequence PD, the demultiplexing input data sequence DMOD, and the demultiplexing output data sequences OD1 and OD2,
Shown respectively. In FIG. 5, the minimum unit square represents one bit, and the thick rectangle surrounding three bits represents one word.
Each bit is transmitted sequentially from the left. Multiple input data string ID
1 and ID2 are output as a multiplexed output data string MOD by the multiplexing means 21 and are divided into 6-bit blocks by the transmission interface converting means 22, and each block is transmitted as a packet from the packet transmitting apparatus 23.

The receiving node 20RN performs the reverse process of the transmitting node 20TN. The blocks included in the received packet interface data sequence PD are combined by the reception interface conversion means 25, the demultiplexed input data sequence DMOD is output, and the demultiplexed data is demultiplexed by the demultiplexing means 26 to demultiplex into the desired channels IF91 and IF92. Output data string
Output as OD1, OD2. At this time, since the block length of 6 bits is an integral multiple of the channel multiplexing period of 2 bits, the channel can be identified by the bit position in the block. That is, assuming that m = 1, 2, 3, the 2m-1st bit of each block is, for example, the data of the channel IF11.
The second bit is the data of channel IF12. Further, since the 3-bit word boundary in each block is also fixed between the third and fourth bits from the head of the block, the word boundary can be identified from the bit position, so that word synchronization means for the received signal is unnecessary.

As described above, the existing packet transmitting / receiving apparatus can be used by converting the multiplexed signal into the existing packet transmitting apparatus interface data string PD. Even if the transmission speeds of the multiplex channel and the packet transmission / reception device are not an integer ratio, the difference in transmission speed can be absorbed by the presence or absence of a transmission packet, so that a flexible multiplex transmission system can be constructed. In the first embodiment, an example is shown in which an input data sequence of two channels is multiplexed, but the same applies to n channels. In the first embodiment, each block has a fixed length of 6 bits, but may have a variable length within the range of the specifications of the packet transmission device. In the first embodiment, the block length is determined so that the word boundary always coincides with the specific position of the block, and there is an advantage that the word synchronization means is unnecessary. However, the word synchronization is unnecessary or the word synchronization means is not required. May be provided in another block length. Further, in the first embodiment, there is an advantage that the channel can be identified by the bit position in the block by setting the block length to an integral multiple of the channel multiplexing period. Need not be limited to this. Second Embodiment In a second embodiment of the present invention, an example is shown in which a 7-channel Gigabit Ethernet input data sequence is multiplexed and transmitted using a 10 Gigabit Ethernet transceiver. A feature of the second embodiment of the present invention is that a clock frequency and a phase shift of a 7-channel Gigabit Ethernet input data sequence are corrected by a clock correction function of the input data sequence, and then multiplexed. Is to transmit by a 10 Gigabit Ethernet transceiver which is expected to be inexpensive.

First, an overview of 10 Gigabit Ethernet standardization technology and Gigabit Ethernet related to the second embodiment will be described, and then the description will be shifted to the second embodiment. Ten
As for Gigabit Ethernet, the following three points are mainly described. (1) MAC frame format (2) Layer 1-2 interface (3) Word synchronization technology (transmission line coding technology) FIG. 6 is a layer diagram of a 10 Gigabit Ethernet currently being standardized. Describe the data flow briefly. 10 Gigabit Ethernet uses MAC (Media Access
Control) Layer 22A (Literature: Multimedia Communication Study Group, `` Point Illustrated Gigabit Ethernet Textbook '', ISBN 4-7561
-3037-2), the transmission data is stored in the MAC frame, and then, the arbitration sublayer 22B (RS: Reconciliation Sublayer)
Inter-frame signals (idle signals, etc.) are inserted between frames, and 10 Gigabit medium-independent interfaces XGIF1 and XGI, which are interfaces between layers 1-2 as continuous data strings
F2, XGIF3, XGIF4 (XGMII: Ten Gigabit Media Independe
nt Interface) (Literature: Howard Frazier, "IEEE P802.3ae
10 Gigabit Ethernet Task Force XGMII Update ", Cisc
o Systems, 11-July-2000, [retrieved on 2000-11-0
6], Retrieved from the Internet <URL: http: // group
er.ieee.org/groups/802/3/ae/public/jul00/Frazier#1
# 0700.pdf>). XGMII will be described later. The transmitting and receiving device of the physical layer (PHY: 23A) X
The GMII data string is subjected to an encoding process suitable for the transmission path, and then transmitted as an optical signal.

The data flow will be described in more detail with reference to the MAC frame format and the XGMII data string. FIG. 7 shows the MAC frame format. MAC frame is preamble 701, frame start 702, destination address 703, source address 704, length 705, transmission data 70
6, padding 707 and frame check sequence 708
Respectively. The unit of the numerical value indicating the length of each field is octet. Next, conversion of a MAC frame into an XGMII data string performed in the RS layer 22B will be described. XGMII is 32 for each transmission and reception
36-bit signal lines XGIF2 and XGIF4 comprising a 4-bit data signal line and a 4-bit control signal line, and clock lines XGIF1 and X
Has GIF3. FIG. 8 shows an XGMI1 transmission data sequence. In FIG. 8, each hexagon indicates an 8-bit signal, and each alphabet within the hexagon has the meaning shown in Table 1 below.

[0020]

[Table 1] In Table 1, for example, S indicates the start of a packet, and the value is OxFB,
That is, it is 11111011. Ox means that FB is an octet value. The RS layer 22B transmits the MAC frame
Four 8-bit wide buses TXD <0: 7> to TX indicated by LaneO to Lane3
Parallel expansion to D <24:31>. Numerical values in <> indicate bit positions in all 32-bit widths with bit position numbers 0 to 31, for example, <0: 7> indicates bit positions 0 to 7.

The first octet of the 7-octet preamble of the MAC frame is replaced with S, T is added to the end of the MAC frame, and I is inserted between MAC frames. Further TXD
1-bit control signal that distinguishes between MAC frame data and inter-frame signals, corresponding to each of <0: 7> to TXD <24:31>
TXC0 to TXC3 are assigned. The control signal value is 0 (Low) when a MAC frame is transmitted, and 1 (High) when an idle or frame delimiter is transmitted. TX # CLK is a transmission clock. When TX_CLK rises or falls, LaneO to Lane3 transmit four octets simultaneously, one octet at a time. A unit of 4 octets transmitted (or received) by one clock of XGMII is represented by one vertical column in FIG. 8 and is called a column. The receiving side has the same format, and the process opposite to that of the transmitting side is executed.

XGMII is an optional interface 1
0 Gigabit connection unit interface (XAUI: Ten Gi
gabit Attachment Unit Interface) (Literature: Rich Taborek
etal, "XAUI / XGXS Proposal", 23-May-2000, [retrieved
on 2000-ll-06], Retrieved from the the Internet <
URL: http://grouper.ieee.org/groups/802/3/ae/publi
c /jul00/taborek#2#0700.pdf>) XAUI
Is an interface that converts an XGMII data string into four 8B / 10B serial signals. The 8B / 10B code will be described later. As shown in FIG. 9, the XGMII data strings TX # CLK and TXD output to the interfaces XGIF1 and XGIF2 are a 10 Gigabit medium independent interface extension sublayer (XGXS: XGMII Extend).
er Sublayer) 907, four 8B / 10B serial signals (XAUI
XAUI data string TXAD
Are inversely converted to XGMII data strings TX # CLK and TXD. Physical layer 2
3A is XGXS910 for XGMII data strings RX # CLK and RXD.
Is converted to an 8B / 10B serial signal, and is inversely converted by the XGXS907. XAUI has a smaller number of signal lines and a larger interface wiring length than XGMII.

Since XGMII and XAUI are interfaces independent of the physical layer, if data to be transmitted is adapted to XGMII or XAUI, it can be transmitted by a 10 Gigabit Ethernet transceiver. Finally, the word synchronization technique is described. In 10 Gigabit Ethernet, word synchronization is realized by using a transmission line code. As the transmission line code, 8B / 10B code (Japanese Patent Laid-Open Publication No. 59-10056 “Code generation method”) and 64B / 66B
Code (Reference: Rick Walker et al, "64b / 66b PCS", 30-Jun
e-2000, [retrieved on 2000-11-06], Retrieved from
the Internet <URL: http: //grouper.ieee.org/groups/
802/3 / ae / public / jul00 / walker # 1 # 0700.pdf>).

In the 8B / 10B code, 8-bit data is converted to a 10-bit code. By adopting as many 10-bit codes as possible with the number of "1" and "0" as equal as possible from among 1024 types, it has DC free characteristics. It is used as a special code indicating a delimiter or the like. Word synchronization is easy because it has a comma sequence that appears only at word boundaries. The 64B / 66B code is composed of a 64-bit payload and a 2-bit header. When the header is "01", it is a data frame, and when it is "10", it is a control frame. DC-free characteristics are obtained by self-synchronizing scrambling of a 64-bit payload. As in the case of the 8B / 10B code, idle, packet delimiters, and the like are indicated by control frames. 64B / 66B word synchronization is performed by detecting a header.

The Ethernet employs an independent synchronization method. This is a method in which the clock frequencies between the transmitting and receiving nodes are not always matched, and a deviation within a certain range is allowed. The independent synchronization method has an advantage that clock distribution is not required as compared with the complete synchronization method in which clock frequencies are matched, but it is necessary to correct a difference in clock frequency. This clock correction, 10 Gigabit Ethernet XGMII
This is easily realized by inserting / extracting an idle signal of XAUI or a special code indicating idle of XAUI on a column basis.

The above is the outline of the 10 Gigabit Ethernet standardization technology. Next, Gigabit Ethernet will be briefly described. The layer configuration of Gigabit Ethernet is almost the same as that of 10 Gigabit Ethernet, and the interface between layers 1-2 is Gigabit Media Independent Independent Interface (GMII).
terface). The GMII has an 8-bit data signal line, a 1-bit control signal line, and a clock line for transmission and reception, respectively. GMII data string format is XG
Similar to MII. See ANSI / IEEE 802.3z
Please refer to.

In Gigabit Ethernet, since an 8B / 10B code is used as a transmission line code, the transmission speed is 1.25 Gb / s (=
1.OGb / s × 10/8). In Gigabit Ethernet, the clock correction is performed using the GMII idle signal or 8B / 1
This is performed by inserting and removing a special code set indicating the idle of the 0B code. The special code set indicating idle is described as / I2 / in Table 5-6 0rdered # Set list on page 130 of the above-mentioned document “Point Illustrated Gigabit Ethernet Textbook”. Hereinafter, the description will proceed to the description of the second embodiment of the present invention, in which a 7-channel Gigabit Ethernet input data sequence is multiplexed and transmitted using a 10-Gigabit Ethernet transceiver.

FIG. 10 shows a process of a transmitting node for multiplexing and transmitting a 7-channel Gigabit Ethernet input data sequence. The transmitting node 20TN corrects the clock frequency and the phase shift of the 7-channel input data sequence by the clock correction units 21A1 to 21A7, respectively, and multiplexes them into the multiplexed input data sequences ID1 to ID7 shown in FIG. -Interleave multiplexing and 4 shown in FIG.
Multiple output interface IF consisting of eight 8-bit buses
Output to 3. 11 to 13 show multiplex input interfaces IF21 to IF27 and multiplex output interface IF of FIG.
3. Data streams flowing through the interfaces XGIF1 and XGIF2 by XGMII are respectively represented by multiple input data strings ID1 to ID7 in FIG.
The multiplex output data strings MOD1 to MOD4 in FIG.
3 is shown in the XGMII data string.

In FIG. 11, each minimum unit rectangle represents one bit, and a bold rectangle indicates an 8B / 10B word boundary. In the code in each square, the one digit number to the right of “D” indicates the channel number to which the bit belongs, and the remaining numbers indicate the bit numbers in the channel. Multiple input data is input with the left bit at the head. FIG. 12 shows four 8-bit multiplex output data strings MOD1 to MOD4, respectively. Each minimum unit rectangle represents one bit, and the symbols in the rectangle are as shown in FIG.
Corresponding to A bold rectangle indicates 8 bits transmitted in one clock.

Next, the multiplex output data sequence MOD1 to MOD4 is divided by the transmission interface conversion means 22 into a block sequence in which each block has a bit width of 32 bits and a length of 350 octets, that is, a size of 4 × 350 = 1400 octets. . Bits D100 to D71599 in FIG. 12 correspond to one block. By setting the block size to 1400 octets, which is an integral multiple of the channel multiplexing period of 4 × 7 = 28 octets, it is possible to identify the channel by the bit position in the block. Furthermore, since the 10-bit word boundary of any of the input data strings ID1 to ID7 in FIG. 11 always exists at a specific position in the block, the word boundary can be identified.

The transmission node 20TN shown in FIG.
Start of 1 octet packet in block as shown
(S), 6 octet preamble (dp) and 1 octet frame start (SFD) at the beginning of the block, packet end
(T) at the end of the block to form a packet, according to the difference between the data transmission speed of the multiplex output interface IF3 and XGMII, while inserting an idle signal (I) between the packets, the inter-frame signal A 4-bit control signal line (TXC0 to TXC3) for distinguishing between (I, S, T) and frame data (dp, SFD, block) is provided to generate an XGMII data string. FIG. 13 shows bits D100 to D71599 constituting one block in FIG. 12 converted into an XGMII data string. Each hexagon represents 8 bits, bits D100 to D107, D2
00 ~ D207, D300 ~ D307, ..., D61592 ~ D61599, D71592
~ D71599 are octets d10, d20, d30, ..., d6 respectively
Corresponds to 199, d7199. Table 1 shows the meaning of the other alphabets. By converting to XGMII data string,
It can be transmitted by a 10 Gigabit Ethernet packet transmission device.

The receiving node 20RN performs the reverse process of the transmitting node 20TN. FIG. 14 shows a process of a receiving node that separates and multiplexes a received data sequence and outputs the data to a desired channel as seven Gigabit Ethernet output data sequences. The receiving node 20RN receives the received data sequence by the 10 Gigabit Ethernet packet receiving device 24, and
Convert to I data string and output to interface XGIF5, XGIF6. FIG. 15 shows the received XGMII data string. The notation in FIG. 15 is based on FIG. Next, the block stored in the packet is extracted from the XGMII data string by the receiving interface conversion means 25. After combining sequentially obtained blocks, the demultiplexing input interface IF8
Output to FIG. 16 shows the resulting demultiplexed input data strings DMOD1 to DMOD4. The notation in FIG. 16 conforms to FIG. The demultiplexing input data strings DMOD1 to MOD4 are demultiplexed by the demultiplexing means 26 into desired channels IF91 to IF97. If a packet is lost due to an error during transmission or the like and data cannot be continuously transmitted to the demultiplexing input interfaces IF91 to IF97, the clock correction means 271 to 2
According to 77, an 8B / 10B special code indicating an error is inserted as necessary.

As described above, by adopting this method,
Existing transmission / reception devices can be used, contributing to a reduction in development costs. Also, when a regenerative repeater is inserted between the transmitting and receiving nodes, an existing one can be used, and no new development is required. Further, clock correction and channel identification processing can be easily realized. Also, the number of channels can be set flexibly. For example, in the multiplexing of a data stream of 6 channels, similarly, it is possible to transmit the data by the 10 Gigabit Ethernet transmitting / receiving apparatus only by increasing the idle signal (I) inserted into the XGMII as compared with the 7 channels.

In the second embodiment, an example of multiplexing input data sequences of seven channels has been described. However, the present invention is not limited to this, and input data sequences of n channels may be multiplexed. In the second embodiment, each block size is 1400 octets, but may be another fixed size. Further, the length may be variable within the range of the specifications of the packet transmitting / receiving apparatus.
Further, in the second embodiment, an example of multiplexing a gigabit Ethernet input data stream has been described. However, the present invention is not limited to this, and an asynchronous transfer mode (ATM: Asynchronous Transfer Mode) may be used as an input signal.
ode) The present invention can be applied to other data such as an input data sequence.

In the second embodiment, an example of octet interleave multiplexing has been described. However, the present invention can be applied to other time division multiplexing methods such as bit multiplexing. In the second embodiment, the Gigabit Ethernet input data sequence has a clock correction function, and the clock correction can be performed by inserting and removing a special code set indicating idle before multiplexing. As long as there is no clock frequency and phase shift between them, it is not necessary to have a clock correction function. Further, even if there is no clock correction function and there is a shift in clock frequency and phase between input data strings, the multiplexing means 21 generates a stuff pulse which is an additional signal containing no data according to the shift. Insert
A packet may be formed by adding position information of the stuff pulse to the block, and the receiving node may include other clock correction means such as performing clock correction by removing the stuff pulse based on the position information. .

In the second embodiment, the block length is determined so that the word boundary always coincides with a specific position in the block, and there is an advantage that the word synchronizing means is unnecessary.
If word synchronization is not required or another word synchronization means is provided, another block division means may be used. Further, in the second embodiment, the channel can always be identified by the bit position in the block by setting the block size to an integral multiple of the channel multiplexing period. However, when the channel identification means is unnecessary or provided in another case, However, it is not necessary to limit the block size to this.

In the second embodiment, the packet transmission / reception device interface is XGMII, and a low cost 10 Gigabit Ethernet transmission / reception device can be used. However, XAUI may be used. Further, the present invention is not limited to 10 Gigabit Ethernet, and another packet transmitting / receiving apparatus and its interface may be used. For example, low cost Gigabit Ethernet transceivers and their interfaces
Using GMII is one example. Further, in the second embodiment, 1 octet indicating S and 6 octets indicating the preamble are added to the head of the block, and octet indicating T is added to the end of the block to form a packet. Relay was possible when there was a device, but the destination address, source address, length, frame check sequence were added, and MAC
If a frame is configured, packets will not be discarded even if there is a hub that performs MAC frame processing between the transmitting and receiving nodes and relays. Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIGS. In the third embodiment of the present invention, an example is shown in which an 8-channel Gigabit Ethernet input data stream is multiplexed and transmitted by a 10-Gigabit Ethernet transceiver. The data rate after multiplexing of the 8-channel Gigabit Ethernet input data sequence is 10 Gb / s (= 1.25 Gb / s × 8), but it cannot be transmitted as it is in 10 Gigabit Ethernet due to various overheads. Therefore, in the third embodiment,
At the transmitting node, the Gigabit Ethernet input data stream (8
The 8B / 10B decoding of the B / 10B word string into 9-bit data (8-bit data and 1-bit control signal) before multiplexing reduces the amount of data to be multiplexed. The receiving node performs 8B / 10B encoding on the demultiplexed data sequence.

FIG. 18 shows a process of a transmitting node for multiplexing and transmitting an 8-channel Gigabit Ethernet input data sequence. After the transmitting node 20TN matches the word boundaries of the input data strings ID1 to ID8 of the eight channels with the clock correction devices 21A1 to 21A8, respectively, the 8B / 10B decoding means 21B1
21B8 to 9-bit data, which are used as multiplexed input data strings ID1 'to ID8', and
, And interleave-multiplexes every two bits from each channel, and outputs to a multiplex output interface IF3 comprising four 8-bit buses. FIGS. 19 and 20 show multiplex input data strings ID1 'to ID8' and multiplex output data strings MOD1 to MOD4, respectively. In FIG. 19, each minimum unit square represents 1 bit, and a bold rectangle indicates a 9-bit word boundary.
Enter the left bit first.

In FIG. 20, LaneO to Lane3 indicate four multiplex output interfaces IF3, respectively. Each minimum unit square represents one bit, and the symbols in each square correspond to those in FIG. Thick rectangle 8 is transmitted in one clock 8
Indicates a bit. Next, the multiplex output data strings MOD1 to MOD4 are
Size 4 × 324 in the transmission interface conversion means 22
= 1 Divide into 1296 octet block strings. The block size of 1296 octets is an integer multiple of 8 octets of the channel multiplexing period, and is selected such that the word boundary (= 9 bit boundary) always coincides with the head position of the block. Bits D100 to D81295 in FIG. 20 correspond to one block. The rest of the process conforms to the second embodiment.

The receiving node 20RN performs the reverse process of the transmitting node 20TN. FIG. 21 shows that the received data stream is demultiplexed and multiplexed into eight Gigabit Ethernet output data streams OD1.
The process of the receiving node outputting to a desired channel as OD8 is shown. The receiving node 20RN receives the received data sequence by the 10 Gigabit Ethernet packet receiving device 24, and converts it into XGMII data sequences RX # CLK and RXD. Next, the XGMII data string R
Extract the block stored in the packet from X # CLK and RXD. After the sequentially obtained blocks are combined, they are output to the demultiplexing input interface IF8.

FIG. 22 shows the resulting demultiplexed input data strings DMOD1 to DMOD4. The notation in FIG. 22 conforms to FIG. The demultiplexing input data strings DMOD1 to DMOD4 are demultiplexed by the demultiplexing means 26 into desired channels IF91 to IF98 as demultiplexing output data strings OD1 'to OD8', respectively.
At this time, since the block size of 1296 octets is an integral multiple of 16 octets of the channel multiplexing period, channel identification is easy. Also, since the word boundary is at the beginning of the block, word synchronization is easy. Further, the demultiplexed output data strings OD1 ′ to OD8 ′ are respectively 8B / 10B encoding means 281 to 288.
8B / 10B encoding and converted into a Gigabit Ethernet output data string.

When a packet is lost due to an error during transmission or the like and data cannot be continuously transmitted to the demultiplexing input interface, the clock correction means 271 to 278 use an 8B / 10B special code indicating an error as necessary. Insert As described above, by adopting this method, it is possible to use an existing transmitting / receiving device, which contributes to a reduction in development cost. Also, unlike the conventional multiplexing method, clock correction and channel identification processing can be easily realized. Gigabit Ethernet input data strings OD1 'to OD8'
By performing 8B / 10B decoding and converting the data into 9-bit data, the amount of data to be multiplexed was reduced, and the number of multiplexed channels could be increased as compared with the second embodiment.

In the third embodiment, the Gigabit Ethernet input data stream has a clock correction function, and the clock can be corrected by inserting and removing a special code set indicating idle before 8B / 10B decoding. 8B / 10B
The clock may be corrected by inserting and removing an idle signal after decoding. Finally, in the first to third embodiments of the present invention, the transmission format between the packet transmitting and receiving devices is not particularly mentioned, for example, in 10 Gigabit Ethernet, 64B / 66B serial data transmission signal (10.3 Gb / s) Alternatively, four 8B / 10B serial data transmission signals (4 × 3.125 Gb / s) are possible and are not limited to one serial data transmission signal.

[0044]

As described above, in a multiplex transmission system for transmitting an input data sequence of n channels (n is an integer of 2 or more) from a transmitting node to a receiving node, the transmitting node multiplexes the input data sequence of n channels, and The resulting multiplexed output data sequence is sequentially divided into blocks, and the packet is converted to an existing packet transmission device interface data sequence by, for example, adding predetermined packet information to the block. By providing this, the existing packet transmission / reception device and regenerative repeater can be used, which contributes to reduction in system development cost. Further, even if the transmission speeds of the multiplex channel and the packet transmission / reception device are not integral multiples, the difference in transmission speed can be absorbed by the presence or absence of a packet, so that a flexible multiplex transmission system can be constructed.

[Brief description of the drawings]

FIG. 1 shows a conventional example of a time division multiplex transmission system.

FIG. 2 shows a data stream flowing through each interface of the conventional time division multiplex transmission system.

FIG. 3 is a basic principle diagram of the present invention.

FIG. 4 shows a time division multiplex transmission system according to a first embodiment of the present invention.

FIG. 5 shows a data stream flowing through each interface of the time division multiplex transmission system according to the first embodiment of the present invention.

FIG. 6 is a layer configuration diagram of a 10 Gigabit Ethernet being standardized.

FIG. 7 shows a MAC frame format defined in IEEE802.3.

FIG. 8: 10 Gigabit medium independent interface (XGMI
I) Indicates a data string.

FIG. 9: 10 Gigabit connection unit interface (XAU
Indicates the layer position of I).

FIG. 10 illustrates a configuration of a transmission node in a time division multiplex transmission system according to a second embodiment of the present invention.

FIG. 11 shows a multiplexed input data sequence in a transmission node according to a second embodiment of the present invention.

FIG. 12 shows a multiplex output data sequence in a transmission node according to the second embodiment of the present invention.

FIG. 13 shows an XG in the transmitting node according to the second embodiment of the present invention.
Shows the MII data string.

FIG. 14 shows a configuration of a receiving node in the time division multiplex transmission system according to the second embodiment of the present invention.

FIG. 15 shows the XG in the receiving node according to the second embodiment of the present invention.
Shows the MII data string.

FIG. 16 shows a demultiplexed input data sequence in a receiving node according to the second embodiment of the present invention.

FIG. 17 shows a demultiplexed output data sequence in the receiving node according to the second embodiment of the present invention.

FIG. 18 shows a configuration of a transmission node in a time division multiplex transmission system according to a third embodiment of the present invention.

FIG. 19 shows a multiplexed input data sequence in the transmitting node according to the third embodiment of the present invention.

FIG. 20 shows a multiplexed output data sequence in the transmitting node according to the third embodiment of the present invention.

FIG. 21 shows a configuration of a receiving node in a time division multiplex transmission system according to a third embodiment of the present invention.

FIG. 22 shows a demultiplexed input data sequence in a receiving node according to the third embodiment of the present invention.

FIG. 23 shows a demultiplexed output data sequence in the receiving node according to the third embodiment of the present invention.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Osamu Ishida, Inventor F-term (reference) 5-3, Otemachi 2-chome, Chiyoda-ku, Tokyo 5K028 AA06 KK01 KK03 KK32 NN31

Claims (12)

[Claims] 1. A multiplex transmission system for transmitting an input data sequence of n channels (n is an integer of 2 or more) from a transmitting node to a receiving node, wherein the input data sequence of the n channels is time-division multiplexed, and a multiplex output interface is provided. A time-division multiplexing means for outputting as a multiplexed output data sequence, and sequentially dividing the multiplexed output data sequence into blocks having a predetermined block length, and forming a packet by adding predetermined packet information to the block, A transmission system comprising: a transmission interface conversion unit that outputs a packet to a packet transmission device interface as a packet transmission device interface data sequence; and a packet transmission device that transmits the packet transmission device interface data sequence. 2. The transmission system according to claim 1, wherein each of the n-channel input data strings includes clock correction means for correcting a difference in clock frequency. 3. The transmission system according to claim 1, wherein said n-channel input data sequence is an 8B / 10B word sequence, and further comprising means for decoding said 8B / 10B word sequence. Sending system. 4. The transmission system according to claim 1, wherein the block length is a length such that any word boundary of the input data sequence always exists at a specific bit position in the block. A transmission system characterized by the above-mentioned. 5. The transmission system according to claim 1, wherein said block length is an integral multiple of a channel multiplexing period. 6. The transmission system according to claim 1, wherein said transmission interface conversion means sets an idle according to a data transmission speed difference between said multiplex output interface and said packet transmission device interface. A transmission system comprising means for inserting between the packets. 7. The transmission system according to claim 1, wherein the packet transmission device interface is a 10 Gigabit Ethernet (registered trademark) transmission device interface. 8. The transmission system according to claim 1, wherein said packet transmission device interface is a gigabit Ethernet transmission device interface. 9. A packet receiving apparatus for receiving a transmission packet data sequence and outputting a packet receiving device interface data sequence to a packet receiving interface, extracting a packet from the packet receiving device interface data sequence, A receiving interface converting unit that combines each of the included blocks to generate a demultiplexed input data sequence; and a demultiplexing unit that performs time division demultiplexing on the demultiplexed input data sequence into a desired channel. Demultiplexing reception system. 10. The demultiplexing receiving system according to claim 9, wherein said packet receiving interface is a 10 Gigabit Ethernet receiving device interface. 11. The receiving system according to claim 9, wherein
A demultiplexing receiving system, wherein the packet receiving interface is a gigabit Ethernet receiving device interface. 12. A multiplexing transmission system for transmitting an input data sequence of n channels (n is an integer of 2 or more) from a transmitting node to a receiving node, wherein the transmitting node time-division multiplexes the input data sequence of the n channels. A time-division multiplexing means for outputting a multiplexed output data stream as a multiplexed output data stream to a multiplexed output interface; A transmission system comprising: a transmission interface conversion unit configured to output the packet to a packet transmission device interface as a packet transmission device interface data sequence; and a transmission system including a packet transmission device that transmits the packet transmission device interface data sequence. The node receives the transmitted packet data sequence, and A packet receiving device that outputs a packet receiving device interface data sequence to a receiving interface; a packet extracting device that extracts a packet from the packet receiving device interface data sequence and combines respective blocks included in the packet sequentially obtained; And a demultiplexing means for time-division demultiplexing the demultiplexed input data sequence into a desired channel.