JP2002271209A - Turbo encoder and turbo decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the load on a circuit due to processing of a tail bit, added to the end of a information sequence in a turbo encode and a turbo decoder, and to reduce the power consumption of the circuit. SOLUTION: In the turbo encoder, outputs of four systems are accumulated in registers 103-106, an information code sequence and a tail-bit code sequence are parallel generated by dedicated circuits 109 and 110 and are selected by a selector 108. In the turbo decoder, they are subjected to buffer processing before being inputted into a turbo decoding section 210. Namely, when the data, after being subjected to rate-dematching processing, is rewritten in memories 201-203, the light pulse of the tail bit is changed somewhat. Thus, the data can be read from the memories (201-203), without discriminating the information sequence from the tail bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a turbo encoder and a turbo decoder.

[0002]

2. Description of the Related Art In recent years, with the spread of mobile communication, expectations for higher accuracy and higher speed of communication are increasing, and high accuracy and higher speed of error correction processing are also required. An error correction code called a turbo code (TURBO code) is currently attracting attention in terms of high accuracy and has also been introduced in next-generation mobile phones.

[0003] The turbo encoder (transmitter) has two recursive systematic encoders (convolutional encoders). One convolutional coder inputs the information sequence as it is, and the other convolutional coder uses the interleaver to disorder the information sequence (mix the data bits in an irregular order). input.

The output (information code sequence) of the turbo encoder is:
The information code sequence itself and the codes output from the two convolutional encoders. A code string obtained by performing an interleaving process on the information sequence itself is not output in a normal operation. The code output from each convolutional encoder is a redundant bit including information of consecutive consecutive bits.

[0005]

In a turbo encoder, after encoding of an information sequence is completed, a tail bit (hereinafter, referred to as a tail bit) for returning bits held in each convolutional encoder to zero.
It is common to input and encode a tail bit. In the decoder, the tail bit serves to return the data held in the register of the Viterbi decoder to zero.

The problem here is that three kinds of codes are output in encoding a normal information sequence, whereas four kinds of codes are output in encoding tail bits. It is.

[0007] Specifically, the output of the encoding of the information sequence is
The information sequence itself (x) and the code (y, y ') output from each of the two convolutional encoders. The information (x ′) obtained by performing interleave processing on the information sequence is not output. This is because if the information sequence (x) can be decoded on the decoding side, x ′ can be obtained by performing an interleaving process on the information sequence (x).

On the other hand, in the case of tail bit encoding,
It is also necessary to output information (x ′) obtained by interleaving the tail bits. This is because it is difficult for the decoding side to return the state of the Viterbi decoder to the initial state without information from the encoding side.

That is, in the encoding of the information sequence, ｛x,
y, y ′} is output, and in the encoding of the tail bits,
{X, y, x ′, y ′} are output, and the procedure for processing the tail bits is different from the procedure for encoding the information sequence. Therefore, on both the encoding side and the decoding side, it is necessary to perform processing different from the encoding / decoding of the information sequence on the tail bits.

[0010] There are several methods for realizing this. However, since the circuit is used for mobile communication, an increase in circuit scale and an increase in power consumption must be minimized.

The present invention simplifies the circuit configuration for processing tail bits, suppresses an increase in circuit scale, and satisfies the demand for low power consumption while efficiently performing turbo encoding / decoding processing. The purpose is to do.

[0012]

According to one preferred aspect of the present invention, a register is provided on the encoder side for temporarily storing the output of an elementary encoder for a fixed length, and an information sequence,
For both tail bits, data is selected from the register to generate a code sequence. The code sequence to be output is switched.

On the decoder side, when tail bits are processed, the memory access for storing the received sequence in the buffer memory is slightly changed, and one data is simultaneously written into two memory areas. By doing so, the tail bits can be read from the memory in the same manner as the information code sequence, and the burden of tail bit processing can be minimized.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a diagram showing a configuration of a turbo encoder and a turbo decoder according to the present embodiment. Figure 1
The upper part of the figure shows an encoder, and the lower part shows a decoder.

In the turbo encoder of FIG.
Reference numeral 101 denotes an interleaver.
Reference numeral 103 denotes an element encoding circuit.
4, 105 and 106 are registers for storing the outputs of the elementary encoders. Reference numeral 107 denotes a code sequence bit counter, reference numeral 108 denotes a selector, reference numeral 109 denotes a code sequence generation circuit (for an information code sequence), and reference numeral 110 denotes a code sequence generation unit. (For tail bit).

Reference numeral 111 denotes a rate matching circuit. The rate matching circuit functions to adjust the transmitted code sequence to a length suitable for the communication channel. That is, when the length of the transmission code is shorter than the communication channel length, the code length is adjusted by performing processing such as repeating the same bit data.

Elemental encoders (convolutional encoders) 101, 10
FIG. 8 shows a specific configuration example of No. 2. In FIG. 8, reference numerals 901 and 902 are registers, and reference numerals 903 and 903.
904 and 905 are exclusive OR gates.

In the case of a mobile phone, a code output from a turbo encoder is modulated and transmitted, and is demodulated and turbo-decoded on the receiving side. In FIG. 1, the modulator and the demodulator are omitted.

The operation of the turbo encoder configured as described above will be described below.

An information sequence (information to be transmitted) sent from an information source is subjected to an interleaving process and input to an element encoder 102, and each outputs two code sequences. .

FIG. 7 shows a code sequence output from the element encoders 101 and 102. That is, assuming that the information sequence to be encoded is {X0, X1, X2,...}, The elementary encoder 101 receives the information sequence as it is, and outputs the passed sequence {X0, X1, X2,. ..} And a redundant bit sequence {Y0, Y1, Y2,. For the elementary encoder 102, the interleaver 100
Information sequence {X'0, X '
, {X′2,...}} And a redundant sequence {Y′0, Y′1, Y ′} and a sequence {X′0, X′1, X′2,. 2,... Are output.

The code sequences of the four systems are temporarily stored in registers 103, 104, 105, and 106 of a predetermined length, respectively.

Of the four series of codes thus obtained, in the normal encoding (encoding of the information series), {Xn}, {Y
n} and {Y′n} (n = 0, 1, 2,...), {X0, Y0, Y′0, X1, Y1, Y′1,
... It is necessary to arrange in the order of｝ and output serially. The rearrangement in the encoding of such an information sequence is as follows.
This is performed by the code sequence generation unit (for information code sequence) 109. That is, the code sequence generation unit (for information code sequence) 109
Extracts the code data from the registers 103 to 106, and outputs {X0, Y0, Y'0, X1, Y1, Y'1,.
・ Output in the order of｝.

On the other hand, in the processing of the tail bit,
Tail bits are generated for each of the four sequences {Xn}, {Yn}, and {X'n} Y'n}, and are added to the end of the turbo code.

As an example of the tail bit addition order, for example, if the tail bits are three bits,
0t, Y0t, X1t, Y1t, X2t, Y2t, X '
0t, Y'0t, X'1t, Y'1t, X'2t, Y '
2t}.

The rearrangement of the tail bits is performed by the code sequence generator (for tail bits) 110. That is, the code sequence generation unit (for information code sequence) 110
Extracts the code data from the registers 103 to 106, and outputs {X0t, Y0t, X1t, Y1t, X2t, Y2
t, X'0t, Y'0t, X'1t, Y'1t, X'2
t, Y′2t}.

Code sequence generator (for information code sequence) 109
The code sequence generation unit (for information code sequence) 110 operates in parallel. The two code sequences thus generated (for the information sequence and for the tail bit) are sent to the rate matching circuit 11
At 1, the rate matching process is performed, and then one of them is selected by the selector 108.

The selection made by the selector 108 is the counter 1
It is controlled based on the count value of 07. In other words, since the number of codes of the information sequence is known, it is possible to know the timing at which the coding of the information sequence ends and the coding of the tail bits starts by counting how many codes have been generated. it can.

In response, selector 108 switches the selected sequence from the information code sequence to the tail bit code sequence.

As described above, the code is held in the fixed-length register, the two code generation circuits select data from the register, and generate two code sequences of an information code sequence and a tail bit code sequence. By switching the selection of the code sequence by the selector at an appropriate timing, the encoding process of the tail bit can be performed without difficulty.

As described above, in the turbo coder according to the present invention, the register for storing the output of the component coder for a fixed length,
A total of two code sequence generators for generating an information code sequence and a tail bit code sequence, a code sequence generator for generating a tail bit code sequence, a selector for switching between them,
A configuration including a sign bit counter for generating a switching signal is employed. According to this configuration, the two component encoders always perform the same encoding processing operation, and the code bit counter counts the number of coded bits. While the counter value is equal to or smaller than the number of bits to be coded, the code sequence generator for the information sequence operates, and its output becomes the output of the turbo coder. The selector operates so that the output of the sequence generation unit becomes the output of the turbo encoder.

The configuration and operation of the turbo encoder have been described above.

Next, the turbo decoder will be described.

In the turbo decoder of the present invention shown in the lower part of FIG. 1, a received code sequence is temporarily buffered in a memory, and thereafter, turbo decoding is performed. At the timing of switching from the information code sequence to the tail bit code sequence, the method of write access to the memory is slightly changed. As a result, the processing of the tail bit code sequence can be easily performed.

In the turbo decoder shown in FIG. 1, reference numerals 201, 202 and 203 denote received sequence storage memories (memory areas). One memory area may be divided into three parts, or the memories may be individually prepared.

Reference numeral 204 denotes a rate dematch circuit, and reference numeral 210 denotes a turbo decoding circuit.

The turbo decoding circuit includes a soft output decoder 211
, An interleaver 212, a soft output decoder 213, and a deinterleaver 214, and the decoding accuracy can be improved by turning this loop many times.

The operation of the circuit on the receiving side configured as described above will be described below.

First, the received signal is stored in the reception sequence storage memories 201, 202 and 203.

FIG. 2 shows a method of storing data in each memory.
Assuming that the received sequence is C0, C2, C3, the memory 2
01 to C0, memory 202 to C1, memory 203 to C3
The data is sequentially buffered while being distributed.

In this way, once the memories 201,
The data stored in 02 and 203 are subjected to a rate dematching process (a process opposite to the rate matching process), and processes such as removal of dummy bits are performed to restore the data.

Then, the data is again written to the memories 201 to 203 via the access control circuit 200. This write access is controlled by the access control circuit 200. The access control circuit 200 counts the number of codes after the rate dematch processing by the counter 205, and determines whether the received sequence is an information code sequence or a tail bit code sequence.

Then, the information code sequence is written in the same manner as the first write. That is, the information sequence “X” is written in the memory (area) 201, “Y” is written in the memory 202, and the memory 203 is written in the memory 203.
“Y ′” is written.

That is, as for the information code sequence, FIG.
Writing is performed sequentially in the order shown in FIG. FIG. 3B shows a write pulse for each memory.

On the other hand, when tail bits are processed, the write control described above cannot be applied, so the access control circuit 200 slightly changes the write access.

Here, also in the processing of the tail bit,
It is desirable that the division of the memories 201 to 203 be the same as the processing of the information series. That is, the classification condition of storing the information series “X” in the memory 201, storing “Y” in the memory 202, and storing “Y ′” in the memory 203 is maintained in the processing of the tail bits. It is desirable.

As described above, the received sequence of the tail bits is represented by {X0t, Y0t, X1t, Y1t, X2t, Y2
t, X'0t, Y'0t, X'1t, Y'1t, X'2
t, Y′2t}.

These tail bits are temporarily stored in the memory 20.
The data is stored as normal in Nos. 1 to 203, read out, subjected to a rate dematching process, and returned to the memory again. In this case,
As in the case of buffering the information sequence, if the buffering is performed while keeping the three memory divisions, each data should be distributed as shown in FIG. In FIG. 4, “*” indicates data whose content is unquestioned (unnecessary data).

However, since it is difficult to realize irregular data distribution as shown in FIG. 4, in practice, FIG.
As shown in (1), the same data is written in the memories 202 and 203.

That is, "Xt0" is written to the memory 201, and the next data "Yt0" is simultaneously written to the memories 202 and 203. By repeating such a write access, data is allocated to each memory as shown in FIG. FIG. 5B shows a write pulse for such a memory access. Memory 20
The feature is that 2,203 write pulses are synchronized.

Here, looking at the arrangement of data stored in each memory of FIG. 5A, it can be seen that the data arrangement shown in FIG. 4 is substantially realized. In other words, in FIG. 5A, only unnecessary data is written in the portion marked with “*” in FIG.

Therefore, when turbo decoding is performed on the tail bits, data is sequentially read from the memories 201, 202, and 203 and decoded in the same manner as in the case of decoding the information sequence. If the data corresponding to is discarded (not used), the decoding of the tail bits
It can be performed as usual without distinction from decoding of the information sequence.

As described above, on the decoder side, when tail bits are processed, the memory access for storing the received sequence in the buffer memory is slightly changed, so that the two memory areas can be used.
Write one data at a time. By doing this,
Reading tail bits from the memory can be performed in the same manner as the information code sequence, and the burden of tail bit processing is reduced.
Minimized.

As described above, in the turbo decoder according to the present invention, the result of the rate matching process on the reception sequence written in the three memories indicates that one data is written into one memory in the information sequence and the tail bit is {Xtn} and {X'tn} write one data to one memory in the same manner as the information sequence, but {Ytn} and {Y'tn} write one data to two memories simultaneously. According to this configuration, the processing for {Ytn} and {Y'tn} can be shared, and the control thereof can be simplified. Therefore, an increase in circuit scale can be minimized.

Although the above description has been made on the assumption that the rate dematch processing is performed, the present invention is not limited to this. That is, when the rate dematch processing is unnecessary, the received sequence is divided into an information sequence and a tail bit, and when each of them is written in a memory in a distributed manner, FIG.
It is also possible to write directly to the memory using the write pulse described in FIG. 5B.

(Embodiment 2) This embodiment is an example in which the turbo coding / decoding device of the present invention is applied to a mobile communication terminal (or a base station for mobile communication).

As shown in FIG. 6, a mobile communication terminal (or a mobile communication base station apparatus) includes an antenna section 301.
, An RF unit 302 that performs frequency conversion, an A / D conversion unit 303 that performs A / D conversion on received data, and an
D / A conversion section 304 for performing A / A conversion, and codec section 305 for performing conversion and reverse conversion of received data into voice and the like.
, A turbo decoder 306, and a turbo encoder 307.

First, at the time of data transmission, data such as voice to be transmitted is converted into digital data by the codec section 305,
It is encoded by the turbo encoder 307. The coded data is converted into analog data by a D / A conversion unit 304, frequency-converted by an RF unit 302, and transmitted from an antenna 301.

Next, at the time of data reception, the data received by the antenna 301 is frequency-converted by the RF section 302 and the A / D
The data is converted into digital data by the conversion unit 303. Subsequently, decoding is performed by the turbo decoder 307, and the codec unit 305 converts the data into original data such as audio. In this circuit, since the circuit of the turbo code / decoder is simplified and downsized, a smaller communication device with low power consumption can be realized.

[0060]

As described above, according to the present invention, the processing of the tail bit code sequence added to the end of the information code sequence can be easily performed. That is, by performing substantially the same processing as the processing of the information sequence, exceptional tail bit processing can be realized, and an increase in circuit scale can be suppressed. Thereby, low power consumption of the circuit is also achieved.
According to the present invention, simplification and low power consumption of a mobile communication device such as a mobile phone and a base station can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a turbo encoder / decoder according to the present invention.

FIG. 2 is a diagram for explaining buffering of a received sequence in the turbo decoder of the present invention.

FIG. 3A is a diagram for describing writing of an information code sequence to a memory in a turbo decoder according to the present invention. FIG. 3B is a waveform diagram showing a state of a write pulse in each memory.

FIG. 4 is a diagram for explaining a desirable mode when a tail bit code sequence is written in a memory;

5A is a diagram for explaining writing of a tail bit code sequence to a memory in a turbo decoder according to the present invention. FIG. 5B is a waveform diagram showing a state of a write pulse in each memory.

FIG. 6 is a block diagram showing the configuration of a mobile communication device equipped with the turbo code / decoder of the present invention.

FIG. 7 is a block diagram showing an example of output data of two component encoders in a turbo encoder.

FIG. 8 is a diagram illustrating an example of a specific configuration of an element encoder in the turbo encoder.

[Explanation of symbols]

 101, 102 element encoder 103 to 106 element encoder output storage register 108 selector 109 code sequence generator (for information code sequence) 110 code sequence generator (for tail bit) 200 access control circuit 201 to 203 reception sequence storage memory 204 Rate dematch circuit 205 counter

Claims (5)

[Claims] A first elementary encoder for performing a recursive convolutional coding process on an information sequence to be coded; and a recursive processing for an information sequence obtained by performing an interleaving process on the information sequence to be coded. A second elementary encoder for performing a convolutional encoding process, an information sequence to be encoded, an information sequence subjected to the interleaving process, a code sequence output from the first elementary encoder, and the second elementary encoder. A plurality of registers for temporarily storing each of the code sequences output from the elementary encoders; a circuit for extracting data bits from each of the plurality of registers to generate an information code sequence; and A circuit for extracting a data bit from each of the registers and generating a code sequence of tail bits; and a circuit for generating a code sequence of tail bits based on the number of information bits encoded by the first or second elementary encoder. There are, or the information code sequence, turbo encoder and having a selection circuit for selecting and outputting one of said tail bit code sequence. 2. A turbo decoder for receiving and decoding data encoded by a turbo encoder, the turbo decoder being configured to store a code of a received information code sequence that has not passed through an element encoder. 1 memory area, a second memory area for storing codes generated by passing through one of the two elementary encoders of the received code sequence, and 2 memory areas of the received code sequence. A third memory area for storing codes generated by passing through the other of the two element encoders, and a tail bit code sequence following the information code sequence,
When accumulating in the second and third memory areas, one code of the last bit is written in the first memory area, and then the next code following the one code is written in the second and third memory areas. 3. A turbo decoder, comprising: a memory access control circuit that repeatedly performs an operation of writing data into a memory area of No. 3. 3. The received tail bit code according to claim 2, wherein a rate matching process for adjusting the length of the transmission sequence to a length suitable for the communication channel is performed on the turbo encoder side. Like the information code sequence, the sequence is once written in the first, second, and third memory areas, the written tail bit code sequence is read out, rate dematch processing is performed, and the tail after rate dematch processing is performed. When writing the bit code sequence again into the first, second, and third memory areas, the memory access control circuit writes one code of the last bit in the first memory area, and then, A turbo decoder which repeats an operation of writing the next code following the one code into the second and third memory areas. 4. A mobile communication terminal device equipped with the turbo coder according to claim 1. 5. A mobile communication terminal device equipped with the turbo decoder according to claim 2.