JP2002261770A - Serial bus testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To rapidly execute the analysis of data that are taken into a capture memory from a high-speed serial bus. SOLUTION: When a physical layer circuit 4n receives the transmission signal of a series of packets from the high-speed serial bus 1 and outputs data to a link layer circuit 5n , a data extraction/writing circuit 60 writes the data into a capture memory 70. Also, an index information analysis circuit 91 discriminates the packet in parallel, analyzes the type and the transmission speed of the packet, and writes at an index memory 90 as index information, by associating with a position on the capture memory 70. After capturing, a controller 30n refers to the index memory 90 and searches for a desired packet, reads the data of a desired packet from the capture memory 70 for discriminating the presence or absence of errors, and displays the data on a display 11, together with index information and packet configuration data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial bus tester, and more particularly, to a serial bus tester capable of quickly executing a process for testing a large number of packets transmitted through a serial bus.

[0002]

2. Description of the Related Art In recent years, printers, digital cameras, external hard disks, and the like are connected to a personal computer body in a daisy-chain or tree structure to enable high-speed communication between arbitrary node devices. , A "high-speed serial bus"). This high-speed serial bus can connect a large number of node devices using a small cable,
Moreover, it has a feature that large-capacity data such as moving image data can be smoothly transferred.

FIG. 18 shows a connection example of a high-speed serial bus. In FIG. 18, a high-speed serial bus 1 is connected to a plurality of node devices 21 by serial bus cables ₁₁ to 1n _{- 1.}
~ 2 _n are serially connected, and each node device 2
_i has a physical layer circuit 4 _i and a link layer circuit 5 _i that perform serial communication protocol control at a hardware level in accordance with an instruction from a higher-level controller 3 _i . The physical layer circuit 4 _i is connected to the serial bus cables 1 _i-1 and 1 _i , and the serial bus cable 1 _i-1 (or 1
_i ), upon receiving a transmission signal transmitted from another node device, transmits the same transmission signal to the serial bus cable 1 _i.
(Or 1 _i-1 ), converts the data into received data, and outputs it to the link layer circuit 5 _i . Further, when inputs transmission data from the link layer circuit 5 _i, into a transmission signal, and outputs to the serial bus cable 1 _i and 1 _i-1.

[0004] The link layer circuit 5 _i in accordance with an instruction of the controller 3 _i higher, generates a transmission packet addressed to another node device, and outputs the transmission data constituting the transmission packet to the physical layer circuit 4 _i. Specifically, 125 case of isochronous packet transfer is guaranteed in microseconds cycle, data length, channel number, when receiving the header information and the actual data comprising a synchronization code from the controller 3 _i, the error determined by calculation An isochronous packet of a predetermined format consisting of an integer multiple of 4 bytes is generated while adding detection header CRC (cyclic redundancy check) data, data CRC data, and the like (see FIG. 19), and two bits from the beginning (100 Mbit / s). s), 4 bits (at a transfer rate of 200 Mbit / s), or 1 byte (at a transfer rate of 400 Mbit / s) is output to the physical layer circuit 4 _i . I do. In the case of an asynchronous packet transferred asynchronously, the node ID of the destination node device is used instead of the channel number.
(Destination ID) and the node ID of the transmission source node device (transmission source ID) are added to the header, and the like (see FIG. 20).

The link layer circuit 5_iIs the physical layer
Circuit 4_iWhen receiving data from
The received packet to be inserted is taken out and the header CRC data
Data and error detection data such as CRC data
Determines whether there is an error and if there is no error, the controller
3_iOutput to For example, whether there is a header CRC error
Is the header calculated from each byte data that makes up the header.
Header CRC value added to the header
Data CRC error.
The presence / absence is determined from each byte data constituting the data block.
The calculated data CRC value is added to the data block.
Is determined based on whether the data matches the CRC data
You. Link layer circuit 5_iAnd physical layer circuit 4_iIs three
Control signal data via the control lines CTL0, CTL1, and LReq.
8 data lines D while handshaking₀~ D
₇Of which, D₀And D₁Of two (100Mbit / s transfer speed
) Or D₀~ D_Three(200Mbit / s)
Or D₀~ D₇Using 8 lines (400Mbit / s or more)
Send and receive communication data or reception data. Physical layer circuit
4 _iPerforms bus arbitration during transmission,
5_iTo control signal data and transmission / reception data
It also has a function of outputting a synchronized clock SCLK.

Various nodes connected to a high-speed serial bus
A serial bus tester for testing the operation of
Has been issued. This serious bus tester is shown in FIG.
No. 2 _nAs shown in the figure, one node
Devices are connected via a bus.
Bus test controller 3_n,Link
Layer circuit 5_n, Physical layer circuit 4_n, Memory 10, table
It has a display device 11, an operation panel 12, and the like. example
For example, if no isochronous transfer is
Device 2₁If you want to perform a test of
Equipment 2₁Test data and nodes used for testing
Equipment 2₁Is the channel number for isochronous transfer,
Node device 2₁Node ID, serious bus tester 2_n
Is stored.

[0007] The node device 2 on the operation panel 12₁Data
When the transfer is instructed, the controller 3 _nRefers to memory 10
The transfer speed (here, 100 Mbit / s),
Device 2₁Destination ID, which is the node ID of
Tester 2_nSource ID, async
Header information including the data length of the NAS packet and the data
The actual data including the transfer instruction is transferred to the link layer circuit 5_nOutput to
I do. Link layer circuit 5_nIs the header CRC data,
Format while adding data CRC data, etc.
A synchronous packet (see FIG. 20) is generated.
Also, the physical layer circuit 4 through the control line LReq_nHigh
Request for the right to use the high-speed serial bus 1 and the transfer rate
Know, physical layer circuit 4_nAccess to the high-speed serial bus
Wins arbitration for access and transfers are permitted through control lines CTL0 and CTL1
, The link layer circuit 5 _nIs the clock SCLK.
(CTL0, CTL1) = (0
1), data line D₀~ D₇Are all 0, and then
The data line D is synchronized with the clock SCLK.₀And D₁Using
Divided into 2 bits from the beginning of the asynchronous packet
The transmitted data to the physical layer circuit 4_nOutput to (this
When the link layer circuit 5_nIs (CTL0, CTL1) = (10)
Output indicates that transmission data is being output.
).

The physical layer circuit 4 _n to which the transmission data is input
Converts the signal into an electrical transmission signal according to a standard and outputs the signal to a high-speed serial bus. Link layer circuit 5 _n has finished transmitting data output of one packet, when the packet to be transmitted to the other is not, the link layer circuit 5 _n completion transmitted to the (CTL 0, CTL1) from (10) (00) The physical layer circuit 4 _n receives the signal and shifts to another process.

[0009] When transmitting the transmission signal of isochronous packet node device 2 ₁ receiving a transmission signal of the asynchronous packet transmitted from the serial bus tester 2 _n is at a transfer rate of 100Mbit / s at a constant period, all other node device ₂ 2-2 physical layer circuit 4 ₂ to 4 _n receives the _n, the link layer circuit 5 ₂ to 5 _n to convert the received data
And outputs (in this case, indicates that the physical layer circuit 4 ₂ to 4 _n is the received data output by outputting via the control line CTL 0, CTL1 and (CTL0, CTL1) = (10 )).

[0010] link layer circuit 5 ₂ to 5 _n, the control line CT
When control signal data indicating that the reception data is being output appears on L0 and CTL1, the reception data is input in synchronization with the clock SCLK, the type of the packet is analyzed, and since the packet is an isochronous packet, the channel included in the header is included. Check whether the number has been instructed to be received from the upper controller. Unless instructed, the received packet is ignored. If instructed, the header and data CRC data are used to check whether there is an error in the header and the data block. Output to the controller. In the serial bus tester 2 _n , the channel number included in the header has been specified to be received in advance by the controller 3 _n , and when there is no error in the header and the actual data, the link layer circuit 5 _n switches to the node device 2 _1. the packet received from the output to the controller 3 _n, the controller 3 _n is to be stored in the memory 10. Each time the isochronous packet is repeatedly received from the node device 2 _1, the same processing is repeated.
If display is instructed on the operation panel 12, the controller 3
_n indicates the received packet stored in the memory 10
1 and the operator can check.

Here, when testing a node device connected to the high-speed serial bus 1, it is necessary to check whether the node device under test is transmitting and receiving packets correctly. 1 must be monitored for all packets transmitted. Some link layer circuits have a snoop function that captures all received packets from the received data sequence input from the physical layer circuit and outputs them to the controller. If you try to send the desired packet to the device,
An extremely high processing speed is required, and the configuration burden is large. Further, since packets transmitted by the snoop function of the link layer circuit do not include transmission packets, all packets transmitted on the serial bus cannot be monitored in chronological order.

In view of this point, the inventor of the present application has invented a serial bus tester which is capable of monitoring all packets transmitted on the high-speed serial bus 1 in a time-series order with a simple configuration (Japanese Patent Application No. 2002-214,197). Hei 10-1224099). This serial bus tester extracts data transmitted and received between the physical layer circuit 4 _n and the link layer circuit 5 _n as shown by reference numeral 2 _n in FIG.
Is provided with a packet fetching circuit 32 for writing the data into the. After the start of the serial bus test, the packet capturing circuit 32 transmits / receives data between the physical layer circuit 4 _n and the link layer circuit 5 _n , and outputs a desired reference packet set in the reference packet setting circuit 27 by the controller 3 _n in advance. A series of data having a certain time relationship is extracted from the designated data and stored in the capture memory 30. After a while
Fast, the controller 3 _n for testing serial bus 1 is intended for the capture memory 30 the packet type, transmission speed, the length of the packet, a channel number, transmission destination ID, source ID, whether the header CRC error, the data CRC Various analyzes such as the presence / absence of an error are performed, the analysis result is stored in the memory 10, and the analysis result and the contents of the packet are displayed on the display device 11.

[0013]

By the way, in recent years, a large amount of moving image data (MP
EG1, MPEG2) based on the standard called MPEG-TS (Empeg Transport Stream)
The data is transferred to a personal computer or a digital video recorder using a serial bus of E1394, or is based on IEEE 1394 based on a standard called SBP-2 (serial bus protocol 2).
In many cases, an optical disk device or a hard disk device is accessed via a serial bus. MP
In EG-TS, consistency with the standard cannot be evaluated unless data in a unit much larger than a packet is collected.
Even with the BP2, it is not possible to evaluate the consistency with the standard unless the packets transmitted through the serial bus are collected for a long time.

For this reason, the capture memory 30 shown in FIG.
It was necessary to use a large capacity of several tens of Mbytes or more. In this case, after fetching the data into the capture memory 30, the controller 3 _n for the serial bus test is used.
However, it takes a long time to analyze the packets in the capture memory 30, and it takes several to ten and several minutes to display the analysis result of the desired packet. The present invention has been made in view of the above-mentioned problems of the prior art,
It is an object of the present invention to provide a serial bus tester that can quickly analyze data taken into a capture memory.

[0015]

In the serial bus tester according to the first aspect of the present invention, the serial bus tester is connected to a serial bus.
A physical layer circuit that receives a transmission signal of a packet transmitted from another node device transmitted on the serial bus and converts it into reception data, or converts transmission data into a transmission signal and outputs it on the serial bus; Generates a transmission packet addressed to another node device according to the instruction of the controller for the serial bus test connected to the layer circuit, and outputs transmission data constituting the transmission packet to the physical layer circuit together with control signal data for handshake. A link layer circuit that inputs received data from a physical layer circuit together with control signal data for handshake, extracts a predetermined received packet, and outputs the packet to a controller for a serial bus test, and a link layer circuit between the physical layer circuit and the link layer circuit. Capture memory for temporarily storing data to be transmitted and received, and link to physical layer circuit A data extraction / write circuit which is connected to a signal line connecting the ear circuits, extracts data transmitted / received between the physical layer circuit and the link layer circuit, and writes the data into a capture memory. In a serial bus tester that performs a desired test process on a packet written to a capture memory, an index memory for temporarily storing index information of a packet temporarily stored in a capture memory, and a data extraction / write circuit, The packet is determined while inputting the data extracted by the data extraction / writing circuit and the write position to the capture memory, and the index information including the type of the packet and the storage position on the capture memory is analyzed. Is stored in the index memory. When performing a desired test process on a packet written in the capture memory, the controller for the serial bus test first performs an index for each packet stored in the index memory. A desired packet is searched for information to obtain index information, a storage position of the desired packet on the capture memory is determined, and data of the desired packet is read from the capture memory. . According to the first aspect, in parallel with the data extracting / writing circuit extracting data transmitted and received between the physical layer circuit and the link layer circuit and writing the data in the capture memory, the index information analyzing circuit determines the type of the packet. The index information including the storage position on the capture memory is analyzed, and the index information is stored in the index memory for each packet. Therefore, when the data has been fetched into the capture memory, the index information has already been analyzed, so the controller for the serial bus test refers to the index memory to quickly search and read the data of the desired packet in the capture memory. As a result, desired processing for a test can be quickly performed on a desired packet. In particular, when it is desired to perform an analysis process on a desired packet in the capture memory, only the items that have not been analyzed by the index information analysis circuit need to be analyzed, and the entire analysis process can be performed promptly. In the serial bus tester according to claim 8 of the present invention, the serial bus tester is connected to the serial bus, receives a packet transmission signal transmitted from the other node device transmitted on the serial bus, converts the packet transmission signal into reception data, and transmits the transmission data. A physical layer circuit that converts the data into a transmission signal and outputs it on the serial bus, and generates a transmission packet addressed to another node device according to the instruction of the external controller for the serial bus test connected to the physical layer circuit and transmits the packet. A transmission data sequence forming a packet is output to the physical layer circuit together with control signal data for handshake, or a reception data sequence is input from the physical layer circuit together with control signal data for handshake, and a predetermined reception packet is extracted. A link layer circuit for outputting to an external controller for a serial bus test, and a cap for temporarily storing data. And Yamemori, is connected to a signal line connecting the physical layer circuit and the link layer circuit, it extracts the data transmitted and received between the physical layer circuit and the link layer circuit,
A data extraction / write circuit for writing to the capture memory, wherein the external controller for serial bus test can perform a desired test process on the packet written to the capture memory. An index memory for temporarily storing the index information of the packet temporarily stored in the memory, and a packet is determined while inputting the data extracted by the data extraction / write circuit and the write position to the capture memory from the data extraction / write circuit. An index information analysis circuit that analyzes the index information including the type of packet and the storage position on the capture memory, and stores the index information in the index memory for each packet. The box information external controller for serial bus test is characterized, it has freely read. According to the eighth aspect, in parallel with the data extracting / writing circuit extracting data transmitted / received between the physical layer circuit and the link layer circuit and writing the data in the capture memory, the index information analyzing circuit determines the type of packet and The index information including the storage position on the capture memory is analyzed, and the index information is stored in the index memory for each packet. Therefore, when the data has been taken into the capture memory, the index information has already been analyzed, so the external controller for the serial bus test refers to the index memory to quickly search and read the data of the desired packet in the capture memory. As a result, desired processing for a test can be quickly performed on a desired packet. In particular, if you want to analyze the desired packet in the capture memory,
Only the items that have not been analyzed by the index information analysis circuit need be analyzed, and the entire analysis process can be performed quickly. 9. The serial bus tester according to claim 1, wherein the data extracting / writing circuit transmits / receives data between the physical layer circuit and the link layer circuit after a desired reference timing, before a reference timing, or before or after a reference timing. May be extracted and written to the capture memory. This makes it possible to easily perform a test for a desired time range, such as immediately after starting the desired operation of the node device to be tested, immediately before starting the desired operation, or before and after starting the desired operation. Claim 1,
9. The serial bus tester according to claim 8, wherein the data extraction / write circuit is transmitted and received between a physical layer circuit and a link layer circuit, wherein the reference packet specification data setting circuit sets data specifying a reference timing packet. A comparison circuit for comparing the extracted data with the reference packet designation data, and using the time when the extracted data and the reference packet designation data match as a reference timing, after the reference timing, before the reference timing, or before or after the reference timing, the physical layer circuit and the link layer. Data transmitted and received between circuits may be extracted and written to the capture memory. Thereby, the reference timing for testing the desired time range can be accurately determined. 9. The serial bus tester according to claim 1, wherein the controller for serial bus test or the external controller for serial bus test analyzes a result of analyzing an arbitrary packet stored in the capture memory. It may be added to the index memory as packet index information. As a result, for a packet that has already been analyzed by the controller for serial bus test or the external controller for serial bus test,
When you search again later, you can quickly get the results of the first analysis. 9. The serial bus tester according to claim 1, wherein the index information analyzed by the index information analysis circuit includes a part of the header information of the packet in addition to the type of the packet and the storage position on the capture memory. All or packet transfer speed, or
The presence or absence of a packet error may be included.

[0016]

Next, one embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of a serial bus test system including a serial bus tester according to the present invention, and the same components as those in FIG. The node devices 2 ₁ , 2 ₂ ,... And the serial bus tester (functioning as one of the node devices) 20 _n are connected by the high-speed serial bus 1. Among the serial bus testers 20 _n , reference numeral 70 denotes a capture memory having a storage capacity of, for example, several tens of megabytes, which can store data for one unit at each of (M + 1) addresses from address 0 to address M. And Here, (M + 1) is a multiple of 2 and the data of one unit is 11 bits long here. The capture memory 70 stores a large amount of packet data exchanged between the physical layer circuit 4 _n and the link layer circuit 5 _n in a time series in association with the control signal data CTL0, CTL1, and LReq (see FIG. 5). ).

Reference numeral 60 denotes a data extraction / write circuit.
Is connected to various signal lines connecting between the link layer circuit 5 _n and the physical layer circuit 4 _n, it extracts all data exchanged between the link layer circuit 5 _n and the physical layer circuit 4 _n, capture memory 70 Write to. Data includes 8-bit data lines D ₀ to D ₇ here the data extraction and write circuit 60 extracts the control line CTLO, CTL1, LR
This is 3-bit control signal data of eq. The data extraction / write circuit 60 manages the write address CRA of the capture memory 70 by a built-in write address counter (not shown), and outputs write address data CRA together with data when performing one write. After the data is written to the address indicated by the write address data CRA, the write address CRA is incremented (the initial value of the write address is 0, and after reaching M, it returns to 0). The data extracting / writing circuit 60 extracts the extracted data and the write address CR.
It also has the function of outputting A externally.

The data extracting / writing circuit 60 is specifically configured as shown in FIG. 2 in FIG.
Is a register circuit, and includes three 11-bit parallel registers (hereinafter simply referred to as registers) 62, 63, and 64
Are connected in series. Input side and eight data lines D ₀ to D ₇ from the lower side of the register 62, the control line CTL 0, CTL
1, three LReq are connected. Register 62 D ₀ to D ₇ and CTL0 are every time inputting a clock SCLK, CTL1, LR
Import and output eq simultaneously. The register 22 outputs the D signal output from the register 62 every time the clock SCLK is input.
₀ to D ₇ and CTL 0, CTL1, simultaneously takes in and outputs the LReq. Each time the clock SCLK is input, the register 64 outputs D _{0 to} D ₇ and CTL 0, CTL 1,
Simultaneously capture and output LReq. Therefore, the data line D
₀ to D ₇ and the control line CTL 0, CTL1, each bit data of LReq is sequentially transferred from the register 62 to 64.

Reference numeral 65 denotes a transfer speed identification circuit,
The output of the register 64 is monitored.
Of the outputs of₀~ D₇CTL0 and CTL1
Apart from the output of the register 64, when transmitting a packet, LR
Identify the transfer rate from eq. That is, the physical layer circuit
4_nReceives the transmission signal from the high-speed serial bus 1 and
When outputting received data in synchronization with the clock SCLK,
Change (CTL0, CTL1) from (00) to (10)
The clock SCLK (D₀~ D ₇) =
(11111111) = (FF)₁₆After outputting
Outputs the transmission speed code, and then the destination of the received packet
Output received data from the head. Transfer at 100 Mbit / s
The speed code is (D₀~ D₇) = (00xxxxxx),
For 200 Mbit / s, the transfer rate code is (D₀~ D₇) =
(0100xxxx), 400Mbit / s, transfer speed
Mode is (D₀~ D₇) = (01000000)
(X is set to 0 and the link layer circuit 5_nIgnored by
).

In the case of 100 Mbit / s, the received data is D ₀ and D
Outputs 2 bits at a time using ₁ and at 200 Mbit / s,
Received data is output 4 bits by using the D ₀ to D _3, the case of 400 Mbit / s, the received data is output 8 bits using D ₀ to D _7. The transfer rate identification circuit 65 monitors CTL0 and CTL1 output from the register 64,
When (CTL 0, CTL1) is changed to (00) from (10), then, (D ₀ to D ₇₎ is (FF) identifies the transfer rate from the value of ₁₆ from the unusual first (D ₀ to D ₇₎ Then, it immediately outputs the transfer speed identification data to the byte position detection circuit and the pattern detection circuit described later.

When the link layer circuit 5 _n attempts to transmit a packet, the link layer circuit 5 _n outputs a transmission request and a transfer rate data to the physical layer circuit 4 _n via a control line Req in advance. Transfer speed identification circuit 6
5 monitors Req output from the register 64,
When the transfer rate data is input together with the transmission request, the transfer rate is identified, and then (CTL0, CTL1) is changed from (00) to (0).
At the time when the data is changed to 1), the transfer speed identification data is output.

Reference numeral 66 denotes a byte position detection circuit. Based on CTL0 and CTL1 output from the register 64 and the transfer speed identification data input from the transfer speed identification circuit 24, what byte of the transmission packet or the reception packet is D _{0 of the} register 64. ~ D
Detect whether it is output from ₇ . Specifically, (CTL
0, CTL1) when inputting the transfer speed identification data in a state of change in the (00) from (10), the head of the reception of the received packet from D ₀ to D ₇ of the register 23 upon receiving the next clock SCLK Data is output. Therefore, if the transfer rate is 100 Mbit / s, the count value K initialized to −1 when (CTL0, CTL1) changes from (00) to (10), and after inputting the transfer rate identification data, clock
Each time SCLK is input, the count is incremented by +1 and a value obtained by adding +1 to a quotient q obtained by dividing the count value K by 4 is output as byte position detection data.

If the transfer rate is 200 Mbit / s, (CTL0,
When (CTL1) changes from (00) to (10), the count value K initialized to −1 is incremented by +1 each time the clock SCLK is input after the transfer speed identification data is input, and the count value is counted. The quotient q obtained by dividing the value K by 2
Is output as byte position detection data.
If the transfer rate is 400 Mbit / s, (CTL0, CTL1)
When the transfer rate identification data is input, the count value K initialized to -1 at the time when the count value changes from 0) to (10) is incremented by +1 each time the clock SCLK is input, and the count value K is incremented by +1. The value obtained is output as byte position detection data.

Conversely, when the transfer speed identification data is input at the time when (CTL0, CTL1) changes from (00) to (01), the time when (CTL0, CTL1) changes from (01) to (10) in the beginning of the transmission data of the transmission packet from D ₀ to D ₇ of the register 23 is output. Therefore, (CTL0,
When the transfer rate identification data is input when (CTL1) changes from (00) to (01), (CTL0, CTL1) becomes (0).
After the count value K is initialized to zero at the time of the change from 1) to (10), if the transfer speed is 100 Mbit / s, each time the clock SCLK is input, the count value is incremented by +1 and the count value K is increased. The value obtained by adding +1 to the quotient q divided by 4 is output as byte position detection data. Transfer speed 200M
bit / s, (CTL0, CTL1) changes from (01) to (1
After the count value K is changed to 0), the count value K is initialized to zero. Then, each time the clock SCLK is input, the count value is incremented by +1 and the quotient q obtained by dividing the count value K by 2 is incremented by +1.
The value obtained is output as byte position detection data. If the transfer rate is 400 Mbit / s, the count value K is initialized to zero when (CTL0, CTL1) changes from (01) to (10), and then the count is incremented by +1 each time the clock SCLK is input. At the same time, the count value K is output as byte position detection data. The byte position detection circuit 66
Outputs the data output strobe signal ST at a timing T / 2 has elapsed after changing the output of the byte position detection data, where T is the cycle of the clock SCLK. Also,
The byte position detection circuit 66 sets the byte position detection data to zero when (CTL0, CTL1) is (00).

Reference numeral 67 denotes a pattern detection circuit, which has a byte position.
The transmission packet or the reception packet detected by the
Output 8-bit pattern at byte position in packet
I do. The pattern detection circuit 26 has a transfer speed indicating 100 Mbit / s.
After inputting the degree identification data, the output of the register 64
D₀And D₁To d₀And d₁, The output D of the register 63₀And D
₁To d_TwoAnd d_Three, The output D of the register 62₀And D₁To d_Four
And d_Five, Link layer circuit 5_nOutput D₀And D₁To d₆
And d₇As (d₀d₁d_Twod_Threed _Fourd_Fived
₆d₇) And output in parallel, 8 bits
Output byte data (here, 100 Mbit / s
At this time, the MSB of each byte data constituting the packet, 2
SB, 3SB, 4SB, 5SB, 6SB, 7SB, LS
B is 2 bits at a time, (D₀D₁) = (MSB2S)
B), (D₀D₁) = (3SB4SB), (D₀D₁)
= (5SB6SB), (D₀D₁) = (7SBLSB)
Physical layer circuit 4_nAnd link layers
Circuit 5_nBetween the two).

The pattern detection circuit 67 operates at 200 Mbit / s
Is input, the outputs D _{0 to} D ₃ of the register 64 are extracted as d ₀ to d ₃ , and the outputs D _{0 to} D ₃ of the register 63 are extracted as d ₄ to d ₇ , and (d ₀ d
₁ d ₂ d ₃ d ₄ d ₅ d ₆ d ₇ ) are arranged in parallel and output in parallel to output 8-bit pattern data (here, when 200 Mbit / s, the MSB of each byte data constituting the packet) , 2SB, 3SB, 4SB, 5S
B, 6SB, 7SB, and LSB are 4 bits each, (D ₀
D ₁ D ₂ D ₃ ) = (MSB2SB3SB4SB), (D
₍₀ D ₁ D ₂ D ₃ ) = (5SB6SB7SBLSB), and the data is transferred between the physical layer circuit 4 _n and the link layer circuit 5 _n .)

Further, the transfer speed identification data indicating 400 Mbit / s
Input from the register 64, the output D₀~ D₇
To d₀~ D₇As (d₀d₁d_Twod_Threed_Four
d_Fived₆d₇) In parallel to output 8 bits
Output pattern data (here, 400Mbit / s
, The MSB of each byte data constituting the packet,
2SB, 3SB, 4SB, 5SB, 6SB, 7SB, L
SB is (D₀D₁D _TwoD_ThreeD_FourD_FiveD₆D₇) = (M
SB2SB3SB4SB5SB6SB7SBLSB) and
Physical layer circuit 4_nAnd link layer times
Road 5_nBetween the two).

Reference numeral 80 denotes a reference packet setting circuit. The controller 30 _n sets data for designating a reference packet when a desired series of packets is taken out of the high-speed serial bus 1. Here, as an example, it is assumed that one or a plurality of combinations of byte positions in a packet and 1-byte data at the byte positions are set. When a plurality is set, the order is the byte position (see FIG. 3). Reference numeral 68 denotes a collating circuit, and a byte position detecting circuit 66
Position detection data and pattern detection circuit 6 output by
7 is fetched when the data output strobe signal (ST) is input from the byte position detection circuit 66, and the fetched byte position detection data and byte data are transferred to the byte set by the reference packet setting circuit 80. The position and the combination of the one-byte data at the byte position are checked to see if they match, and when they all match in the order set by the reference packet setting circuit 80, the reference packet detection signal is sent to the data extraction / write control circuit and the index information analysis described later. Output to the circuit.

Reference numeral 69 denotes a data extraction / write control circuit, which internally has a write address counter (not shown) which is incremented in synchronization with the clock SCLK.
Control signal lines and the data lines D ₀ to D ₇ which are output in synchronization with
CTL0, CTL1, LReq 11-bit data (DATA)
In the capture memory 70, a write address (CRA) specified by a write address counter is written.

When the serial bus tester 20 _n is in an operating state, the data extraction / write control circuit 69
TA is written to the capture memory 70 in order from address 0 (after writing to address M, return to address 0 and continue writing). In the case of (trigger signal start mode), the writing is completed when (M + 1) pieces of data have been written since the reference packet detection signal was input from the matching circuit 68 (or the trigger signal was input from the controller). And outputs a capture end signal to an index information analysis circuit described later. In the case of the reference packet stop mode (or trigger signal stop mode), when the reference packet detection signal is input from the matching circuit 68 (or when the trigger signal is input from the controller), the writing is completed and the capture end signal is output. . In the case of the reference packet step-over mode (or the trigger signal step-over mode), from the time when the reference packet detection signal is input from the matching circuit 68 (or the time when the trigger signal is input from the controller), the (M + 1) / 2 data DATA At the time of writing, the writing is completed and a capture end signal is output.

Register circuit 61, transfer speed identification circuit 6
5, byte position detection circuit 66, pattern detection circuit 67,
The collation circuit 68 and the data extraction / write control circuit 69 constitute a data extraction / write circuit 60.

Reference numeral 90 denotes an index memory capable of storing analysis information for each packet and management information of the index memory for a large number of packets. The index memory 90 stores, for each packet, a serial number, a packet type, a packet length, a transfer speed, a channel number (in the case of an isochronous packet), a destination ID (in the case of an asynchronous packet), and a transmission source ID (in the case of an asynchronous packet). ), Packet start capture memory address, packet end capture memory address, primary items (primary items correspond to index information in this embodiment), packet header CRC error, and data CR.
Storage areas PF _{0 to} PF _N (N is 1000) for storing secondary items of time stamps indicating presence / absence of a C error and a time difference from a predetermined reference timing, progress of analysis, and preliminary information (annotation information input by a user). (A sufficiently large integer above) (see FIG. 4).

At the end of the index memory 90, the management information
The information storage area RF is provided.
Index information about the packet
Storage area PF_ZStart address AD_Z, Capture notes
Index of the oldest packet in the repository 70
Storage area PF in which information is stored_SStart address A
D _S, The newest packet in the capture memory 70
Storage area PF in which index information about
_EStart address AD_EIs stored.

Reference numeral 91 denotes an index information analysis circuit.
11-bit data DATA output from the data extraction / write control circuit 69 of the data extraction / write circuit 60
And a write address CRA to determine the packet and analyze the packet, the packet type, packet length, transfer speed, channel number (for isochronous packet), destination ID (for asynchronous packet), source ID (in the case of an asynchronous packet),
The analysis results of the packet start capture memory address and the packet end capture memory address (primary items) are stored as index information together with the serial number of the packet in the storage areas PF _{0 to} PF _N of the index memory 90.
In a packet unit.

When the serial bus tester 20 _n is in the operating state, the index information analysis circuit 91 extracts and extracts data.
Although it intended to make write from the head of the storage area PF ₀ analysis and index memory 90 of the determination and the index information of the packet based on the data DATA and write address CRA inputted from the write control circuit 69 (to the end of the storage area PF _N After writing, the first storage area PF ₀
If the reference packet start mode (or trigger signal start mode) is selected according to the capture mode set by the controller, the matching circuit 68 outputs the reference packet detection signal (or the trigger signal from the controller). A certain period of time from the time of input (9 (M + 1) data
The analysis result of the data DATA and the write address CRA input from the data extraction / write control circuit 69 during the time required to store the divided portion is stored in the index memory 90, and the reference packet stop mode (or the trigger signal stop mode) ) And the reference packet step-over mode (or the trigger signal step-over mode), a predetermined time ((M + 1) packets are stored in the capture memory 70 until the reference packet detection signal (or the trigger signal from the controller) is input from the matching circuit 68. During the time required to store the data, the data DATA input from the data extraction / write control circuit 69 and the analysis result of the write address CRA are stored in the index memory 90.

The index information analysis circuit 91 is based on
Quasi-packet start mode (or trigger signal start
Mode), the matching circuit 68 detects the reference packet.
Signal (or trigger signal from controller) input
At this time, the data
Index analyzed for packets containing data DATA
Storage area PF in which information is stored_iStart address A_(i)
AD_SAnd AD_ZAs, and data extraction and writing
Immediately before the capture end signal is input from the
The index information of the analyzed packet is stored in
Storage area PF _jStart address A_(j)AD_EAs
It is stored in the management information storage area RF.

In the reference packet stop mode (or trigger signal stop mode), a storage area PF in which index information of a packet that has been analyzed immediately before the capture end signal is input from the data extraction / write control circuit 69 is stored. _i start address a to _(i) as AD _E and AD _z, also, of the capture memory 70, the next address after the write address CRA you entered from the data extraction and write control circuit 69 at the time of the input capture end signal Of the packets whose index information is first written in the index memory 90 and whose analysis progress data has been analyzed for the primary items, is a storage area where the index information is stored for the packets whose primary item has been analyzed. management information storage area RF PF _k start address a to _(k) as AD _S For storage.

In the reference packet step-over mode (or trigger signal step-over mode), when the reference packet detection signal (or the trigger signal from the controller) is input from the matching circuit 68, the data is input from the data extraction / write control circuit 69. The start address A _(i) of the storage area PF _i in which the index information analyzed for the packet including the data DATA therein is stored as AD _Z , and immediately before the capture end signal is input from the data extraction / write control circuit 69. the start address of the memory storage area PF _j index information of a packet having been subjected to analysis a with _(j) as AD _E, further, among the capture memory 70, data extraction and write control circuit upon receiving the capture end signal Next address of write address CRA being input from 69 Among the packets that have already been stored, the index information is first written in the index memory 90, and the analysis progress data is the storage of the index information for the packets whose primary item has been analyzed. Start address A of area PF _k
(k) is stored in the management information storage area RF as AD _S.

Reference numeral 10 denotes a memory, which stores programs and data necessary for an evaluation test of the node device. The memory 10 also stores packets transmitted to the serial bus tester 20 _n during the evaluation test. Reference numeral 11 denotes a display device for displaying the results of the evaluation test. Reference numeral 12 denotes an operation panel, which is used to select a capture mode for performing the evaluation test, set data for designating a reference packet, and instruct display of the evaluation test result. Do.

Reference numeral 30 _n denotes a controller for a serial bus test, which is constituted by, for example, a microcomputer. The controller 30 _n performs an evaluation test of a desired node device using an evaluation test program and data stored in the memory 10 in accordance with an instruction from the operation panel 12 by the operator.
Specifically, in order to cause a desired node device to perform a desired operation,
It instructs the link layer circuit 5 _n to transmit a packet addressed to the desired node device, or receives and outputs a packet transmitted from the desired node device to the serial bus tester 20 _n and stores it in the memory 10. Then, the contents of the received packet stored in the memory 10 are displayed according to the instruction of the worker. Also, during a certain time, the high-speed serial bus 1
In order to capture all the packets transmitted over the data, a capture mode is set for the data extraction / write circuit 60 and the index information analysis circuit 91, a trigger signal is output, and designated data of the reference packet is set. Further, for a predetermined amount of continuous packets stored in the capture memory 70, items other than the analysis target of the index information analysis circuit 91 are analyzed, and the analysis results of the index information analysis circuit 91 are added to the display device 11.
To be displayed. The other components of the serial bus tester 20 _n are configured exactly the same as in FIG.

Next, the operation of the above embodiment will be briefly described with reference to FIGS. 5 to 7 are explanatory diagrams of the storage contents of the capture memory 70, FIGS. 8 to 9 are explanatory diagrams of the storage contents of the index memory 90, and FIG. 10 is a diagram illustrating the storage contents and the index of the capture memory 70 in the reference packet step-over mode. FIG. 11 is an explanatory diagram showing the relationship between the storage contents of the memory 90 and FIG. 11 is an explanatory diagram showing the relationship between the storage contents of the capture memory 70 and the index memory 90 in the reference packet start mode.
Is the capture memory 7 in the reference packet stop mode
FIG. 13 is an explanatory diagram showing the relationship between the storage content of 0 and the storage content of the index memory 90. FIG. 13 is an explanatory diagram showing the relationship between the storage content of the capture memory 70 and the storage content of the index memory 90 in the trigger signal step-over mode. FIG. 14 is an explanatory diagram showing the relationship between the storage contents of the capture memory 70 in the trigger signal start mode and the storage contents of the index memory 90. FIG. FIG. 4 is an explanatory diagram showing a relationship with stored contents. Here, it is assumed to perform the operation test of the node devices 2 _1, high-speed nodes connected to the serial bus 1 device 2 _1, 2 _2, ... and the pre-operational state neither serial bus tester 20 _n is There also channel number data required to test in advance node device 2 ₁ in the memory 10, the node equipment 2 ₁ performs isochronous transfer, the node equipment 2
Node ID of ₁ and node I of serious bus tester 20 _n
It is assumed that D and the like are stored. It is assumed that the link layer circuit 5 _n does not have a snoop function.

(1) Receiving a packet from the high-speed serial bus When the node devices 2 ₁ , 2 _2, etc. output a packet transmission signal on the high-speed serial bus 1, the physical layer of the serial bus tester 20 _n Circuit _4n receives and clocks
In synchronization with SCLK and outputs the received data to the link layer circuit 5 _n. At this time, (CTL0, CTL1) is first changed from (00) to (10), and the data lines D _{0 are provided for} a predetermined number of clocks.
The to D ₇ and (FF) _16, after outputted a next transfer rate data in one clock only the data lines D ₀ to D _7, data lines from the head to synchronize the received packet to the clock SCLK D
_{0 to} D _h (h = 7, 200 Mbit / at 400 Mbit / s transfer rate)
h = 3 for s and h = 1 for 100 Mbit / s). At this time, the physical layer circuit 4 _n outputs (CTL0, CTL1) =
(01) indicates that the receiving data is being output).
Link layer circuit 5 _n is the physical layer circuit 4 _n receives the packet, the control line CTL 0, CTL1 from (00) (10)
, The received data is input in synchronization with the clock SCLK. Then, the received packet specified in advance as a target to be captured by the own node from the controller 30 _n is extracted, and the presence or absence of an error is determined using error detection data such as header CRC data and data CRC data. Output to _n . When the controller 30 _n receives the received packet from the link layer circuit 5 _{n, the} controller 30 _n stores the received packet in the memory 10. And operation panel 1
In accordance with the instruction in 2, necessary processing such as display on the display device 11 is performed. When the physical layer circuit 4 _n finishes receiving data output of one packet, indicating the reception completion to the (CTL 0, CTL1) from (01) (00).

(2) Transmission of packet to high-speed serial bus Conversely, when link layer circuit 5 _n outputs transmission data of a transmission packet addressed to another node device to physical layer circuit 4 _n based on an instruction of controller 30 _n. , Outputs serial stream data to LReq in advance, and outputs the physical layer circuit 4 _n
Request for the right to use the high-speed serial bus 1 and specify the transfer speed. When the physical layer circuit 4 _n wins the arbitration and gives the transfer permission by setting (CTL0, CTL1) to (11) for one clock, the link layer circuit 5 _n (CTL0, CTL1)
The transmission packet is prepared while setting (01) for a certain predetermined clock to (01) and (D _{0 to} D ₇ ) to (00) _16.
0, CTL1) as (10) and transmit packet as clock SCL
Data lines from the head in synchronism with the K D ₀ ~D _h (transfer rate 4
H = 7 at 00Mbit / s, h = 3,100 at 200Mbit / s
At the time of Mbit / s, h = 1) is output (at this time, the link layer circuit 5 _n sets (CTL0, CTL1) = (10) to indicate that transmission data is being output). The physical layer circuit 4 _n to which the transmission data has been input is converted into an electrical transmission signal in accordance with the standard and output to the high-speed serial bus 1. The link layer circuit 5 _n finishes outputting one packet of transmission data,
When there is no other packet to be transmitted, the link layer circuit 5 _n changes (CTL0, CTL1) from (10) to (00) to indicate transmission completion, and upon receiving the signal, the physical layer circuit 4 _n performs other processing. Move to

By the way, the link layer circuit 5 _n which does not have a snoop function is unable to capture all of the received packets based on the received data input from the physical layer circuit 4 _n. In this embodiment, the capture memory 7
0 and the data extraction / write circuit 60, a series of desired large amount of packets transmitted on the high-speed serial bus 1 can be captured, and the index memory 90 and the index information analysis circuit 91 The analysis of the fetched packet is performed in parallel with the fetching operation of the packet.

That is, during the operation of the serial bus tester 20 _n , in the data extraction / write circuit 60, the data lines D _{0 to} D ₇ transmitted and received between the physical layer circuit 4 _n and the link layer circuit 5 _n are connected. 8 bits and control lines CTLO, CTL1,
The 11-bit data including the 3-bit control signal data of LReq is sequentially transferred from the registers 62 to 64 in synchronization with the clock SCLK, and output to the data extraction / write control circuit 69. Data extraction / write control circuit 69
Synchronously writes 11-bit data output from the register 64 as data DATA in the capture memory 70 in order from the head address 0 in synchronization with the clock SCLK.
After reaching the address M, the operation of returning to the head address and writing again in order is repeated. When the transfer rate data is output from D _{0 to} D ₇ of the register 64 when receiving the packet, or when the transfer rate data is output from LReq of the register 64 when transmitting the packet, the transfer rate identification circuit 65 determines the transfer rate. The data is identified and output to the byte position detection circuit 66 and the pattern detection circuit 67.

On the other hand, while the serial bus tester 20 _n is operating, the index information analysis circuit 91 receives the 11-bit data DATA and the write address CRA output from the data extraction / write control circuit 69 and analyzes them in real time. To determine the type of packet, the packet type, packet length, transfer speed, channel number (for isochronous packet), destination ID (for asynchronous packet), source ID (for asynchronous packet), packet The analysis result (primary item) of the first capture memory address and the packet end capture memory address and the analysis progress data indicating that the primary item has been analyzed and the secondary item has not been analyzed are represented by the serial number of the packet (initial value). The value is the first storage area of the index memory 90 together with 1). PF ₀ will be written in the order on a packet-by-packet basis from, and after reaching the end of the storage area PF _N is repeating the operation of writing to order again back to the top of the storage area PF _0.

For example, assuming that the writing of the primary item of the packet has progressed to the storage area PF _{i-1 of} the index memory 90 (the serial number written to the storage area PF _i-1 is a). When the physical layer circuit 4 _n receives a transmission signal of a packet from the high-speed serial bus 1 and outputs received data in synchronization with the clock SCLK, first,
Change (CTL0, CTL1) from (00) to (10). The index information analysis circuit 91 outputs the data DATA (CTL0, CTL
1) and LReq are monitored and (CTL0, CTL1) is (00)
It is determined that the preceding part of the received packet has started at the point when the state changes from (10) to (10), and the write address CR at that point is determined.
Writes A as a packet start capture memory address in the storage area PF _i address A _(i) +7. And
The serial number (= a + 1) obtained by adding 1 to the serial number of the packet in the storage area PF _i-1 is written to the address A _{(i )} . (CT
L0, CTL1) is (00) from (10) to the D ₀ to D ₇ of the predetermined number of clocks from the odd time data DATA (F
Since one clock only D ₀ to D ₇ immediately became F) ₁₆ indicates the transfer rate data, writes it to the address A _(i) +3.

Subsequently, when the transfer speed is 400 Mbit / s,
D of data₀~ D₇From (CTL0, CTL1) is (10)
Until just before changing to (00), the main part of the received packet
Are output one byte at a time from the beginning (RA in FIG. 5).₀~ RA
_m), When the transfer speed is 200Mbit / s,₀
~ D_Three(CTL0, CTL1) changes from (10) to (00)
Until immediately before, the body of the received packet is
Are output at the same time (RB in FIG. 5).₀~ RB_m),transfer speed
Is 100Mbit / s, D of data DATA₀And D₁From (CTL
0, CTL1) until just before it changes from (10) to (00)
The body part of the received packet is output two bits at a time from the beginning.
(RC in FIG. 6)₀~ RC_m). Therefore, the index
The information analysis circuit 91 analyzes the main part of the received packet.
And the transaction code (tcode; transa
ction code) to identify the packet type and address
A_(i)Write +1 and the type is isochronous spa
If it is a packet, the channel number in the header is the address
_(i)+4, if it is an asynchronous packet
Each of the destination ID and the source ID in the header is an address A
_(i)+5, A_(i)Write to +6. Then, the receiving packet
Count the length (number of bytes) of the main part of the
_(i)Write +2. Finally, the data DATA (CTL0, CT
When L1) changes from (10) to (00), the reception packet
Is determined to be complete, and the write address at that time is determined.
End of packet capture of address just before CRA
Address A as memory address_(i)Write +8,
Indicates that the primary item has been analyzed and the secondary item has not been analyzed
Analysis progress data at address A _(i)Write +11
No.

For example, if the received packet RA in FIG. 5 is to be analyzed, of the primary items, transfer speed = 400 Mbit / s, packet length = 200 bytes, packet start capture memory address = 111, packet end capture memory Address = 316 (see FIG. 8 (1)). If the received packet RB is to be analyzed, the transfer speed =
200 Mbit / s, packet length = 460 bytes, packet start capture memory address = 350, packet end capture memory address = 1275 (see FIG. 8 (2)). If the received packet RC in FIG. 6 is to be analyzed, 1
Of the following items, transfer speed = 100 Mbit / s, packet length =
600 bytes, packet top capture memory address = 1
301, packet end capture memory address = 37
06 (see FIG. 8 (3); x in FIGS. 5 to 7).
Is 0, but is ignored as data constituting the packet).

Also, assuming that the writing of the primary item of the packet has progressed to the storage area PF _{j-1 of} the index memory 90 (the serial number written to the storage area PF _j-1 is c), the link layer circuit 5 _n even when outputs the transmission data of the transmission packet addressed to the physical layer circuit 4 to _n other nodes devices, index information analyzing circuit 91 is data DA
The TA (CTL0, CTL1), monitors the LReq, when the link layer circuit 5 _n has output a serial stream data to LReq, leave temporarily stores transmission speed in said data, then the data DATA ( (CTL0, CTL1) from (01) to (1
It is determined that the transmission packet has started at the point of time when it changes to 0), and the write address CRA at that point is written to the address A _(j) +7 of the storage area _PFj as the packet start capture memory address. Then, the storage area PF _j-1
Serial number obtained by adding 1 to the serial number of the packet (= c +
1) is written to address A _(j) .

When the transfer speed is 400 Mbit / s, the data
D of data₀~ D₇From (CTL0, CTL1) is (10)
Until just before changing to (00), the main part of the transmitted packet
Are output one byte at a time from the beginning (TA in FIG. 6).₀~ TA
_m), When the transfer speed is 200Mbit / s,₀
~ D_Three(CTL0, CTL1) changes from (10) to (00)
Until immediately before, the main part of the transmitted packet is
Output at each bit (TB in FIG. 7).₀~ TB_m),transfer speed
Is 100Mbit / s, D of data DATA₀And D₁From (CTL
0, CTL1) until just before it changes from (10) to (00)
The body part of the transmitted packet is output two bits at a time from the beginning.
(TC in FIG. 7)₀~ TC_m). Therefore, the index
The information analysis circuit 91 analyzes the main part of the transmission packet.
And the transaction code (tcode) in the header
Address A by identifying the packet type from_(j)+1
And if the type is isochronous packet
If the channel number in the header is address A_(j)Write +4
If the packet is an asynchronous packet,
Address A for each of the destination ID and source ID_(j)+5, A
_(j)Write to +6. And the body part of the transmitted packet
The length (number of bytes) of the address A_(j)Write +2
Get in. Finally, (CTL0, CTL1) of data DATA is (1
Transmission packet ends when it changes from (0) to (00)
It is determined that the write address CRA of the
The previous address is the packet end capture memory address.
Address A as address_(j)+8 is written and the primary item is
Analysis progress indicating that the analysis has been completed and the secondary item has not been analyzed
Address A for status data_(j)Write +11.

For example, if the transmission packet TA in FIG. 6 is to be analyzed, of the primary items, transfer speed = 400 Mbit / s, packet length = 200 bytes, packet start capture memory address = 3862, packet end capture memory Address = 4061 (see FIG. 9 (1)). If the transmission packet TB in FIG. 7 is to be analyzed, among the primary items,
The transfer speed = 200 Mbit / s, the packet length = 460 bytes, the packet start capture memory address = 4122, and the packet end capture memory address = 5042 (see FIG. 9B). If the transmission packet TC in FIG. 7 is to be analyzed, the primary items are as follows: transfer rate = 100 Mbit / s, packet length = 600 bytes, packet start capture memory address = 5125, packet end capture memory address = 7524 (See FIG. 9 (3)).

(3) Capture in Reference Packet Step Over Mode (See FIG. 10) As described above, the data extraction / write circuit 60 transmits various data transmitted and received between the physical layer circuit 4 _n and the link layer circuit 5 _n. Has been written to the capture memory 70,
In a state where the index information analyzing circuit 91 in parallel is the analysis of the index information of the packet written in the capture memory 70, applied to the node device 2 ₁ some desired operation command with an asynchronous packet transfer rate 100Mbit / s Suppose that it is desired to monitor all transmission packets on the high-speed serial bus 1 over a certain time range before and after the transmission. Note that the memory 10 the node ID representing the nodes connected equipment 2 ₁ node ID and serial bus tester 20 _n for high-speed serial bus 1 is assumed to be already stored.

First, when the operator performs the setting operation of the reference packet step-over mode on the operation panel 12, the controller _30n sets the data extraction / write control circuit 69 and the index information analysis circuit 91 to the reference packet step-over mode. Then, as data specifying the reference packet with the operation panel 12, a destination ID and source ID of the asynchronous packet for a desired operation command given to the node device 2 _1, the actual data (here representative of a desired operation command 4 Byte length) input operation. For example, enter the node ID of the node device 2 ₁ as a transmission destination ID, enter the node ID of the serial bus tester 20 _n as a source ID, and inputs the 4-byte data representing a desired operation command as real data. Then, the controller 30
_As shown in FIG. 3, _n is the upper byte and lower byte of the transmission destination ID input by the operator as the first and second bytes of the reference packet, and _n is the upper byte of the transmission source ID. The byte and the lower byte are input as the fifth and sixth bytes of the reference packet, and the first to fourth bytes of the actual data representing the desired operation command are respectively
It is set as the 21st to 24th bytes of the reference packet.

[0055] Thereafter, when the user instructs the transmission of the asynchronous packet for a desired operation command for the node device 2 ₁ worker in the operation panel 12, the controller 30 _n refers to the memory 10, the transfer speed (here, 100Mbit / s to), the node device 2 ₁ destination ID indicating a transmission source ID representing the serial bus tester, the data length of the asynchronous packet, the header information including the synchronization code, the link layer circuit 5 actual data desired operation instruction and outputs to _n, instructing transmission of an asynchronous packet for a desired operation command for the node device 2 _1.

Controller 30_nReceived a transmission instruction from
Link layer circuit 5_nIs header CRC, data CRC
Asynchronous in the specified format while adding
A packet (see FIG. 20) is generated and the control line LR
Physical layer circuit 4 through eq _nTo high-speed serial bus 1
Notifies the request for the right to use and the transfer rate, and
Road 4_nWins arbitration for access to high-speed serial bus 1
The control lines CTL0 and CTL1 are kept for one clock only (11)
When the transfer permission is given, the link layer circuit 5 _nIs
(CTL0, CTL1) for a certain predetermined clock (01),
(D₀~ D₇) To (00)₁₆While sending packets
Prepare and set (CTL0, CTL1) to (10) as clock SC
Data line D synchronized with LK₀And D₁Asynchronous using
Transmission data divided into 2 bits from the beginning of the eggplant packet
Physical layer circuit 4_n(Link at this time)
Ear circuit 5_nIs the transmission data as (CTL0, CTL1) = (10).
Data is being output).

The physical layer circuit 4 _n to which the transmission data has been input
Converts the signal into an electrical transmission signal according to the standard and outputs the signal to the high-speed serial bus 1. When the link layer circuit 5 _n finishes outputting one packet of transmission data and there are no other packets to be transmitted, the link layer circuit 5 _n (CTL0, CTL1)
From (10) to (00) to indicate transmission completion, and upon receiving this signal, the physical layer circuit 4 _n shifts to another process.

[0058] Node various data exchanged between the devices 2 ₁ to provide the desired operation instruction and the link layer circuit 5 _n and the physical layer circuit 4 _n data extraction and write circuit 6
Clock SC in the format of 11-bit data DATA by 0
The packet is written to the capture memory 70 in synchronization with the LK, and at the same time, the packet is discriminated by the index information analysis circuit 91 and the primary item is analyzed.
Is written to. The data extraction / write circuit 60
Of the high-speed serial bus 1
When the request for securing the usage right and the transfer rate are output, the transfer rate identification circuit 65 identifies the transfer rate.
4 when (CTL0, CTL1) changes from (00) to (01), the transfer rate identification data indicating the current 100 Mbit / s is transferred to the byte position detection circuit 66 and the pattern detection circuit 67.
Output to

The byte position detection circuit 66
Output (CTL0, CTL1) changed from (00) to (01)
At the time, the transfer speed identification data indicating 100 Mbit / s was input.
(CTL0, CTL1) changes from (01) to (10)
At this point, the count value K is initialized to zero, and the clock SCLK is
It counts up by +1 each time it is input. Soshi
And the value obtained by adding +1 to the quotient q obtained by dividing the count value K by 4
(Byte position detection circuit)
Numeral 65 indicates that the byte position detection data is initialized to zero in advance.
). The pattern detection circuit 67 indicates 100 Mbit / s.
When the transfer speed identification data is input, the register 64
Output D₀And D₁To d₀And d₁, The output D of the register 63
₀And D₁To d_TwoAnd d_Three, The output D of the register 62₀And D₁
To d_FourAnd d _Five, Link layer circuit 5_nOutput D₀And D₁
To d₆And d₇As (d ₀d₁d_Twod_Threed_Four
d_Fived₆d₇) And output in parallel,
Outputs 8-bit pattern data.

Each time the data strobe signal ST is input from the byte position detection circuit 66, the collation circuit 68 determines the detected byte position output from the byte position detection circuit 66 at that point in time for each byte set in the reference packet setting circuit 80. It is checked whether the byte position matches the position. If the position matches, the 8-bit pattern detected by the pattern detection circuit 67 at that time matches the byte data set in the reference packet setting circuit 80 in association with the byte position. To check.

The detection pattern when the detected byte position is 1 matches the upper byte data of the transmission destination ID set corresponding to the first byte position 1 set in the reference packet setting circuit 80. The detection pattern when the detection byte position is 2 is the transmission destination ID set corresponding to the second byte position 2 set in the reference packet setting circuit 80
The detection pattern when the detected byte position is 5 is the lower byte data of the reference packet setting circuit 80.
The detection pattern when the upper byte data of the transmission source ID set in correspondence with the third byte position 5 set in, and the detection byte position is 6 is set in the reference packet setting circuit 80 in 4. The detection pattern when the lower byte data of the transmission source ID set corresponding to the sixth byte position 6 matches and the detection byte position is 21 to 24 is
When the first to fourth bytes of the 4-byte data representing the desired operation command set corresponding to the fifth to eighth byte positions 5 to 8 set in the reference packet setting circuit 80 match, Reference numeral 68 outputs a reference packet detection signal to the data extraction / write control circuit 69 and the index information analysis circuit 91.

The data extraction / write control circuit 69 previously set to the reference packet step-over mode continues to write data DATA to the capture memory 70 even after the input of the reference packet detection signal. When the writing of data DATA has progressed by half of the total number of addresses of the capture memory 70, the writing to the capture memory 70 is stopped,
The capture end signal CE is output. On the other hand, the index information analysis circuit 91 previously set to the reference packet step-over mode determines the packet and sets the primary items even after the input of the reference packet detection signal until the capture end signal CE is input from the data extraction / write control circuit 69. Although writing to the analysis and index memory 90, a storage area for writing a primary item analyzed for packet (reference numeral PC ₀ in FIG. 10) including the data dATA in the input at input the reference packet detection signal PF _i , the start address A _(i) of the storage area PF _i is changed to A
It is written into the management information storage area RF as D _Z.

Serial bus tester 20_nSent by
Node machine that received the asynchronous packet transmission signal
Vessel 2₁At an isochronous packet rate of 100 Mbit / s.
When the transmission signal of the
Tester 20_nPhysical layer circuit 4_nReceive and receive data
Link layer circuit 5_nOutput to Link
Layer circuit 5_nReceives the data in synchronization with the clock SCLK.
Enter and include in header because it is an isochronous packet
Controller 30 whose channel number is higher _nReceived from
Check that the communication has been instructed, and confirm that
Header and data CRC using header CRC and data CRC.
Check the block for errors.
Troller 30_nOutput to Controller 30_nIs a note
Is stored in the memory 10.

[0064] The physical layer circuit 4 _n and the link layer circuit 5 when the packet from the node device 2 ₁ is received
Various data exchanged with _n
The data is written to the capture memory 70 in chronological order by the data extraction / write circuit 60, and the packet is discriminated and the primary item is analyzed by the index information analysis circuit 91, and is written to the index memory 90. Each time it receives the isochronous packet from the node device 2 ₁ serial bus tester 20 _n, the same processing is repeated.

Thereafter, the reference packet detection signal is input first.
And then reduce it to half of the total number of addresses in the capture memory 70
When the writing of data DATA advances by a corresponding amount, the data
Extraction / write control circuit 69 transfers to capture memory 70
Finish writing and control the capture end signal CE.
Roller 30_nTo the index information analysis circuit 91
You. The index information analysis circuit 91 sends a capture end signal
Entering the signal CE, the packet being analyzed at that time (Fig.
10 sign PC_{# 0}See) for index memory
The analysis operation is completed without writing data to packet 90 (packet P
C_{# 0}Some items are already stored in the storage area PF_{j + 1}Write on
When the storage area PF_{j + 1}Analysis progress
Write the primary item unanalyzed in the status data). And,
Analysis was completed just before inputting the capture end signal CE
Packet (code PC in FIG. 10)_{# 1}) Of index information
Written storage area PF_jStart address A_(j)A
D _EIn the management information storage area RF as
The capture end signal CE in the capture memory 70 is input.
Input from the data extraction / write control circuit 69
Active write address CRA (code ad in FIG. 10)_{# 0})
After the next address (when CRA is M, the start address
Of the packets already stored in
Information is written to the index memory 90, and
For which the analysis progress data has been analyzed for primary items
(PC of FIG. 10)_{# 2}Index information about
Area PF in which information is written_kStart address A_(k)
AD _SIs stored in the management information storage area RF.

[0066] As a result, the capture memory 70, high-speed serial bus 1 about the asynchronous packet PC ₀ to provide a desired operation command to the node equipment 2 ₁
Since the information of a series of all the packets transmitted within a certain period of time is stored in the index memory 90 and the index information of each packet stored in the capture memory 70 is stored in the index memory 90, Node device 2 ₁
Operating characteristics can be accurately and quickly inspected. Here, for convenience of explanation, it is assumed that the relationship between the storage content of the capture memory 70 and the storage content of the index memory 90 at the end of the capture is as shown in FIG.

(6) Analysis of Secondary Items and Display of Analysis Information in Reference Packet Step Over Mode Controller 30 _{n that} has received capture end signal CE in reference packet step over mode first stores a work area in memory 10. To secure. Then, referring to AD _Z of the management information storage area RF of the index memory 90, the serial number stored in the address A _(i) of the storage area PF _i starting from the address AD _Z of the index memory 90 is represented by b, and the address A _{(i )} the packet head capture memory address stored in the +7 stored in the work area as ad _0, further, by referring to the management information storage area RF of AD _S and AD _E, storage area starting from the address AD _S of index memory 90 PF _k address a _(k) the serial number stored in bs, starting at address AD _E storage area P
The serial number stored at the address A _(j) of F _j is stored as bE in the work area.

First, a collection of serial numbers (b-50) to (b + 49) extending over 100 before and after centering on b
Is defined as the 0th group. And 100 immediately before the 0th group
The collection of the individual {(b-150) to (b-51)} is the -1st
Group, 100 pieces immediately before the first group {(b-250) to (b)
-151) The group of｝ is referred to as a second group, and
r group {bs ~ (b-((r-1) * 100 + 51))}
Divided into 100 units immediately after the 0th group, $ (b + 50) ~
The group of (b + 149)｝ is divided into the first group,
A group of 00 pieces {(b + 150) to (b + 249)} is referred to as a second group, and the r′th group {(b + (r′−1))
× 100) to bE｝.

Then, in the index memory 90, all the storage contents of all the storage areas (referred to as PF _{a to} PF _c ) corresponding to the zeroth group are read and transferred to the work area secured in the memory 10. The code and address of each storage area moved to the work area of the memory 10 are stored in the index memory 9.
And on the 0 same sign (PF _a ~PF _c) assigning an address. Then, first, per storage area PF _a corresponding to the beginning of the serial number of the 0 group in the work area (b-50),
It is checked whether or not the analysis progress data of the address A _(a) +11 has been analyzed for the secondary item. If analyzed, the packet start capture memory address at address A _(a) +7 (= ad _as ) and address A _(a) +
8 packet end capture memory address (= ad _ae
Reference to that), transferred from the capture memory 70 to the work area by reading the data (data DATA address ad _{the as} to AD _ae) for Packet PC _{(b-5 0)} of the serial number (b-50), the packet Configuration data (data that constitutes a packet format such as a header and a data block) or packet configuration data and CLT0, CLT1, and LReq control signal data) Index information of the primary item, presence / absence of various errors in the secondary item, and time stamp If there is annotation information, the annotation information is displayed in a predetermined format on the display device 11.
Is initially displayed. However, since the analysis of the secondary items has not yet been performed, the capture memory 70 first refers to the packet start capture memory address at address A _(a) +7 and the packet end capture memory address at address A _{(a )} +8. Packet P with serial number (b-50)
The data for C _(b-50) is read and moved to the work area.

When the type of the packet at the address A _(a) +1 indicates a packet including a header, a CRC is calculated from each byte data of the header portion of the data read from the capture memory 70, and the CRC is calculated at the end of the header. The header CR is compared with the value of the added header CRC.
It is determined whether there is a C error. Further, address A _(a) +1
If the type of the packet indicates a packet including a data block, a CRC is calculated from each byte data of the data block portion of the data read from the capture memory 70, and the value of the data CRC added at the end of the data block is calculated. Then, the presence or absence of a data CRC error is determined by comparing with. Then, the header CRC error and the data CR
Apart of C Error writing for errors in the working area of the storage area PF _a addresses _{A (a)} +9 memory 10. Then, among the capture memory 70, and data DATA stored in the storage area PF _a addresses _{A (a)} +7 on the stored packet head capture memory address (= ad _as),
Calculate the time difference when capturing the stored data DATA to ad _0, the sign of the time stamp when written before the timestamp as written to the address Address _{A (a)} +10 storage area PF _a (ad ₀ Is negative,
If it is written later, the sign of the time stamp is positive, and if it is the same as ad ₀ , the time stamp is 0). Finally, the address address A of the memory area PF _a
(a) Add the secondary item analyzed as the progress data of the analysis of +11. Then, the packet configuration data (or the packet configuration data and the control signal data of CLT0, CLT1, and LReq), the index information of the primary item, the presence / absence of various errors in the secondary item, the time stamp, and the address A
_(a) If the annotation information of +12 to 39 exists, the display device 1 combines the annotation information and analyzes it in a predetermined format as analysis information.
1 is initially displayed.

Next, the controller 30 _n
Second serial number of group 0 in the work area (b-49)
For the storage area PF _{a + 1} corresponding to the address A _{(a + 1)}
It is checked whether the progress data of the analysis of +11 has already been analyzed for the secondary item. Not yet, address A _{(a + 1)}
Referring to the end of packet capture memory address of the packet start capture memory address and the address _{A (a + 1)} +8 +7, serial numbers from the capture memory 70 (b
-49) The data of the packet is read out and moved to the work area. If the type of the packet at the address A _{(a + 1)} +7 indicates a packet including a header, the capture memory 7
From the data read from 0, a CRC is calculated from each byte data of the header part, and the presence / absence of a header CRC error is determined by comparing the CRC with the value of the header CRC added at the end of the header. Further, when the type of the packet at the address A _{(a + 1)} +1 indicates a packet including a data block, of the data read from the capture memory 70,
The CRC is calculated from each byte data of the data block part, and the data CR added at the end of the data block is calculated.
The presence or absence of a data CRC error is determined by comparing with the value of C. The presence / absence of an error is separately determined for the header CRC error and the data CRC error in the storage area PF _{a + 1 of the} work area.
To the address A _{(a + 1)} +9.

Subsequently, in the capture memory 70, the data stored at the packet start capture memory address stored in the address A _{(a + 1)} +7 of the storage area PF _{a + 1}
The time difference between the DATA and the data DATA stored in ad ₀ at the time of capture is calculated, and a time stamp is stored in the storage area P.
F _{a + 1} address address _{A (a +} 1) is written to +10.
Lastly, the address A _{(a + 1)} of the storage area PF _{a + 1}
The secondary item analyzed already is added as the analysis progress data of +11. Hereinafter, similarly, the 3rd to 100th serial numbers (b-4) of the 0th group in the working area of the memory 10
8) For each packet corresponding to (b + 50), the presence / absence of a header CRC error and a data CRC error and the time stamp are analyzed, and the packets are written to the storage areas PF _{a + 2 to} PF _c in the work area of the memory 10. .

The first packet configuration data of group 0 (or
Or packet configuration data and control signals for CLT0, CLT1, and LReq
Data) index information as primary item, secondary item
The presence or absence of various errors and the time stamp
After the initial display on the display device 11 in the
Displays analysis information on the second packet of group 0.
Press the down cursor key on the operation panel 12 once.
You. Then, the controller 30_nIs the 0th group described above.
In parallel with the analysis of the secondary items of each packet, the memory 1
In the work area 0, the packet corresponding to the second packet of the group 0
Storage area PF _{a + 1}Address A_{(a + 1)}+7 packet
Start capture memory address and address A_{(a + 1)}+8
Refer to the packet end capture memory address of
Packet of serial number (b-49) from capture memory 70
Read out the data of the
You. And address A_{(a + 1)}+11 analysis progress
Check if secondary items have been analyzed by referring to data and analyze
If the packet configuration data is already
Data and control signal data of CLT0, CLT1, LReq)
Eye index information and the presence or absence of various errors in secondary items
Time stamp, if there is annotation information, together with the annotation information
And in a predetermined format as packet analysis information
It is displayed on the display device 11. The secondary item has not been analyzed yet
If it is, it will be displayed excluding secondary items, and then it will be analyzed
Where added to the display.

Similarly, the zeroth group f (where 1 ≦ f <
When the down cursor key is pressed once while the analysis information of the (100) th packet is displayed, the controller 30 _n displays the analysis information on the packet next to the currently displayed packet in the zeroth group. Let it. On the other hand, when the up cursor key is pressed once in a state where the analysis information of the fth (0 <100) packet of the 0th group is displayed, the controller 30 _n The analysis information on the packet immediately before the currently displayed packet is displayed. Pressing the down cursor key while the analysis information of the last packet of group 0 is displayed is ignored, and pressing of the up cursor key while analysis information of the first packet of group 0 is displayed is also ignored. Is done.

[0075] packet to give the desired operation instruction 50 th packet of the 0 group to the node device 2 ₁ tested (reference numeral PC _(b) of FIG. 10), so that the 100 packets of the group 0 By checking the analysis information, the node device 2 ₁ is given before and after a desired operation command is given to the node device 2 _1.
It is possible to analyze in detail what kind of operation was performed at what timing. Moreover, since the primary item of each packet in the 0th group has been analyzed during capture,
After the capture, the controller 30 _n only needs to analyze the secondary items, so that the analysis processing of each packet can be promptly performed, and the operator can quickly check the complete analysis information of the desired packet. .

When displaying the analysis information of the 50th packet of the 0th group, the controller 30 _n also displays a mark representing the reference packet. When the user inputs arbitrary annotation information on the operation panel 12 while displaying the analysis information of the f-th packet in the 0th group, the controller 30 _n additionally displays the annotation information and stores the annotation information in the work area storage area PF. _{(a + f-1)} of the address _{a (a + f-1)} is written in the + 12-39.

When the operator wants to check the analysis information of the packet of the (-1) th group immediately before the 0th group, the operation panel 1
2. Press the front group key once. When the front group key is pressed, the controller 30 _n ignores the pressing of the front group key if the analysis of the secondary items of all the packets of the zeroth group has not been completed yet, and if the analysis has already been completed, the operation is completed. index memory all data storage area PF _a ~PF _c of the zeroth group in the region 90
Is saved to the corresponding storage area. Of the index memory 90, transferred to a work area secured by reading all of the contents of the entire storage area corresponding to (-1) group (the PF _d ~PF _e) in the memory 10. The code and address of each storage area has been transferred to the work area allocated the same reference numerals (PF _d ~PF _e) the address and on the index memory 90. Then, first, the (-) in the work area
1) per storage area PF _d corresponding to the beginning of the serial number (b-0.99) of the group, checking whether the progress data of the analysis stored in the storage area PF _d is a secondary item parsed. If analyzed, the data of the packet with the serial number (b-150) is read out from the capture memory 70 with reference to the packet start capture memory address and the packet end capture memory address and moved to the work area, and the packet configuration data is read. (Or packet configuration data and control signal data of CLT0, CLT1, and LReq), index information of the primary item, presence / absence of various errors and time stamp of the secondary item, and, if there is annotation information, the annotation information in a predetermined format. An initial display is performed on the display device 11. However,
Here, since the analysis of the secondary items has not been completed, first, the data of the packet with the serial number (b-150) is read from the capture memory 70 and moved to the work area.

[0078] Then, when the type of the stored packets in the storage area PF _d indicates a packet including a header, of the data read from the capture memory 70, calculates a CRC from each byte data of the header portion, the header of the last The presence / absence of a header CRC error is determined by comparing with the value of the header CRC added to the header CRC. Further, when the type of the packet indicates a packet including a data block, a CRC is calculated from each byte data of the data block portion of the data read from the capture memory 70, and the CRC of the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing the value with the value. The presence / absence of an error is separately determined for the header CRC error and the data CRC error in the storage area PF _d of the work area of the memory 10.
Write to. Then, among the capture memory 70, and data DATA stored in the stored in the storage area PF _d packet head capture memory address, the time difference between the time of capture of the stored data DATA to ad ₀ is calculated, the time stamp written into the storage area PF _d as. Finally,
2 the progress data stored in the storage area PF _d Analysis
Add the next item analyzed. Then, the packet configuration data (or the packet configuration data and the control signal data of CLT0, CLT1, and LReq), the index information of the primary item, the presence / absence of various errors and the time stamp of the secondary item, the time stamp, and the annotation information if any Together, they are initially displayed on the display device 11 as analysis information in a predetermined format.

Next, for the storage area PF _{d + 1} corresponding to the second serial number (b-149) of the (-1) group in the work area, the controller 30 _n adds the storage area PF _{d + 1} to the storage area PF _{d + 1} . It is checked whether or not the stored analysis progress data has been analyzed for the secondary item. Since it is not yet, the serial number (b-149) is obtained from the capture memory 70 by referring to the packet start capture memory address and the packet end capture memory address. Is read and moved to the work area. Then, when the type of the packet stored in the storage area PF _{d + 1} indicates a packet including a header, a CRC is calculated from each byte data in the header portion of the data read from the capture memory 70, and the CRC is calculated at the end of the header. The presence / absence of a header CRC error is determined by comparing with the value of the added header CRC. Further, when the type of the packet indicates a packet including a data block, a CRC is calculated from each byte data of the data block portion of the data read from the capture memory 70, and the CRC of the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing the value with the value.
The presence / absence of an error is separately determined for the header CRC error and the data CRC error in the storage area PF of the work area of the memory 10.
Write to _{d + 1} .

Subsequently, in the capture memory 70, the data stored in the packet start capture memory address stored in the storage area PF _{d + 1} of the work area of the memory 10
The time difference between the DATA and the data DATA stored in ad ₀ at the time of capture is calculated, and a time stamp is stored in the storage area P.
Write to F _{d + 1} . Lastly, “secondary item analyzed” is added to the analysis progress data stored in the storage area PF _{d + 1} . Hereinafter, in the same manner, the third (-1) group in the work area
(B-148) to (b-5)
For each packet corresponding to 1), the presence / absence of a header CRC error and a data CRC error and the time stamp are analyzed, and the storage areas PF _{d + 2 to} P
_Write to Fe.

The first packet configuration data (or the packet configuration data and the control signal data of CLT0, CLT1, and LReq) of the (-1) group, the index information of the primary item, the presence / absence of various errors as the secondary item, After displaying the time stamp and the annotation information on the display device 11 in a predetermined format,
When the user wants to display the analysis information on the second packet of the (-1) th group, the down cursor key is pressed once on the operation panel 12. Then, in parallel with the above-described analysis of the secondary item of each packet of the (-1) group, the controller 30 _n stores the memory corresponding to the second packet of the (-1) group in the work area. With reference to the packet start capture memory address and the packet end capture memory address stored in the area PF _{d + 1} , the data of the packet with the serial number (b-149) is read from the capture memory 70 and moved to the work area. Then, referring to the analysis progress data stored in the storage area PF _{d + 1} , it is checked whether or not the secondary item has been analyzed. If analyzed, the packet configuration data (or the packet configuration data and CLT0, CLT1,. LReq control signal data) Primary item index information, Secondary item presence / absence of various errors, time stamp, and annotation information, if any, are combined with the annotation information in a predetermined format as packet analysis information. 11 is displayed. If the secondary item has not been analyzed yet, it is displayed excluding the secondary item,
Then, when it is analyzed, it is added to the display.

Similarly, the f of the (-1) group (where 1
When the down cursor key is pressed once in a state where the analysis information of the ≤f <100) th packet is displayed, the controller 30 _n selects the packet next to the currently displayed packet in the (-1) group. Display analysis information about Conversely,
In a state where the analysis information of the f-th (1 <f ≦ 100) -th packet of the (-1) group is displayed, the up cursor key is set to 1
When pressed times, the controller 30 _n among the first (-1) group, and displays the analysis information about the previous packet of the packet currently being displayed. Pressing the down cursor key while the analysis information of the last packet of the (-1) group is displayed is ignored, and pressing the down cursor key while the analysis information of the first packet of the (-1) group is displayed. Pressing the cursor key is also ignored. Since the (-1) of parsed even while capturing the primary item of each packet group, after capturing, since the controller 30 _n may be the only analysis of the secondary items, quickly analyzing process each packet This allows the operator to quickly check the complete analysis information of the desired packet.

Similarly, when the analysis information of the packets in the h-th group is displayed, and when the analysis of the secondary items is completed for all the packets in the h-th group, the previous group key is pressed.
The controller 30 _n stores all data in the storage areas PF _{u to} PF _v corresponding to all packets in the h-th group in the work area under the condition that −r <h ≦ r ′.
0, and all data in the storage areas PF _{w to} PF _t corresponding to all packets of the (h−1) th group are moved from the index memory 90 to the work area, and the secondary items of each packet are Analysis and display of analysis information of the packet desired by the user are performed. Conversely, if the analysis information of the packet in the h-th group is displayed, and the analysis of the secondary items is completed for all the packets in the h-th group, and the next group key is pressed, the controller 30 _n returns −r ≦ On the condition that h <r ', the storage area PF corresponding to all packets of the h-th group in the work area
_{u ~PF v} is retracted to all data of the corresponding storage area of the index memory 90, a storage area corresponding from the index memory 90 for all packets of the (h + 1) group PF _p
-Move all data of PF _q to the work area,
Analysis of the next item and display of analysis information of the packet desired by the user are performed.

[0084] (5) In addition Capturing the reference packet start mode (see FIG. 11), although the above description has been explained a case of performing the capture by the reference packet step over mode, unlike this, desired to node equipment 2 ₁ When capturing and analyzing a packet transmitted on the high-speed serial bus 1 within a certain fixed time after the operation command is given, the operator first performs a setting operation of the reference packet start mode on the operation panel 12, data extraction and by the controller 30 _n
Write control circuit 69 and index information analysis circuit 91
Is set to the reference packet start mode. Thereafter, data input for designating an asynchronous packet for a desired operation command as a reference packet is input on the operation panel 12, and the reference packet setting circuit 8 is set by the controller _30n.
After setting to 0, transmission of a desired operation command is further instructed.

When the reference packet start mode is set
The data extraction / write control circuit 69 detects the reference packet.
All addresses of the capture memory 70 from the signal input point
When data DATA writing has progressed by 90% of the number
Stop writing to capture memory 70 and capture
An end signal CE is output. Meanwhile, the reference packet start
The index information analysis circuit 91 set to the mode
Data DA being input when the quasi-packet detection signal is input
Packet containing TA (PC in FIG. 11)₀See)
The storage area for writing the analyzed primary item is PF_iBecame
In the case, the storage area PF_iStart address A_(i)AD_ZPassing
And AD_STo the management information storage area RF as
When the capture end signal CE is input, the
Packet (code PC in FIG. 11)_{# 0}See)
Ends the analysis operation without writing to the memory 90
(Packet PC_{# 0}Some items are already stored in the storage area P
F _{j + 1}Has been written to the storage area PF_{j + 1}of
Write the primary item unanalyzed in the analysis progress data.)
The analysis is performed immediately before the capture end signal CE is input.
(The code PC in FIG. 11)_{# 1}B)
Storage area PF in which index information is written_jStart a
Dress A_(j)AD_ETo the management information storage area RF as
Get in.

[0086] As a result, the capture memory 70, the node device 2 ₁ after gave the desired operation command, information of all packets of a sequence transmitted within a predetermined time over the high-speed serial bus 1 is stored and an index for the index information of each packet stored in the capture memory 70 in the memory 90 is stored, it is possible to inspect later the operating characteristics of the node equipment 2 ₁ accurately and quickly. Here, for convenience of explanation, the capture memory 7
It is assumed that the relationship between the storage contents of 0 and the storage contents of the index memory 90 is as shown in FIG.

(6) 2 in Reference Packet Start Mode
Analysis of next item and display of analysis information Capture end signal C in standard packet start mode
The controller 30 _{n that} has received E first secures a work area in the memory 10. Then, by referring to the AD _S of the management information storage area RF of the index memory 90, a serial number stored in the address storage area PF _i starting at address AD _S of index memory 90 A _(i) b
s, and stores the address A _(i) +7 on the stored packet head capture memory address in the work area as the ad _0, further, by referring to the management information storage area RF of AD _E,
Stored in a work area a serial number that addresses stored in A _(j) of the beginning storage area PF _j from the address AD _E of index memory 90 as bE.

Then, first, a group of serial numbers bs to (bs + 99) extending from bs to 100 is determined as a zeroth group. Then, 100 ｛(bs +
100) to (bs + 199)} as a first group,
100 pieces immediately after the group {(bs + 200)-(bs + 29)
9) The group of {} is divided into the r'th group {(bs + r '* 100) to bE} by referring to the second group.

Then, as in the case of the reference packet step-over mode, all the storage areas (PF _{i to} PF _c) corresponding to the zeroth group in the index memory 90 are set.
Is read out and moved to the work area secured in the memory 10. Codes and addresses on the index memory 90 are assigned to the codes (PF _{i to} PF _c ) and addresses of each storage area moved to the work area. Then, first, per storage area PF _i corresponding to the beginning of the serial number bs 0th group in the work area of the memory 10, the progress data of the analysis stored in the storage area PF _i is a secondary item parsed Check whether, so still, with reference to the packet head capture memory address and the address end of packet capture memory address, code P of serial number b _s packet (FIG. 11 from the capture memory 70
(See C ₀ ) and transfer it to the work area.

[0090] Then, when the type of the stored packets in the storage area PF _i indicates a packet including a header, of the data read from the capture memory 70, calculates a CRC from each byte data of the header portion, the header of the last The presence / absence of a header CRC error is determined by comparing with the value of the header CRC added to the header CRC. Further, when the type of the packet indicates a packet including a data block, a CRC is calculated from each byte data of the data block portion of the data read from the capture memory 70, and the CRC of the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing the value with the value. Then, write the separate existence of an error in the header CRC and data CRC error in the storage area PF _i workspace.
Then, among the capture memory 70, storage area PF and data DATA stored in the stored packet head capture memory address _i, the data stored in the ad ₀ DATA
Calculate the time difference when capturing a written as a time stamp in the storage area PF _i (sign timestamps when written before ad ₀ is negative and the sign of the time stamp when written after the positive And ad ₀
If the same, the time stamp is set to 0). Finally,
The progress data of the analysis of the storage area PF _i add a secondary item parsed. Then, the packet configuration data (or the packet configuration data and the control signal data of CLT0, CLT1, and LReq), the index information of the primary item, the presence / absence of various errors and the time stamp of the secondary item, the time stamp, and the annotation information if any Together, they are initially displayed on the display device 11 as analysis information in a predetermined format.

[0091] Next, the controller 30 _n is, the memory 10
The second serial number of the 0th group in the work area (bs + 1)
It is checked whether the analysis progress data of the storage area PF _{i + 1} corresponding to the above has already been analyzed for the secondary item, and since it is not yet, the packet start capture memory address and the packet end capture memory address of the storage area PF _{i + 1} , The serial number (bs
The data of the packet of (+1) is read and moved to the work area. When the type of the packet stored in the storage area PF _{i + 1} indicates a packet including a header, a CRC is calculated from each byte data of the header portion of the data read from the capture memory 70, and The header CR is compared with the value of the added header CRC.
It is determined whether there is a C error. Further, when the type of the packet indicates a packet including a data block, a CRC is calculated from each byte data of the data block portion of the data read from the capture memory 70, and the CRC of the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing the value with the value. And
The presence / absence of an error is written into the storage area PF _{i + 1} of the work area separately for the header CRC error and the data CRC error.

[0092] Then, among the capture memory 70, a storage area PF i _{+ 1} data stored in the stored packet head capture memory address to DATA, the time difference between the time of capture of the stored data DATA to ad ₀ Calculate and write it to the storage area PF _{i + 1} as a time stamp. Lastly, “secondary item analyzed” is added to the progress data of the analysis of the storage area PF _{i + 1} . Hereinafter, similarly, the 3rd to 100th serial numbers of the 0th group in the work area, bs + 2) to
For each packet corresponding to (bs + 99), the presence / absence of a header CRC error and a data CRC error and the time stamp are analyzed, and the storage areas PF _{i + 2 to} PF in the work area are analyzed.
_Write to _c .

After the analysis information of the first packet of the 0th group is initially displayed on the display device 11, the user
If you want to display analysis information about the th packet,
The down cursor key is pressed once on the operation panel 12. Then
In parallel with the above-described analysis of the secondary item of each packet of the zeroth group, the controller 30 _n performs the packet start of the storage area PF _{i + 1} corresponding to the second packet of the zeroth group in the work area. The capture memory 7 is referred to by referring to the capture memory address and the packet end capture memory address.
The data of the packet with the serial number (bs + 1) from 0 (see PC _{(bs + 1) in} FIG. 11) is read and moved to the work area. Then, referring to the progress data of the analysis of the storage area PF _{i + 1} , it is checked whether the secondary item has been analyzed. If analyzed, the packet configuration data (or the control of the packet configuration data and CLT0, CLT1, LReq) Signal data), the index information of the primary item, the presence / absence of various errors of the secondary item, the time stamp, and the annotation information, if any, together with the information in a predetermined format as packet analysis information.
1 is displayed. If the secondary item has not been analyzed yet, it is displayed excluding the secondary item, and then added to the display when it has been analyzed.

Similarly, the zeroth group f (0 ≦ f <
With the analysis information of the 100) th packet displayed,
When the down cursor key is pressed once, the controller 30
_n displays analysis information on the packet next to the currently displayed packet in the zeroth group. Conversely, when the up cursor key is pressed once in a state where the analysis information of the f-th (0 <100) packet of the 0th group is displayed, the controller _30n will The analysis information relating to the packet immediately before the packet being displayed is displayed. 0th
Pressing the down cursor key while the analysis information of the last packet of the group is displayed is ignored, and pressing of the up cursor key while the analysis information of the first packet of the zeroth group is displayed is also ignored. .

[0095] The first packet of the group 0 because the packet to give the desired operation command to the node device 2 ₁ tested, by checking the analysis information of the 100 packets of the group 0, the node equipment 2 later it gave the desired operation command to _1, or to which action the node equipment 2 ₁ at any timing, it is possible to analyze in detail. In addition, since the primary item of each packet in the zeroth group has been analyzed during the capture, the controller 3
Since only the secondary items need to be analyzed for 0 _n, the analysis processing of each packet can be promptly performed, and the operator can quickly check the complete analysis information of the desired packet.

When the user wants to check the analysis information of the packet of the first group next to the group 0, the user presses the next group key once on the operation panel 12. When the next group key is pressed, the controller 30 _n ignores the pressing of the next group key if the analysis of the secondary items of all the packets of the 0th group has not been completed yet, and if the analysis has already been completed, the operation is completed. 0th group storage area PF _{i in the} area
All data PF _c retract into the corresponding storage area of the index memory 90. And the index memory 9
0, all storage areas (PF _{d to} P _d) corresponding to the first group
Reading all of the contents of the F _e) memory 10
Then, analysis is performed on the secondary items of each packet and analysis information of the packet desired by the operator is displayed. Since the primary item of each packet of the first group has also been analyzed during capture, the controller 30 _n returns 2 after capture.
Since it is only necessary to analyze the next item, the analysis processing of each packet can be promptly performed, and the operator can quickly check the complete analysis information of the desired packet.

Similarly, when the analysis information of the packet in the h-th group is displayed, and when the analysis of the secondary items is completed for all the packets in the h-th group, the front group key is pressed.
The controller 30 _n stores all data in the storage areas PF _{u to} PF _v corresponding to all packets of the h-th group in the work area under the condition that 0 <h ≦ r ′.
0, and all data in the storage areas PF _{w to} PF _t corresponding to all packets of the (h−1) th group are moved from the index memory 90 to the work area, and the secondary items of each packet are Analysis and display of analysis information of the packet desired by the user are performed. Conversely, if the analysis information of the packets in the h-th group is displayed, and if the analysis of the secondary items is completed for all the packets in the h-th group, and the next group key is pressed, the controller 30 _n sets 0 ≦ h. <R ′, the storage area PF _u corresponding to all packets in the h-th group in the work area
All data ～PF _v is retracted into the corresponding storage area of the index memory 90, corresponding from the index memory 90 for all packets of the (h + 1) group storage area PF _p ~
The entire data of the PF _q is moved to the work area, the secondary items of each packet are analyzed, and the analysis information of the packet desired by the user is displayed.

[0098] (7) Capture (see FIG. 12) of the reference packet stop mode different from this, it is transmitted over the high-speed serial bus 1 within a certain time period immediately before giving the desired operation command to the node equipment 2 ₁ captures that packet, if you want to analyze, the operator is setting operation of the reference packet stop mode first the operation panel 12, the controller 30 _n by the data extraction and write control circuit 69 and the index information analyzing circuit 9
1 is set to the reference packet stop mode. Thereafter, data input for designating an asynchronous packet for a desired operation command as a reference packet is input on the operation panel 12, and the reference packet setting circuit 8 is set by the controller _30n.
After setting to 0, transmission of a desired operation command is further instructed.

When the reference packet stop mode is set
The data extraction / write control circuit 69 detects the reference packet.
Write to the capture memory 70 at the time of signal input
It stops and outputs a capture end signal CE. On the other hand,
Index information set in quasi-packet stop mode
The information analysis circuit 91 receives the capture end signal CE
The packet being analyzed at the point (code PC in FIG. 12)_{# 0}See)
Analysis without writing to index memory 90
Finish the operation (Packet PC_{# 0}Some items have already been
Storage area PF_{j + 1}When writing to the
Area PF_{j + 1}Of the primary items not analyzed
Write). Then, a capture end signal CE is input.
The packet that has just been analyzed immediately before
_{# 1}Storage area P in which index information is written
F_jStart address A_(j)AD _EAs management information storage
Write to the area RF, and
Data extraction when the capture end signal CE is input.
The write address being input from the output / write control circuit 69
SCRA (the code ad in FIG. 12)_#) And following address
(If the CRA is M, the address after the start address)
Index information is the earliest in the ket
Analysis progress data written to the memory 90
Is a packet whose primary item has been analyzed (PC
_{# 2}Note) index information about
Storage area PF_kStart address A_(k)AD _SManaged as
The information is stored in the information storage area RF.

[0100] As a result, the capture memory 70 stores information of all the packets of sequence transmitted over the high-speed serial bus 1 within a certain time until providing a desired operation command to the node device 2 ₁ is stored, and, since the index information of each packet stored in the capture memory 70 in the index memory 90 is stored, it is possible later to check the operation characteristics of the node equipment 2 ₁ accurately and quickly. Here, for convenience of explanation, the capture memory 7
It is assumed that the correspondence between the storage contents of 0 and the storage contents of the index memory 90 is as shown in FIG.

(8) 2 in reference packet stop mode
Analysis of next item and display of analysis information Capture end signal C in standard packet stop mode
The controller 30 _{n that} has received E first secures a work area in the memory 10. Then, the serial number stored in the address A _(k) of the storage area PF _k starting from the address AD _S of the index memory 90 is referred to as b by referring to the AD _S of the management information storage area RF of the index memory 90.
s, and stores the address A _(k) +7 on the stored packet head capture memory address in the work area as the ad _0, further, by referring to the management information storage area RF of AD _E,
Stored in a work area a serial number that addresses stored in A _(j) of the beginning storage area PF _j from the address AD _E of index memory 90 as bE.

First, a group (bE-99) to bE of 100 serial numbers immediately before bE is defined as a zeroth group. Then, 100 ｛(bE−
199) to (bE-100)} are referred to as (-1).
Group, 100 immediately before the (-1) th group (bE-299)
-(BE-200)}, the group of (-r) {bs ~ (bE-r * 100)} is referred to as the group (-2).
Divide up to.

[0103] Then, as in the case of the reference packet start mode, among the index memory 90, reads all of the contents of all the storage area corresponding to the 0th group (the PF _a ~PF _k) memory Move to the work area secured at 10. The code and address of each storage area has been transferred to the work area of the memory 10 allocated codes (PF _a ~PF _k) and address on the index memory 90. Then, first, the serial number bs at the head of the 0th group in the work area
With regard to the appropriate storage area PF _a to, the progress data of the analysis is to check whether the secondary item parsed. Wakashi, if parsed, by referring to the stored packet head capture memory address and end of packet capture memory address in the storage area PF _a, from the capture memory 70 reads the data packet serial number (bE-99) Move to the work area, and if there is packet configuration data (or packet configuration data and control signal data of CLT0, CLT1, and LReq), index information of primary item, presence / absence of various errors, time stamp, and annotation information of secondary item, The annotation information is initially displayed on the display device 11 in a predetermined format. However,
Here, since the analysis of the secondary items has not yet been performed, the data of the packet with the serial number (b _E -99) is read from the capture memory 70 and moved to the work area.

[0104] Then, when illustrating a packet including a type header storage area PF _a the stored packets of the working area of the memory 10, among the data read from the capture memory 70, the CRC from each byte data of the header portion It is calculated and compared with the value of the header CRC added at the end of the header to determine whether there is a header CRC error. Further, when the type of the packet indicates a packet including a data block, a CRC is calculated from each byte data of the data block portion of the data read from the capture memory 70, and the CRC of the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing the value with the value. Then, separately for errors in the header CRC and data CRC error, it is written into the storage area PF _a work area of the memory 10. Then, among the capture memory 70, stored in the storage area PF _a the stored packet head capture memory address data
The time difference between the DATA and the data DATA stored in ad ₀ at the time of capture is calculated, and a time stamp is stored in the storage area P.
The sign of the time stamp when written before writing to F _a (ad ₀ is negative, the sign of the time stamp when written after a positive, and a time stamp 0 if same as ad ₀ ). Finally, the storage area PF _a
Is added to the progress data of the analysis of (2).
Then, the packet configuration data (or the packet configuration data and the control signal data of CLT0, CLT1, and LReq), the index information of the primary item, the presence / absence of various errors and the time stamp of the secondary item, and the information if there is the annotation information are put together. To cause the display device 11 to initially display it as analysis information in a predetermined format.

Next, the controller 30 _n determines that the analysis progress status data of the storage area PF _{a + 1} corresponding to the second serial number (bE-98) of the zeroth group in the work area has been subjected to the secondary item analysis. Check if it is. Since not yet
With reference to the packet start capture memory address and the packet end capture memory address, the data of the packet with the serial number (bE-98) is read from the capture memory 70 and moved to the work area. Then, the storage area PF
_When the type of the packet stored in _{a + 1} indicates a packet including a header, a CRC is calculated from each byte data of the header portion of the data read from the capture memory 70, and the header added to the end of the header is calculated. The presence or absence of a header CRC error is determined by comparing the value with the CRC value. Further, when the type of the packet indicates a packet including a data block, a CRC is calculated from each byte data of the data block portion of the data read from the capture memory 70, and the CRC of the data CRC added at the end of the data block is calculated. The presence or absence of a data CRC error is determined by comparing the value with the value. Then, the presence / absence of an error is written into the storage area PFa _{+ 1} of the work area of the memory 10 separately for the header CRC error and the data CRC error.

Subsequently, in the capture memory 70, the data stored at the packet start capture memory address stored in the storage area PFa _{+ 1} of the work area of the memory 10
The time difference between the DATA and the data DATA stored in ad ₀ at the time of capture is calculated, and a time stamp is stored in the storage area P.
F _{a + 1} address address _{A (a +} 1) is written to +10.
Finally, the progress data of the analysis of the storage area PF _{a + 1} is
Add the next item analyzed. Hereinafter, similarly, the 3rd to 100th serial numbers (bE-9) of the 0th group in the work area
7) For each packet corresponding to -bE, the header CR
The analysis of the presence and the time stamp of the C errors and data CRC error, and writes in the storage area PF a _{+ 2} ~PF _c in the workspace.

After the analysis information of the first packet of the 0th group is initially displayed on the display device 11, the operator sets the 2nd packet of the 0th group.
If you want to display analysis information about the th packet,
The down cursor key is pressed once on the operation panel 12. Then
In parallel with the above-described analysis of the secondary item of each packet of the zeroth group, the controller 30 _n performs the packet start of the storage area PF _{a + 1} corresponding to the second packet of the zeroth group in the work area. The capture memory 7 is referred to by referring to the capture memory address and the packet end capture memory address.
The data of the packet with the serial number (bE-98) is read from 0 and moved to the work area. Then, referring to the progress data of the analysis, it is checked whether the secondary item has been analyzed. If the secondary item has been analyzed, the packet configuration data (or the packet configuration data and the control signal data of CLT0, CLT1, and LReq), and the primary item The presence / absence of various errors of the secondary item, the time stamp, and the annotation information, if any, are displayed together with the annotation information on the display device 11 in a predetermined format as packet analysis information. If the secondary item has not been analyzed yet, it is displayed excluding the secondary item, and then added to the display when it has been analyzed.

Similarly, the zeroth group f (where 1 ≦ i <
With the analysis information of the 100) th packet displayed,
When the down cursor key is pressed once, the controller 30
_n displays analysis information on the packet next to the currently displayed packet in the zeroth group. Conversely, f of group 0
(However, when the up cursor key is pressed once with the analysis information of the 1 <i ≦ 100) packet displayed,
The controller 30 _n displays analysis information on the packet immediately before the currently displayed packet in the zeroth group.
Pressing the down cursor key while the analysis information of the last packet of group 0 is displayed is ignored, and pressing of the up cursor key while analysis information of the first packet of group 0 is displayed is also ignored. Is done.

[0109] The 100 th packet of the 0 group because packets gave the desired operation command to the node device 2 ₁ tested, by checking the analysis information of the 100 packets of the group 0, the node equipment 2 what has been operating in the node equipment 2 ₁ which timing is immediately before to give the desired operation command to _1, it can be analyzed in detail.
Moreover, for the first-order entry for each packet of the 0 group because it already analyzed during capture, after capture, the controller 30 _n may be the only analysis of the secondary items, expediting the analysis of each packet The operator can quickly check the complete analysis information of the desired packet.

When the operator wants to check the analysis information of the packet of the (-1) th group before the 0th group, the operation panel 12
Press the front group key once. When the front group key is pressed, the controller 30 _n ignores the pressing of the front group key if the analysis of the secondary items of all the packets in the 0th group has not been completed yet,
If it has already been completed, the storage area P of the 0th group in the work area
All data F _a ~PF _c is retracted into the corresponding storage area of the index memory 90. Of the index memory 90, the (-1) was transferred to a work area secured in the memory 10 reads out all of the contents of all the storage areas corresponding (and PF _d ~PF _e) the group, each packet The analysis of the secondary items and the analysis information of the packet desired by the operator are performed. Since the (-1) of parsed even while capturing the primary item of each packet group, after capturing, since the controller 30 _n may be the only analysis of the secondary items, quickly analyzing process each packet Can proceed,
The operator can quickly check the complete analysis information of the desired packet.

Hereinafter, similarly, when the analysis information of the packets of the h-th group is displayed, and when the analysis of the secondary items is completed for all the packets of the h-th group, the front group key is pressed.
The controller 30 _n stores all data in the storage areas PF _{u to} PF _v corresponding to all packets of the h-th group in the index area 9 under the condition that −r <h ≦ 0.
0, and all data in the storage areas PF _{w to} PF _t corresponding to all packets of the (h−1) th group are moved from the index memory 90 to the work area, and the secondary items of each packet are Analysis and display of analysis information of the packet desired by the user are performed. Conversely, if the analysis information of the packet in the h-th group is displayed, and the analysis of the secondary items is completed for all the packets in the h-th group, and the next group key is pressed, the controller 30 _n returns −r ≦ On the condition that h <0, the storage area PF _u corresponding to all packets of the h-th group in the work area
All data ～PF _v is retracted into the corresponding storage area of the index memory 90, corresponding from the index memory 90 for all packets of the (h + 1) group storage area PF _p ~
The entire data of the PF _q is moved to the work area, the secondary items of each packet are analyzed, and the analysis information of the packet desired by the user is displayed.

[0112] (9) Capture (see FIG. 13) in the trigger signal step over mode different from this, for example, the node equipment 2 ₁ a over a period of time before and after a certain desired time in transmitting a packet to start the desired operation When the operator wishes to capture and analyze a packet transmitted over the high-speed serial bus 1, the operator first sets the trigger signal step-over mode on the operation panel 12, and the data extraction / write control circuit 69 by the controller 30 _n. And index information analysis circuit 9
1 is set to the trigger signal step-over mode.
Subsequently, when instructing transmission of a desired operation command from the operation panel 12 to the node device 2 ₁ addressed, the controller 30 _n sends the asynchronous packet for a desired operation command node equipment 2 ₁ destined to initiate the desired operation. Thereafter, when the operator performs a trigger operation on the operation panel 12 at a desired timing, the controller 30 _n outputs a trigger signal to the data extraction / write control circuit 69 and the index information analysis circuit 91.

Set to trigger signal step-over mode
The received data extraction / write control circuit 69 generates a trigger signal
Input of data DATA to the capture memory 70
Writing continues, but from the input of the trigger signal
Data of half the number of all addresses in the capture memory 70
Where the writing of DATA has progressed, the capture memory 70
Stops writing to memory and outputs capture end signal CE
I do. On the other hand, set to trigger signal step over mode
The index information analysis circuit 91 receives the trigger signal.
Even after input, the data extraction / write control circuit 69 captures
Until the input of the call end signal CE, the packet discrimination and
Analysis of next item and writing to index memory 90
The data DA being input when the trigger signal is input
Packet containing TA (PC of FIG. 13)₀See)
The storage area for writing the analyzed primary item is PF_iBecame
In the case, the storage area PF_iStart address A_(i)AD_ZWhen
And writes it in the management information storage area RF. Index information
The information analysis circuit 91 inputs a capture end signal CE.
And the packet being analyzed at that time (reference P in FIG. 13).
C _{# 0}For ()), writing to the index memory 90
End the analysis operation without doing (packet PC_{# 0}Some per
Items in the storage area PF_{j + 1}When writing to
Is the storage area PF_{j + 1}Primary to analysis progress data
Write as item unanalyzed). And the capture end signal
The packet that has been analyzed just before the CE is input (Fig. 1
Sign PC of 3_{# 1}) Index information written
Storage area PF_jStart address A_(j)AD_EManaged as
Write to the information storage area RF, and furthermore, capture memory
70, when the capture end signal CE is input.
Write during input from data extraction / write control circuit 69
Address CRA (code ad in FIG. 13)_#) Next address
After that (when CRA is M, it is stored after the start address)
Index information is the earliest
The data is written to the
The packet whose data has been analyzed for the primary item (the code in FIG. 13)
PC_{# 2}Index information) is written
Storage area PF_kStart address A_(k)AD_SAs
It is stored in the management information storage area RF.

[0114] As a result, the capture memory 70 is transmitted after starting a desired operation in the node device 2 _1, over the high-speed serial bus 1 around a timing obtained by multiplying the trigger at any time within a predetermined time The information of all the packets in the series is stored in the index memory 90.
Since the index information of each packet stored in the capture memory 70 are stored in the later, the operating characteristics of the node equipment 2 ₁ can be accurately and quickly inspected.

(10) Analyzing Secondary Items and Displaying Analysis Information in Trigger Signal Step Over Mode The controller 30 _{n that} has received the capture end signal CE in the trigger signal step over mode is then in the reference packet step over mode. since the same processing as in a state in which to initiate the desired operation to the node device 2 _1, before and after the operator has to trigger at a desired timing,
It has what operation the node equipment 2 ₁ at any timing, it is possible to analyze in detail. Moreover,
For a parsed during capture for primary items of each packet, after capturing, since the controller 30 _n may be the only analysis of the secondary items, can proceed quickly analyze the processing of each packet, worker Can quickly check the complete analysis information of the desired packet.

[0116] (11) Capture (see FIG. 14) in the trigger signal start mode different from this, for example, the node equipment 2 ₁ high-speed serial within a predetermined time from one desired timing during transmitting the packet to start the desired operation capture the packets transmitted over the bus 1, if you want to analyze, the operator is setting operation of the trigger signal start mode first the operation panel 12, data extraction and write control circuit 69 and the index information analyzed by the controller 30 _n The circuit 91 is set to the trigger signal start mode. Subsequently, when instructing transmission of a desired operation command from the operation panel 12 to the node device 2 ₁ addressed, the controller 30 _n sends the asynchronous packet for a desired operation command node equipment 2 ₁ destined to initiate the desired operation. Thereafter, the operation panel 12 is operated at a desired timing.
When the operator performs a trigger operation, the controller 30
_n outputs a trigger signal to the data extraction / write control circuit 69 and the index information analysis circuit 91.

The data set in the trigger signal start mode
The data extraction / write control circuit 69 receives a trigger signal.
Only 90% of the total number of addresses in the capture memory 70 from the point
Capture memo where data writing has progressed
The writing to the memory 70 is stopped, and the capture end signal CE
Is output. On the other hand, the trigger signal start mode is set.
Index information analysis circuit 91 receives a trigger signal
When a packet containing data DATA
A packet containing data DATA (reference numeral PC in FIG. 14) ₀reference)
The storage area for writing the primary items analyzed for_i
When the storage area PF_iStart address A_(i)To
AD_ZAnd AD_SIs written to the management information storage area RF
When the capture end signal CE is input,
The packet under analysis (the code PC in FIG. 14)_{# 0}See)
Is an analysis operation without writing to the index memory 90
(Packet PC_{# 0}Some items have already been recorded
Storage area PF_{j + 1}Has been written to the storage area P
F_{j + 1}Of primary item not analyzed in progress data of analysis
In). Then, immediately after the capture end signal CE is input.
The packet that has been analyzed before (the PC in FIG. 14)_{# 1}three
Storage area PF in which index information is written_j
Start address A_(j)AD_EAs management information storage area
Write to RF.

[0118] As a result, a series in capture memory 70 are transmitted after to initiate the desired operation to the node device 2 _1, after the operator has to trigger, over the high-speed serial bus 1 within a predetermined time information of all packets are stored in, and, because the index information for each packet stored in the capture memory 70 in the index memory 90 is stored, subsequently, accurately and quickly the operating characteristics of the node equipment 2 ₁ Can be inspected.

(12) 2 in trigger signal start mode
Analysis of next item and display of analysis information Capture end signal CE in trigger signal start mode
Controller 30 _n you enter Since the the later reference packet start mode same processing as when, in a state in which to initiate the desired operation to the node device 2 _1, immediately before the operator has to trigger at a desired timing it has what operation the node equipment 2 ₁ at any timing, it is possible to analyze in detail. Moreover, since the primary item of each packet has been analyzed during the capture, the controller 30 _n only needs to analyze the secondary item after the capture, so that the analysis process of each packet can proceed promptly. The operator can quickly check the complete analysis information of the desired packet.

[0120] (13) (see FIG. 15) captured in the trigger signal stop mode different from this, for example, the node equipment 2 ₁ high speed within a certain desired timing before a predetermined time of transmitting the packet to start the desired operation When capturing and analyzing a packet transmitted on the serial bus 1, the operator first performs a trigger signal stop mode setting operation on the operation panel 12.
The controller 30 _n to set the data extraction and write control circuit 69 and the index information analyzing circuit 91 to the trigger signal stop mode. Subsequently, when instructing transmission of a desired operation command from the operation panel 12 to the node device 2 ₁ addressed,
The controller 30 _n sends the asynchronous packet for a desired operation command node equipment 2 ₁ destined to initiate the desired operation. Thereafter, the operation panel 1 is operated at a desired timing.
When the operator performs a trigger operation by using the controller 3, the controller 3
0 _n outputs a trigger signal to the data extraction and write control circuit 69 and the index information analyzing circuit 91.

The data extraction / write control circuit 69 set to the trigger signal stop mode stops writing to the capture memory 70 at the time of input of the trigger signal, and outputs the capture end signal CE. On the other hand, the index information analysis circuit 91 set to the trigger signal stop mode
Does not write to the index memory 90 for the packet being analyzed at the time of input of the capture end signal CE (see reference numeral PC _{# 0 in} FIG. 15), and terminates the analysis operation (some items per packet PC _{# 0).} Storage area P already
When the data has been written to F _{j + 1} , the analysis progress status data of the storage area PF _{j + 1} is written as primary item unanalyzed).
The management start address of the written memory area PF _j of the index information of the packet that has finished the analysis just before you enter a capture end signal CE (reference numeral PC # ₁ in FIG. 15) A and _(j) as AD _E The write address CRA (FIG. 1) being input from the data extraction / write control circuit 69 at the time when the data is written to the information storage area RF and the capture end signal CE is input from the capture memory 70.
The index information is written to the index memory 90 at the earliest of the packets stored after the address following the code ad _# 5 (after the head address when CRA is M), and the analysis progress data management information storage area RF but starting address of a storage area PF _k the index information is written on the packet that primary item parsed (reference numeral PC # ₂ in FIG. 15) a _{(k) is} as AD _S
To memorize.

[0122] As a result, a series in capture memory 70 are transmitted after to initiate the desired operation to the node device 2 _1, over the high-speed serial bus 1 immediately before the worker to trigger within a predetermined time information of all packets are stored in, and, because the index information for each packet stored in the capture memory 70 in the index memory 90 is stored, subsequently, accurately and quickly the operating characteristics of the node equipment 2 ₁ Can be inspected.

(14) 2 in trigger signal stop mode
Analysis of next item and display of analysis information Capture end signal CE in trigger signal stop mode
Controller 30 _n you enter Since the the later reference packet stop mode same processing as when, in a state in which to initiate the desired operation to the node device 2 _1, immediately before the operator has to trigger at a desired timing it has what operation the node equipment 2 ₁ at any timing, it is possible to analyze in detail. Moreover, since the primary item of each packet has been analyzed during the capture, the controller 30 _n only needs to analyze the secondary item after the capture, so that the analysis process of each packet can proceed promptly. The operator can quickly check the complete analysis information of the desired packet.

[0124] In any capture mode, input from the link layer circuit 5 _n, the received packet is stored in the memory 10 also when the operator instructs the display on the operation panel 12, the controller 30 _n memory 10 And all the configuration data is displayed on the display device 11. Also, a received packet can be set as the reference packet.

According to this embodiment, a series of packets transmitted on the high-speed serial bus 1 including the packets transmitted from the serial bus tester 20 _n are separate from the serial bus test controller 30 _n . A desired process such as reading and display from the capture memory 70 can be performed later through the path, so that the serial bus tester 20 _n can operate at high speed without increasing the processing speed of the controller 30 _n. While capturing a large amount of packets transmitted on the bus 1, a desired packet can be transmitted to another node device in parallel.

The data extraction / write circuit 60 of the serial bus tester 20 _n extracts various data transmitted and received between the physical layer circuit 4 _n and the link layer circuit 5 _n and writes the data in the capture memory 70 in parallel. Then, the index information analysis circuit 91 determines a packet from the extracted various data, and stores the storage position of the packet on the capture memory 70 in the index memory 90 for each packet. Therefore, the capture memory 70
After the data has been fetched into the serial bus test, the serial bus test controller 30 _n can quickly search and read the data of the desired packet in the capture memory 70 with reference to the index memory 90, and as a result, For, desired processing for testing including display of all configuration data can be performed quickly. In addition, the index information analysis circuit 91 also analyzes the packet type, transfer speed, packet length, transmission destination ID, transmission source ID, and channel number during the capture and stores them in the index memory 90. When the controller 30 _n wants to analyze various items for a desired packet in the capture memory 70, only the items that have not been analyzed by the index information analysis circuit 91 need to be analyzed, and the entire analysis process can be performed quickly. The operator can quickly obtain the analysis result of the desired packet.

Further, the data extraction / write circuit 60
Extract various data transmitted / received between the physical layer circuit 4 _n and the link layer circuit 5 _n after the desired reference timing, before the reference timing, or before or after the reference timing,
Since the data is stored in the capture memory 70, a test for a desired time range, such as immediately after starting the desired operation in the node device to be tested, immediately before starting the desired operation, or before or after starting the desired operation, is performed. Can be easily performed. At this time, the timing at which the desired reference packet set and input by the operator is transmitted on the high-speed serial bus 1 can be used as the reference timing, so that the reference timing for testing the desired time range is accurately determined. You can also.

In the above embodiment, the controller of the serial bus tester analyzes the presence or absence of the header CRC error and the data CRC error of the captured packet after the capture. Data DATA and write address CR input from the data extraction / write control circuit by the analysis circuit
At the same time as analyzing the index information of each packet based on A, if the packet type indicates that the packet includes a header, a header CRC is calculated from each byte data of the header part and added to the end of the header. By comparing with the header CRC value
It is determined whether or not there is a header CRC error, and when the type of the packet indicates that the packet includes a data block, data CRC is performed from each byte data of the data block.
Is calculated and compared with the value of the data CRC added to the end of the data block to determine whether or not there is a data CRC error, and to determine whether or not there is an error separately for the header CRC error and the data CRC error. The indicated data may be included in the index information and stored in the index memory. In this case, the header CRC error and data CRC error determination circuit may be built in the index information analysis circuit, but the link layer circuit of the serial bus tester also requires the header CRC error and the data CRC error.
Since the C error determination circuit is built in, the determination circuit built in the link layer circuit may be used as well.

One or more of the primary items of the transfer speed, packet length, channel number, source ID, and destination ID may be analyzed by the controller of the serial bus tester.

Further, the serial bus tester according to the above-described embodiment can be realized using a general-purpose personal computer. For example, as shown in FIG. 16, a CPU 101, a memory 102, a hard disk 103, a display device 104, a keyboard 10 connected to an internal bus 100.
The serial bus test expansion board 20 is added to the personal computer 120 including the PC 5. The functions of the controller, the memory, the operation panel, and the display device (see reference numerals 30 _n , 10, 12, and 11 in FIG. 1) of the serial bus tester are respectively a CPU 101 and a memory 102 (providing a work area).
And a hard disk 103 (for storing a test program and test data, etc.), a keyboard 105, and a display device 104.
Embodied in The serial bus test expansion board 20 includes a physical layer circuit 4 _n , a link layer circuit 5 _n , a data extraction / write circuit 60, a capture memory 70, a reference packet setting circuit 80, an index memory 90, an index information analysis circuit 91, and an internal bus. The CPU 101 has an I / F (interface) circuit 201 for connecting to the link layer 100, the link layer circuit 5 _n , the data extraction / write circuit 60, the capture memory 70, and the reference packet via the I / F circuit 21. The setting circuit 80, the index memory 90, and the index information analysis circuit 91 perform control and exchange various data.

Further, in the above-described embodiment, an example is shown in which the controller is built in the serial bus tester. However, the controller may be provided outside the serial bus tester main body. For example, as shown in FIG. 17, a configuration may be provided in which, for example, a personal computer 121 that implements the function of the controller is provided outside the serial bus tester main body 22. The personal computer 121 has an internal bus 1
CPU 123, memory 124, hard disk 125, display device 126, keyboard 127,
I / F for connecting to serial bus tester main body 22
(Interface) The circuit 128 includes a controller, a memory, an operation panel, and a display device (see reference numerals 30 _n , 10, 12, and 11 in FIG. 1) of the serial bus tester.
5, the keyboard 127 and the display device 124. The serial bus tester main body 22 includes a physical layer circuit 4 _n , a link layer circuit 5 _n , a data extraction / write circuit 60,
Capture memory 70, reference packet setting circuit 80, index memory 90, index information analysis circuit 91
And I for connecting to the personal computer 121
The I / F circuits 128 and 23 are connected by a cable 200. The CPU 123 sends the link layer circuit 5 via the I / F circuits 128 and 23.
_n , a control for the data extraction / write circuit 60, the capture memory 70, the reference packet setting circuit 80, the index memory 90, and the index information analysis circuit 91, and exchange of various data.

[0132]

According to the present invention, when the data has been fetched into the capture memory, the index information has already been analyzed. Therefore, the controller for the serial bus test refers to the index memory to determine the desired packet in the capture memory. Data retrieval and reading can be performed quickly, and as a result, desired processing for a test can be performed quickly on a desired packet. In particular, when it is desired to perform an analysis process on a desired packet in the capture memory, only the items that have not been analyzed by the index information analysis circuit need to be analyzed, and the entire analysis process can be performed promptly.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a serial bus test system including a serial bus tester according to one embodiment of the present invention.

FIG. 2 is a specific configuration diagram of a data extraction / write circuit in FIG.

FIG. 3 is an explanatory diagram of reference packet designation data set in a reference packet setting circuit in FIG. 1;

FIG. 4 is an explanatory diagram of storage contents of an index memory in FIG. 1;

FIG. 5 is an explanatory diagram of storage contents of a capture memory in FIG. 1;

FIG. 6 is an explanatory diagram of storage contents of a capture memory in FIG. 1;

FIG. 7 is an explanatory diagram of storage contents of a capture memory in FIG. 1;

FIG. 8 is an explanatory diagram of storage contents of an index memory in FIG. 1;

FIG. 9 is an explanatory diagram of storage contents of an index memory in FIG. 1;

FIG. 10 is an explanatory diagram showing a relationship between storage contents of a capture memory and storage contents of an index memory in a reference packet step over mode.

FIG. 11 is an explanatory diagram showing the relationship between the storage content of a capture memory and the storage content of an index memory in a reference packet start mode.

FIG. 12 is an explanatory diagram showing the relationship between the storage content of a capture memory and the storage content of an index memory in a reference packet stop mode.

FIG. 13 is an explanatory diagram showing the relationship between the storage contents of the capture memory and the storage contents of the index memory in the trigger signal step-over mode.

FIG. 14 is an explanatory diagram showing the relationship between the contents stored in a capture memory and the contents stored in an index memory in a trigger signal start mode.

FIG. 15 is an explanatory diagram illustrating a relationship between storage contents of a capture memory and storage contents of an index memory in a trigger signal stop mode.

FIG. 16 is a configuration diagram showing a modified example of the serial bus tester of FIG. 1;

FIG. 17 is a configuration diagram showing another modified example of the serial bus tester of FIG. 1;

FIG. 18 is an explanatory diagram showing a connection example of a conventional high-speed serial bus.

FIG. 19 is an explanatory diagram showing an example of a format of an isochronous packet used in a high-speed serial bus.

FIG. 20 is an explanatory diagram showing an example of a format of an asynchronous packet used in a high-speed serial bus.

FIG. 21 is an explanatory diagram showing a connection example of a high-speed serial bus test system using a conventional serial bus tester.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 High-speed serial bus 1 ₁ , 1 ₂ ... 1 _n-1 high _- speed serial bus cable 2 ₁ 2 ₂ ... 2 _n-1 node device 10 Memory 11, 104, ₁
26 display device 12 operation panel 105, 127
Keyboard 20 _n Serial bus tester 20 Serial bus test expansion board 22 Serial bus tester main body 30 _n Controller 120, 121 Personal computer 4 _n Physical layer circuit 5 _n Link layer circuit 60 Data extraction / write circuit 70 Capture memory 80 Reference packet Setting circuit 90 Index memory 91 Index information analysis circuit

Continuation of the front page F term (reference) 5K032 AA02 BA08 CD01 DB19 DB28 EA07 5K033 AA02 BA08 CC01 DB12 DB20 EA07 5K035 AA01 EE04 JJ04 KK01

Claims (14)

[Claims] 1. A serial bus which is connected to a serial bus and receives a packet transmission signal from another node device transmitted on the serial bus and converts the packet into reception data or converts transmission data into a transmission signal. A physical layer circuit to be output to the upper side, and connected to the physical layer circuit, generates a transmission packet addressed to another node device according to an instruction of a controller for a serial bus test, and transmits transmission data constituting the transmission packet for handshaking. A link layer circuit that outputs to the physical layer circuit together with the control signal data of the above, or receives the received data from the physical layer circuit together with the control signal data for handshake, extracts a predetermined received packet, and outputs it to the controller for the serial bus test. And a cache for temporarily storing data transmitted and received between the physical layer circuit and the link layer circuit. Capture memory, and a data extraction / write circuit connected to a signal line connecting the physical layer circuit and the link layer circuit, for extracting data transmitted / received between the physical layer circuit and the link layer circuit, and for writing the data to the capture memory. A serial bus test controller performs a desired test process on the packet written to the capture memory by a serial bus tester; and an index memory for temporarily storing index information of the packet temporarily stored in the capture memory. From the data extraction / writing circuit, the packet is determined while inputting the data extracted by the data extraction / writing circuit and the write position to the capture memory, and the index information including the type of the packet and the storage position on the capture memory is determined. Analyze and index each packet And an index information analysis circuit for storing index information in an index memory.When performing a desired test process on a packet written in the capture memory, the serial bus test controller first stores the index information in the index memory. A desired packet is searched for the index information for each stored packet to obtain the index information, the storage position of the desired packet on the capture memory is determined, and the data of the desired packet is read from the capture memory. A serial bus tester characterized in that: 2. A data extracting / writing circuit extracts data transmitted / received between a physical layer circuit and a link layer circuit after a desired reference timing, before a reference timing, or before or after a reference timing, and writes the data into a capture memory. The serial bus tester according to claim 1, wherein: 3. A data extraction / write circuit, comprising: a reference packet designation data setting circuit for setting data for designating a reference timing packet; data transmitted / received between a physical layer circuit and a link layer circuit; A comparison circuit that compares data is transmitted and received between the physical layer circuit and the link layer circuit after the reference timing, before the reference timing, or before or after the reference timing, when the extracted data matches the reference packet designation data as a reference timing. 2. The serial bus tester according to claim 1, wherein said data is extracted and written into a capture memory. 4. The index information according to claim 1, wherein the index information includes a part or all of the header information of the packet in addition to the type of the packet and the storage position on the capture memory. The serial bus tester described. 5. The index information according to claim 1, wherein the index information includes a packet transfer speed.
Or the serial bus tester according to 3 or 4. 6. The serial bus tester according to claim 1, wherein the index information includes the presence or absence of a packet error. 7. A controller for a serial bus test,
The analysis result of an arbitrary packet stored in the capture memory is added to the index memory as index information of the packet, and the result is added to the index memory. 6. The serial bus tester according to 6. 8. A serial bus which is connected to a serial bus and receives a packet transmission signal transmitted from the other node device transmitted on the serial bus and converts the packet into reception data or converts transmission data into a transmission signal. A physical layer circuit to be output on the upper side and a physical layer circuit connected to the physical layer circuit to generate a transmission packet addressed to another node device in accordance with an instruction of an external controller for a serial bus test, and to transmit a transmission data sequence constituting the transmission packet. Output to the physical layer circuit together with the control signal data for shake, or input the received data string from the physical layer circuit together with the control signal data for handshake, extract a predetermined received packet, and output it to the external controller for serial bus test Link layer circuit, capture memory for temporarily storing data, and link with the physical layer circuit. An external controller for a serial bus test, comprising: a data extraction / write circuit that is connected to a signal line connecting the clearer circuit, extracts data transmitted / received between the physical layer circuit and the link layer circuit, and writes the data into a capture memory. A serial bus tester capable of performing a desired test process on a packet written in a capture memory; an index memory for temporarily storing index information of the packet temporarily stored in the capture memory; and a data extraction circuit. From the data extraction circuit, the packet is determined while inputting the extracted data and the write position to the capture memory, and the index information including the type of the packet and the storage position on the capture memory is analyzed. Is stored in the index memory. That includes and index information analyzing circuit, a serial bus tester index information in the packet stored in the index memory external controller for serial bus test, characterized in, that it has freely read. 9. A data extracting / writing circuit extracts data transmitted / received between a physical layer circuit and a link layer circuit after a desired reference timing, before a reference timing, or before or after a reference timing, and writes the extracted data into a capture memory. The serial bus tester according to claim 8, wherein: 10. A data extraction / write circuit, comprising: a reference packet designation data setting circuit for setting data for designating a reference timing packet; a data transmitted / received between a physical layer circuit and a link layer circuit; Data is compared, and the data transmitted / received between the physical layer circuit and the link layer circuit after the reference timing, before the reference timing, or before or after the reference timing is extracted as a reference timing and written to the capture memory. The serial bus tester according to claim 8, wherein: 11. The packet according to claim 8, wherein the index information includes a part or all of the header information of the packet in addition to the type of the packet and the storage position on the capture memory. The serial bus tester described. 12. The serial bus tester according to claim 8, wherein the index information includes a packet transfer speed. 13. The serial bus tester according to claim 8, wherein the index information includes the presence or absence of a packet error. 14. The index memory, wherein an analysis result of an arbitrary packet stored in the capture memory by an external controller for a serial bus test can be added to the index memory as index information of the packet. 14. The serial bus tester according to claim 8, wherein the serial bus tester is characterized in that: