JP2002261139A - Method for manufacturing semiconductor and its system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor and its system that can support high integration and high-speed by means of monitoring fluctuations due to process variations in a system LSI or the like. SOLUTION: A laser 23 is irradiated on a substrate 1 where a pattern or a film is formed, and variations among chips of reflected light levels fluctuating by fluctuation of process conditions is obtained in a chip group within a wafer, and this fluctuation is monitored within the wafer or among wafers, and thus control over the process conditions in a semiconductor manufacturing can be achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a highly integrated and high-speed system LSI or the like, which detects a defect that occurs, analyzes the defect, and takes measures to manufacture the semiconductor. A method and a system thereof.

[0002]

2. Description of the Related Art Conventionally, in manufacturing semiconductors,
For each semiconductor manufacturing process, the process conditions were set such that the thickness of the film and the dimensions after exposure or after etching were measured and these were within a predetermined range.

At this time, if the film formation or etching pattern formed on a semiconductor substrate (wafer) is not within a predetermined range, the defect rate of semiconductor chips in the wafer increases, and the yield of semiconductors (non-defective product rate) ) Will drop.

[0004] The reason why the film thickness or the pattern dimension at the time of exposure / etching does not fall within a predetermined range is as follows: the pressure of the reaction gas, the temperature of the substrate support, the imprint voltage when generating plasma, the process gas. This is caused by fluctuation of various process conditions such as contamination of impurities, a focal position at the time of exposure, a superposition level at the time of exposure, or an input error of an artificial process condition.

[0005] Even in the same liquid crystal display element manufacturing process, if the process conditions such as the pressure of the reaction gas and the level of superposition at the time of exposure fluctuate, the liquid crystal display element cannot be used as a display element. The situation is the same in the manufacturing process of the printed circuit board, and a change in the process condition causes a short circuit of the pattern and a defective connection.

Conventionally, as a light measurement technique, a semiconductor substrate is manufactured by irradiating light onto a semiconductor substrate to measure a film thickness on the semiconductor substrate and, if the thickness is not within a predetermined range, changing a process parameter. Methods are known.

Conventionally, as a SEM length measurement technique, a semiconductor substrate is irradiated with an electron beam to measure a dimension of a formed pattern at the time of exposure or etching, and when it is not within a predetermined range, a process parameter is changed. There is known a method of manufacturing a semiconductor.

Conventionally, as a technique for measuring the thickness of a film or the size of a formed pattern, a method of measuring the film thickness or the pattern by irradiating a wafer with white light and dispersing light emitted from the pattern on the wafer is known. Techniques for measuring dimensions are also known.

Further, a circuit pattern formed on a wafer is irradiated from a direction inclined by 45 degrees with respect to a main straight line group of the circuit pattern, and zero-order diffracted light from the main straight line group is irradiated with an aperture of the objective lens. A foreign matter inspection device that is prevented from being input into the device is known from Japanese Patent Application Laid-Open No. 1-117024. This prior art also describes that a line group other than the main line group is shielded from light by a spatial filter.

[0010]

By the way, in recent years, high integration and high speed have been achieved also in system LSIs and the like, and in addition to the conventional foreign matter defect, the film thickness of the interlayer insulating film, the surface roughness of the wiring layer, etc. The occurrence of timing defects, operating voltage defects, and the like due to process defects is expected.

However, the management of these process conditions is not necessarily achieved only by precise measurement as in the above-mentioned prior art, but can be sufficiently achieved by monitoring the fluctuation of the process variation.

[0012] An object of the present invention is to solve the above problems.
It is an object of the present invention to provide a method of manufacturing a semiconductor and a system thereof capable of coping with high integration and high speed by monitoring a variation in process variation in a system LSI or the like.

[0013]

SUMMARY OF THE INVENTION The basic idea and characteristics of the present invention are as follows. In managing these processes, it is often unnecessary to measure an absolute value, and when this absolute value is not measured, for example, It is possible to provide a method capable of measuring the state of the entire surface of the substrate at a high speed, and to pay attention to the fact that a large amount of results obtained by the high-speed measurement are suitable for the above process management.

According to the present invention, a laser is irradiated onto a substrate on which a pattern or a film is formed, and a variation between chips of a reflected light level which fluctuates due to a change in process conditions is obtained in a chip group in a wafer. An object of the present invention is to achieve the above object by monitoring a change within a wafer or between wafers.

That is, the present invention provides a measuring step of optically measuring the film thickness of an insulating layer formed on a semiconductor substrate or the state of surface roughness of a wiring layer, and the film thickness of the insulating film measured in the measuring step. A quantification step for quantifying the state of the thickness or the surface roughness of the wiring layer; and the insulating layer or the wiring layer based on the thickness of the insulating film or the state of the surface roughness of the wiring layer quantified in the quantification step. And a management system for managing the variation of the process conditions.

Further, according to the present invention, a semiconductor substrate on which an insulating layer or a wiring layer is formed is irradiated with UV or DUV laser light, and reflected light obtained from the semiconductor substrate is detected to detect the thickness of the insulating film or the wiring. A measuring step of converting the signal into a signal corresponding to the surface roughness of the layer, based on the signal converted in the measuring step,
A quantification step of quantifying the state of the film thickness of the insulating film or the surface roughness of the wiring layer; and the insulating based on the thickness of the insulating film or the state of the surface roughness of the wiring layer quantified in the quantification step. And a management system for managing a change in process conditions of a layer or a wiring layer.

Further, according to the present invention, a semiconductor substrate on which chips are arranged and on which an insulating layer or a wiring layer is formed is irradiated with UV or DUV laser light to detect reflected light obtained from the semiconductor substrate and detect an insulating film. A measurement step of converting the signal into a signal corresponding to the film thickness of the wiring layer or the surface roughness of the wiring layer, and the variation between the chips regarding the film thickness of the insulating film or the surface roughness of the wiring layer based on the signal converted in the measurement step. Between the chips calculated in the chip group in the semiconductor substrate, and monitoring the variations obtained in the chip-to-chip variation calculation process in the semiconductor substrate or between the semiconductor substrates to determine the process conditions of the insulating layer or the wiring layer. A semiconductor manufacturing method and system including a management step of managing fluctuations.

Further, according to the present invention, a semiconductor substrate on which an insulating layer or a wiring layer is formed is irradiated with UV or DUV laser light, and reflected light obtained from the semiconductor substrate is detected to detect the thickness of the insulating film or the wiring. A measuring step of converting the signal into a signal corresponding to the surface roughness of the layer, based on the signal converted in the measuring step,
A quantification step for quantifying the thickness of the insulating film or the surface roughness of the wiring layer; and a plurality of groups according to the thickness of the insulating film or the surface roughness of the wiring layer quantified in the quantification step. Classification step, a yield calculation step of calculating a semiconductor yield for each group classified in the classification step, and the insulating layer or the wiring for a group in which the yield calculated in the yield calculation step is smaller than a target value. Controlling the process conditions of the layer to the process conditions of the insulating layer or the wiring layer of the group having the calculated high yield.

Further, according to the present invention, a semiconductor substrate on which chips are arranged and on which an insulating layer or a wiring layer is formed is irradiated with UV or DUV laser light to detect reflected light obtained from the semiconductor substrate and detect an insulating film. A measurement step of converting the signal into a signal corresponding to the film thickness of the wiring layer or the surface roughness of the wiring layer, and evaluating the quality of each chip for the film thickness of the insulating film or the surface roughness of the wiring layer based on the signal converted in the measurement step. And a quality evaluation step of providing the quality evaluation result for each chip.

Further, the present invention is characterized in that, in the measuring method of the semiconductor manufacturing method and the semiconductor manufacturing method, scattered reflected light generated from a semiconductor substrate is detected.

Further, according to the present invention, in the quantification step of the semiconductor manufacturing method and the semiconductor system, the quantified film thickness of the insulating film or the surface roughness of the wiring layer is presented as a distribution on a semiconductor substrate. It is characterized by including a step.

In the present invention, the quantified film thickness of the insulating film or the state of the surface roughness of the wiring layer is presented as a frequency distribution on the semiconductor substrate in the quantifying step of the semiconductor manufacturing method and the system thereof. It is characterized by including a presentation step.

In the present invention, in the quantification step of the method of manufacturing a semiconductor device and the system therefor, the state of the film thickness of the insulating film or the surface roughness of the wiring layer quantified on a chip-by-chip basis is represented as a distribution on a semiconductor substrate. It is characterized by including a presenting step of presenting.

Further, the present invention includes a step of presenting the state of the thickness of the insulating film or the surface roughness of the wiring layer quantified in a chip unit in the quantifying step of the semiconductor manufacturing method and the system thereof. It is characterized.

Further, the present invention is characterized in that the step of calculating the yield of the semiconductor manufacturing method and the system includes a step of presenting the calculated semiconductor yield for each group.

As described above, according to the above configuration,
In a short time, process variations within or between wafers can be quantified and monitored, so that process variations that cause semiconductor defects can be discovered and countermeasures promptly. It can be known at an early stage as shown, and the yield can be effectively improved.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A system LS according to the present invention having a required ultrafineness, high-speed signal and high performance in the future.
An embodiment of a semiconductor manufacturing method and a system for manufacturing I at a high yield will be described with reference to the drawings.

That is, when manufacturing a system LSI 1b having ultra-fineness, high-speed signal and high performance, FIG.
As shown in FIG.
Not only the short-circuit defect 2a and the disconnection defect 2b between the wiring patterns having a size of about 0.3 μm or less become a problem, but also an interlayer insulating film formed on the semiconductor substrate as shown in FIG. 3 (about 0.3 to 1 μm) (10 to 50% including the inclination) and the thickness of the wiring pattern 4 as well as the surface roughness (grain) (10 to 50 nm). About (When the wiring width is about 0.1 μm, about 10 to 50% of the wiring width)
Is a problem. In particular, in high-speed semiconductor devices,
The variation in the film thickness of the interlayer insulating film 3 affects C (conductance) and L (inductance) of the wiring pattern, and causes a problem of signal timing shift (delay). The surface roughness of the wiring pattern 4 causes a problem that the resistance increases at the time of a high-speed clock (high-frequency signal). That is, the system LSI 1b
In such cases, the thickness (about 0.3 to 1 μm) of the interlayer insulating film 3 formed on the semiconductor substrate (about 10 to 5
0%) and variations in the thickness of the wiring pattern 4, as well as variations in surface roughness (grain) slightly affect the quality (high-speed transmission, high-speed response, etc.). In DRAMs, SRAMs, flash memories, and the like, as the density increases (for example, 1 Gbit or more), the thickness (including the inclination) of the interlayer insulating film 3 and the thickness of the wiring pattern 4 change as well. Variations in surface roughness (grain) will affect quality.
However, since the film formation of the wiring layer is usually performed by sputtering, the dispersion of the film thickness is small, and the measurement can be easily and accurately performed by a normal measuring device. Description is omitted.

Therefore, according to the present invention, the thickness of the interlayer insulating film 3 (0.3 to
Fluctuation (variation) of about 1 μm (including inclination)
0%), and the variation (variation) in the surface roughness (grain) (10-5) of the wiring pattern 4 having the wiring width of about 0.1 to 0.3 μm or less.
(About 0 nm) is quickly monitored not only between wafers but also between chips in a wafer, so that an abnormal state is immediately found, and a detailed analysis is performed on the semiconductor substrate (semiconductor wafer) in this abnormal state. The aim is to realize a high yield by finding abnormal processes and taking countermeasures.

In the present invention, not only the variation (variation) (including inclination) of the thickness of the interlayer insulating film 3 and the variation (variation) of the thickness of the wiring pattern 4 but also the variation (grain) of the surface roughness (grain) thereof. As shown in FIG. 2, as the object 1 to be monitored for monitoring (variation) at a high speed, the memory LS
There is a semiconductor wafer 1a in which chips 1aa of I are two-dimensionally arranged at predetermined intervals. The chip 1aa composed of the memory LSI mainly includes the memory cell region 1ab
In addition, a peripheral circuit area 1ac including a decoder and a control circuit and the other area 1ad are formed.
The memory cell region 1ab has a minimum line width of, for example, 0.1 to
A memory cell pattern of about 0.3 μm is regularly arranged (repeated) two-dimensionally. However, the peripheral circuit region 1ac has a minimum line width of, for example, 0.2 to
A pattern of about 0.4 μm is formed as a non-repetitive pattern that is not regularly arranged two-dimensionally. As another area, for example, there is a bonding area area (the minimum line width is, for example, on the order of 10 μm, which is almost equal to no pattern).

As the object 1 to be measured, FIG.
As shown in FIG. 1, there is a semiconductor wafer 1b in which chips 1ba formed of LSIs (including a system LSI) such as a microcomputer are two-dimensionally arranged at predetermined intervals. A chip 1ba composed of an LSI such as a microcomputer is mainly formed of a register group area 1bb, a memory section area 1bc, a CPU core section area 1bd, and an input / output section area 1be. FIG. 3 shows the register group area 1bb and the memory section area 1
bc, CPU core area 1bd, input / output area 1b
3 conceptually shows an arrangement with e. The register group area 1bb and the memory section area 1bc are formed by regularly (two-dimensionally) arranging a pattern having a minimum line width of, for example, about 0.1 to 0.3 μm. The CPU core area 1bd and the input / output area 1be form a pattern having a minimum line width of, for example, about 0.1 to 0.3 μm in a non-repeating manner.

As described above, the object to be measured 1 is not limited to the chips 22 (1aa, 1b) even if the object is a semiconductor wafer.
Although a) is regularly arranged, in the chip, the minimum line width differs for each region, and the pattern may be repeated, non-repeated, or absent.

When measuring the surface roughness (grain) of the wiring pattern, the object to be measured 1 is shown in FIG.
As shown in (a), a wiring pattern (patterned by etching or the like) or a wiring layer (merely Al,
Metals such as Cu and W are deposited by sputtering etc.)
4a is formed. When measuring the thickness of the interlayer insulating film 3a, the object 1 to be inspected is as shown in FIG.
As shown in (b), a CVD is formed on the wiring pattern 4b.
An insulating film 3a made of SiO ₂ , SiN ₄ or the like is formed by using a method such as CMP (Chemical Mechanical).
Polishing (polishing) results in a flattened state. In addition, even when measuring the surface roughness (grain) of the wiring pattern 4, as shown in FIG. 4B, SiO ₂ , Si
An insulating film 3a of N ₄ or the like may be formed, and the surface thereof may be polished by CMP and flattened. 4a indicates an upper wiring pattern, 4b indicates a lower wiring pattern, and 4c indicates a lower wiring pattern.

Next, not only the fluctuation (including the inclination) of the thickness of the interlayer insulating film 3a and the fluctuation of the thickness of the wiring pattern 4a with respect to the DUT 1 but also the surface roughness (grain) thereof. First, an embodiment of a measuring device that monitors fluctuations at a high speed will be described with reference to FIGS. This measuring device is configured to detect foreign substances attached to the surface of a semiconductor wafer. That is, the first embodiment of the measuring apparatus includes the substrate mounting table 304, the xyz stages 301, 302, 303, and the stage controller 3.
Stage section 300 composed of the laser light source 1
01, a beam splitter composed of a concave lens 102 and a convex lens 103, and three illumination optical system units 100 composed of an illumination lens 104 having a conical curved surface;
NA (Numerical Aperture) is 0.
Detection lens (objective lens) having about 35 to 0.45
201, imaging lens 203, ND (Neutral D)
efficiency) filter 207, beam splitter 20
4. Ultraviolet (UV) light or deep ultraviolet (DUV: Deep)
Ultraviolet) One-dimensional detectors (image sensors) 205, 20 such as TDI sensors having sensitivity to light
6 and a processing unit 4
00 and a white illumination optical system section 500 including a white light source 106 and an illumination lens 107.

In particular, an anti-blooming type is desirable as the TDI sensor. As described above, when the anti-blooming type is used as the TDI sensor, measurement in the vicinity of the saturation region becomes possible.

The details of the arithmetic processing section 400 will be described later.

The three illumination optical system units 100 pass the laser light composed of UV or DUV light emitted from the laser light source 101 through a beam splitter composed of a concave lens 102 and a convex lens 103 and an illumination lens 104 having a conical curved surface. As shown in FIG. 6, the beam 23 having a slit shape is transferred from three directions 10, 11, and 12 in a plan view.
The longitudinal direction of the slit beam 23 is set to the chip 22 with respect to the wafer (substrate to be measured) 1
Is configured to be illuminated in the direction of arrangement. In addition,
The reason why the slit-shaped beam 23 is used as the illumination light is to realize high-speed measurement of the surface roughness of the wiring film and the thickness of the insulating film. That is, as shown in FIG.
The beam 23 illuminated on the wafer 1 on which the chips 22 are arranged in the x direction of the scanning direction of 01 and the y direction of the scanning direction of the y stage 302 is narrow in the scanning direction y of the y stage 302 and its vertical direction x (The scanning direction of the x-stage 301) is formed by a wide slit beam. The slit-shaped beam 23 is illuminated so that an image of the light source forms an image on the surface of the wiring film in the y direction, and becomes parallel light in the x direction. In addition, three directions 10, 1
The illumination of the slit-shaped beams 23 from 1 and 12 may be performed individually, or may be performed simultaneously from the two directions 10 and 12. Further, the slit-shaped beam 23 may be simultaneously emitted from only two directions 10 and 12.

By the way, the longitudinal direction of the slit-like beam 23 is set so that the chip 2
2 and at right angles to the scanning direction y of the y stage 302 are the TDI sensors 205 and 20.
6 can be kept parallel to the traveling direction of the stage, so that a normal TDI sensor can be used, and the comparison between image signals between chips can be simplified, and the measurement coordinates can be measured. Can be easily calculated, and as a result, the measurement of the surface roughness of the wiring film, the thickness of the insulating film, and the like can be speeded up. In particular,
Illumination of the slit-like beam 23 from the directions 10 and 12 directs the chips 22 with respect to the wafer 1 in the arrangement direction,
In addition, in order to make the y-axis 302 perpendicular to the scanning direction y, the illumination lens 104 having a conical curved surface
Is required.

The illumination lens 104 has a different focal length at a position in the longitudinal direction of the cylindrical lens, and has a linearly changed focal length. With this configuration, even if illumination is performed diagonally (both α1 and φ1 inclinations are compatible),
It can be illuminated with a slit-like beam 23 that is narrowed down in the y direction and collimated in the x direction. That is, the illumination lens 104 has parallel light in the x direction and φ
Illumination around 1 = 45 degrees can be realized. In particular,
By making the slit-shaped beam 23 parallel to the x direction, a diffracted light pattern can be obtained from a wiring pattern in which the main straight line groups are oriented in the x and y directions.
As a method of manufacturing the illumination lens 104 having a conical curved surface,
A glass or quartz material can be used as a material, and a cone having a predetermined bottom area and height can be polished, and a plane on one side can be cut out from a predetermined position to create a lens. Further, the NA of the illumination lens 104 may be about 0.02 to 0.2.

In the present invention, the critical direction in the y direction and the collimation in the x direction are realized using the conical lens 104. Laser light composed of UV or DUV light emitted from the laser light source 101 passes through a beam expander including a concave lens 102 and a convex lens 103,
The light enters the conical lens 104. In the conical lens 104,
It is illuminated in a collimated form because it has no lens effect in the x direction. Further, since the curvature is different at both ends of the conical lens 104, the focal position is different. At the same time, in the y direction, the light is focused on the surface of the wiring layer on the wafer 1 due to the curvature of the conical lens 104.

FIG. 6 shows three illumination optical systems 100 constituted by one laser light source 101 as the laser light source 101.
FIG. The laser beam emitted from the laser light source 101 is divided into two by a branch optical element 110 such as a half mirror.
One is reflected by mirrors 111 and 112, and the other is reflected by mirrors 113 and 112 and is directed downward by mirror 113 to concave lens 102, whereby an illumination beam from the direction of 11 can be obtained. Optical element 1
Proceed to 14. One of the light beams branched by the branching optical element 114 is reflected by a mirror 115 and is made to enter the concave lens 102 downward by a mirror 117 so that 1
An illumination beam from the direction 0 can be obtained, and the other side can be obtained by making the mirror 116 face down and enter the concave lens 102. By the way, when illuminating only from the direction of 11, it can be realized by switching from the branch optical element 110 to the mirror element 118. In the case of illuminating only from the directions 10 and 12, it can be realized by withdrawing the branch optical element 110 from the optical path or by switching to a straight optical element.
Also, of the illuminations from 10 and 12 directions, for example, 12
When illuminating from only a direction, switching from the branch optical element 114 to the mirror element 119 can be realized.

As the laser light source 101, it is preferable to use a harmonic (wavelength: 266 nm (far ultraviolet laser light)) twice as high as the second harmonic SHG of a high-output YAG laser.
As the laser light source 101, a KrF (krypton fluoride) excimer laser light source (wavelength: 249 nm), A
rF (argon fluoride) excimer laser light source, F ₂ excimer laser light source, second harmonic of Ar laser (wavelength 24
4 nm), He-Cd laser light source (wavelength is 325 nm)
Can be used. Each laser light source is a light source that emits deep ultraviolet (DUV) laser light.

The detection optical system 200 converts the light emitted from the wiring layer of the wafer 1 into a detection lens (objective lens) 201 having an NA of about 0.35 to 0.45 and an imaging lens 20.
3. One-dimensional detectors 205 and 206 such as a TDI sensor having sensitivity to far ultraviolet light (excimer laser light) pass through an ND filter (adjust the light amount regardless of the wavelength band) 207 and a beam splitter 204. It is composed of When measuring the surface roughness (grain) on the surface of the patterned wiring pattern, a spatial filter is used in the spatial frequency region of the objective lens 201, that is, in the sense that the Fourier transform image due to the reflected diffraction light from the repeated wiring pattern is shielded. The image may be at an image forming position of Fourier transform (corresponding to an exit pupil). Thus, when a spatial filter is provided, the one-dimensional detectors 205 and 206
As a result, only surface roughness on the surface of the wiring pattern is detected.

Here, the illumination area on the wafer 1 is controlled by the one-dimensional detector 20 such as a TDI sensor by the objective lens 201 and the imaging lens 203 constituting a relay lens.
5, 206.

Next, measurement of the surface roughness (grain) of the surface on which the wiring layer 4 is formed as the object to be measured (wafer) 1 will be described. That is, the wiring layer (the state of the wiring film before being patterned) 4a shown in FIG.
Is irradiated with the slit-shaped excimer laser beam 23 on the substrate to be measured (wafer) 1 a on which
Scattered light will be generated according to the state of the surface roughness. If there is no surface roughness, some scattered light will be generated,
More are specularly reflected and 0.35-
It will not be incident on NA having about 0.45.
Further, for example, the wavelength of the illumination excimer laser light (240 to
The state of surface roughness (grain) based on micro unevenness (pitch of about 50 nm to 1 μm in a plane) of about 10 to 50 nm called microroughness of about 4 to 20% of about 300 to about 50 nm is about 10 to 50 nm. Like the minute foreign matter, a large amount of the scattered light 5 is generated and incident on the objective lens 201, and the incident scattered light 5 is converted into the image forming lens 20.
Then, the image is formed at 3, and can be detected by the one-dimensional detectors 205 and 206 such as a TDI sensor through the ND filter 207 and the beam splitter 204.

Here, the order of the ND filter 207 and the beam splitter 204 does not need to be the order described here. In particular, when the ND filter 207 is disposed after the beam splitter 204, the two detectors 205, 2
This has the effect that the intensity of light entering 06 can be controlled independently.

The ratio between the transmittance and the reflectance of the beam splitter 204 does not need to be 50%. For example, when the transmittance is set to 1% and the reflectance is set to 99%, light having an intensity of about 1/100 is incident on one of the detectors, and light having different intensities is received. By using signals obtained from the two detectors, the apparent dynamic range of the detectors can be improved. Therefore, the arithmetic processing unit 400 uses the signal obtained from the detector 205 and the signal obtained from the detector 206 to generate a detection signal corresponding to the surface roughness (grain) of the wiring layer whose dynamic range is improved. Obtainable. In particular, in the signal obtained by the detector 206 receiving the light of high intensity, the signal indicating the surface roughness (grain) of high intensity is emphasized, and the signal obtained by receiving the light of low intensity by the detector 205 is obtained. In the resulting signal, a component close to a background having a small intensity (there is almost no grain) is emphasized. Therefore, the arithmetic processing unit 400 can improve the dynamic range of the signal showing the grain by correlating the ratio between the two signals and the like.

However, the dynamic range can also be changed by controlling and changing the illuminance (power) of the beam emitted from the illumination optical system such as the laser light source 101, and the beam splitter 204 and one of the detectors 206 can be changed. Can be eliminated.

Next, an oxide film (SiO ₂ ) whose surface is flattened by CMP is used as an object to be measured (wafer) 1b.
Example 1 for measuring the thickness of an insulating film formed of a transparent film such as a transparent film or a nitride film (SiN ₄ ) will be described. That is, FIG.
When the slit-shaped excimer laser beam 23 is applied to the substrate to be measured (wafer) 1b in which the insulating film 3a is formed on the wiring pattern 4b shown in (b), the wiring mainly passes through the insulating film 3a. It will reach the surface of pattern 4b. Then, most of the light is specularly reflected on the surface of the wiring pattern 4b and emerges from the surface of the insulating film 3a, but is not incident on the NA of the objective lens 201 having about 0.35 to 0.45. . However, scattered reflected light 6a, 6b is generated from the edge of the wiring pattern 4b, and strong scattered reflected light 6a that is not attenuated from the thin portion of the insulating film 3 comes out of the surface of the insulating film, and The weak scattered reflected light 6b which is incident on the pupil and is attenuated from a thick portion of the insulating film 3a to a thin portion.
Emerges from the surface of the insulating film and enters the pupil of the objective lens 201. Thus, the illumination light is, for example, at the wavelength of the illumination excimer laser light (240 to 300 nm).
), The insulating film 3
The intensity of the scattered and reflected light incident on the objective lens 201 varies according to the difference in the film thickness a. As a result, many scattered light beams 6a and 6b whose intensity is changed according to the film thickness of the insulating film 3 are formed by the imaging lens 203 to form an image.
One-dimensional detectors 205 and 206 such as a TDI sensor through a D filter 207 and a beam splitter 204
Can be detected by

Next, as an object to be measured (wafer) 1b, an oxide film (SiO ₂ ) whose surface is flattened by CMP.
Example 2 for measuring the thickness of an insulating film formed of a transparent film such as a nitride film or a nitride film (SiN ₄ ) will be described. That is, FIG.
Is irradiated with a slit-shaped excimer laser beam 23 on a substrate to be measured (wafer) 1b having an insulating film 3a formed on a wiring pattern 4b shown in FIG. Will reach the surface. Then, as shown in FIG. 7, the wiring pattern 4b
The intensity of the light 36, 37, 38 changes due to the interference between the edge (scattering object) 34 and the mirror image 34 '. That is, these intensities I change in accordance with the thickness of the insulating film 3a. As a result, when detection is performed from the same direction, the intensity of the detection light changes. However, when considering this model, the output of the detection light does not change depending on the direction of illumination. This has also been confirmed by experiments.

Next, a detection optical system for detecting the intensities of the light beams 36, 37, and 38 from three directions will be described with reference to FIG. That is, light 36 emitted in three directions θ1, θ2, θ3,
37 and 38 are imaged by detection lenses 210, 211 and 212, and detected by detectors 216, 217 and 218, respectively. These detection signals are output from the A / D converters 451 and 452,
A / D conversion is performed at 453 and the result is input to the arithmetic unit 454.
As a result, as shown in FIG.
The thickness of the insulating film 3a can be measured from the relationship between the two signal intensities.

The number of the detection systems 210, 211 and 212 is not necessarily three, but may be two. The detection system here includes a plurality of detection systems 200 shown in FIG. 5 (for example, an inclination angle β1 = 0 degrees with respect to a vertical axis, β2 = 4
5 degrees). If the range of the thickness variation of the insulating film 3a to be measured is about 50 nm or less, the thickness can be measured from the intensity signal I detected from one direction.

In the present invention, as described above, in a high-speed semiconductor device, the variation in the thickness of the interlayer insulating film 3 on the wafer and the C (conductance) of the wiring pattern measured in an operation test performed almost after completion. , And L (inductance), and the relationship between the surface roughness of the wiring pattern 4 on the wafer and the R (resistance) of the wiring pattern measured in an operation test performed almost after completion.

For this purpose, first, the thickness variation (μ (average value), σ (standard deviation)) of the interlayer insulating film 3 on the wafer, and the surface roughness (μ (average value)) of the wiring pattern 4 on the wafer , Σ (standard deviation)) in chip units and / or wafer units and / or lot units,
It is necessary to find each representative point.

Next, the thickness variation (μm) of the interlayer insulating film 3 between the wafers, between the chips in the wafer, and in the radial direction.
(T) (average value), σ (t) (standard deviation)), and surface roughness of the wiring pattern 4 (μ (g) (average value), σ (g)
5 and FIG.
Explanation will be made using 0. The difference between the maximum value and the minimum value may be used instead of the standard deviation.

First, an insulating film 3 is formed on the wiring pattern 4a by CVD or the like, and the surface is formed by CMP (Chemic).
4B, the wafer 1 flattened by, for example, mechanical polishing is mounted on the substrate mounting table 304, and the surface is irradiated with the beam 23 as shown in FIG. The intensity signals I1 and I2 corresponding to the thickness of the insulating film 3 are input to the pre-processing circuit 450 of the arithmetic processing unit 400. In the preprocessing circuit 450, each signal is A
A / D conversion is performed by a / D converter (not shown), shading correction and noise removal are performed, and furthermore, correlation data (for example, a ratio I1 / 1) in which the dynamic range indicating the thickness of the insulating film is improved. I2) Obtain 461 and temporarily store it in a data memory (not shown).

The insulating film thickness calculating section 451 includes a maximum / minimum removing circuit section 405 for removing the maximum and minimum from the film thickness data 461 read from the data memory, and a film thickness data St obtained from the removing circuit 405. From the average value (μ (t)) of the film thickness St in the N × N pixel group and its variance (σ
(T)) over the entire surface of the wafer, the average value (μ _p (t)) and its variance (σ _p (t)) of the film thickness St at a representative location on the wafer, and the distribution at the representative location for each chip. A calculating unit 424 for calculating an average value (μ _c (t)) of the film thickness St and its standard deviation (σ _c (t)); a film thickness data St obtained from the removing circuit 405; The average value (μ (t), μ _p (t), μ _c (t)) of the film thickness St and the variance (σ (t) at the calculated entire surface of the wafer, the representative portion on the wafer, and the representative portion for each chip. ), Σ _p (t), σ _c (t)). The calculation unit 42
Reference numeral 4 denotes a part for calculating an average value, which includes a calculation circuit 407, a sum calculation circuit 410, and an average value calculation circuit 413, and a square calculation circuit 406, a square sum calculation circuit 409, and a variation calculation circuit 412. And a part for obtaining a variance. Then, the range on the wafer (the position of the representative portion) for obtaining the average value and the variance of the film thickness St is given by the coordinates on the wafer from the memory position controller 422. The memory position controller 422 receives the stage coordinate system from the overall control unit 417.

As described above, the data memory 404
The overall control unit 417 displays the distribution of the thickness of the insulating film for each N × N pixel group, the distribution of the dispersion, and the distribution of the difference between the maximum value and the minimum value on the entire surface of the wafer in the display device 421 by contour lines. When displayed, the result shown in FIG. 11A is obtained.
Therefore, in the present invention, as shown in FIG. 11B, for example, as shown in FIG. (T) fluctuation Δμ (t), variance (variation) σ
(T) variation Δσ (t) or local maximum μ
Difference (variation) Δt between max (t) and minimum value μmin (t)
If (μmax (t) −μmin (t)) exceeds the allowable range, it can be output to the storage device 427 or the like as a defect. In addition, a template of the distribution of the local average value μ (t) of the film thickness St and the distribution of the local variance σ (t) of the standard wafer is prepared, and a chip at a location exceeding the allowable range from the template is stored as a defective chip. It is also possible to output to the device 427 or the like.

The film thickness calculating section 451 calculates an average value ｛μ () as a parameter indicating a variation Δt of a local average value μ (t) of the film thickness St and a local dispersion σ (t) over a specific region of the wafer. μ (t)), μ (σ (t))} and variance {σ (μ (t)), σ (σ (t))}, and a parameter indicating the obtained variation Δt over a specific region of the wafer. Mean value {μ (μ (t)), μ (σ (t))}
The variance {σ (μ (t)), σ (σ (t))} is used as a representative value of the wafer as shown in FIG.
7 makes it possible to grasp the transition for each lot.

As the specific region of the wafer, the severest portion on the wafer can be grasped in advance, so that the local average of the film thickness measured over a plurality of chips 131 shown in FIG. Value μ (t) and local variance σ
The frequency distribution of (t) (the average value ｛μ (μ
(T)), μ (σ (t))} and variance {σ (μ
(T)), σ (σ (t))}. ) Can be used as the representative value of the wafer. FIG. 13B shows a film thickness measurement region in the chip. As shown in FIGS. 14A and 14B, the specific region of the wafer may be, for example, line-symmetric in the x direction.
FIG. 14 (b) may be partially measured in the chip.

Further, as shown in FIG. 15, the overall control unit 417 controls the yield of the wafer obtained through the network based on the result of the inspection by the probe inspection apparatus and the representative value (average) of the film thickness of the wafer. Value ｛μ (μ (t)), μ
(Σ (t))} and variance {σ (μ (t)), σ (σ
(T)) By pre-correlating with｝),
Conversely, the yield of the wafer can be calculated based on the newly measured representative value of the thickness of the wafer.

Further, as shown in FIG. 16A, the overall control unit 417 instructs the memory position controller 422 to
By setting representative locations (for example, locations where the gate line width is narrow) 161 and 162 in the chips 1aa and 1ba, the film thickness calculation unit 451 allows the average value μ of the film thickness at the representative locations.
(T) and its variance σ (t) are calculated and stored in the memory 40.
4 is stored. Then, the overall control unit 417 determines in FIG.
As shown in (c), since a large number of chips are arranged on the wafer, the average value μ (t) of the film thickness at a representative portion in the chip and its variance σ (t) are plotted on the horizontal axis. The calculated frequency distribution (variation distribution for each chip in a wafer) can be calculated. In this frequency distribution, a chip in which the average value μ (t) of the film thickness and its variance σ (t) are equal to or more than a specified value is shown by oblique lines in FIG. Furthermore,
FIG. 16D shows the difference between the yield of the chip indicated by the oblique lines and the yield of the other chips. As described above, since it has been found that there is a difference in the yield, which is the inspection result of the probe inspection apparatus, it is meaningful to measure the thickness of the representative portion in the chip. The setting of the representative portion in the chip is performed by displaying the arrangement information of the circuit pattern in the chip on the display device 42
1 and can be performed by designating a point where a high-frequency signal at which a variation in film thickness becomes a problem is transmitted.

Further, the overall control unit 417 is configured as shown in FIG.
The semiconductor chips can be classified into a plurality of groups according to the frequency distribution shown in FIG. And the overall control unit 41
7 can calculate the yield of the semiconductor chips by checking the result of the operation test by the probe test with the pass / fail judgment result for each of the classified groups. Further, the overall control unit 417 controls the network to control the process conditions of the insulating layer for the group in which the calculated yield is smaller than the target value so as to be the process conditions of the insulating layer in the group in which the calculated yield is large. 4
Production line management system (not shown) connected to 28
, It is possible to feed back to the process steps of the insulating layer.

As shown in FIG. 18, the chip 1a
It is possible to display the variation of the film thickness at the point 181 where the high frequency signal which is a problem in performance in b and 1bb is transmitted, on the display device 421 in shades or colors. As a result, a chip is classified into a high-quality product with a small variation (high-grade product), a medium-quality product with a relatively small variation (intermediate product), and a low-quality product with a large variation (low-grade product). It is also possible. Then, by marking the selected result on each chip, it is possible to cut the wafer into chips from the state of the wafer, and then sort the good products into high-grade products, intermediate-grade products, and low-grade products. Naturally, it is also possible to sort out non-defective products and defective products in chip units. Further, by marking each of the non-defective products and the non-defective products, it is possible to select the non-defective products and the non-defective products after cutting the chips from the wafer state.

The defect rate can also be grasped by displaying the hatched map or the number of chips shown in FIG. 16B on the display device 421 or the like. Of course, when outputting to the display device 421 or the like, contour lines of the film thickness in chip units may be displayed.

As described above, in the present invention,
Since a large number of chips composed of system LSIs are arranged on the wafer, the average values of the film thicknesses {μ (μ (t)), μ (σ (t))} measured from a representative portion in the chip, and Variation (dispersion) {T (x, y) − between the chips for the variance {σ (μ (t)), σ (σ (t))}
It is important to find μ (x, y) or σ (x, y)}. Note that (x, y) indicates coordinates in the chip. T (x, y) indicates basic data of the film thickness in the chip (standard data of the film thickness).

Further, an insulating film 3a is formed at a predetermined position in the chip.
As shown in FIGS. 17A and 17B, in order to measure the film thickness of TE, TEs arranged in a grid pattern under the insulating film 3a were used.
A G pattern 171 may be formed. By arranging the lattice-like TEG patterns 171 in this manner, scattered light from more edge portions can be detected by the detection optical system 200, and the film thickness at more points can be measured. You can do it.

For example, in the overall control unit 417,
As shown in FIG. 19A, by plotting the level of variation in the film thickness on a chip-by-chip basis, it is possible to correlate with the circuit operation characteristic inspection result by the probe inspection device. FIG. 19B shows a frequency distribution of film thickness variations (μ (t), σ (t)) in a wafer. FIG. 19C shows the variation (Δμ (t), Δσ (t)) of the variation in the film thickness in the wafer, for example, in the y direction.

As described above, for example, as shown in FIG. 20, the overall control unit 417 controls the insulating film 3a on the wafer.
Is displayed on the screen 20 of the display device 421 by displaying, for example, contour lines, shading values, colors, and the like on the screen 20 of the display device 421 (including variations between specific locations (representative locations) in the chip). Can be identified as appropriate. In addition, the overall control unit 417 checks the transition 22 of the film thickness Δt at the representative location on the wafer or the representative location in the representative chip in lot units, and displays it on the screen 20 of the display device 421. This makes it possible to manage whether or not the film thickness has become abnormal.

Next, the measurement of the surface roughness of the wiring layer 4a will be described.

That is, similarly to the measurement of the thickness of the insulating film 3a, the wafer 1 on which the wiring layer 4a is formed is mounted on the substrate mounting table 304, and as shown in FIG. From the detectors 205 and 206, the intensity signals indicating the state of surface roughness on the surface of the wiring pattern
I1 and I2 are input to the pre-processing circuit 450 of the arithmetic processing unit 400. In the preprocessing circuit 450, each signal is A /
A / D conversion is performed by a D converter (not shown), shading correction, noise elimination, and the like are performed, and furthermore, correlation data (for example, the ratio I1) in which the dynamic range indicating the state of surface roughness (grain) is improved. / I2) 461
Is temporarily stored in a data memory (not shown).

The surface roughness calculating section 451 reads the data from the data memory.
Determine the maximum and minimum from the read surface roughness data 461
A maximum / minimum removal circuit section 405 to be removed;
From the surface roughness data Sg obtained from FIG.
Average value (μ (g)) of surface roughness for each N × N group
Standard deviation (σ (g)), surface at specific location on wafer
Average value of roughness (μ_p(G)) and its standard deviation (σ
_p(G)), and surface roughness at specific locations for each chip
Average value (μ_c(G)) and its standard deviation (σ
_c(G)) a calculating unit 424 for calculating
05 and the calculation unit 4
24, the specific location on the wafer,
And surface roughness (grain) at specific locations for each chip
Average value (μ (g), μ _p(G), μ_c(G)) and its
Standard deviation (σ (g), σ_p(G), σ_c(G))
And a data memory 404. And rough
Wafer for which the average and standard deviation of grains are to be calculated
The upper range (specific position) is the same as the film thickness measurement.
The coordinates on the wafer from the re-position controller 422
Given.

As described above, the data memory 404
The overall control unit 417 displays the surface roughness distribution of the wiring layer for each N × N pixel group, the distribution of the dispersion, and the distribution of the difference between the maximum value and the minimum value on the entire surface of the wafer stored in the display device 421 by contour lines. When displayed, the result shown in FIG. 11A is obtained. Therefore, in the present invention, the overall control unit 417
For example, as shown in FIG. 11B, when viewed in the radial direction of the wafer, the variation Δμ (g) of the average value μ (g) and the variance (variation) in a local portion (for example, an N × N pixel group) of the surface roughness Sg. ) Variation of σ (g) Δσ (g) or difference (variation) between local maximum value μmax (g) and minimum value μmin (g)
If Δg = (μmax (g) −μmin (g)) exceeds the allowable range, it can be output to the storage device 427 or the like as a defect. Further, a template of the distribution of the local average value μ (g) of the film thickness Sg and the distribution of the local variance σ (g) of the standard wafer is prepared, and the chips at locations beyond the allowable range from the template are stored as defective chips. Device 42
7 and the like.

The surface roughness calculator 451 calculates the local average value μ (g) of the surface roughness (grain) Sg and the local variance σ (g).
Mean values ｛μ (μ (g)) and μ (σ) as parameters indicating the variation Δg of the
(G))} and variance {σ (μ (g)), σ (σ
(G)) is determined, and the average value {μ (μ) as a parameter indicating the obtained variation Δg over the specific region of the wafer is determined.
(G)), μ (σ (g))} and variance {σ (μ
(G)), σ (σ (g))} as representative values of the wafer,
As shown in FIG. 12, the management by the overall control unit 417 makes it possible to grasp the transition for each lot.

As the specific region of the wafer, the severest portion on the wafer can be grasped in advance, and therefore the local average of the surface roughness measured over a plurality of chips 131 shown in FIG. Value μ (g) and local variance σ
The frequency distribution of (g) (FIG. 13 (c) shows the average value ｛μ (μ
(G)), μ (σ (g))} and variance {σ (μ
(G)), σ (σ (g))}. ) Can be used as the representative value of the wafer. FIG. 13B shows a surface roughness measurement region in the chip. As shown in FIGS. 14A and 14B, the specific region of the wafer may be, for example, line-symmetric in the x direction. FIG. 14 (b) may be partially measured in the chip.

Further, as shown in FIG. 15, the overall control unit 417, as shown in FIG. 15, obtains the yield of the wafer obtained through the network based on the result of the inspection by the probe inspection apparatus and the representative value (average average) of the surface roughness of the wafer. Value ｛μ (μ (g)), μ
(Σ (g))} and variance {σ (μ (g)), σ (σ
(G)) By pre-correlating with｝),
Based on the representative value of the newly measured wafer surface roughness,
Conversely, the yield of the wafer can be calculated.

Further, as shown in FIG. 16A, the overall control unit 417 instructs the memory position controller 422 to
By setting representative locations (for example, locations where the gate line width is narrow) 161 and 162 in the chips 1aa and 1ba, the surface roughness calculation unit 451 allows the surface roughness average value μ (g) and the variance σ of the surface roughness at the representative locations. (G) is calculated and stored in the memory 4
04. Then, the overall control unit 417 determines in FIG.
As shown in (c), since a large number of chips are arranged on the wafer, the average value μ (g) of the surface roughness at a representative portion in the chip and its dispersion σ (g) are plotted on the horizontal axis. The calculated frequency distribution (variation distribution for each chip in a wafer) can be calculated. In this frequency distribution, a chip in which the average value μ (g) of surface roughness and its variance σ (g) are equal to or more than a specified value is shown by hatching in FIG. FIG. 16D shows the difference between the yield of the chip indicated by the oblique lines and the yield of the other chips. in this way,
Since it has been found that there is a difference in the yield, which is the inspection result of the probe inspection device, it is meaningful to measure the surface roughness of a representative portion in the chip. Note that the setting of the representative portion in the chip can be performed by displaying the arrangement information of the circuit pattern in the chip on the display device 421 and designating a portion to which a high-frequency signal for which variation in surface roughness is a problem is transmitted. it can.

Further, the overall control unit 417 determines whether or not the
The semiconductor chips can be classified into a plurality of groups according to the frequency distribution shown in FIG. And the overall control unit 41
7 can calculate the yield of the semiconductor chips by checking the result of the operation test by the probe test with the pass / fail judgment result for each of the classified groups. Further, the overall control unit 417 controls the network layer process condition for the group in which the calculated yield is smaller than the target value so as to be the process condition of the wiring layer in the group in which the calculated yield is large. 4
Production line management system (not shown) connected to 28
, It is possible to feed back to the process steps of the wiring layer.

Further, as shown in FIG.
It is possible to display the variation of the film thickness at the point 181 where the high frequency signal which is a problem in performance in b and 1bb is transmitted, on the display device 421 in shades or colors. As a result, a chip is classified into a high-quality product with a small variation (high-grade product), a medium-quality product with a relatively small variation (intermediate product), and a low-quality product with a large variation (low-grade product). It is also possible. Then, by marking the selected result on each chip, it is possible to cut the wafer into chips from the state of the wafer, and then sort the good products into high-grade products, intermediate-grade products, and low-grade products. Naturally, it is also possible to sort out non-defective products and defective products in chip units. Further, by marking each of the non-defective products and the non-defective products, it is possible to select the non-defective products and the non-defective products after cutting the chips from the wafer state.

Further, by outputting the map or the number of chips indicated by oblique lines shown in FIG. 16B on the display device 421 or the like, the defect rate can be grasped. Of course, when outputting to the display device 421 or the like, contour lines of surface roughness in chip units may be displayed.

As described above, in the present invention,
Since a large number of chips composed of system LSIs are arranged on a wafer, the average values of surface roughness {μ (μ (t)), μ (σ (t))} measured from a representative portion in the chip,
And the variance {σ (μ (t)), σ (σ (t))} between chips (variation) ｛T (x, y)
It is important to find -μ (x, y) or σ (x, y)}. Note that (x, y) indicates coordinates in the chip. T (x, y) indicates basic data of surface roughness in the chip (standard data of surface roughness).

The wiring layer 4a is provided at a predetermined location in the chip.
21A and 21B for measuring the surface roughness of
As shown in FIG. 7, a pad-shaped TEG pattern 211 may be formed. By forming the TEG pattern 211 in this manner, the scattered light generated by the surface roughness of the surface of the TEG pattern can be detected by the detection optical system 200, and the state of the surface roughness can be accurately measured. .

For example, in the overall control unit 417,
As shown in FIG. 19A, by plotting the level of variation in surface roughness in chip units, it is possible to relate the level to the circuit operation characteristic inspection result by the probe inspection apparatus. FIG. 19B shows a frequency distribution of surface roughness variations (μ (g), σ (g)) in the wafer. FIG. 19C shows the variation (Δμ (g), Δσ (g)) of the variation in the surface roughness in the wafer, for example, in the y direction.

As described above, for example, as shown in FIG. 20, the overall control unit 417
Is displayed on the screen 20 of the display device 421 by using, for example, contour lines, shading values, colors, and the like on the surface roughness distribution 21 (including variations between specific locations (representative locations) in the chip). Can be identified as appropriate. In addition, the overall control unit 417 examines the variation 22 of the surface roughness of the representative location on the wafer or the representative location in the representative chip on a lot basis and displays the variation 22 on the screen 20 of the display device 421. By
It is possible to manage whether the surface roughness has become abnormal.

In the embodiment described above, as shown in FIG. 22, similarly to the foreign matter inspection apparatus, the measuring apparatus shown in FIG. 5 according to the present invention is used as a line monitor, and the measurement is performed by each measuring apparatus. The management system 220 collects the data of the thickness of the insulating layer and the surface roughness of the wiring layer.
Calculate distributions showing variations on the wafer based on the data collected by, and correlate with the operation or performance test results of the semiconductor chip obtained from the probe inspection device 221 and feed the results back to the process steps Is also possible. In this case, the management system 220 is connected to the overall control unit 417 of each measurement device via the network 428. And the management system 22
Of course, the display device 421, the storage device 427, and the like are connected to 0, and a part of the processing performed by the overall control unit 417 can be shifted.

[0086]

According to the present invention, process variations within a wafer or between wafers can be quantified and monitored in a short period of time. Therefore, it is possible to cope with the cause of the decrease in the yield at an early stage when a sign appears, and it is possible to effectively improve the yield.

[Brief description of the drawings]

FIG. 1 is a sectional view of a device showing a failure example of a system LSI according to the present invention.

FIG. 2 is a diagram showing semiconductor memory chips arranged on a semiconductor substrate (wafer) according to the present invention.

FIG. 3 is a diagram showing a system LSI chip arranged on a semiconductor substrate (wafer) according to the present invention.

FIG. 4 is a diagram for explaining a case where a surface of a wiring layer having a rough surface is obliquely illuminated with DUV laser light and a case where a DUV laser light is obliquely illuminated on an insulating layer having a wiring pattern in a lower layer. is there.

FIG. 5 is a diagram showing a schematic configuration of a semiconductor manufacturing system including a measuring apparatus according to the present invention.

6 is a plan view of the measuring device shown in FIG.

FIG. 7 is a principle view showing another embodiment of the insulating film thickness measuring apparatus.

8 is a diagram showing a schematic configuration of the embodiment shown in FIG. 7;

FIG. 9 is an explanatory diagram for measuring a film thickness using the apparatus shown in FIG. 8;

FIG. 10 is a configuration diagram specifically showing an arithmetic processing unit and an overall control unit shown in FIG. 5;

FIG. 11 is a diagram showing a distribution of a process state (film thickness of an insulating layer and surface roughness of a wiring layer) in a wafer.

FIG. 12 is a diagram showing a transition of a lot in a process state (variation in film thickness of an insulating layer and surface roughness of a wiring layer) in a wafer.

FIG. 13 is a diagram showing an example in which the process state of a plurality of chip groups (variation in the thickness of an insulating layer and the roughness of a wiring layer) is represented as a representative value of a wafer.

FIG. 14 is a diagram showing an example in which the process state (variation in the thickness of the insulating layer and the roughness of the wiring layer) of a plurality of chip groups is represented as a representative value of the wafer.

FIG. 15 is a diagram showing a relationship between a process state (variation in the thickness of an insulating layer and surface roughness of a wiring layer) as a representative value of a wafer and a wafer yield.

FIG. 16 is a diagram showing a relationship between a position representing a process state in a chip, a distribution of a process state between chips in a wafer, and a yield (non-defective product or defective product).

FIG. 17 is a diagram showing an example of a TEG pattern for measuring a film thickness.

FIG. 18 is a diagram showing a portion where a process state is represented between chips;

FIG. 19 is a diagram for explaining that process states are classified into a plurality of groups on a chip-by-chip basis.

FIG. 20 is a diagram showing a distribution of a process state (including a chip unit) on a wafer displayed (presented) on a screen of a display device and a transition of a lot thereof.

FIG. 21 is a diagram showing an example of a TEG pattern for measuring surface roughness of a wiring layer.

FIG. 22 is a diagram for explaining the position of a semiconductor manufacturing system according to the present invention in a manufacturing line.

[Explanation of symbols]

1, 1a, 1b: substrate to be measured (semiconductor substrate, wafer), 1aa, 1ba: semiconductor chip, 1bb: register group area, 1bc: memory area, 1bd: CPU core area, 1be: input / output area, 2a ... Short-circuit defect, 2b disconnection defect, 3, 3a interlayer insulating film (insulating layer), 4, 4a,
4b, 4c: wiring pattern (wiring layer), 20: screen, 2
1 ... distribution of film thickness and surface roughness, 22 ... lot transition of film thickness and surface roughness, 23 ... excimer laser beam, 100 ... illumination optical system unit, 101 ... laser light source, 131 ... multiple chips, 161, 162 ... in chip , Detecting optical system unit, 204 Beam splitter, 207 ND
Filters, 205, 206: detector, 220: management system, 221: probe inspection device, 304: substrate mounting table, 300: stage unit, 400: arithmetic processing unit, 404
... Data memory, 417 ... Overall control unit, 421 ... Display device, 422 ... Memory position controller, 424 ... Calculation unit, 427 ... Storage device, 428 ... Network, 450
... Pre-processing circuit, 451.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shunji Maeda 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Manufacturing Research Laboratory, Hitachi, Ltd. Address: Within Hitachi, Ltd., Production Technology Laboratory (72) Inventor: Rei Hamamatsu 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside: Hitachi, Ltd. 292-machi, Hitachi, Ltd., Production Technology Research Laboratory, Hitachi Ltd. (72) Inventor Hidetoshi Nishiyama 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture F-term in Hitachi, Ltd. Production Technology Research Laboratories F-term (reference) CA48 DB08 DJ20 DJ38

Claims (22)

[Claims] A measuring step of optically measuring a thickness of an insulating layer formed on a semiconductor substrate or a surface roughness of a wiring layer; and a film thickness or a wiring layer of the insulating film measured in the measuring step. A quantification step of quantifying the state of the surface roughness of the insulating layer or the process conditions of the insulating layer or the wiring layer based on the state of the surface roughness of the wiring layer quantified in the quantification step. And a management step of managing fluctuations. 2. A semiconductor substrate on which an insulating layer or a wiring layer is formed is irradiated with UV or DUV laser light to detect reflected light obtained from the semiconductor substrate to detect the thickness of the insulating film or the surface roughness of the wiring layer. A quantifying step of quantifying a state of the thickness of the insulating film or a surface roughness of the wiring layer based on the signal converted in the measuring step; A method for managing a variation in the process conditions of the insulating layer or the wiring layer based on the quantified film thickness of the insulating film or the state of surface roughness of the wiring layer. 3. A semiconductor substrate on which chips are arranged and on which an insulating layer or a wiring layer is formed is irradiated with UV or DUV laser light, and reflected light obtained from the semiconductor substrate is detected to detect the thickness of the insulating film. A measuring step of converting the signal into a signal corresponding to the surface roughness of the wiring layer; and, based on the signal converted in the measuring step, a variation in the thickness of the insulating film or the surface roughness of the wiring layer between the chips in the semiconductor substrate. A variation calculation process to be determined within the group of chips, and a variation determined by the variation calculation process between the chips is monitored in the semiconductor substrate or between the semiconductor substrates to manage a variation in a process condition of the insulating layer or the wiring layer. And a managing step. 4. A semiconductor substrate having an insulating layer or a wiring layer formed thereon is irradiated with UV or DUV laser light, and reflected light obtained from the semiconductor substrate is detected to detect the thickness of the insulating film or the surface roughness of the wiring layer. A quantifying step of quantifying a state of the thickness of the insulating film or a surface roughness of the wiring layer based on the signal converted in the measuring step; A classification step of classifying the plurality of groups according to the quantified thickness of the insulating film or the surface roughness of the wiring layer; and a yield calculation step of calculating a semiconductor yield for each group classified in the classification step. For the group in which the yield calculated in the yield calculation step is smaller than the target value, the process condition of the insulating layer or the wiring layer is changed to the professional level of the insulating layer or the wiring layer of the group in which the calculated yield is large. And a control step of controlling the process conditions. 5. A semiconductor substrate on which chips are arranged and on which an insulating layer or a wiring layer is formed is irradiated with UV or DUV laser light, and reflected light obtained from the semiconductor substrate is detected to detect the thickness of the insulating film or A measuring step of converting the signal into a signal corresponding to the surface roughness of the wiring layer, and evaluating the quality of each chip for the thickness of the insulating film or the surface roughness of the wiring layer based on the signal converted in the measuring step. A quality evaluation step of giving a quality evaluation result for each chip. 6. The method of manufacturing a semiconductor according to claim 1, wherein in the measuring step, scattered reflected light generated from the semiconductor substrate is detected. 7. The quantifying step includes a presenting step of presenting the quantified film thickness of the insulating film or the state of the surface roughness of the wiring layer as a distribution on the semiconductor substrate. The method for manufacturing a semiconductor according to any one of the above. 8. The method according to claim 1, wherein said quantifying step includes a presenting step of presenting the quantified film thickness of the insulating film or the surface roughness of the wiring layer as a frequency distribution on the semiconductor substrate. 5. The method for manufacturing a semiconductor according to any one of the items 4. 9. The method according to claim 1, wherein the quantifying step includes a step of presenting a state of the film thickness of the insulating film or the surface roughness of the wiring layer quantified on a chip-by-chip basis as a distribution on a semiconductor substrate. 5. The method for manufacturing a semiconductor according to any one of 1 to 4. 10. The method according to claim 1, wherein the quantifying step includes a presenting step of presenting a state of the thickness of the insulating film or the surface roughness of the wiring layer quantified on a chip-by-chip basis. A method for manufacturing a semiconductor according to one aspect. 11. The semiconductor manufacturing method according to claim 5, wherein said yield calculation step includes a presentation step of presenting the calculated semiconductor yield for each group. 12. A measuring device for optically measuring the film thickness of an insulating layer formed on a semiconductor substrate or the surface roughness of a wiring layer, and the film thickness or wiring layer of the insulating film measured by the measuring device. Quantifying means for quantifying the state of the surface roughness of the insulating layer or the process conditions of the insulating layer or the wiring layer based on the state of the surface roughness of the insulating layer or the wiring layer quantified by the quantifying means. A semiconductor manufacturing system, comprising: management means for managing fluctuations. 13. A semiconductor substrate having an insulating layer or a wiring layer formed thereon is irradiated with UV or DUV laser light to detect reflected light obtained from the semiconductor substrate to detect the thickness of the insulating film or the surface roughness of the wiring layer. A measuring device that converts the signal into a signal corresponding to the following: a quantifying unit that quantifies the state of the film thickness of the insulating film or the surface roughness of the wiring layer based on the signal converted by the measuring device; A semiconductor manufacturing system comprising: management means for managing a change in process conditions of the insulating layer or the wiring layer based on the quantified state of the thickness of the insulating film or the surface roughness of the wiring layer. . 14. A semiconductor substrate on which chips are arranged and on which an insulating layer or a wiring layer is formed is irradiated with UV or DUV laser light, and reflected light obtained from the semiconductor substrate is detected to detect the thickness of the insulating film or A measuring device that converts the signal into a signal corresponding to the surface roughness of the wiring layer, and a variation in the thickness of the insulating film or the surface roughness of the wiring layer between the chips in the semiconductor substrate based on the signal converted by the measuring device. Means for calculating inter-chip variation to be determined within the group of chips, and monitoring the variation obtained by the inter-chip variation calculating means within a semiconductor substrate or between semiconductor substrates to manage a change in process conditions of the insulating layer or the wiring layer. A semiconductor manufacturing system, comprising: a management unit. 15. A semiconductor substrate having an insulating layer or a wiring layer formed thereon is irradiated with UV or DUV laser light to detect reflected light obtained from the semiconductor substrate to detect the thickness of the insulating film or the surface roughness of the wiring layer. A measuring device that converts the signal into a signal corresponding to the following: a quantifying unit that quantifies the state of the film thickness of the insulating film or the surface roughness of the wiring layer based on the signal converted by the measuring device; Classifying means for classifying into a plurality of groups according to the state of the quantified film thickness of the insulating film or surface roughness of the wiring layer; and a yield calculating means for calculating the yield of semiconductor in each group classified by the classifying means. For the group in which the yield calculated by the yield calculating means is smaller than the target value, the process condition of the insulating layer or the wiring layer is changed to the group of the insulating layer or the wiring layer of the group in which the calculated yield is large. Control means for controlling the process conditions. 16. A semiconductor substrate on which chips are arranged and on which an insulating layer or a wiring layer is formed is irradiated with UV or DUV laser light, and reflected light obtained from the semiconductor substrate is detected to detect the thickness of the insulating film. A measuring device that converts the signal into a signal corresponding to the surface roughness of the wiring layer; and, based on the signal converted by the measuring device, evaluate the quality of each chip for the thickness of the insulating film or the surface roughness of the wiring layer. A semiconductor manufacturing system, comprising: quality evaluation means for giving a quality evaluation result to each chip. 17. The semiconductor manufacturing system according to claim 12, wherein the measuring device is configured to detect scattered reflected light generated from the semiconductor substrate. 18. The quantification means further comprising a display means for presenting the quantified state of the thickness of the insulating film or the surface roughness of the wiring layer as a distribution on the semiconductor substrate. The semiconductor manufacturing system according to any one of the above. 19. The quantifying means further comprises a display means for presenting the quantified thickness of the insulating film or the roughness of the wiring layer as a frequency distribution on the semiconductor substrate. 15. The semiconductor manufacturing system according to any one of the fifteenth to fifteenth aspects. 20. The quantification means, further comprising a display means for presenting a state of the film thickness of the insulating film or the surface roughness of the wiring layer quantified for each chip as a distribution on a semiconductor substrate. 16. The semiconductor manufacturing system according to any one of 12 to 15. 21. The apparatus according to claim 12, wherein said quantifying means includes a display means for presenting a state of the film thickness of the insulating film or the surface roughness of the wiring layer quantified on a chip-by-chip basis. A semiconductor manufacturing system according to one of the above. 22. The semiconductor manufacturing system according to claim 15, wherein said yield calculating means includes a display means for presenting the calculated semiconductor yield for each group.