JP2002252384A - Piezoelectric ceramic - Google Patents
Piezoelectric ceramicInfo
- Publication number
- JP2002252384A JP2002252384A JP2001049229A JP2001049229A JP2002252384A JP 2002252384 A JP2002252384 A JP 2002252384A JP 2001049229 A JP2001049229 A JP 2001049229A JP 2001049229 A JP2001049229 A JP 2001049229A JP 2002252384 A JP2002252384 A JP 2002252384A
- Authority
- JP
- Japan
- Prior art keywords
- piezoelectric ceramic
- internal electrode
- piezoelectric actuator
- internal electrodes
- exposed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、加圧により電圧を
生じさせるセンサや、電圧を加えて変位又は力を生じさ
せる積層型圧電アクチュエータの構造に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sensor for generating a voltage by applying pressure and a structure of a laminated piezoelectric actuator for generating a displacement or a force by applying a voltage.
【0002】[0002]
【従来の技術】従来の密閉ケースに封入しない圧電アク
チュエータとして、特開2000−270568号公報
に記載されたものが公知である。また、密閉ケースに封
入した形では、積層型圧電セラミックの内部電極2は露
出状態、または組み立て時の電極変形防止のため樹脂が
塗布されていた。2. Description of the Related Art As a conventional piezoelectric actuator which is not enclosed in a sealed case, one described in Japanese Patent Application Laid-Open No. 2000-270568 is known. In the case where the internal electrodes 2 of the laminated piezoelectric ceramic are sealed in a sealed case, a resin is applied in an exposed state or in order to prevent electrode deformation during assembly.
【0003】[0003]
【発明が解決しようとする課題】従来技術は、積層型圧
電セラミックの内部電極2が露出していると、内部電極
2の積層間で絶縁破壊を生じる欠点がある。また、エポ
キシ樹脂の塗布したものでは、塗布材料と母材の層間に
ボイドが発生し、ボイドによって形成される空間内の内
部電極間で絶縁破壊を起こすという欠点があった。The prior art has a disadvantage that when the internal electrodes 2 of the laminated piezoelectric ceramic are exposed, dielectric breakdown occurs between the laminations of the internal electrodes 2. In addition, in the case where the epoxy resin is applied, a void is generated between the layer of the applied material and the base material, and a dielectric breakdown occurs between internal electrodes in a space formed by the void.
【0004】したがって、本発明の課題は、露出した内
部電極2と圧電セラミクス層1を共に、耐電圧及び絶縁
破壊を防止するような絶縁材料としてシリコンを付着さ
せ、耐電圧や絶縁抵抗の低下をしないようにすることで
ある。[0004] Therefore, an object of the present invention is to deposit silicon as an insulating material for preventing the withstand voltage and dielectric breakdown of both the exposed internal electrode 2 and the piezoelectric ceramic layer 1 to reduce the withstand voltage and the insulation resistance. It is not to be.
【0005】[0005]
【課題が解決するための手段】積層型圧電セラミックの
内部電極2の露出する面の内部電極2の一部または全部
にシリコン材料を付着し覆う。Means for Solving the Problems A silicon material is attached to and covers a part or the whole of the internal electrode 2 on the exposed surface of the internal electrode 2 of the laminated piezoelectric ceramic.
【0006】[0006]
【作用】本発明によれば、積層型圧電セラミックの圧電
セラミック1を挟んだ相隣り合う内部電極2の層状の電
極間が電気絶縁材料で覆われるため、内部電極2が密閉
ケース内の気体に暴露されず、また、低粘度のシリコン
材料を塗布させることによりシリコン材の内部にボイド
が発生することが無く、内部電極間の気体を介した放電
をおさえ、絶縁材料であるシリコン材が放電を防止する
ため、耐電圧と絶縁抵抗を向上させることが可能であ
る。According to the present invention, the space between the layered electrodes of the adjacent internal electrodes 2 sandwiching the piezoelectric ceramic 1 of the laminated piezoelectric ceramic is covered with an electrically insulating material, so that the internal electrodes 2 are exposed to the gas in the closed case. By not being exposed and applying a low-viscosity silicon material, voids are not generated inside the silicon material, and the discharge through the gas between the internal electrodes is suppressed, and the silicon material, which is an insulating material, discharges. To prevent this, it is possible to improve the withstand voltage and the insulation resistance.
【0007】[0007]
【実施の形態】以下に発明の実施例を、図面を参照して
更に説明する。Embodiments of the present invention will be described below with reference to the accompanying drawings.
【0008】図1は、本実施例による積層型圧電セラミ
ックを示す図であり、圧電セラミックシートにAg/P
d系の内部電極2を印刷した圧電セラミックシートと、
内部電極2を印刷していない圧電セラミックシートを積
層し、その後熱プレスにより一体化した後、焼成を行っ
ている。さらに、焼成処理を行った焼成体は、機械加工
による外形形状加工と、内部電極2が1層おきに対向電
極となるように絶縁体3および外部電極4の形成を行っ
ている。また、内部電極2の露出する面の加工は、ダイ
ヤモンドカッターで切断後、切断面のラップ処理を行っ
ている。FIG. 1 is a view showing a laminated piezoelectric ceramic according to the present embodiment.
a piezoelectric ceramic sheet on which d-type internal electrodes 2 are printed;
Piezoelectric ceramic sheets on which the internal electrodes 2 are not printed are laminated, then integrated by hot pressing, and then fired. Further, in the fired body that has been subjected to the firing treatment, the outer shape processing is performed by machining, and the insulator 3 and the external electrode 4 are formed so that the internal electrodes 2 become counter electrodes every other layer. In the processing of the exposed surface of the internal electrode 2, after cutting with a diamond cutter, lapping of the cut surface is performed.
【0009】図3は、図1の積層型圧電セラミックにシ
リコン材料を付着させたものの断面A−Aの拡大を示
す。内部電極2が露出した面に、圧電セラミック層1と
内部電極2とが共にシリコン材料で覆われるように付着
させる。付着させるシリコン材料は、電気高絶縁材料と
して電子部品に広く使用されており、デッピング又は噴
射塗布を行うことにより、1ミクロンメートル以上の層
状の膜を付着形成することが出来る。FIG. 3 shows an enlarged cross section AA of the laminated piezoelectric ceramic of FIG. 1 with a silicon material adhered thereto. The piezoelectric ceramic layer 1 and the internal electrode 2 are attached to the exposed surface of the internal electrode 2 so that both the piezoelectric ceramic layer 1 and the internal electrode 2 are covered with a silicon material. Silicon materials to be deposited are widely used as electronically high insulating materials for electronic components, and can form a layered film of 1 micron or more by dipping or spray coating.
【0010】図2は、上記シリコン材料を付着させた積
層型圧電セラミックを密閉ケース7に組み込んだ形態を
示したものであり、外部電極4から密閉ケース外に電気
的に接続させるリード線8を付設したものである。FIG. 2 shows a form in which the laminated piezoelectric ceramic to which the above-mentioned silicon material is adhered is incorporated in a sealed case 7, and a lead wire 8 for electrically connecting the external electrode 4 to the outside of the sealed case is provided. It is attached.
【0011】他の実施形態として、密閉ケース内にシリ
コン材料を一部又は全体に充填し、積層型圧電セラミッ
クの周囲をシリコン材料で覆い、表面に付着させたもの
と同様の効果を得ることが出来る。As another embodiment, it is possible to obtain the same effect as that obtained by partially or entirely filling a sealed case with a silicon material, covering the periphery of the laminated piezoelectric ceramic with the silicon material, and attaching the piezoelectric material to the surface. I can do it.
【図1】積層型圧電セラミックを示す図である。FIG. 1 is a view showing a laminated piezoelectric ceramic.
【図2】密閉ケース入り圧電アクチュエータを示す図で
ある。FIG. 2 is a view showing a piezoelectric actuator in a sealed case.
【図3】シリコンを付着させた積層型圧電セラミクスの
断面を示す図である。FIG. 3 is a diagram showing a cross section of a laminated piezoelectric ceramic to which silicon is attached.
1 圧電セラミック層 2 内部電極層 3 絶縁層 4 外部電極 5 積層型圧電セラミクス 6 シリコン材料 7 密閉ケース 8 リード線 DESCRIPTION OF SYMBOLS 1 Piezoelectric ceramic layer 2 Internal electrode layer 3 Insulating layer 4 External electrode 5 Stacked piezoelectric ceramics 6 Silicon material 7 Sealed case 8 Lead wire
Claims (2)
層が2層以上となるよう積層した積層体と、この積層体
の側面に内部電極が1層おきに対向電極となるように絶
縁体層の形成または内部電極の一部を形成せずに圧電セ
ラミックの一部を絶縁体層とし、その上に外部電極を形
成した積層型圧電セラミックを密閉ケースに封入した圧
電アクチュエータにおいて、積層型圧電セラミックの表
面に露出する内部電極の一部または全部に、絶縁材料を
付着させたことを特徴とする圧電アクチュエータ。1. A laminate in which three or more piezoelectric ceramic layers and two or more internal electrode layers are laminated, and an insulator is provided such that every other internal electrode is a counter electrode on the side surface of the laminate. In a piezoelectric actuator in which a part of the piezoelectric ceramic is used as an insulator layer without forming a layer or part of the internal electrode, and a multilayer piezoelectric ceramic with external electrodes formed on it is enclosed in a closed case, A piezoelectric actuator, wherein an insulating material is attached to part or all of an internal electrode exposed on a surface of a ceramic.
を用いた圧電アクチュエータ。2. The piezoelectric actuator according to claim 1, wherein silicon is used as an insulating material.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001049229A JP2002252384A (en) | 2001-02-23 | 2001-02-23 | Piezoelectric ceramic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001049229A JP2002252384A (en) | 2001-02-23 | 2001-02-23 | Piezoelectric ceramic |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2002252384A true JP2002252384A (en) | 2002-09-06 |
Family
ID=18910364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001049229A Pending JP2002252384A (en) | 2001-02-23 | 2001-02-23 | Piezoelectric ceramic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2002252384A (en) |
-
2001
- 2001-02-23 JP JP2001049229A patent/JP2002252384A/en active Pending
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A712 Effective date: 20061219 |