JP2002252288A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiple value mask ROM which is difficult to receive the influence of short channel effect without using a special refinement technol ogy. SOLUTION: A source Shottky electrode 14 is formed on the region 4 of MOS FET which is the memory cell of a mask ROM and a drain Shottky electrode 15 is formed on the drain region 5. The multiple value condition is stored because the distances between the source region 4 and the gate electrode 3 is different.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device.

[0002]

2. Description of the Related Art A mask ROM in which information is written in advance by using a mask pattern in a semiconductor device manufacturing process is used as a nonvolatile memory in electronic equipment such as a personal computer.

In recent years, as the information to be stored has increased, the storage capacity of the mask ROM has been required to increase. Usually, an increase in storage capacity is realized by miniaturizing individual devices constituting a mask ROM. However,
In some cases, the manufacturing technology for miniaturization cannot keep up with the demand for large capacity, or the cost of the manufacturing technology required for miniaturization is technically feasible but too high for the actual product price.

In order to solve this problem, a method has been conceived which realizes different drive current values and can store multi-values, instead of the conventional on-state and off-state selection of the transistor of the mask ROM. I have.

FIG. 9 shows a method of manufacturing a conventional storage device capable of performing such multi-value storage.

Each memory cell including a transistor having a source region 4, a drain region 5, a gate insulating film 2, and a gate electrode 3 formed thereon is formed on a silicon substrate 1.
Is integrated on top. Each memory cell is isolated by an isolation region 8. Polycrystalline silicon 9 is formed on each transistor.

First, a mask 11 is formed so that an opening is located on a gate electrode 3 of a desired transistor formed on a transistor array. Then, impurity ions are implanted into the gate electrode 3 of this transistor. Thus, this transistor has a certain threshold.

Next, a mask 11 is formed on the gate electrode 3 of another transistor so as to locate an opening. Then, a different threshold value is given by implanting a different amount of impurity ions from the previous transistor.

By repeating such a process a plurality of times, transistors having a plurality of different threshold values can be integrated on a substrate and stored in a multi-valued manner.

However, in this method, the device
When the size is reduced, the threshold value fluctuates due to the fluctuation of the threshold value due to the short channel effect and the fluctuation of the number of impurities to be doped. There is also a problem that the magnitudes of a plurality of drive currents to be detected fluctuate.

[0011]

Conventionally, the threshold current of each transistor of a memory cell is changed by changing the amount of impurities to obtain multi-valued data. However, when a transistor is miniaturized, the magnitude of a plurality of drive currents to be detected fluctuates due to a threshold change due to a short channel effect or fluctuation of the number of impurities.

The present invention has been made in view of the above problems, and has as its object to provide a multi-valued nonvolatile semiconductor memory device which is hardly affected by a short channel effect and a fluctuation in the number of impurities even when miniaturized. I do.

[0013]

In order to solve the above-mentioned problems, the present invention relates to a nonvolatile semiconductor memory device having a plurality of memory cells and capable of reading multi-valued storage information.
The memory cell includes a transistor, and the transistor has a Schottky electrode formed on a source region and a drain region.

In a nonvolatile semiconductor memory device having a first memory cell having a first transistor and a second memory cell having a second transistor, the first transistor and the second transistor may have a source A nonvolatile semiconductor memory device having a Schottky electrode formed over a region and a drain region, wherein the first transistor and the second transistor have different distances between a source region and a gate electrode. provide.

In a nonvolatile semiconductor memory device having a first memory cell having a first transistor and a second memory cell having a second transistor, the first transistor and the second transistor may have a source A non-volatile semiconductor memory device having a Schottky electrode formed over a region and a drain region, wherein the first transistor and the second transistor have different distances between the drain region and the gate electrode. provide.

At this time, the first and second memory cells can read multi-valued storage information.

In addition, a semiconductor layer, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film, and a channel formed in the semiconductor layer below the gate insulating film A transistor comprising: a region, a source region and a drain region disposed in the semiconductor so as to face each other across the channel region, and a Schottky electrode formed on the source region and the drain region. Wherein a plurality of transistors having different distances between an end of the source region on the gate electrode side and an end of the gate electrode on the source region side are provided.

Further, according to the present invention, there is provided a semiconductor device comprising: a semiconductor layer; a gate insulating film formed on the semiconductor layer; a gate electrode formed on the gate insulating film; A transistor comprising: a formed channel region; a source region and a drain region disposed in the semiconductor so as to face each other across the channel region; and a Schottky electrode formed on the source region and the drain region. The present invention provides a storage device including a plurality of transistors each having a different distance between an end of the transistor on the gate electrode side and an end of the gate electrode on the drain region side of the transistor.

The present invention is also a storage device in which memory cells in which at least three different states are recorded are integrated, wherein the memory cells are composed of a semiconductor layer and a gate formed on the semiconductor layer. An insulating film, a gate electrode formed on the gate insulating film, a channel region formed in the semiconductor layer below the gate insulating film, and opposed to each other in the semiconductor with the channel region interposed therebetween. A transistor including a source region and a drain region, and a Schottky electrode formed on the source region and the drain region; and an end of the source region on the gate electrode side of the transistor and the source of the gate electrode. A storage device is characterized in that the distance from the end on the area side is different.

According to another aspect of the present invention, there is provided a storage device in which memory cells in which at least three different states are recorded are integrated, wherein the memory cells include a semiconductor layer and a gate formed on the semiconductor layer. An insulating film, a gate electrode formed on the gate insulating film, a channel region formed in the semiconductor layer below the gate insulating film, and opposed to each other in the semiconductor with the channel region interposed therebetween. A transistor including a source region and a drain region, and a Schottky electrode formed on the source region and the drain region; and an end of the transistor on the gate electrode side of the drain region and the drain of the gate electrode. Provided is a storage device characterized in that a distance from an end on an area side is different.

In the present invention, transistors having different distances between the source region and the gate electrode in the direction of the substrate surface are integrated on the substrate. By recording the difference in the amount of drive current due to the difference in the distance between the source region and the gate electrode in the direction of the substrate surface as three or more different states, a multivalued memory device can be provided. This is the same even if transistors having different distances in the substrate surface direction between the drain region and the gate electrode are used.

[0022]

FIG. 1 is a cross-sectional view of a transistor integrated on a nonvolatile memory device according to the present invention and showing different drive currents. One memory cell is constituted by the memory transistor. Here, examples of four states of transistors having different driving currents are shown. These four states enable the memory cell to record four values.

A common structure of the transistors shown in the states 1 to 4 is that the transistor has a semiconductor substrate 1, a gate insulating film 2 formed on the semiconductor substrate 1, and a gate electrode 3 formed on the gate insulating film 2. Is provided. Gate insulating film 2
A channel region 6 is formed in the lower semiconductor substrate 1. In the semiconductor substrate 1, a source region 4 and a drain region 5, which are opposed to each other with a channel region therebetween, are provided separately from each other. On the source region 4, a source Schottky electrode 14 is formed. Drain region 5
A drain Schottky electrode 15 is formed thereon.

In these transistors, as shown in order of state 1, state 2, state 3, and state 4, the distance between the source region 4 and the gate electrode 3 is long. That is, the lateral distance from the substrate 1 between the end of the source region 4 on the gate electrode 3 side and the end of the gate electrode 3 on the source region 4 in the transistor shown in State 1 is L _side S1, and the transistor shown in State 2 is Gate electrode 3 of source region 4
Of the substrate 1 between the side end and the end of the gate electrode 3 on the source region 4 side
L _side S2, the lateral distance from the substrate 1 between the end of the source region 4 on the gate electrode 3 side and the end of the gate electrode 3 on the source region 4 side in the transistor shown in State 3 the _{L side} S3, and the distance between transverse and _{L side} S4 to the substrate 1 between the source region 4 end of the edge and the gate electrode 3 of the gate electrode 3 side of the source region 4 in the transistor shown in state 4, L _side S
1 <L _side S2 <L _side S3 <L _side S4
The relationship holds.

The current value is smaller in this order: drive current of transistor in state 1> drive current of transistor in state 2> drive current of transistor in state 3> drive current of transistor in state 4. By adjusting the distance between the source region 4 and the gate electrode 3 in this manner, the drive current of the transistor can be made different, and this can be stored as a multi-value.

This means that the gate electrode 3 of the drain region 5
Between the end of the gate electrode 3 and the end of the gate electrode 3 on the drain region 5 side
The same can be said by differentiating. That is, state 1
Of the drain region 5 in the transistor shown in FIG.
Between the end on the pole 3 side and the end on the drain region 5 side of the gate electrode 3
Let L be the lateral distance from the substrate 1_sideD1, state 2
Of the drain region 5 in the transistor shown in FIG.
Between the end on the pole 3 side and the end on the drain region 5 side of the gate electrode 3
Let L be the lateral distance from the substrate 1_sideD2, state 3
Of the drain region 5 in the transistor shown in FIG.
Between the end on the pole 3 side and the end on the drain region 5 side of the gate electrode 3
Let L be the lateral distance from the substrate 1_{sid e}D3, state 4
Of the drain region 5 in the transistor shown in FIG.
Between the end on the pole 3 side and the end on the drain region 5 side of the gate electrode 3
Let L be the lateral distance from the substrate 1 _sideD4
And L_sideD1 <L_sideD2 <L_sideD3
<L _sideThe relationship of D4 holds.

The current value is smaller in this order: drive current of transistor in state 1> drive current of transistor in state 2> drive current of transistor in state 3> drive current of transistor in state 4. By adjusting the distance between the drain region 5 and the gate electrode 3 in this manner, the drive current of the transistor can be made different,
This can be stored as a multi-value.

Next, FIG. 2 shows an example of a method of manufacturing the transistor structure shown in FIG.

First, as shown in FIG.
A silicon oxide film 2 is formed on a p-type silicon substrate 1 by a manufacturing process of an OSFET. This silicon oxide film 2
Polycrystalline silicon 3 is formed thereon. On this polycrystalline silicon 3, tungsten silicide 10 and silicon nitride 11 are formed. Next, the polycrystalline silicon 3, the tungsten silicide 10, and the silicon nitride 11 are shaped into a gate electrode by etching. Next, polycrystalline silicon 12 is deposited on the entire surface of the substrate to a thickness of t _poly .

Next, as shown in FIG. 2B, sidewalls of the polycrystalline silicon 13 having a width L _side are left on both sides of the gate electrode 3 by reactive ion etching (RIE).
Next, arsenic is ion-implanted, so that the source region 4 and the drain region 5 are arranged in the semiconductor substrate 1 so as to be opposed to each other. A channel region 6 is formed below the gate insulating film 2 between the source region 4 and the drain region 5.

Next, after removing the exposed silicon oxide film, titanium is deposited and overheated to form the source region 4.
A source Schottky electrode 14 made of titanium silicide is formed thereon, and a drain Schottky electrode 15 made of titanium silicide is formed on the drain region 5.

The distance L _side S in the direction parallel to the substrate 1 between the end of the source region 4 on the side of the gate electrode 3 and the end of the gate electrode 3 on the side of the source region 4 is equal to the thickness t of the polysilicon 12.
It can be controlled by changing _poly . That _{L side} S becomes wider if thicker thickness _{t po ly} of polycrystalline silicon 12, narrower Thinner.

Similarly, the substrate 1 between the end of the drain region 5 on the gate electrode 3 side and the end of the gate electrode 3 on the drain region 5 side
The distance L _side D in the direction parallel to the
_Can be controlled by changing the thickness t _poly of
That is, if the thickness t _poly of the polycrystalline silicon 12 is increased, L _side D is increased, and if the thickness is reduced, the thickness is reduced. As the polycrystalline silicon 12 for adjusting L _side , another mask such as silicon oxide may be used.

FIG. 3 shows that the thickness of the polycrystalline silicon 12 is 0.1
The results of measuring the dependence of the drive current on the gate electrode for transistors having μm, 0.15 μm, and 0.2 μm are shown. As described above, the thickness t _poly of the polycrystalline silicon 12 is proportional to the distance L _side S in the direction parallel to the substrate 1 between the end of the source region 4 on the gate electrode 3 side and the end of the gate electrode 3 on the source region 4 side. I do. Similarly, the distance L in the direction parallel to the substrate 1 between the end of the drain region 5 on the gate electrode 3 side and the end of the gate electrode 3 on the drain region 5 side.
_It is proportional to _side D.

As shown in FIG. 3, it can be seen that the drive current becomes smaller as the thickness of t _poly becomes longer. That is, as the above-mentioned L _side S or L _side D becomes wider, the drive current becomes smaller.

FIG. 4 shows the distance L _side S in the direction parallel to the substrate 1 between the end of the source region 4 on the side of the gate electrode 3 and the end of the gate electrode 3 on the side of the source region.
FIG. 9 is a diagram simulating the potential distribution near the source-Schottky electrode 14 of the transistor when changing to 50 μm and 0.075 μm.

As described above, the graph becomes steeper as L _side S becomes shorter, indicating that the spatial distribution of the potential becomes steeper. This explains that the probability of electrons tunneling from the source Schottky electrode 14 to the channel region increases, so that the drive current also increases. This is the same in the relationship between the drain region and the gate electrode.

Using such a mechanism, L
_By integrating a plurality of transistors having different _side S or L _side D and using MOSFETs storing different states as memory cells, a multi-valued mask R
OM is realized.

FIG. 5 shows an example of a manufacturing process of a multi-value mask ROM according to the present invention. For the method of changing each memory cell is described as the thickness of the polycrystalline silicon 12 shown that _{t poly 1 <t} poly 2 in FIG.

First, polycrystalline silicon is uniformly deposited on a semiconductor substrate 1 on which a gate portion having a laminated structure of polycrystalline silicon 3, tungsten silicide 10, and silicon nitride 11 is formed via a gate insulating film 2. Then, using multiple resist depositions and RIE, different thicknesses t _poly 1> t for each memory cell as shown in FIG.
Etching is performed so that _poly 2 remains.

The subsequent steps are the same as those described with reference to FIG. 2, so that the end of the source region 4 on the gate electrode 3 side and the end of the gate electrode 3 on the source region 4 side are formed as shown in FIG. The distance in the direction parallel to the substrate 1 is L _side S1 <L
Different transistors can be integrated to achieve _side S2. At this time, the distance between the end of the drain region 5 on the side of the gate electrode 3 and the end of the gate electrode 3 on the side of the drain region 5 in the direction parallel to the substrate 1 is L _side D1 <L.
_side D2.

Next, FIG. 6 shows a multi-value mask R according to the present invention.
7 shows another example of the manufacturing process in the OM.

First, a polycrystalline silicon film is deposited via a gate insulating film 2 on a semiconductor substrate 1 on which a gate portion having a laminated structure of polycrystalline silicon 3, tungsten silicide 10, and silicon nitride 11 is formed. . Next, R
IE forms sidewalls of polysilicon of the same length in each memory cell.

Next, a resist 21 as shown in FIG. 6 is deposited, and the side wall made of polycrystalline silicon of a certain transistor is etched by RIE to reduce the width. Then, another transistor portion is opened, and the side wall made of polycrystalline silicon of this transistor is etched to have different widths. Thus, different widths L _side S1 <L _si
A polycrystalline silicon sidewall 20 of _de S2 and L _side D1 <L _side D2 is formed.

The subsequent steps are the same as those described with reference to FIG. 2, so that the end of the source region 4 on the gate electrode 3 side and the end of the gate electrode 3 on the source region 4 side are formed as shown in FIG. The distance in the direction parallel to the substrate 1 is L _side S1 <L
Different transistors can be integrated to achieve _side S2. At this time, the distance between the end of the drain region 5 on the side of the gate electrode 3 and the end of the gate electrode 3 on the side of the drain region 5 in the direction parallel to the substrate 1 is L _side D1 <L.
_side D2.

FIG. 7 shows another example of the manufacturing process in the multi-value mask ROM according to the present invention.

First, a semiconductor substrate 1 on which a gate portion having a laminated structure of polycrystalline silicon 3, tungsten silicide 10, and silicon nitride 11 is formed via a gate insulating film 2 is prepared. Then, a resist 21 is deposited on this substrate so that a certain transistor is opened, and oblique ion implantation is performed to form a source region 4 and a drain region 5 as shown in FIG.

Next, a source region and a drain region are formed by ion-implanting a resist on this transistor so that another transistor is opened. At this time, the distance L _side S in the direction parallel to the substrate 1 between the end of the source region 4 on the side of the gate electrode 3 and the end of the gate electrode 3 on the side of the source region is changed by changing the implantation angle. Can be closed. Thus, the multi-value ROM of the present invention can be formed.

[0049]

As described above, even if the transistor is miniaturized, a threshold value variation due to a short channel effect and a threshold value variation due to fluctuation of the number of impurities can be prevented, and a multi-valued nonvolatile semiconductor memory device can be provided.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of each multi-valued transistor of a memory device according to the present invention.

FIGS. 2A, 2B, and 2C are cross-sectional views illustrating main steps of a method for manufacturing a transistor in a memory device according to the present invention.

FIG. 3 is a graph showing electrical characteristics of a multivalued transistor according to the present invention.

FIG. 4 is a diagram simulating a potential distribution near a source Schottky electrode of a multi-valued transistor according to the present invention.

FIG. 5 is a sectional view showing a first manufacturing step of the storage device according to the present invention.

FIG. 6 is a sectional view showing a second manufacturing step of the storage device according to the present invention.

FIG. 7 is a sectional view showing a third manufacturing step of the storage device according to the present invention.

FIG. 8 is a sectional view of a storage device realized by the first manufacturing process of the present invention.

FIG. 9 is a diagram showing an example of a manufacturing process of a conventional multi-value mask ROM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Gate insulating film 3 ... Gate electrode 4 ... Source region 5 ... Drain region 14 ... Source / Schottky electrode 15 ... Drain / Schottky electrode 8 ... Element isolation region 9 ... Polycrystalline silicon 12 ... Polycrystalline silicon 20 ... Side wall 21 ... Resist

Continued on the front page (72) Inventor Akira Nishiyama 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture Inside the Toshiba Yokohama Office (72) Inventor Takeshi Uchida 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Prefecture In-house (72) Inventor Toshinori Numata 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa F-term (reference) 5F083 CR01 CR20 GA30 JA35 JA39 PR37 ZA21

Claims (5)

[Claims] 1. A nonvolatile semiconductor memory device having a plurality of memory cells from which multi-valued storage information can be read, wherein the memory cells include transistors, and the transistors are formed on a source region and a drain region. A nonvolatile semiconductor memory device having a Schottky electrode. 2. A nonvolatile semiconductor memory device having a first memory cell including a first transistor and a second memory cell including a second transistor, wherein the first transistor and the second transistor have a source A nonvolatile semiconductor memory device having a Schottky electrode formed over a region and a drain region, wherein a distance between a source region and a gate electrode of the first transistor and the second transistor is different. 3. A nonvolatile semiconductor memory device having a first memory cell including a first transistor and a second memory cell including a second transistor, wherein the first transistor and the second transistor have a source. A nonvolatile semiconductor memory device having a Schottky electrode formed over a region and a drain region, wherein a distance between the drain region and the gate electrode is different between the first transistor and the second transistor. 4. The memory device according to claim 2, wherein said first and second memory cells are capable of reading multi-valued storage information.
14. The nonvolatile semiconductor memory device according to claim 1. 5. The memory cell according to claim 3, wherein said first and second memory cells are capable of reading multi-valued storage information.
14. The nonvolatile semiconductor memory device according to claim 1.