JP2002251889A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory in which chip size is not enlarged and a region of a ROM block can be utilized effectively even when the number of times of use of a ROM block which cannot be rewritten freely by a user is increased. SOLUTION: This device is provided with a plurality of cell blocks Block0- Block1023 in which a memory cell array is divided, and a plurality of ROM blocks Block-ROM0, Block-ROM1 which are provided as a storage region which cannot be rewritten freely by a user, which have respectively storage capacity being smaller than each cell block, and to which different block addresses are allotted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a ROM block that cannot be freely rewritten by a user, and is used for, for example, a NAND flash memory.

[0002]

2. Description of the Related Art In a NAND flash EEPROM, a demand for an increase in the number of ROM blocks has been increasing due to a demand for a higher security function on a user side, but a conventional system uses a plurality of ROM blocks. Attempting to do so would increase the chip size each time. This will be described in detail below.

FIG. 6 shows a conventional NAND flash EE.
FIG. 2 is a block diagram schematically showing a configuration of a PROM.

In FIG. 6, A9 to A23 are row-related address signals, A9 to A12 are page address signals, and A13 to A13.
A23 is a block address signal. Block0 ~ Block102
Reference numeral 3 denotes a cell block in which an array of NAND memory cells is divided into a plurality.

The row decoders RD0 to RD1023 are provided corresponding to the cell blocks Block0 to Block1023, and control gate drive circuits (word line selection circuits) 66 to be described later.
Control gate selection signals CG0 to CG15 from the cell blocks CB0 to CG15.
And word line drive signals (WL0-0 to WL15-0) to (WL0-1023 to WL15-1023) for selectively driving the third word line.

[0006] Block-ROM0 and Block-ROM1 are ROM blocks, and each of the cell blocks Block0 to Block1.
023.

[0007] The row decoder 61 for ROM0 and the row decoder 62 for ROM1 are composed of the ROM blocks Block-ROM0 and Bloc.
The activation is controlled by a ROM block selection signal ROM0, ROM1 from a ROM block selection circuit 65, which will be described later.
CG0 to CG15 are input from the memory, and word line drive signals (WL0-R0 to WL15-R0) for selectively driving the word lines of the ROM blocks Block-ROM0 and Block-ROM1 based on the input signals, (WL0-R1 to WL15-R1)
Is output.

The command decoder 63 decodes a command input and outputs a CMD-ROMBA signal (ROM block access control signal).

The cell block selection circuit 64 receives the block address signals A13 to A23 and the CMD-ROMBA signal, and when the CMD-ROMBA signal is in an inactive state, the cell block selection circuit 64 responds to the block address signals A13 to A23 in response to the block address signals A13 to A23.
To activate the block selection signals Block0 to Block1023 for correspondingly selecting .about.Block1023.

The ROM block selection circuit 65 receives the block address signal A13 and the CMD-ROMBA signal,
When the MBA signal is active, a ROM block selection signal ROM0, RO for selecting a corresponding one of the ROM blocks Block-ROM0 or Block-ROM1 according to the block address signal A13.
It activates M1 alternatively.

The control gate drive circuit 66 outputs control gate selection signals CG0 to CG15 based on the page address signals A9 to A12.

Next, the operation of the above configuration will be described.

FIG. 7 shows the ROM block Block-RO in FIG.
FIG. 6 is a diagram showing an address map when accessing either M0 or Block-ROM1.

Two ROM blocks Block-ROM0, Block-ROM
When accessing any of ROM1, the command decoder
By inputting a command to 63 and setting the CMD-ROMBA signal to "H" (active state), the cell block selection circuit 64 is deactivated, the ROM block selection circuit 65 is activated, and the logic level of the address signal A13 is set. Depending on the ROM block Block-
Select ROM0 or Block-ROM1.

However, the conventional ROM block Block-ROM
0 and Block-ROM1 are cell blocks Block0 to Block, respectively.
It has the same size as one 1023 (storage capacity for 16 pages in this example), and there is a disadvantage that if a plurality of ROM blocks are prepared, the chip size becomes larger by that amount.

The ROM blocks Block-ROM0 and Block-ROM0
The ROM 1 is an area for storing identification (ID) codes and the like, and a storage capacity of about one page is sufficient.
Most of the area was wasted.

[0017]

As described above, in the conventional NAND flash EEPROM system, the ROM block which cannot be freely rewritten by the user in response to the user's request for the enhancement of the security function or the like. Each time the number of uses increases, the chip size becomes large, and most of the area of the ROM block is wasted.

The present invention has been made in order to solve the above-mentioned problems. Even when the user increases the number of ROM blocks that cannot be freely rewritten, the chip size does not increase, and the area of the ROM blocks does not increase. It is an object of the present invention to provide a semiconductor memory device that can effectively utilize the above.

[0019]

A first semiconductor memory device according to the present invention is provided with a plurality of cell blocks into which a memory cell array is divided and a memory area which is not freely rewritten by a user. And a plurality of ROM blocks each having a smaller storage capacity and different block addresses.

According to a second semiconductor memory device of the present invention, a plurality of cell blocks in which a memory cell array is divided and a memory area which is not freely rewritten by a user are provided.
A memory block having a storage capacity equivalent to one block of the plurality of cell blocks is divided into a plurality of blocks, and a plurality of ROM blocks to which different block addresses are assigned are provided.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<First Embodiment> FIG. 1 shows a first embodiment of the present invention.
FIG. 3 is a block diagram schematically showing a configuration of a NAND flash EEPROM according to the embodiment.

In FIG. 1, A9 to A23 are row-related address signals, A9 to A12 are page address signals, and A13 to A13.
A23 is a block address signal. Block0 ~ Block102
Reference numeral 3 denotes a plurality of cell blocks obtained by dividing an array of NAND memory cells.

The row decoders RD0 to RD1023 are provided corresponding to the above-mentioned cell blocks Block0 to Block1023, and have a control gate drive circuit (word line selection circuit) 15 to be described later.
Control gate selection signals CG0 to CG15 from the cell blocks CB0 to CG15.
And word line drive signals (WL0-0 to WL15-0) to (WL0-1023 to WL15-1023) for selectively driving the third word line.

ROM blocks Block-ROM0 and Block-RO
M1 is provided as a storage area that cannot be freely rewritten by the user, and has a smaller storage capacity (size) than each of the cell blocks. In this example, a ROM block having a storage capacity corresponding to one of the cell blocks Block0 to Block1023 is divided into two ROM blocks Block-ROM0 and Block-ROM1, and each ROM block Block-ROM0 And Block-ROM1
Are assigned different block addresses.

One ROM row decoder 11 is provided for each of the ROM blocks Block-ROM0 and Block-ROM1. Activation is controlled when a CMD-ROMBA signal from a command decoder 12, which will be described later, is active. Control gate selection signal from the control gate drive circuit 15
CG0 to CG15 are input, and word line drive signals (WL0-R to WL7-R) or ROM block Block-ROM for selecting a word line of the ROM block Block-ROM0 based on the input.
Word line drive signal (WL8-R) for selecting one word line
~ WL15-R).

The command decoder 12 decodes a command input and activates a CMD-ROMBA signal (ROM block access control signal).

When the CMD-ROMBA signal from the command decoder 12 is in an inactive state, the cell block selecting circuit 13 selects the cell block Bloc based on the block address signals A13 to A23.
The block selection signals Block0 to Block1023 for selectively selecting k0 to Block1023 are selectively activated.

The address switching circuit 14 includes a page address signal A12, a block address signal A13, and a CMD-ROMB.
The A signal is input, and the page address signal A12 / block address signal A13 is selectively selected according to the inactive state / active state of the CMD-ROMBA signal and output as an address switching signal A12S. Is input to the control gate drive circuit 15 described later.

The control gate drive circuit 15 includes page address signals A9 to A11 and the address switching signal A12S.
Is input and the control gate selection signal is
CG0 to CG15 are output.

FIG. 2 shows the address switching circuit 14 in FIG.
The following shows a specific example.

The CMOS transfer gates 21 and 22 are selectively turned on by a complementary signal comprising a CMD-ROMBA signal from the command decoder 12 and its inverted signal. The CMOS transfer gates 21 and 22 receive a page address signal A12 and a block address signal A13 at one end, respectively, and the other ends are collectively connected. The signal of the collective connection node is a two-stage inverter circuit.
It is output as an address switching signal A12S via 23 and 24.

Next, the operation of the NAND flash EEPROM having the configuration shown in FIG. 1 will be described with reference to FIGS. A0 to A8 are column addresses (Column
Address) signal.

FIG. 3 is a block diagram showing the cell blocks Block0 to Bl shown in FIG.
FIG. 14 is a diagram showing an address map when a normal access is made to any word line of ock1023.

FIG. 4 shows the ROM block Block-RO in FIG.
FIG. 6 is a diagram showing an address map when accessing any one of the word lines of M0 and Block-ROM1.

(1) When normal access is made to a word line of any of the cell blocks Block0 to Block1023 (for example, Block1023).

As shown in FIG. 3, the page address (Page
Address) signals A9-A12 are all "L", and block address (Block Add) signals A13-A23 are all "H".
Here, the output signal CMD-ROMBA of the command decoder 12 is "
L "(inactive state), the cell block selecting circuit 13 is active, and the ROM row decoder 11 is inactive.

As a result, the cell block selection circuit 13
The block address signals A13 to A23 are decoded, and one of the block selection signals Block0 to Block1023 is selectively activated ("H" level), whereby the row decoder RD1023 is selected.

At this time, the output signal CM of the command decoder 12
The D-ROMBA is "L", and the address switching circuit 14 selects the page address signal A12 and outputs the address switching signal A12S
Becomes "L" and the control gate drive circuit 15 activates the control gate selection signal CG0, so that the corresponding word line of the cell block Block1023 is selected by the word line drive signal WL0-1023.

(2) ROM blocks Block-ROM0, Block-ROM
When accessing the word line of any of ROM1 (for example, Block-ROM1).

As shown in FIG. 4, the page address signal A9
To A11 are set to "L", and page address signal A12 and block address signals A14 to A23 are undefined (Don't Care)
It is. Then, the block address signal A13 is set to "H", a predetermined command is input, and the output signal CMD-ROMBA of the command decoder 12 is set to "H" (active state), so that the cell block selecting circuit 13 is inactive. And ROM
The row decoder 11 is activated.

At this time, the address switching circuit 14 selects the block address signal A13 and sets the address switching signal A12S
Becomes "H" and the control gate drive circuit 15 activates the control gate selection signal CG8, so that the corresponding word line of the ROM block Block-ROM1 is selected by the word line drive signal WL8-R.

<Second Embodiment> In the NAND flash EEPROM of the first embodiment, for example, data cannot be erased by individually selecting the ROM blocks Block-ROM0 and Block-ROM1. The second that improved
The embodiment will be described below.

FIG. 5 is a block diagram showing a second embodiment according to the present invention.
FIG. 2 is a block diagram schematically showing a configuration of an AND-type flash EEPROM.

The second embodiment differs from the first embodiment in the following points (1) to (3), and is otherwise the same. Is omitted.

(1) The block address signal A13 and the output signal CMD-ROMBA of the command decoder 12 are input and the RO
A ROM block selection circuit 50 for selectively activating the M block selection signal ROM0 or ROM1 is added.

(2) The address switching circuit 14 is omitted, and the page address signals A9 to A12 are input to the control gate drive circuit 15.

(3) Instead of the ROM row decoder 11,
Activation is controlled by the ROM block selection signals ROM0 and ROM1 from the ROM block selection circuit 50, and the control gate selection signal CG from the control gate drive circuit 15 is output.
0 to CG7 are input, and word line drive signals (WL0-R0 to WL7-R0) and (WL0-R1) for selectively driving the word lines of the ROM blocks Block-ROM0 and Block-ROM1 based on the input.
~ WL7-R1) to output the row decoder 51 for ROM0 and ROM1
A row decoder 52 is provided.

The operation in the second embodiment is different from the operation in the first embodiment in that (1) the normal access to any one of the word lines of the cell blocks Block0 to Block1023 in FIG. The operation is the same, and (2) R
The operation when accessing one of the word lines of the OM block Block-ROM0 or Block-ROM1 is different.
The operation when accessing the word line of M1 will be described below.

As shown in FIG. 4, the page address signal A9
To A11 are set to "L", and page address signal A12 and block address signals A14 to A23 are undefined (Don't Care)
It is. Then, the block address signal A13 is set to "H", a predetermined command is input, and the output signal CMD-ROMBA of the command decoder 12 is set to "H" (active state), so that the cell block selecting circuit 13 is inactive. And ROM
Activate the block selection circuit 50. At this time, the ROM block selection signal ROM1 is activated, and the ROM1 row decoder 52 is activated.

Here, since the page address signals A9 to A11 are all "L" and the control gate drive circuit 15 activates the control gate selection signal CG0, the ROM block Block-ROM1 is activated by the word line drive signals WL0-R1. Is selected.

The NAND flash EE of the above embodiment
According to the PROM, two ROM blocks, Block-ROM0 and Block-RO, each requiring a storage capacity of about one page.
Even if M1 needs to be prepared, cell block Block0
Only the use of one block out of .about.Block1023 is sufficient, so that the chip size can be reduced.

Even when it is necessary to prepare three or more ROM blocks, one block of the cell blocks Block0 to Block1023 is divided into three or more ROM blocks according to the above embodiments. By assigning a different block address to each ROM block, only one cell block needs to be used, so that the chip size can be reduced.

[0054]

As described above, according to the present invention, even when the user increases the number of ROM blocks that cannot be freely rewritten, the chip size does not increase and the area of the ROM blocks is effectively used. Semiconductor memory device that can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a configuration of a NAND flash EEPROM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of an address switching circuit in FIG. 1;

FIG. 3 is a diagram showing an address map when a normal access is made to any one of word lines of cell blocks Block0 to Block1023 in FIG. 1;

FIG. 4 is a block diagram of a ROM block Block-ROM0 and Block-RO in FIG.
The figure which shows the address map at the time of accessing any word line of M1.

FIG. 5 is a block diagram schematically showing a configuration of a NAND flash EEPROM according to a second embodiment of the present invention.

FIG. 6 is a block diagram schematically showing a configuration of a conventional NAND flash EEPROM.

FIG. 7 is a block diagram showing the ROM blocks Block-ROM0 and Block-RO in FIG.
The figure which shows the address map at the time of accessing any word line of M1.

[Explanation of symbols]

 Block0 to Block1023 ... cell block, RD0 to RD1023 ... row decoder, Block-ROM0, Block-ROM1 ... ROM block, 11 ... row decoder for ROM, 12 ... command decoder, 13 ... cell block selection circuit, 14 ... address switching circuit, 15 ... Control gate drive circuit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Makoto Takizawa 25-1 Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture F-term in Toshiba Microelectronics Corporation (Reference) 5B025 AD01 AD02 AE00

Claims (6)

[Claims] 1. A memory cell array comprising: a plurality of divided cell blocks; and a storage area which is not rewritable by a user. Each storage block has a smaller storage capacity than each of the cell blocks. And a plurality of ROM blocks. 2. A plurality of cell blocks in which a memory cell array is divided and a plurality of memory blocks provided as a storage area which is not freely rewritten by a user and having a storage capacity equivalent to one block of the plurality of cell blocks. A semiconductor memory device comprising: a plurality of ROM blocks that are divided and respectively assigned different block addresses. 3. A predetermined command input is decoded, and RO is decoded.
A command decoder for activating an M block access control signal; and a plurality of command decoders provided corresponding to the plurality of cell blocks, for selecting a word line of the corresponding cell block based on a word line selection signal when in an active state. A row decoder, a block selection circuit for selectively activating the plurality of row decoders based on a block address signal when the ROM block access control signal is in an inactive state, and an active state of the ROM block access control signal. An address switching circuit for selecting a part of the page address signal / part of the block signal in response to the inactive state and outputting the selected part as the address switching signal; and selecting the word line in response to the page address signal including the address switching signal A word line selection circuit for outputting a signal; One of the plurality of ROM blocks is configured to be activated when the ROM block access control signal is in an active state, and to select a word line of one of the plurality of ROM blocks based on the word line selection signal. 3. The semiconductor memory device according to claim 2, further comprising a ROM block row decoder. 4. The method according to claim 1, wherein the plurality of ROM blocks are two, and the address switching circuit is configured to control one bit of the page address signal or a block address signal in response to an active / inactive state of the ROM block access control signal. 4. The semiconductor memory device according to claim 3, wherein one bit is selected to output an address switching signal. 5. Decoding a predetermined command input, and
A command decoder for outputting an M block access control signal; and a plurality of rows provided corresponding to the plurality of cell blocks and for selecting a word line of the corresponding cell block based on a word line selection signal when in an active state. A decoder, a block selection circuit for selectively activating the plurality of row decoders based on a block address signal when the ROM block access control signal is in an inactive state, and a decoder provided corresponding to the plurality of ROM blocks. , A plurality of Rs for selecting a word line of a corresponding ROM block based on a part of the word line selection signal in an active state.
A row decoder for an OM block, a ROM that is activated and controlled when the ROM block access control signal is in an active state, and selectively activates the plurality of row decoders for the ROM block based on a part of the block address signal 3. The semiconductor memory device according to claim 2, further comprising: a block selection circuit; and a word line selection circuit that outputs the word line selection signal based on a page address signal. 6. The plurality of ROM blocks and the plurality of ROM block row decoders are respectively two, and the ROM block selecting circuit is configured to control the two ROM blocks in accordance with a 1-bit logic level of the block address signal.
6. The semiconductor memory device according to claim 5, wherein the row decoder for block is selectively activated.