JP2002247529A - Sequential scanning converting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform sequential scanning conversion without any deterioration in picture quality even if a 2-3 pull-down phase shifts or when 2-3 pull-down and other signals are mixed. SOLUTION: Identical frame fields are found from field differences and interpolated, field by field.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for converting an interlaced video signal into a progressively scanned video signal.

[0002]

2. Description of the Related Art A video signal of interlaced scanning is shown in FIG.
As shown in (1), the scanning position differs for each field.

[0003] Interlaced scanning has the advantage of increasing the vertical resolution of an image while suppressing the transmission frequency band. However, when the number of high vertical frequency components increases, interference such as line flicker becomes noticeable. On the other hand, as shown in FIG. 6B, the video signal of the progressive scanning has the same scanning position every frame. Even if there are many vertical high frequency components,
Interference caused by interlaced scanning such as line flicker does not occur.

Therefore, an interpolated scanning line is created between the scanning lines of the interlaced scanning, and the scanning is converted into a sequential scanning. This is called progressive scan conversion.

In the progressive scan conversion, motion adaptive processing is mainly performed, but when the input video signal is a signal whose frame rate has been converted by 2-3 pull-down, it is preferably performed by progressive scan conversion in accordance with the 2-3 pull-down phase. Image quality can be obtained. A method of detecting a 2-3 pull-down phase and performing sequential scan conversion is described in U.S. Pat. No. 4,982,280. In the case of 2-3 pull-down, there is a feature that the field difference of all pixels becomes zero in a 5-field cycle. By detecting this feature, the pull-down phase is estimated, and the interpolation signal is converted into a field unit. This is a method of switching the video signal to be guided.

[0006]

In the above conventional method,
In order to determine whether or not the signal is a 2-3 pull-down signal every five fields, if the 2-3 pull-down phase is shifted during the five-field period of the determination timing or the signal is no longer a 2-3 pull-down signal, the next Until the determination timing, the scan conversion is performed sequentially using the wrong interpolation signal, and the image quality is degraded.

An object of the present invention is to provide an apparatus for sequentially performing scan conversion without deterioration in image quality even when the 2-3 pull-down phase is shifted or when 2-3 pull-down and other signals are mixed.

[0008]

SUMMARY OF THE INVENTION A progressive scanning conversion apparatus according to the present invention comprises a current input signal of an interlaced scanning video signal, three cascade-connected field delay means, the same frame field determination means, and selector means. The current input signal, the one-field delay signal output by the field delay means and the two-field delay signal are led to the same frame field determination means, and the one-field delay signal and the two-field delay signal output by the field delay means And the three-field delay signal to the selector means, and the same frame field determination means determines that there is a field difference between the current input signal and the one-field delay signal in the vertically flat part of the one-field delay signal. Count, 2 field delay signal and 1 field delay The result of counting the total number of pixels determined to have a difference between the signals is compared, the field having the smaller count value is determined to be the same frame field as the one-field delayed signal, and the selector means interpolates the two-field delayed signal. If the current input signal and the one-field delay signal are determined to be the same frame field at the previous field timing, the two-field delay signal is selected as an interpolation signal, and the two-field delay signal and the one-field delay signal are the same. If it is determined that the frame field is a frame field, the three-field delay signal is selected as an interpolation signal. If it is determined that neither the current input signal nor the two-field delay signal is the same as the one-field delay signal, the motion adaptation is performed. By selecting the output of the interpolation means as an interpolation signal, a 2-3 pull-down phase Shift or, 2-3
An object of the present invention is to provide an apparatus for sequentially performing scan conversion without deterioration in image quality even when a pull-down signal and other signals are mixed.

[0009]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an apparatus for performing progressive scan conversion according to the present invention. FIG. 1 shows a system for realizing the present embodiment. The current input signal input from the interlaced scanning video signal input terminal 101 is input to the field memory 102 and the same frame field determination circuit 105.
It is led to.

The field memory 102 outputs a signal obtained by delaying the current input signal by one field. The field memory 103 outputs a signal obtained by delaying the output signal of the field memory 102 by one field. Field memory 1
04 outputs a signal obtained by delaying the output signal of the field memory 103 by one field. Field memory 10
2. Field memory 103, field memory 104
In the following, the output signals are expressed as a one-field delay signal, a two-field delay signal, and a three-field delay signal, respectively, according to the delay amount with reference to the input signal.

FIG. 2 shows the relationship between the field memory outputs when a 2-3 pull-down signal is input as an input signal. Here, A (t) and A (b) are interlaced scanning signals converted from the video frame A, and A (t) and A (t)
(T) of (b) represents the top field in FIG. 6, and (b) represents the bottom field.

Signals converted from one video frame into an interlaced scanning field signal such as A (t) and A (b) are referred to as the same frame field.

2-3 Image frames A, B, before pull-down
C and D are A (t), A by 2-3 pull-down.
(B), B (t), B (b), B (t), C (b), C
(T), D (b) and D (t) are converted into interlaced scanning field signals. Same frame field determination circuit 105
Is the same frame field as the (1) current input signal with respect to the one-field delay signal. (2) The same frame field as the two-field delay signal. (3) The same frame field as both the current input signal and the two-field delay signal. (4) It is determined whether the current input signal and the two-field delay signal are not the same frame field.

FIG. 3 shows one specific configuration of the same frame field determination circuit 105.

The one-field delay signal is input from an input terminal 301 (signal a). The one-line delay circuit 302
A signal (signal b) obtained by delaying the one-field delay signal by one line is output. The difference circuit 303 outputs a difference value between the one-field delay signal (signal a) and the one-line delay signal (signal b) and guides the difference value to the flat part detection circuit 304. When the absolute value of the input difference value is equal to or smaller than a predetermined value, the flat portion detection circuit 304 determines that the input signal is flat, and outputs the determination result to the gate circuit 30.
7 and a gate circuit 311.

The current input signal is input from an input terminal 305 (signal c) and guided to a difference circuit 306. Difference circuit 30
6 outputs a difference value between the current input signal (signal c) and the one-field delay signal (signal a) and guides it to the field difference detection circuit 314. The field difference detection circuit 314 determines that there is a frame difference if the absolute value of the derived difference value is equal to or greater than a predetermined value, and guides the determination result to the gate circuit 307.
The gate circuit 307 performs a gating process for validating the determination result of the difference from the field difference detection circuit 314 only when the flat portion detection circuit 304 determines that the image is flat.
The output is directed to a field accumulation circuit 308. The field accumulation circuit 308 accumulates the determination of the presence of the field difference gated by the gate circuit 307 for one field. If the current input signal and the one-field delay signal are in the same frame field, the accumulated value is small. If the current input signal and the one-field delayed signal are not the same frame field, the accumulated value is large. Are not the same frame field. The two-field delay signal is input from the input terminal 309 (signal d), and the differential circuit 3
It is led to 10. The difference circuit 310 outputs a difference value between the two-field delay signal (signal d) and the one-field delay signal (signal a), and guides the difference value to the field difference detection circuit 315.
The field difference detection circuit 315 determines that there is a frame difference if the absolute value of the derived difference value is equal to or greater than a predetermined value, and guides the determination result to the gate circuit 311. Gate circuit 3
Numeral 11 performs a gating process for validating the determination result with the difference from the field difference detection circuit 315 only when the flat portion detection circuit 304 determines that the surface is flat, and guides the output to the field accumulation circuit 312. Field accumulation circuit 312
Accumulates a field difference determination gated by the gate circuit 311 for one field. If the two-field delay signal and the one-field delay signal are the same frame field, the accumulated value is small, and if the two-field delay signal is not the same frame field, the accumulated value is large. It is determined that the delayed signals are not the same frame field. State determination circuit 3
Reference numeral 13 denotes a field accumulation circuit 312 based on the determination results of the field accumulation circuits 308 and 312.
If it is determined that only the same field is not the same field, state "1"
Is determined, and when it is determined that only the field accumulation circuit 308 is not the same field, it is determined that the state is “2”, and when it is not determined that both the field accumulation circuit 312 and the field accumulation circuit 308 are not the same field. Is determined to be state "3", and when it is determined that both the field accumulation circuit 312 and the field accumulation circuit 308 are not the same field, the state is determined to be "4".
At the next field timing, the state determination output terminal 316
To the state determination result. This is summarized in FIG.

The selector circuit 107 in FIG. 1 selects an output signal in accordance with the state determination result derived from the same frame field determination circuit 105. That is, the state determination result is "
When the result is "1", a one-field delay signal is selected. When the state determination result is "2", a three-field delay signal is selected.
When the state determination result is "3", a three-field delay signal is selected. When the state determination result is “4”, the motion adaptive interpolation signal output from the motion adaptive interpolation signal generation circuit 106 is selected. The signal selected by the selector circuit 107 is 2
The signal is guided to the interpolation signal output terminal 109 as an interpolation signal for progressive scanning conversion with respect to the field delay signal.

The above operation will be described with reference to FIG. For example, when the current input signal is C (t), the one-field delay signal is C (b), the two-field delay signal is B (t), and the three-field delay signal is B (b). The same frame field detection circuit 105 outputs the one-field delay signal C (b)
The current input signal is C (t) and the two-field delay signal is B
It is determined which of (t) is the same frame. The one-field delay signal C (b) and the current input signal are C (t), the one-field delay signal C (b) and the two-field delay signal are B
In (t), adjacent interlaced scan fields do not have data at the same vertical position, but have the same value as data at the same vertical position in a flat portion. Can be determined. Here, there is almost no pixel having a field difference between the one-field delay signal C (b) and the current input signal C (t), and the one-field delay signal C (b) and the two-field delay signal have a field difference of B (t). Since many pixels are detected, the same frame field determination circuit 105
The state determination result "1" is changed to the next field timing (FIG. 3).
In this case, the current field signal is output at D (t). At the next field timing (in FIG. 3, the current field signal is D (t)), the one-field delay signal is C (t) and the two-field delay signal is C (t).
(B) The three-field delay signal is B (t). Since the state determination result is “1”, the selector circuit 107
As the field delay signal, a one-field delay signal C (t) is selected as an interpolation signal for C (b). In this way, C (t) which is the same frame field as C (b)
Can be interpolated, and the original video frame C can be restored without deterioration in image quality by progressive scan conversion.

Next, a case where the 2-3 pull-down phase is terminated halfway will be described with reference to FIG. For example, if the current input signal is D
In the case of (t), the one-field delay signal is C (b), the two-field delay signal is B (t), and the three-field delay signal is B (b). Here, this timing is a timing at which C (t) is input to the current input signal if the 2-3 pull-down is continuous. The same frame field detection circuit 105 determines whether the one-field delay signal C (b) is the same frame as the current input signal is D (t) or the two-field delay signal is B (t). The one-field delay signal C (b) and the current input signal are D (t), the one-field delay signal C (b) and the two-field delay signal are B (t),
Are not the same top field. Therefore, a pixel having a field difference between the one-field delay signal C (b) and the current input signal D (t) and the one-field delay signal C (b)
And the two-field delay signal are detected in a large number of both of the pixels having the field difference of B (t). Therefore, the same frame field determination circuit 105 outputs the state determination result “4” to the next field timing (in FIG. The signal is E
(Timing of (t)). At the next field timing (in FIG. 4, the current field signal is the timing of E (t)), the one-field delay signal is D (t), the two-field delay signal is C (b), and the three-field delay signal is B (t). ). Since the state determination result is “4”, the selector circuit 107 selects the motion adaptive interpolation signal C ′ (t) as the interpolation signal for C (b) for the two-field delay signal. If the processing is performed assuming that the 2-3 pull-down phase is maintained until the determination timing of the 5 fields and the cycle as in the conventional example, the interpolation is performed by D (t) which is not the same frame field as C (b). Therefore, the image becomes a double image, but according to the present invention, C
Since interpolation can be performed using the motion adaptive interpolation signal C ′ (t) for (b), it is possible to output a video that does not cause a sense of discomfort due to the motion adaptive processing.

[0020]

As described above, the progressive scan conversion apparatus of the present invention can restore the original picture frame of the 2-3 pull-down picture without deteriorating the picture quality. In addition, even when the 2-3 pull-down phase is shifted or the 2-3 pull-down and other signals are mixed, sequential scan conversion can be performed without displaying a disturbed image such as a double image.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a time series diagram of each data at the time of 2-3 pull-down input.

FIG. 3 is a diagram showing a specific configuration of a same frame field determination unit 105 of FIG. 1 and a layout of scanning lines.

FIG. 4 is a time-series diagram of each data when 2-3 pull-down is terminated on the way.

FIG. 5 is a diagram showing a determination algorithm for the same frame field determination.

FIG. 6 is an explanatory diagram of a scanning line structure.

[Explanation of symbols]

Reference numeral 101: interlaced scanning video signal input terminal, 102: field memory, 103: field memory, 104: field memory, 105: identical frame field determination circuit, 106: motion adaptive interpolation signal generation circuit, 107: selector circuit, 108: real line Signal output terminal, 109: interpolation signal output terminal, 301: input terminal, 302: one-line delay circuit, 303: difference circuit, 304: flat portion detection circuit, 305: input terminal, 306: difference circuit, 307: gate circuit, 308: Field accumulation circuit, 309: Input terminal, 310: Difference circuit, 311: Gate circuit, 312
... Field accumulation circuit, 313 ... State judgment circuit, 314
... field difference detection circuit, 315 ... field difference detection circuit, 316 ... state determination output terminal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Mitsuo Nakajima 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Digital Media Development Division, Hitachi, Ltd. (72) Inventor Masahiro Ogino 292 Yoshidacho, Totsuka-ku, Yokohama-shi, Kanagawa Address Co., Ltd.Digital Media Development Division, Hitachi, Ltd. 6-16-16, Hitachi, Ltd. Device Development Center Co., Ltd. (72) Inventor Masaaki Matsukawa 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Image Information Systems, Ltd. (72) Inventor Wataru Kato Yokohama-shi, Kanagawa Prefecture 292 Yoshida-cho, Totsuka-ku Hitachi Image Information Systems, Ltd. T-term F-term (reference) 5C063 BA04 BA10 CA01 CA05

Claims (1)

[Claims] 1. An apparatus for converting an interlaced video signal into a progressively scanned video signal, comprising: a current input signal of the interlaced video signal; three field delay means connected in cascade; , Selector means, the current input signal, and 1 output by the field delay means.
The field delay signal and the two-field delay signal are guided to the same frame field determination means, and the one-field delay signal, the two-field delay signal, and the three-field delay signal output by the field delay means are guided to the selector means. The means is arranged such that, in a vertically flat portion of the one-field delay signal, the current input signal and one
The result of counting the number of all pixels determined to have a field difference of the field delay signal is compared with the result of counting the number of all pixels determined to have a difference between the two-field delay signal and the one-field delay signal. Is determined to be the same frame field as the one-field delay signal, and the selector means as an interpolation signal for the two-field delay signal, at the previous field timing, the current input signal and the one-field delay signal match the same frame field. If it is determined, the two-field delay signal is selected as the interpolation signal. If the two-field delay signal and the one-field delay signal are determined to be the same frame field, the three-field delay signal is selected as the interpolation signal. Both the signal and the two-field delay signal are the same as the one-field delay signal. An apparatus for performing progressive scan conversion, wherein an output of the motion adaptive interpolation means is selected as an interpolation signal when it is determined that the field is not one frame field.