JP2002247456A - Scanning circuit and image pickup device using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a scanning circuit that is compatible with various functions. SOLUTION: This invention provides the scanning circuit that is characterized in that the scanning circuit includes a shift register and a pulse output circuit that is placed at each stage of the shift register and outputs a plurality of pulses on the basis of a pulse from the shift register, the pulse output circuit includes a level conversion circuit that converts a voltage range of the pulse from the shift register and the pulse output circuit outputs a plurality of the pulses with different voltage ranges.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a scanning circuit comprising a shift register and a pulse output circuit, and an imaging apparatus such as a digital still camera and a video camcorder using the scanning circuit.

[0002]

2. Description of the Related Art In recent years, research and development of an image sensor called a CMOS type image sensor which reads out a photoelectric conversion signal not by a CCD (charge coupled device) but by a MOSFET transistor has been active. The CMOS image sensor is expected to be an image sensor for portable use, particularly, because it is easy to integrate peripheral circuits on a chip due to its affinity with a CMOS logic LSI process, and is driven by low voltage and low power consumption. .

[0003] As a method of reading out an optical signal stored in a pixel of a CMOS type image sensor, a method of reading out by a scanning circuit based on a shift register is generally used. For example, in JP-A-11-111016, a control signal is generated by a logical operation of each stage output of a shift register and an external input pulse, a control signal is applied to a transistor of a pixel unit for each horizontal line, and a read signal is read to a signal storage unit. A method of soaking is disclosed.

FIG. 12 shows this conventional scanning circuit. Figure 1
2, the output φSR of the shift register
An arbitrary row in the pixel area is selected by the control signal φS.
EL and φRES are generated. φSEL is supplied to a selection switch 5 for controlling on / off of a source follower of a pixel, and φRES is supplied to a reset switch 4 for resetting an input node of the source follower.

[0005]

In the conventional scanning circuit shown in FIG. 12, since the shift register and the pulse output circuit operate at the same power supply voltage,
The output control signals φSEL and φRES are output pulses in the same voltage range. For this reason, in the conventional solid-state imaging device, there were various restrictions.

[0006]

According to one aspect of the present invention, a plurality of pulses are output based on a pulse of a shift register provided at each stage of the shift register. A pulse output circuit, wherein the pulse output circuit includes a level conversion circuit that converts a voltage range of a pulse from the shift register, and the pulse output circuit outputs pulses in a plurality of different voltage ranges. Is provided.

In another means, a photoelectric conversion unit converts incident light into an electric signal and accumulates the electric signal, an amplification transistor which amplifies and outputs a signal from the photoelectric conversion unit, and an amplifying transistor which accumulates and outputs the electric signal. A plurality of pixels each including a transfer transistor that transfers the electrical signal to the amplification transistor, and a processing transistor that performs predetermined processing, and a control electrode of the transfer transistor for turning off the transfer transistor. A scanning circuit for controlling the signal level to be applied to lower the signal level applied to the control electrode of the processing transistor, for switching the processing transistor off, wherein the scanning circuit includes a shift register, The shift register provided at each stage of the shift register has a plurality of pulses based on the pulse. A pulse output circuit that outputs a pulse having a plurality of different voltage ranges. The pulse output circuit includes a level conversion circuit that converts a voltage range of the pulse from the shift register. An imaging device is provided.

In another means, a photoelectric conversion unit that converts incident light into an electric signal and accumulates the electric signal, an amplification transistor that amplifies and outputs a signal from the photoelectric conversion unit, and a control electrode of the amplification transistor A plurality of pixels each including a reset transistor for resetting and a processing transistor for performing predetermined processing, and a signal level applied to a control electrode of the reset transistor for switching off the reset transistor, the processing transistor A scanning circuit for controlling the signal level to be lower than a signal level applied to a control electrode of the processing transistor for switching off, the scanning circuit being provided in a shift register and each stage of the shift register. And outputs a plurality of pulses based on the shift register. A pulse output circuit, wherein the pulse output circuit includes a level conversion circuit that converts a voltage range of a pulse from the shift register, and the pulse output circuit outputs a pulse having a plurality of different voltage ranges. Is provided.

In another aspect, the photoelectric conversion unit converts incident light into an electric signal and accumulates the electric signal, a first processing transistor that performs predetermined processing on a signal from the photoelectric conversion unit and outputs the processed signal, A plurality of pixels each including a transfer transistor for transferring the electric signal accumulated in the conversion unit to the first processing transistor, and a second processing transistor for performing a predetermined process, and switching off the transfer transistor Scanning circuit for controlling the signal level applied to the control electrode of the transfer transistor to be lower than the signal level applied to the control electrode of the processing transistor for switching off the second processing transistor. Wherein the scanning circuit comprises: a shift register; and the shift register provided at each stage of the shift register. Or has a pulse output circuit for outputting a plurality of pulses based on that pulse, the pulse output circuit includes a level converting circuit for converting the voltage range of the pulse from the shift register, the pulse output circuit,
Provided is an imaging device that outputs a plurality of pulses in different voltage ranges.

In another means, a photoelectric conversion unit for converting incident light into an electric signal and storing the electric signal, a first processing transistor for performing predetermined processing on a signal from the photoelectric conversion unit and outputting the signal, and a reset signal And a plurality of pixels each including a reset transistor for supplying a second transistor for performing a predetermined process, and a signal level applied to a control electrode of the transfer transistor for switching off the transfer transistor. A scanning circuit for switching off the second processing transistor, the control circuit controlling the signal level to be lower than a signal level applied to a control electrode of the processing transistor, wherein the scanning circuit includes a shift register and the shift register. A pulse output from the shift register provided at each stage of the register, based on the pulse. An output circuit, the pulse output circuit includes a level converting circuit for converting the voltage range of the pulse from the shift register, the pulse output circuit,
Provided is an imaging device that outputs pulses in a plurality of different voltage ranges.

In another means, a photoelectric conversion unit for converting incident light into an electric signal and storing the converted signal, a first processing transistor having a main electrode connected to the photoelectric conversion unit for performing predetermined processing, a main electrode, A plurality of pixels each including a second processing transistor that performs a predetermined process that is not connected to the photoelectric conversion unit, and a control electrode of the first transistor for switching off the first transistor. A scanning circuit for controlling a signal level to be applied to be lower than a signal level to be applied to a control electrode of the processing transistor for switching off the second processing transistor; A register and a pulse output circuit for outputting a plurality of pulses based on the pulse of the shift register provided at each stage of the shift register Wherein the pulse output circuit includes a level conversion circuit for converting a voltage range of a pulse from the shift register, and the pulse output circuit outputs pulses in a plurality of different voltage ranges. I will provide a.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail. In the following embodiment, M
The OS type field effect transistor is described as a MOSFET.

(First Embodiment) A first embodiment of the present invention will be described.

FIG. 1 shows an n-th unit block of a scanning circuit having a plurality of stages. A scanning circuit is formed by connecting the shift register unit blocks 21 in a plurality of stages.

The pulse output circuit 22 outputs the output φSR (n) of the shift register unit block 21 and the external input pulse φ
With B0 as input, output pulses φA (n), φB (n)
Generate

Here, φSR (n), φB0, φA (n)
Is a pulse of a common positive power supply VDD at a high level and a pulse of a common negative power supply VSS at a low level, and φB (n) is a pulse of VBH at a high level and VBL at a low level.

The process of generating φB (n) will be described.
The logical product φB1 of φSR (n) and φB0 is the level conversion circuit 2
3 from the voltage range of VDD to VSS to VBH to
It is converted into a pulse φB2 in the voltage range of VBL. φB2
Is input to the buffer 24, and finally the output pulse φB
(N). Buffer 24 is VBH, VB
ΦB (n) is VBH
To VBL.

On the other hand, φA (n) inputs φA1 obtained by inverting φSR (n) to the buffer, and outputs a final output pulse φA (n).
(N), the level conversion of the pulse voltage range is not performed in the generation process.

The level conversion circuit 2 is included in the pulse output circuit 22.
3 provides output pulses φ having different voltage ranges.
A (n) and φB (n) can be generated, and a special circuit operation can be performed in a circuit to be scanned. In addition, since only one shift register is required, the chip area can be reduced.

(Embodiment 2) Embodiment 2 of the present invention will be described.

FIG. 2 shows an n-th unit block of a scanning circuit having a plurality of stages.

The pre-stage circuit 26 operated by the positive power supply VDD and the negative power supply VSS is a logic circuit including at least a shift register unit block. On the other hand, the post-stage circuit 27 is a logic circuit that operates on the positive power supply VDD and the negative power supply VL, and generates a final output pulse. However, if the level conversion circuit 23 has sufficient driving capability, it can be omitted. here,
The voltage relationship between the two negative power supplies is set to VSS> VL.

Inverting input φI input from pre-stage circuit 26
NB is applied to an input gate of an inverter composed of a PMOSFET 28 and an NMOSFET 29, and is further connected to a negative power supply VL.
The output φOUTB, which is in phase with φINB but after level conversion, is fed back to the gate 30.

The low level of φINB is VSS,
Since the voltage is higher than L, if a simple CMOS inverter is used, the NMOSFET 29 is not completely turned off, so that a through current flows.

In the level conversion circuit 23 of the present embodiment, the NM which is fed back with φOUTB whose low level is VL is input.
Since the OSFETs 30 are connected in series, the through current is cut off. PMO to which forward rotation input φIN is input
In the CMOS inverter formed by the SFET 31 and the NMOSFET 32, the NMOSFET 33 is connected in series, and φOUT is inputted to the gate of the NMOSFET 33.

Therefore, in the level conversion circuit 23, the provision of the through current suppressing circuit including the NMOSFET 30 and the NMOSFET 31 eliminates an increase in power consumption due to the through current. Even when the level differs on the positive power supply side, it is clear that through current can be suppressed by a circuit configuration similar to that of the present embodiment. This through current suppression effect is more effective as the number of stages of the scanning circuit increases, as in the case of a scanning circuit of a solid-state imaging device having multiple pixels.

(Embodiment 3) Embodiment 3 of the present invention will be described.

FIG. 3 shows an n-th unit block of a scanning circuit having a plurality of stages.

The level conversion circuit included in the scanning circuit according to the second embodiment has a high effect of suppressing a through current but has a problem that the area of the entire scanning circuit becomes large because a wiring for feedback is required. .

The third embodiment of the present invention is an improvement of this point. An NMOS FE having a gate electrode and a drain electrode directly connected and connected in series between an inverter composed of a PMOSFET 28 and an NMOSFET 29 and a negative power supply VL.
T30 constitutes a through current suppression circuit. With this configuration, the NMOSFET 30 acts as a resistance to a through current.

Since the number of elements is small and the number of wirings for feedback can be reduced, both the effect of reducing the chip area and the effect of suppressing the through current can be achieved.

Although the level conversion circuit of this embodiment is an inverter, the inverter-based derivative gates NAND and NOR can also be configured as shown in FIGS. 4 (a) and 4 (b). .

(Embodiment 4) Embodiment 4 of the present invention will be described.

This embodiment relates to a solid-state imaging device (FIG. 8) using the scanning circuit of FIG. 5 as a vertical scanning circuit. The level shift circuit in the scanning circuit of FIG. 5 is the level shift circuit 23 included in the scanning circuits of the first to third embodiments described above.

FIG. 8 shows a solid-state image sensor, in which the scanning circuit of FIG. 5 is driven as a vertical scanning circuit, and which improves the dynamic range of the solid-state image sensor.

FIG. 8 shows an arrangement for four unit pixels, but there is no particular limitation on the number of pixels, and the arrangement need not be a two-dimensional arrangement.

In the unit pixel, a photodiode 1 as a photoelectric conversion unit, an amplifying MOSFET 2 for amplifying a signal generated in the photoelectric conversion unit, and an amplifying M
Transfer MOS for transferring signal charges to the input of OSFET2
FET 3 is connected as shown.

A reset MOSFET 4 for resetting the input of the amplifying MOSFET 2 and an output of the pixel are turned on.
A selection MOSFET 5 to be turned off is provided.

Using the driving pulse timing shown in FIG.
The operation of the solid-state imaging device according to the present embodiment will be described. In the solid-state imaging device according to the present embodiment, the row selection pulse φSEL becomes a high level for each row by the vertical scanning circuit 6,
A source follower circuit composed of pixels in a certain row and a constant current source 9 is activated, and a corresponding output appears on the vertical output line 7.

During the accumulation period, the reset pulse φRES is at a high level, and the input of the amplification MOSFET 2 is in a reset state. However, during the pixel selection period, the reset MOSFET 4 is turned off and the amplification MOSFET 2 is turned off.
The input of 2 is in a floating state.

In order to remove fixed pattern noise, first, the output immediately after the reset is applied to the signal storage unit 1 via the transfer gate 8a.
0 is stored. Subsequently, the transfer pulse φTX goes high, and the optical signal charge is transferred from the photodiode 1 to the input of the amplifying MOSFET 2. The output after the signal transfer is stored in the signal storage unit 9 via the transfer gate 8b. By taking the difference between the output immediately after reset and the output after signal transfer, solid pattern noise can be removed.

Considering the dynamic range in the pixel area of the solid-state imaging device, the reset level defining the upper limit of the dynamic range is VRESH for the gate high level of the reset MOSFET 4, Vth for the threshold value of the MOSFET, and Vth for the pixel source follower power supply. Assuming that the common positive power supply includes VDD, when the reset MOSFET 4 performs a reset operation in the pentode region, that is, VRESH-
If the relationship of Vth <VDD holds, VRES
It is represented by H-Vth.

On the other hand, when the reset operation is performed in the triode region, that is, when the relationship of VRESH-Vth> VDD holds, the reset level becomes VDD. In the conventional scanning circuit, since VRESH = VDD, the reset level can be increased only to VDD-Vth. However, in the scanning circuit of the present invention, since the level conversion circuit is built in, φRES is set to a voltage. Range VR
It is possible to extend the dynamic range by setting the reset level higher than before by making pulses of ESH to VSS.

It is needless to say that the chip area is greatly reduced as compared with the case where a plurality of scanning circuits having different power supply voltages are used.

(Fifth Embodiment) A fifth embodiment of the present invention will be described.

This embodiment relates to a solid-state imaging device (FIG. 8) using the scanning circuit of FIG. 6 as a vertical scanning circuit. The level shift circuit in the scanning circuit of FIG. 6 is the level shift circuit 23 included in the scanning circuits of the first to third embodiments described above.

FIG. 8 shows a solid-state image sensing device, in which the scanning circuit of FIG. 6 is driven as a vertical scanning circuit, and which has improved dark current characteristics of the solid-state image sensing device.

Hereinafter, the dark current characteristics will be described.

In the unit pixel shown in FIG. 8, a photodiode 1 as a photoelectric converter, an amplifying MOSFET 2 for amplifying a signal generated in the photoelectric converter, and a signal charge are transferred from the photodiode 1 to an input of the amplifying MOSFET 2. The transfer MOSFET 3 is connected as shown in the figure. Further, a reset MOSFET 4 for resetting the input of the amplification MOSFET 2 and a selection MOSFET 5 for turning on / off the output of the pixel are provided.

In consideration of the dark current characteristic of the pixel structure shown in FIG. 8, not only the dark current component generated in the photodiode 1 but also the dark current component generated under the gate electrode of the transfer MOSFET 3 has an S / N ratio. Comes involved.

The charge generated during the accumulation period at the Si-SiO2 interface of the gate oxide film of the transfer MOSFET 3 or at the depletion layer below it is diffused to the photodiode 1 side, and the signal charge is read out. Since it is superimposed on the signal charge and affects as a false signal, the S / N ratio is deteriorated. Therefore, generally, in an image sensor in which a switching transistor is provided adjacent to the photoelectric conversion unit, it is necessary to suppress dark current in the switching unit in order to improve image quality.

As a method of suppressing the dark current generated near the gate electrode, it is considered that the threshold value of the MOSFET transistor as the transfer switch is set high and the vicinity of the gate electrode is sufficiently filled with holes during the accumulation period. Can be

However, additional channel doping for controlling the threshold value is required, which not only increases the cost, but also affects the impurity profile from the photodiode to the vicinity of the transfer switch. It may worsen, and problems such as afterimages may occur. Particularly, in a CMOS image sensor of a type in which a photodiode is depleted immediately after transfer, the influence is further increased, and it has been difficult to design a device structure near the photodiode and the transfer switch.

Further, the MOSFET transistor in the switch section adjacent to the photodiode and the other M
Since the OSFET transistor is formed at the same time, the threshold value of the other transistor is also increased, which increases the difficulty in circuit design. When the dynamic range of the pixel source follower is considered, assuming that the threshold voltage of the MOSFET is Vth and the common positive power supply is VDD, the upper limit of the voltage on the vertical output line corresponding to the output voltage in darkness is V
DD-2 * Vth.

Here, when the threshold value Vth increases, the upper limit decreases, and the signal amplitude that can be obtained on the vertical output line is suppressed.

Since the power supply voltage supplied to the circuit decreases as the size of the MOSFET transistor decreases,
The effect of this problem is even more pronounced.

In this embodiment, the transfer MOSFE
The pulse φTX (n) applied to the gate of T3 is from VDD to
The level is converted from the voltage range of VSS to VDD to VTXL.

Here, VTXL is set lower than the common negative power supply VSS. This makes it possible to control the potential under the gate electrode of the transfer MOSFET 3 during the exposure / accumulation period, easily bring the hole under the gate electrode into a hole accumulation state, and suppress a dark current component generated under the gate electrode. Can be.

On the other hand, the low level of φRES (n)) is V
Since it is still SS, the following effects are obtained. At the moment when the reset MOSFET 3 is turned off, the reset MOSF
The reset level described in the fourth embodiment is specifically lower than VRESH-Vth by ΔCK due to clock leakage due to gate-source capacitance coupling of ET3. The decrease ΔCK due to this clock leak is φRE
When the low level of S decreases, the amplitude of φRES increases because it increases. As in the present embodiment, when the low level is V
If it remains SS, ΔCK will not increase,
Reduction of the dynamic range is avoided.

During the accumulation period in which φTX is at a low level in all rows, or in all rows except for one row, φT
In the read period in which X is at the low level, the through current of the level conversion unit cannot be ignored. Therefore, by employing a level conversion circuit having a built-in through current suppression circuit as described in the second or third embodiment, low power consumption can be realized, and the effect is particularly high.

(Embodiment 6) Embodiment 6 of the present invention will be described.

This embodiment relates to a solid-state imaging device (FIG. 9) using the scanning circuit of FIG. 7 as a vertical scanning circuit. The level shift circuit in the scanning circuit of FIG. 7 is the level shift circuit 23 included in the scanning circuits of the first to third embodiments described above.

FIG. 9 shows a solid-state image pickup device, in which the scanning circuit of FIG. 7 is driven as a vertical scanning circuit, and which embodies a method of improving linearity and dynamic range. The selection MOSFET 5 is an amplification MOS
In the solid-state imaging device connected between the FET 2 and the pixel unit power supply VDD, the gate high level (VSELH) applied to the selection MOSFET 5 is reset by the reset MOSF.
By setting it higher than the gate high level (VDD) of ET4, the linearity on the low luminance side is improved, and the effective dynamic range is expanded. In the present embodiment, the area of the scanning circuit portion can be reduced by using the scanning circuit of FIG.

In the fourth to sixth embodiments, the case where the signal charge is an electron has been described. Even when the signal charge is a hole, it is apparent that the same effect can be obtained by reversing the polarity. is there. In addition, the above embodiments 4 to 6
Although not limited to the circuit configuration, voltage value, and the like described above, the effect is more remarkable as the power supply voltage becomes lower and the process becomes finer.

(Embodiment 7) An imaging apparatus using the solid-state imaging device described in Embodiments 4 to 6 will be described with reference to FIG.

In FIG. 11, reference numeral 101 denotes a barrier which functions both as protection of the lens and as a main switch; 102, a lens for forming an optical image of a subject on the solid-state image sensor 104;
Reference numeral 03 denotes an aperture for varying the amount of light passing through the lens 102, reference numeral 104 denotes a solid-state imaging device for capturing a subject formed by the lens 102 as an image signal, and reference numeral 105 denotes an image signal output from the solid-state imaging device 104. An image signal processing circuit including a variable gain amplifier section for amplifying and a gain correction circuit section for correcting a gain value; , 107 are A / D converters 1
A signal processing unit 108 for performing various corrections on the image data output from 06 and compressing the data;
04, an imaging signal processing circuit 105, an A / D converter 106,
A timing generation unit for outputting various timing signals to the signal processing unit 107; 109, an overall control / operation unit for controlling various operations and the entire still video camera; 110, a memory unit for temporarily storing image data; Is an interface unit for recording or reading on a recording medium, 112 is a detachable recording medium such as a semiconductor memory for recording or reading image data, and 113 is an interface unit for communicating with an external computer or the like. .

Next, the operation of the image pickup apparatus at the time of photographing in the above configuration will be described.

When the barrier 1 is opened, the main power supply is turned on, and then the control system power supply is turned on.
The power of the imaging system circuit such as the / D converter 6 is turned on.

Then, in order to control the exposure amount, the overall control / calculation unit 109 opens the aperture 103, and the signal output from the solid-state image sensor 104 is converted by the A / D converter 106, and then the signal is processed. The data is input to the unit 107. The overall control / arithmetic unit 9 calculates the exposure based on the data.

The brightness is determined based on the result of the photometry, and the overall control / arithmetic unit 9 controls the aperture according to the result.

Next, based on the signal output from the solid-state imaging device 104, a high-frequency component is extracted and the overall control / arithmetic unit 109 calculates the distance to the subject. Thereafter, the lens is driven to determine whether or not the lens is in focus. When it is determined that the lens is not focused, the lens is driven again to perform distance measurement.

After the in-focus state is confirmed, the main exposure starts.

When the exposure is completed, the image signal output from the solid-state image sensor 104 is A / D-converted by the A / D converter 106, passes through the signal processing unit 107, and is controlled by the overall control / operation unit 10
9 is written to the memory unit.

Thereafter, the data stored in the memory unit 110 passes through the recording medium control I / F unit under the control of the overall control / arithmetic unit 109 and is recorded on a removable recording medium 112 such as a semiconductor memory.

Further, the image may be processed by inputting it directly to a computer or the like through the external I / F unit 113.

[0076]

As described above, the scanning circuit of the present invention has a built-in level conversion function and can output a plurality of pulses having different voltage ranges. The operation can be performed.

In particular, in the solid-state imaging device of the present invention in which such a scanning circuit is applied to a solid-state imaging device, a high-quality solid-state imaging device with improved dynamic range and dark current characteristics can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a unit block of a scanning circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a unit block of a scanning circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram illustrating a unit block of a scanning circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram illustrating another level conversion circuit having the same function as the level conversion circuit of the scanning circuit according to the third embodiment of the present invention.

FIG. 5 is a diagram illustrating two stages of unit blocks of a scanning circuit according to a fourth embodiment of the present invention.

FIG. 6 is a diagram illustrating two stages of unit blocks of a scanning circuit according to a fifth embodiment of the present invention.

FIG. 7 is a diagram illustrating two stages of unit blocks of a scanning circuit according to a sixth embodiment of the present invention.

FIG. 8 is a diagram illustrating a solid-state imaging device according to Embodiments 4 and 5 of the present invention.

FIG. 9 is a diagram illustrating a solid-state imaging device according to a sixth embodiment of the present invention.

FIG. 10 is a diagram illustrating a part of the drive timing when driving the solid-state imaging device according to the fourth embodiment.

FIG. 11 is a diagram illustrating an imaging apparatus using the solid-state imaging device according to Embodiments 4 and 5.

FIG. 12 is a diagram showing a conventional scanning circuit.

[Explanation of symbols]

 Reference Signs List 1 photodiode 2 amplification MOSFET 3 transfer MOSFET 4 reset MOSFET 5 selection MOSFET 6 vertical scanning circuit 7 vertical output line 8a, 8b transfer gate 9 constant current source 10 signal storage unit 11 horizontal scanning circuit 21 unit block of shift register 22 Pulse output circuit 23 Level conversion circuit 24, 25 Buffer circuit 26 Pre-stage circuit of level conversion circuit 27 Post-stage circuit of level conversion circuit 28 PMOSFET constituting inverter 29 NMOSFET constituting inverter 30 NMOSFET constituting through current suppression circuit

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Dai Fujimura 3-30-2 Shimomaruko, Ota-ku, Tokyo Inside Canon Inc. (72) Inventor Katsuhito Sakurai 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inside (72) Inventor Tomoko Eguchi 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Inventor Masanori Ogura 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. F Terms (reference) 4M118 AA02 AA05 AB01 BA14 CA03 DD10 FA06 FA34 FA42 FA45 GD03 5C024 BX01 CX32 CX43 GX04 GY36 HX15 HX23 HX51 JX00

Claims (23)

[Claims] 1. A shift register, comprising: a shift register; and a pulse output circuit that outputs a plurality of pulses based on a pulse from the shift register provided at each stage of the shift register. A scanning circuit including a level conversion circuit for converting a voltage range of a pulse from a register, wherein the pulse output circuit outputs pulses in a plurality of different voltage ranges. 2. The scanning circuit according to claim 1, wherein the level shift circuit includes a through current suppression circuit that suppresses a through current. 3. The scanning circuit according to claim 1, wherein said level shift circuit includes a complementary inverter. 4. The scanning circuit according to claim 3, wherein said through current suppressing circuit suppresses a current flowing through said complementary inverter. 5. The circuit of claim 1, wherein the through current suppressing circuit includes a transistor connected in series between the complementary inverter and a power supply, wherein the transistor has a level-converted pulse generated by the pulse output circuit. 5. The scanning circuit according to claim 4, wherein the scanning circuit is controlled by: 6. A photoelectric conversion unit that converts incident light into an electric signal and stores the electric signal, an amplification transistor that amplifies and outputs a signal from the photoelectric conversion unit, and the electric signal that is stored in the photoelectric conversion unit. A plurality of pixels each including a transfer transistor that transfers a signal to the amplification transistor, and a processing transistor that performs a predetermined process, and a signal level applied to a control electrode of the transfer transistor for switching off the transfer transistor.
A scanning circuit for controlling the processing transistor to be turned off, the scanning circuit controlling the signal level to be lower than a signal level applied to a control electrode of the processing transistor, the scanning circuit includes a shift register, and each of the shift register. A pulse output circuit that outputs a plurality of pulses based on the pulse provided by the shift register provided in each stage; and the pulse output circuit includes a level conversion circuit that converts a voltage range of the pulse from the shift register. An imaging device, wherein the pulse output circuit outputs pulses in a plurality of different voltage ranges. 7. The imaging device according to claim 6, wherein the level shift circuit includes a through current suppression circuit that suppresses a through current. 8. The imaging device according to claim 6, wherein the processing transistor includes a reset transistor for resetting a control electrode of the amplification transistor. 9. The imaging device according to claim 6, wherein the scanning circuit applies a pulse of the same amplitude to a control electrode of the transfer transistor and a control electrode of the processing transistor. apparatus. 10. A photoelectric conversion unit that converts incident light into an electric signal and stores the electric signal, an amplification transistor that amplifies and outputs a signal from the photoelectric conversion unit, and a reset for resetting a control electrode of the amplification transistor. A plurality of pixels each including a transistor and a processing transistor for performing predetermined processing, and for switching off the reset transistor,
A scanning circuit for controlling the signal level applied to the control electrode of the reset transistor to be lower than the signal level applied to the control electrode of the processing transistor for switching off the processing transistor; The scanning circuit includes a shift register, and a pulse output circuit that outputs a plurality of pulses based on a pulse from the shift register provided at each stage of the shift register, and the pulse output circuit includes the shift register. An image pickup apparatus, comprising: a level conversion circuit for converting a voltage range of a pulse from a pulse generator; 11. The imaging device according to claim 10, wherein the level shift circuit includes a through current suppression circuit that suppresses a through current. 12. The imaging device according to claim 10, wherein the processing transistor includes a selection transistor for supplying a predetermined potential to the amplification transistor so as to output a signal from the amplification transistor. apparatus. 13. The imaging device according to claim 10, wherein the scanning circuit applies a pulse having the same amplitude to a control electrode of the transfer transistor and a control electrode of the processing transistor. apparatus. 14. A photoelectric conversion unit that converts incident light into an electric signal and stores the signal, a first processing transistor that performs predetermined processing on a signal from the photoelectric conversion unit and outputs the signal, and a signal that is stored in the photoelectric conversion unit. A plurality of pixels each including a transfer transistor for transferring the electrical signal to the first processing transistor, and a second processing transistor for performing predetermined processing; and the transfer for switching off the transfer transistor. The signal level applied to the control electrode of the transistor is
A scanning circuit for controlling the second processing transistor to be turned off so as to be lower than a signal level applied to a control electrode of the processing transistor, wherein the scanning circuit includes a shift register; A pulse output circuit for outputting a plurality of pulses based on the shift register provided in each stage of the register, wherein the pulse output circuit converts a voltage range of a pulse from the shift register; An imaging apparatus including a conversion circuit, wherein the pulse output circuit outputs pulses in a plurality of different voltage ranges. 15. The imaging device according to claim 13, wherein the level shift circuit includes a through current suppression circuit that suppresses a through current. 16. The scanning circuit according to claim 1, wherein the scanning circuit applies pulses of the same amplitude to a control electrode of the transfer transistor and a control electrode of the second processing transistor.
The imaging device according to 3 or 14. 17. A photoelectric conversion unit that converts incident light into an electric signal and accumulates the signal, a first processing transistor that performs predetermined processing on a signal from the photoelectric conversion unit and outputs the processed signal, and supplies a reset signal. A plurality of pixels each including a reset transistor and a second processing transistor that performs predetermined processing, and a signal level applied to a control electrode of the transfer transistor for switching off the transfer transistor,
A scanning circuit for controlling the second processing transistor to be turned off so as to be lower than a signal level applied to a control electrode of the processing transistor, wherein the scanning circuit includes a shift register; and the shift register. A pulse output circuit that outputs a plurality of pulses based on the pulse provided by the shift register provided at each stage, wherein the pulse output circuit converts a voltage range of a pulse from the shift register. An imaging apparatus including a circuit, wherein the pulse output circuit outputs pulses in a plurality of different voltage ranges. 18. The imaging device according to claim 16, wherein the level shift circuit includes a through current suppression circuit that suppresses a through current. 19. The imaging apparatus according to claim 16, wherein the scanning circuit applies pulses of the same amplitude to a control electrode of the reset transistor and a control electrode of the second processing transistor. 20. A photoelectric conversion unit for converting incident light into an electric signal and storing the electric signal, a first processing transistor having a main electrode connected to the photoelectric conversion unit and performing a predetermined process, and a main electrode comprising the photoelectric conversion unit. A plurality of pixels each including a second processing transistor that performs a predetermined process that is not connected to a plurality of pixels, and a signal level applied to a control electrode of the first transistor for switching off the first transistor. A scanning circuit for switching off the second processing transistor so as to be lower than a signal level applied to a control electrode of the processing transistor, wherein the scanning circuit includes a shift register and the shift circuit. A pulse output circuit that outputs a plurality of pulses based on the pulse of the shift register provided at each stage of the register; The output circuit includes a level converting circuit for converting the voltage range of the pulse from the shift register, the pulse output circuit includes an imaging device and outputs a pulse of a plurality of different voltage ranges. 21. The imaging device according to claim 19, wherein the level shift circuit includes a through current suppression circuit that suppresses a through current. 22. The control circuit according to claim 19, wherein the control circuit applies pulses of the same amplitude to a control electrode of the first processing transistor and a control electrode of the second processing transistor. Imaging device. 23. A lens which forms an image on the plurality of pixels, an analog / digital conversion circuit for converting signals from the plurality of pixels into digital signals, and a signal from the analog / digital conversion circuit. 22. A signal processing circuit for processing
The imaging device according to any one of the above.