JP2002247065A - Switching hub and operating clock changeover method to be used therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching hub capable of reducing power consumption without impairing communication performance among terminals. SOLUTION: When a link is established between terminals 2-1 to 2-4, ports 11-1 to 11-4 generate link establishment signals. A link detecting part 15 totals the link establishment signals and transmits the number to a frequency deciding circuit 14 as the number of link information. The frequency deciding circuit 14 decides an operating frequency of the switching hub 1 based on the number of link information and transmits a clock control signal to a variable clock oscillator 13. The variable clock oscillator 13 outputs clocks to communication control parts 12-1 to 12-4 based on the clock control signal. The communication control part 12-1 to 12-4 and a bus 100 is operated by being synchronized with the clocks to be outputted from the variable clock oscillator 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching hub and an operation clock switching method used for the same, and more particularly to a switching hub for interconnecting OA equipment such as a personal computer.

[0002]

2. Description of the Related Art Recently, OA of personal computers and the like has been developed.
As the number of devices increases, it is desired to reduce power consumption. As a method of connecting these OA devices to each other, there is a method of configuring a network via a network device.

[0003] Generally, network equipment is generally operated for 24 hours, and the power of the network equipment is always ON even at night or on holidays when the OA equipment (terminal) is not used.

[0004] One of the network devices is a switching hub. Generally, a switching hub is always operating at a performance capable of processing data even when data flows in at a maximum communication speed in all of its ports.

[0005]

However, in the conventional switching hub, if there is an unused port among a plurality of ports to which the OA device is connected, the switching hub operates with more performance than necessary, resulting in unnecessary operation. Often become.

It is an object of the present invention to solve the above-mentioned problems and to provide a switching hub and an operation clock switching method used therefor which can reduce power consumption without impairing communication performance between terminals. .

[0007]

SUMMARY OF THE INVENTION A switching hub according to the present invention is a switching hub including a plurality of ports to each of which terminals are connected, and processes communication between the terminals according to the number of ports used. There are provided means for calculating a minimum required operating clock frequency that does not impair performance, and means for changing the operating clock frequency according to the calculation result.

An operation clock switching method for a switching hub according to the present invention is an operation clock switching method for a switching hub including a plurality of ports to each of which terminals are connected, wherein the switching between the terminals depends on the number of ports used. Calculating the minimum operation clock frequency that does not impair the processing performance of the communication, and changing the operation clock frequency according to the calculation result.

That is, the switching hub of the present invention comprises:
The operating clock frequency is changed according to the number of ports used, and the operation is performed at the minimum necessary clock frequency that does not impair the processing performance of communication between terminals. Thus, the power consumption of the switching hub itself can be reduced.

[0010] More specifically, the switching hub of the present invention has four ports, and when two terminals are connected via the ports, the number of ports that are linked up is calculated, According to the calculation result, the operation clock frequency is reduced to a value that does not impair the processing performance of communication between terminals. This makes it possible to reduce power consumption without impairing the processing performance of communication between terminals.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a switching hub according to one embodiment of the present invention. Figure 1
, The switching hub 1 has four ports 11-1
~ 11-4, each with a terminal (OA equipment)
2-1 to 2-4 can be connected.

In this embodiment, for example, the switching hub 1
To two terminals 2- via ports 11-1 and 11-2.
When the switching hubs 1 and 2 are connected, the switching hub 1 calculates the number of the ports 11-1 and 11-2 that are linked up, and changes the operation clock frequency to the terminals 2-1 and 2- according to the calculation result. The processing performance of two-way communication is reduced to a value that does not impair. Thus, the power consumption of the switching hub 1 can be reduced.

FIG. 2 is a block diagram showing a detailed configuration of the switching hub according to one embodiment of the present invention. In FIG. 2, the switching hub 1 has ports 11-1 to 11-4.
Communication control units 12-1 to 12-4, variable clock oscillator 13, frequency determination circuit 14, link detection unit 15
It is composed of

The ports 11-1 to 11-4 are connected to the terminals 2-1 to 2-1.
2-4 and 100BASE-TX Fast Ethernet (registered trademark), convert the packets received from the terminals 2-1 to 2-4 into electrical levels, and send them to the communication control units 12-1 to 12-4.

The ports 11-1 to 11-4 convert the packets sent from the communication control units 12-1 to 12-4 into electrical levels and send the packets to the terminals 2-1 to 2-4. Further, the ports 11-1 to 11-4 generate link establishment signals 101 to 104 to the link detection unit 15 when a link is established between the terminals 2-1 to 2-4.

The communication control unit 12-1 has ports 11-1 to 11-1.
The destination is determined from the destination address of the packet received from 1-4, and is passed to the communication control unit 12-2 of the destination port via the bus 100. In addition, it passes the packet received from another communication control unit 12-3 to the port 11-1.

The other communication control units 12-2 to 12-4 operate in the same manner as the communication control unit 12-1. The communication control units 12-1 to 12-4 and the bus 100 operate in synchronization with a clock output from the variable clock oscillator 13.

The variable clock oscillator 13 is a clock oscillator capable of outputting at least two types of frequencies, and outputs a clock having a frequency specified by the clock control signal 112. This variable clock oscillator 13 can be realized by a clock oscillator and a frequency dividing circuit.

The frequency determining circuit 14 determines the operating frequency of the switching hub 1 based on the link number information 111 sent from the link detecting unit 15 and
The clock control signal 112 is transmitted. This frequency determination circuit 14 can be realized by a simple arithmetic circuit.

The link detection unit 15 includes ports 11-1 to 11-11.
-4, the link establishment signals 101 to 104 are totaled, and the number is transmitted to the frequency determination circuit 14 as link number information 111.

FIG. 3 is a diagram for explaining the operation of the switching hub 1 according to one embodiment of the present invention, and FIG. 4 is a flowchart showing the operation of the switching hub 1 according to one embodiment of the present invention. The operation of the switching hub 1 according to one embodiment of the present invention will be described with reference to FIGS.

First, as shown in FIG. 2, the terminal 2 is connected to all four ports 11-1 to 11-4 of the switching hub 1.
The operation in the case where 1-2 are connected will be described below.

Ports 11-1 to 11-4 and terminals 2-1 to 2-1
When all the terminals 2-4 are connected by 100BASE-TX Fast Ethernet, data of a maximum of 100 Mbps is transmitted from the terminals 2-1 to 2-4. Therefore, the bus 100 connecting the communication control units 12-1 to 12-4
Needs to process 400 Mbps data. When the bus width of the bus 100 is 32 bits, the bus clock needs to be at least 12.5 MHz or more.

The ports 11-1 to 11-4 are connected to the terminals 2-1 to 2-1.
When a link is established between the server and the server 2-4 (step S in FIG. 4)
1) The link establishment signals 101 to 104 are transmitted to the link detection unit 1
5 (step S2 in FIG. 4).

The link detection unit 15 includes ports 11-1 to 11
-4 is calculated based on the number of link establishment signals 101 to 104 from the -4 (step S3 in FIG. 4), and the frequency determination circuit 1
4 (step S4 in FIG. 4).

The frequency determination circuit 14 calculates a necessary bus band based on the link number information 18 from the link detection unit 15 and determines a clock frequency (step S5 in FIG. 4).
This bus bandwidth is calculated using the formula (data amount per port) × (number of ports with established links) ÷ (bus width). In this example, (100 Mbp
s) × (4 ports) ÷ (32 bits) = 12.5 MHz
Becomes This can be realized with a simple arithmetic circuit.

Therefore, in the case of the above example, the frequency determination circuit 14 supplies the variable clock oscillator 13 with 12.5 MHz
The clock control signal 112 outputs the above clock.
Is output (step S6 in FIG. 4).

The variable clock oscillator 13 generates a clock having a frequency specified by the clock control signal 112 sent from the frequency determination circuit 14 to generate the communication control units 12-1 to 12-1.
Output to 12-4 (step S7 in FIG. 4). In the case of this example, the variable clock oscillator 13 sends the communication control unit 12-
A clock of 12.5 MHz is output to 1 to 12-4. The communication controllers 12-1 to 12-4 operate in synchronization with a clock sent from the variable clock oscillator 13.
The operation of the communication control units 12-1 to 12-4 is well known to those skilled in the art and is not directly related to the present invention, so that the description thereof is omitted.

Thus, the packets transmitted from the terminals 2-1 to 2-4 are transmitted to the destination terminal without being dropped in the switching hub 1.

Next, as shown in FIG. 3, the terminals 2-1 and 2-2 are connected to two ports 11-1 and 11-2 of the four ports 11-1 to 11-4 of the switching hub 1. The operation when is connected is described below.

When the ports 11-1 and 11-2 are respectively connected to the terminals 2-1 and 2-2 by 100BASE-TX Fast Ethernet, data of a maximum of 100 Mbps is transmitted from the terminals 2-1 and 2-2. Come.

Therefore, the communication control units 12-1 to 12-
It is necessary for the bus 100 connecting 4 to process 200 Mbps data. When the bus width of the bus 100 is 32 bits, the bus clock frequency must be at least 6.25 MHz or more.

The ports 11-1 and 11-2 are connected to the terminals 2-1 and 2-1.
When a link is established with the 2-2 (step S in FIG. 4)
1), the link establishment signals 101 and 102 are transmitted to the link detection unit 1
5 (step S2 in FIG. 4).

The link detection unit 15 is connected to the ports 11-1, 11
Based on the number of link establishment signals 101 and 102 from -2, the total number of ports to which a link is established is calculated (step S3 in FIG. 4), and the link number information 111 is transmitted to the frequency determination circuit 14 (step in FIG. S4).

The frequency determination circuit 14 has link number information 111
The required bus bandwidth is calculated based on the above, and the clock frequency is determined (step S5 in FIG. 4). In this case,
(100 Mbps) × (2 ports) ÷ (32 bits) =
6.25 MHz. The frequency determination circuit 14 outputs the clock control signal 112 so as to output a clock of 6.25 MHz or more to the variable clock oscillator 13 (Step S5 in FIG. 4).

The variable clock oscillator 13 generates a clock having a frequency specified by the clock control signal 112 sent from the frequency determination circuit 14 to generate the communication control units 12-1 to 12-1.
12-4 (step S5 in FIG. 4). In the case of this example, the variable clock oscillator 13 sends the communication control unit 12-
A clock of 6.25 MHz is output to 1 to 12-4. The communication control units 12-1 to 12-4 operate in synchronization with the 6.25 MHz clock sent from the variable clock oscillator 13 (step S5 in FIG. 4).

Thus, the communication control units 12-1 to 12-12
-4 operates at a clock frequency of 6.25 MHz from the variable clock oscillator 13.

In general, when the operating clock frequency decreases, the power consumption also decreases. Therefore, the power consumption of the switching hub 1 is reduced as compared with the case where four terminals 2-1 to 2-4 are connected to the switching hub 1. can do.

As described above, since the operating clock frequency of the switching hub 1 can be reduced, the operating frequency of the switching hub 1 is reduced, so that the communication control unit 12-1 is reduced.
12-4, the cooling fan (not shown) of the switching hub 1 can be stopped, and the power consumption can be further reduced.

Further, the minimum required operation clock frequency is calculated from the number of used ports, and the terminal 2-1 to 2-
Since it operates at a clock frequency that does not impair the processing performance of the communication between the terminals 4, even when the operating clock frequency of the switching hub 1 decreases, the processing performance of the communication between the terminals 2-1 to 2-4 does not deteriorate.

At present, the communication speed of Ethernet generally used in the terminals 2-1 to 2-4 and the like is 10 Mbps or 100 Mbps. Normally, the switching hub 1 has a performance capable of processing packets without dropping even if terminals of 100 Mbps are connected to all the ports 11-1 to 11-4.

However, actually, the ports 11-1 to 11-1
In many cases, a 10 Mbps terminal is connected to 11-4. In this case, even if the operating clock frequency of the switching hub 1 is reduced, the processing performance of the communication between the terminals 2-1 to 2-4 is not impaired.

FIG. 5 is a block diagram showing a detailed configuration of a switching hub according to another embodiment of the present invention. 5, a switching hub according to another embodiment of the present invention has the same configuration as that of the embodiment of the present invention shown in FIG. 2 except that 100M operation signals 121 to 124 are added in addition to the link detection signals 101 to 104. The same components are denoted by the same reference numerals. The operation of the same component is the same as that of the embodiment of the present invention.

The 100M operation signals 121 to 124 indicate that the ports 11-1 to 11-4 are operating in the 100 Mbps mode. As a result, the port 11-
It is possible to calculate not only the required bus performance but also the communication speed of each of the ports 11-1 to 11-4 and calculate the minimum necessary operating clock frequency by linking up the ports 1 to 11-4. Become.

FIG. 6 is a flowchart showing the operation of the switching hub 1 according to another embodiment of the present invention. The operation of the switching hub 1 according to another embodiment of the present invention will be described with reference to FIGS.

In FIG. 5, terminals 2-1 and 2-2 operate at a data transmission rate of 100 Mbps, and terminals 2-3 and 2-4 operate at a data transmission rate of 10 Mbps. The case will be described below.

As for the ports 11-1 to 11-4, the own port is 1
When operating in the 00 Mbps mode (Step S in FIG. 6)
11), and outputs a 100M operation signal 121 to the link detector 15 (Step S12 in FIG. 6).

The ports 11-1 and 11-2 are connected to the terminals 2-1 and 2-1.
When a link is established with the 2-2 (step S1 in FIG. 6)
3), the link establishment signals 101 and 102 are transmitted to the link detection unit 1
5 (step S14 in FIG. 6). At this time, since the terminals 2-1 and 2-2 are operating at 100 Mbps,
1 is sent from the ports 11-1 and 11-2 to the link detection unit 15.
00M operation signals 121 and 122 are also output.

The ports 11-3 and 11-4 are connected to the terminal 2
When a link is established between -3 and 2-4 (step S13 in FIG. 6), link establishment signals 103 and 104 are output to the link detector 15 (step S14 in FIG. 6). However, at this time, since the terminals 2-3 and 2-4 operate at 10 Mbps, the 100M operation signals 123 and 124 are not output to the link detection unit 15 from the ports 11-3 and 11-4.

The link detecting section 15 has a link establishment signal 101
The total number of ports to which links are established is calculated from the numbers of .about.104 (step S15 in FIG. 6), and the link number information 111 is transmitted to the frequency determination circuit 14 (step S1 in FIG. 6).
6). At this time, the port operating in the 100 Mbps mode is counted as 10. In this example, 1
0 + 10 + 1 + 1 = 22.

The frequency determination circuit 14 has link number information 111
The required bus bandwidth is calculated based on the above, and the clock frequency is determined (step S17 in FIG. 6). In this case,
(10 Mbps) × (22) ÷ (32 bits) = 6.8
75 MHz. The frequency determination circuit 14 outputs the clock control signal 112 so as to output a clock of 6.25 MHz or more to the variable clock oscillator 13 (Step S18 in FIG. 6).

The variable clock oscillator 13 generates a clock having a frequency specified by the clock control signal 112 sent from the frequency determination circuit 14 and generates the communication control units 12-1 to 12-1.
Output to 12-4 (step S19 in FIG. 6). In the case of this example, the variable clock oscillator 13 sends the communication control unit 12
A clock of 6.25 MHz is output to -1 to 12-4. The communication control units 12-1 to 12-4 operate in synchronization with the 6.25 MHz clock sent from the variable clock oscillator 13 (step S20 in FIG. 6).

Thus, the communication control units 12-1 to 12-12
-4 operates at a clock frequency of 6.25 MHz from the variable clock oscillator 13.

As described above, two 100 Mbps terminals 2-1 and 2-2 and two 10 Mbps terminals 2-
When 3, 2-4 are connected, the bus clock frequency is 12.5 MHz in one embodiment of the present invention, but is 6.875 MHz in this embodiment, and the operating clock frequency can be further reduced. .

[0055]

As described above, according to the present invention, in a switching hub including a plurality of ports to which terminals are connected, the processing performance of communication between the terminals is impaired according to the number of ports used. By calculating the minimum necessary operating clock frequency and changing the operating clock frequency according to the calculation result, there is an effect that power consumption can be reduced without impairing the communication performance between terminals.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a switching hub according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a detailed configuration of a switching hub according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating an operation of the switching hub according to one embodiment of the present invention.

FIG. 4 is a flowchart illustrating an operation of the switching hub according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating a detailed configuration of a switching hub according to another embodiment of the present invention.

FIG. 6 is a flowchart illustrating an operation of a switching hub according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Switching hub 2-1 to 2-4 Terminal 11-1 to 11-4 Port 12-1 to 12-4 Communication control unit 13 Variable clock oscillator 14 Frequency determination circuit 15 Link detection unit 100 Bus 101 to 104 Link establishment signal 111 Link number information 112 Clock control signals 121 to 124

Claims (10)

[Claims] 1. A switching hub including a plurality of ports to each of which terminals are connected, wherein a minimum required operating clock frequency which does not impair communication processing performance between the terminals according to the number of ports used. And a means for changing the operation clock frequency according to the calculation result. 2. The switching hub according to claim 1, wherein the port is configured to generate a link establishment signal when a link is established with the terminal. 3. The means for calculating the operation clock frequency includes means for calculating a total number of ports to which a link is established based on the number of link establishment signals, and a bus bandwidth required based on the total number of ports. Means for calculating the operating clock frequency by calculating the following equation:
The switching hub as described. 4. The terminal according to claim 1, wherein the port generates an operation mode signal according to a data transmission rate of the terminal and generates a link establishment signal when a link is established with the terminal. The switching hub according to claim 1, wherein 5. The means for calculating the operation clock frequency includes means for calculating a total number of ports to which a link has been established based on the number of the link establishment signals, and means for calculating the total number of ports and the operation mode signal. 5. The switching hub according to claim 4, further comprising: means for calculating a required bus bandwidth based on the calculated clock frequency and determining the operation clock frequency. 6. A method for switching an operation clock of a switching hub including a plurality of ports each connected to a terminal,
A step of calculating a minimum operation clock frequency that does not impair the processing performance of the communication between the terminals according to the number of ports used; and a step of changing the operation clock frequency according to the calculation result. An operation clock switching method, characterized in that: 7. The operation clock switching method according to claim 6, wherein said port generates a link establishment signal when a link is established with said terminal. 8. The step of calculating the operation clock frequency includes the step of calculating the total number of ports with which links are established based on the number of link establishment signals, and the step of calculating a required bus bandwidth based on the total number of ports. Calculating the operation clock frequency to determine the operation clock frequency. 9. The terminal according to claim 1, wherein the port generates an operation mode signal in accordance with a data transmission rate of the terminal, and generates a link establishment signal when a link is established with the terminal. 7. The operation clock switching method according to claim 6, wherein: 10. The step of calculating the operation clock frequency includes the step of calculating a total number of ports for which a link is established based on the number of link establishment signals, and a step of calculating the total number of ports and the operation mode signal. 10. The method according to claim 9, further comprising the step of: calculating a required bus bandwidth based on the calculated clock frequency to determine the operating clock frequency.