JP2002246903A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit, which is capable of reaching a phase-locked state in a short time, after a phase detector has started a phase comparison operation. SOLUTION: A PLL circuit is equipped with a voltage-controlled oscillator 40; a phase detector 10 which compares the phase of signals obtained by multiplying the frequency of the signals outputted from the voltage-controlled oscillator 40 by 1/N (N denotes an integer of 1 or larger) with that of input signals and outputs phase difference signals corresponding to a phase difference; a charging pump circuit 20 which supplies a current on the basis of the phase difference signals outputted from the phase detector 10, a loop filter 30 which comprises a resistor R1, to which a current is supplied from the charging pump circuit 20 and a capacitor C2 connected to the resistor R1 in series; and a potential feed means Q1, which supplies a prescribed potential to at least one end of the resistor R1 of the loop filter 30 for a prescribed period, after the phase detector has started a phase comparison operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a PLL (Phase Locked Loop) circuit for generating an output signal whose phase is synchronized with an input signal.

[0002]

2. Description of the Related Art In general, a PLL circuit controls the phase of an input signal and the frequency of an output signal of a VCO (voltage controlled oscillator) by one.
A control voltage is obtained by comparing the phase of a signal obtained by multiplying the output signal by a factor of / N (hereinafter, referred to as a frequency-divided signal). Occurs. Here, N is an integer of 1 or more. When N is 1, the frequency of the input signal is equal to the frequency of the output signal, and when N is 2 or more, an output signal obtained by multiplying the frequency of the input signal is obtained.

In a PLL circuit, the phase of an input signal is compared with that of a divided signal by a phase detector. The phase difference signal output from the phase detector is integrated by the charge pump circuit and the loop filter. That is, the charge pump circuit supplies a current to the loop filter based on the phase difference signal output from the phase detector, thereby obtaining a control voltage for controlling the VCO. The loop filter is composed of, for example, a resistor and a capacitor connected in series, and has a low-pass characteristic.

[0004] FIG. 4 shows a change with time of the control voltage _{V C} in the conventional PLL circuit. At time _{t 0,} V
The CO starts oscillating, the phase detector starts the phase comparison operation, and the charge pump circuit also starts supplying current.

[0005] However, when the frequency of the input signal is low, the phase comparison period in the phase detector becomes long, so that the charge pump circuit and the loop filter require a long integration period. Also, when the current supply capacity of the charge pump circuit is small, a long integration period is required as in the above case. As a result, as shown in FIG. 4, period required for the control voltage V _C rises to near the control voltage V _∞ in the steady state (t 2 _{-t 0)} is disadvantageously long.

[0006]

SUMMARY OF THE INVENTION In view of the above, the present invention provides a PLL capable of reaching a phase locked state in a short time after a phase detector starts a phase comparison operation.
It is intended to provide a circuit.

[0007]

In order to solve the above problems, a PLL circuit according to the present invention is a PLL circuit for generating an output signal whose phase is synchronized with an input signal, wherein the frequency changes according to a control voltage. A voltage-controlled oscillator for generating an output signal, and the frequency of the output signal of the voltage-controlled oscillator being 1 / N
The phase of the signal obtained by the multiplication is compared with the phase of the input signal (N is an integer of 1 or more), and a phase detector that outputs a phase difference signal according to the phase difference between them and an output from the phase detector A loop filter that includes a charge pump circuit that supplies a current based on a phase difference signal, a resistor supplied with a current from the charge pump circuit, and a capacitor connected in series with the resistor, and creates a control voltage based on the current And a potential supply means for supplying a predetermined potential to at least one end of the resistor included in the loop filter during a predetermined period after the phase detector starts the phase comparison operation.

[0008] According to the PLL circuit of the present invention configured as described above, by using the potential supply means, the resistance included in the loop filter can be maintained for a predetermined period after the phase detector starts the phase comparison operation. Since a predetermined potential is supplied to at least one end of the phase-locked circuit, the phase locked state can be reached in a short time after the phase comparison operation is started.

Here, the potential supply means includes a second resistor and a second capacitor connected in series, and based on a time constant determined by the second resistor and the second capacitor, The period for supplying the potential may be determined.

If a variable resistor is used as the second resistor, or a variable capacitor is used as the second capacitor, it is easy to adjust the period for supplying a predetermined potential. Furthermore, if a variable resistor is used as the second resistor and a variable capacitor is used as the second capacitor, the period for supplying the predetermined potential can be adjusted over a wide range.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. Note that the same elements are denoted by the same reference numerals and description thereof is omitted.

FIG. 1 is a block diagram of a PLL circuit according to a first embodiment of the present invention. This PLL circuit compares the phase of an input signal with the phase of a signal obtained by multiplying the frequency of an output signal of a VCO (voltage controlled oscillator) 40 by 1 / N (hereinafter referred to as a frequency-divided signal) to control a voltage of a control voltage. I asked the V _C,
By controlling the VCO40 using the control voltage V _C, to generate an output signal whose phase is synchronized with the input signal. Here, N is an integer of 1 or more. When N is 1, the frequency of the input signal is equal to the frequency of the output signal, and N
Is 2 or more, an output signal obtained by multiplying the frequency of the input signal is obtained. As the input signal, for example, a reference clock signal is used.

[0013] VCO40 oscillates at a frequency according to the control voltage V _C to be applied, and outputs the signal obtained by the oscillation as an output signal. The divider circuit 50 divides the frequency of the output signal of the VCO 40 by 1 / N to generate a divided signal. When the frequency of the input signal is always equal to the frequency of the output signal, the frequency dividing circuit 50 is unnecessary. The phase comparator 10 compares the phase of the input signal with the phase of the frequency-divided signal, and outputs a phase difference signal according to the phase difference. The phase difference signal output from the phase detector 10 is supplied to the charge pump circuit 20 and the loop filter 3.
Integrated by zero.

The charge pump circuit 20 includes the phase detector 1
Loop filter based on the phase difference signal output from 0
30 to the current I_OUTSupply. Loop filter 30
Includes a resistor R1 and a capacitor C1 connected in series.
Have low-pass characteristics. For loop filter 30
The current I supplied from the charge pump circuit 20
_OUTIs converted to voltage to control VCO 40
Control voltage V_CIs obtained.

The phase comparison operation signal _VPD is an enable signal for operating the PLL circuit, and changes from a high level to a low level at the start of the phase comparison operation. As a result, the VCO 40 starts oscillating, and the phase detector 10
Starts the phase comparison operation, and the charge pump circuit 20 also starts supplying current. However, when the frequency of the input signal is low, the phase comparison period in the phase detector 10 becomes long, so that the charge pump circuit 20 and the loop filter 30 require a long integration period. Also,
Even when the current supply capacity of the charge pump circuit is small,
As above, a long integration period is required.

In the present embodiment, P
A predetermined potential is supplied to one end (the connection point between the charge pump circuit 20 and the VCO 40) of the resistor R1 included in the loop filter 30 using the channel transistors Q1 and Q4. The predetermined potential is created by lowering the power supply voltage _VDD by a potential difference _VA by using, for example, a transistor in a saturated state connected in series.
Here, the potential (V _DD −V _A ) is set to PL under a certain condition.
It is desirable to set the value close to the steady value _V∞ determined by the operation of the L circuit. Thus, before the PLL circuit reaches the locked state, the gain control voltage V _C close to the steady-state value V _∞, charging of the capacitor C1 included in the loop filter 30 can also be performed. The operation will be described below.

When the phase comparison operation signal _VPD is at a high level, the transistor Q4 is off. When the phase comparison operation signal _VPD changes from the high level to the low level, the transistor Q4 turns on. further,
The transistor Q1 connected in series with the transistor Q4 is also turned on.

The period during which the transistor Q1 is on is determined by the time constant of the resistor R2 and the capacitor C2. When the phase comparison operation signal _VPD changes from the high level to the low level, the P-channel transistor Q2
Is turned on, and charging of the capacitor C2 via the resistor R2 is started. When the charging of the capacitor C2 is completed, the transistor Q1 is turned off, and the control voltage V
_C converges to a steady value determined by the operation of the PLL circuit.

Here, whether the resistor R2 is a variable resistor,
Alternatively, if the capacitor C2 is a variable capacitor,
This time constant can be easily adjusted. Further, if the resistor R2 is a variable resistor and the capacitor C2 is a variable capacitor, the time constant can be adjusted over a wide range.

Further, in the present embodiment, by providing the N-channel transistor Q3, even if the capacitor C2 is charged with an overvoltage before the start of the phase comparison operation, the overvoltage can be discharged.

[0021] FIG. 3 shows the time variation of the control voltage _{V C} in the PLL circuit according to the present embodiment. At time t _0, when the phase comparison operation signal V _PD is changed from the high level to the low level, the operation of the PLL circuit starts. Period T determined by the time constant of the resistor R2 and the capacitor C2
In the transistor Q1 is turned on, close rapidly the control voltage _{V C} to a predetermined potential _(V DD -V _A). With elapsed time T, the transistor Q1 is turned off, the control voltage V _C is converged to a steady value V _∞ determined by the operation of the PLL circuit.

Next, a second embodiment of the present invention will be described. FIG. 2 shows a PL according to the second embodiment of the present invention.
It is a block diagram of an L circuit.

In the present embodiment, P is set so as to reach the phase locked state in a short time after the start of the phase comparison operation.
Using the channel transistors Q1 and Q4, the other end (the capacitor C1) of the resistor R1 included in the loop filter 30 is used.
Is supplied with a predetermined potential. The predetermined potential is created by lowering the power supply voltage _VDD by a potential difference _VA by using, for example, a transistor in a saturated state connected in series. Here, the potential (V _DD-
V _A) is preferably a value close to a steady value V _∞ determined by the operation of the PLL circuit under certain conditions. As a result, before the PLL circuit reaches the locked state, the steady-state value V
It can be obtained near the control voltage V _C to _∞. Time variation of the control voltage V _C in the PLL circuit according to this embodiment also,
It is similar to that shown in FIG.

Incidentally, as in the first embodiment,
Supplies to the potential _(V D D -V _{A) (connection} point of the charge pump circuit 20 and VCO 40) one end of the resistor R1 included in the loop filter 30, as in the second embodiment, the resistor R1 The potential (V _DD −V _A ) may be supplied to the other end (connection point with the capacitor C1).

[0025]

As described above, according to the PLL circuit of the present invention, by using the potential supply means, it is included in the loop filter for a predetermined period after the phase detector starts the phase comparison operation. Since a predetermined potential is supplied to at least one end of the resistor, the phase locked state can be reached in a short time after starting the phase comparison operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a PLL circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a time change of a control voltage in the PLL circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a time change of a control voltage in a conventional PLL circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Phase detector 20 Charge pump 30 Loop filter 40 VCO 50 Divider circuit R1, R2 Resistance C1, C2 Capacitor Q1-Q4 Transistor

Claims (5)

[Claims] 1. A PLL circuit that generates an output signal whose phase is synchronized with an input signal, comprising: a voltage-controlled oscillator that generates an output signal whose frequency changes according to a control voltage; The phase of the signal obtained by multiplying by 1 / N is compared with the phase of the input signal (N is 1
A phase detector that outputs a phase difference signal corresponding to the phase difference, a charge pump circuit that supplies a current based on the phase difference signal output from the phase detector, and the charge pump circuit. And the current supplied from the
A loop filter that includes a capacitor connected in series with the resistor and creates the control voltage based on the current; and for a predetermined period after the phase detector starts a phase comparison operation, the loop filter A potential supply means for supplying a predetermined potential to at least one end of the included resistor. 2. The potential supply means includes a second resistor and a second capacitor connected in series, and based on a time constant determined by the second resistor and the second capacitor. 2. The PLL circuit according to claim 1, wherein a period for supplying the predetermined potential is determined. 3. The PLL circuit according to claim 2, wherein said second resistor is a variable resistor. 4. The PLL circuit according to claim 2, wherein said second capacitor is a variable capacitor. 5. The PLL circuit according to claim 2, wherein said second resistor is a variable resistor, and said second capacitor is a variable capacitor.