JP2002238284A - Motor drive control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily obtain a control signal when a motor is activated in digital control. SOLUTION: When the motor is to be activated, a drive control signal is selected by a switch circuit 12. The drive control signal is obtained by processing a signal from a Hall sensor using a combination circuit 10. Contrarily, in a three-time detection circuit 16, the drive control signal that is digitally generated by a control signal generation circuit 14 is selected by a switch circuit after the rotation is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a motor drive control circuit for generating a motor drive control signal based on a motor rotor position detection signal.

[0002]

2. Description of the Related Art Conventionally, there has been known a motor control circuit for detecting a rotor position by a Hall sensor and controlling a motor drive current supplied to a stator coil. For example, in the case of a three-phase brushless motor, the position of the rotor to which the permanent magnet is attached is detected by three Hall sensors, and the motor drive current to the three-phase stator coils is determined according to the output of the Hall sensor of each phase. Control. In a normal case, a control signal from the motor drive control circuit is supplied to the inverter, and the on / off of the switching transistor of the inverter is controlled in accordance with the control signal, so that a three-phase AC current corresponding to the rotor position is applied to the stator coil of the motor. To drive the motor.

Here, digital control has been used in such a motor drive control circuit. According to the digital control, there is an advantage that the influence of the fluctuation of the power supply voltage is small and that the motor drive can be easily controlled by various digital signals from a microcomputer or the like.

In the case of such digital control, the motor drive control circuit creates a control signal for each phase on the basis of the rise or fall of the output signal of the Hall sensor.

[0005]

However, at the time of startup when the motor is not rotating, the output signal of the Hall sensor does not rise or fall. Therefore, it was necessary to obtain a start signal by some means.

The present invention has been made in view of the above problems, and has as its object to provide a motor drive control circuit that can easily obtain a control signal at the time of starting a motor in digital control.

[0007]

SUMMARY OF THE INVENTION The present invention provides a position detecting sensor for detecting a rotor position, a logic circuit for forming a first drive control signal in response to an output of the position detecting sensor, and an output of the rotor position detecting sensor. And a signal forming circuit that forms a second drive control signal based on the count result, and the first and second drive control signals are input, and one of them is selected and output. A first drive control signal is selected when the motor is started, and a second drive control signal is selected after the motor starts rotating.

As described above, at the time of startup, the first drive control signal by the analog circuit based on the output of the rotational position detection sensor is obtained, so that appropriate startup can be performed, and thereafter, the digital second drive control signal based on the count. Thus, appropriate rotation control can be performed.

It is preferable that the selection circuit selects the first drive control signal until the rotation speed reaches a predetermined rotation speed after the motor is started. By switching the drive control signal after the rotation speed has increased to a predetermined rotation speed (for example, 100 rpm), occurrence of reverse rotation or the like can be reliably prevented.

Further, it is preferable that a signal obtained by adding an overlap waveform to the first drive control signal after the start up to the predetermined number of revolutions is used.
Thus, noise can be suppressed even at a low rotation speed.

Preferably, the overlap waveform is formed by adding the first drive control signal delayed according to the overlap period to the first drive control signal that is not delayed.

When the motor drive command is 0 while the motor is being driven by the second drive control signal and the number of rotations of the motor is equal to or less than the predetermined number of rotations, the first drive is performed. Preferably, a control signal is selected. This makes it possible to reliably switch the drive control signal.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the overall configuration of a circuit according to the embodiment. FIG. 2 shows the waveform of each signal. In three Hall sensors (not shown), three pairs of sensor signals S
AH, SAL, SBH, SBL, SCH, and SCL are obtained. These sensor signals are all H level signals during the 180 ° period and L level signals during the other 180 ° period. Such a signal is obtained by converting the output of a Hall sensor having a substantially sine curve into an H level or an L level by a comparator. Then, the sensor signals SAH and S
AL, SBH and SBL, SCH and SCL have opposite phases, and A, B, and C indicate each phase of three-phase alternating current.
Each phase is shifted by 120 °.

The sensor signals SAH, SAL, SBH,
The SBL, SCH, and SCL are supplied to the combinational circuit 10. The combination circuit 10 includes six AND gates 10a to 10f as shown in FIG. And
AND gates 10a to 10f are SAH and SB, respectively.
L, SBH and SCL, SCH and SAL, SAL and SB
H, AND between SBL and SCH, SCL and SAH. As a result, six control signals ATS, BTS,
CTS, ABS, BBS, CBS are obtained. These control signals are supplied to the switch circuit 12.

Further, the sensor signals SAH, SAL, SB
H, SBL, SCH, and SCL correspond to the control signal generation circuit 14.
Also supplied. The control signal generation circuit 14 generates the sensor signals SAH, SAL, SBH, SBL, SCH, SCL
Is detected, a predetermined number is counted by a counter from the rise, and the control signals ATO, BT
O, CTO, ABO, BBO, CBO are formed. The count value (H level period) of this counter is set to a value determined in advance by the number of rotations of the motor.

Further, the control signal generation circuit 14 adds an advance period before the H-level period of the control signal to be formed and an overlap period after the H-level period, and outputs this as a control signal.

In FIG. 2, control signals ATS, BTS, CTS, AB obtained in combinational circuit 10 are shown.
S, BBS, CBS, and control signals ATO, BTO, CTO, ABO, BB obtained in the control signal generation circuit 14.
O and CBO are shown as being the same for convenience.

Further, the sensor signals SAH, SAL, SB
H, SBL, SCH, and SCL are also supplied to the detection circuit 16 three times. The three-time detection circuit 16 outputs the sensor signal SA
When the rising edges of H, SAL, SBH, SBL, SCH, and SCL are detected three times, an H level is output. The output of the three-time detection circuit 16 is supplied to the set input S of the flip-flop 18. This flip-flop 18
Is set to an H level by an H level input to a set input S, and is reset to an L level by an H level input to a reset input R. A PWM command is input to a reset input R of the flip-flop 18 as a motor output determination signal. This PWM command becomes H level when the output torque command is 0. Therefore, the flip-flop 18
Are detected by the detection circuit 16 three times.
L, SBH, SBL, SCH, SCL rise is 3
Times, the signal becomes H level and the PWM command becomes 0
It becomes L level when it becomes.

The PWM command is a signal about the duty ratio of the PWM signal corresponding to the motor driving torque. The PWM driving of the switching transistor on the sink side of the inverter is controlled by the PWM signal to control the motor drive current. In the present embodiment,
When the PWM command is 0, it is regarded as a stop state and the flip-flop 18 is reset. In addition, the flip-flop 18 is activated by a power-on reset signal when the power is turned on.
It is also preferable to reset.

The output of the flip-flop 18 is supplied to the switch circuit 12 as a mode switching signal. When the mode switching signal is L, the switch circuit 12 selects the control signal from the combinational circuit 10 and switches the mode. Signal is H
At this time, the control signal from the control signal generation circuit 14 is selected.

Accordingly, when the motor is started, the control signals ATS, BTS, CTS, AB
S, BBS, CBS are selected, the motor starts to rotate,
The control signals ATO, BTO, and CTO of the control signal generation circuit 14 start from when the sensor signal changes and the rise starts to be detected.
TO, ABO, BBO, and CBO will be selected.

The output of the switch circuit 12 is
0 is supplied. As shown in FIG. 4, the inverter 20 includes source-side transistors QAH, QBH, and QCH each having one end connected to a power supply line, and a sink-side transistor QAL disposed between the other end of these source-side transistors and ground. , QBL and QCL. Then, the above-described control signals AT, BT, CT, AB, BB, and CB are input to respective control terminals. The connection points A, B, and C between the source-side transistor and the sink-side transistor are connected to the end of each phase stator coil of the motor 22 to which the other end is commonly connected.

Accordingly, a current flows through the corresponding coil of the motor 22 via the switching transistor of the inverter 20 which is turned on. Then, the PWM control of the sink-side transistor is performed based on the torque command during the ON period in the drawing, so that the output torque of the motor is controlled.

As described above, according to the present embodiment, the combination circuit 10 of the switch circuit 12 is
Or the control signal from the control signal generation circuit 14 is used. And
The switch circuit 12 selects the combinational circuit 10 at the time of activation, and selects the control signal generation circuit 14 after the activation. Therefore, at the time of startup when the motor 22 is not rotating, the motor 2 is controlled by the control signal output from the combinational circuit 10.
2 can be rotated. This is because the signal from the Hall sensor is determined by the state of the rotor at that time, so that a magnetic field for rotating the rotor of the motor 22 can be generated by generating a control signal corresponding to the rotor position. . Then, once the rotation has begun, the control signal generation circuit 14 can count by an internal counter based on the rise of the sensor signal of the Hall sensor to form a control signal.

Since the control signal generation circuit 14 generates the control signal based on the count by the counter, the H level period of the control signal can be easily changed by setting the count value. Therefore, in this control signal generation circuit, a predetermined advance period and an overlap period are added to the control signal, so that the motor 22 can be appropriately driven.

[Second Embodiment] In the first embodiment, the sensor signals SAH, SAL, SBH, SBL,
When three rising edges of SCH and SCL are detected, the control signal is switched to the control signal from the control signal generation circuit 14. However, normal rotation is not always guaranteed by three rises. For example, if the motor 22 rotates reversely after stopping, the motor 22 may still be rotating reversely upon detection of three startups after startup. In this state, when the motor 22 is driven by the control signal based on the rising edge of the sensor signal in the normal mode, the motor 22 may be driven to rotate in the reverse direction. In the present embodiment, the occurrence of reverse rotation is prevented.

FIG. 5 shows the configuration of the second embodiment. Control signals ATS, BTS, CT output from combinational circuit 10
S, ABS, BBS, CBS are selected by a selection circuit (sel) 3
0a to 30f. Also, the control signals ATS, B
TS, CTS, ABS, BBS, and CBS are also supplied to flip-flops 32a to 32f. Overlap rising signals are input to clock input terminals of the flip-flops 32a to 32f. This overlap rising signal is generated by the sensor signals SAH, SAL, S
A signal created from BH, SBL, SCH, SCL,
These signals rise every 30 degrees of the phase of these signals.
Therefore, the outputs of the flip-flops 32a to 32f output control signals ATS, BTS, CTS, and AB according to the rising timing of the overlap rising signal.
A signal in which the rise and fall of S, BBS, and CBS are delayed is obtained.

Outputs of the flip-flops 32a to 32f are input to OR circuits 34a to 34f. The other ends of the OR circuits 34a to 34f have control signals ATS, BT
S, CTS, ABS, BBS, CBS are input. Therefore, the outputs of the OR circuits 34a to 34f include:
The rising edge is a control signal ATS, BTS, CTS, AB
A signal defined by S, BBS, and CBS and whose fall is defined by a delayed signal from flip-flops 32a to 32f is output. That is, the signals to which the overlap periods are given are output from the OR circuits 34a to 34f.

The outputs of the OR circuits 34a to 34f are input to the selection circuits 30a to 30f. The selection circuits 30a to 30a
30f includes control signals ATS, BTS, CTS, AB
S, BBS, and CBS are also input, and one of these input signals is selected three times by the output of the detection circuit 16. That is, from the selection circuits 30a to 30f,
The control signals ATS, BTS, CTS, ABS, BBS, CBS are output as they are from the start up to three rises of the sensor signal, and thereafter the control signals ATS, BTS, C
Outputs of the OR circuits 34a to 34f in which overlap periods are added to TS, ABS, BBS, and CBS are output.

The outputs of the selection circuits 30a to 30f are input to the selection circuits 36a to 36f. This selection circuit 36a-
36f, control signals ATO, BTO, CTO, ABO, BBO, CBO output from the control signal generation circuit 14
Are also supplied, and either one of them is selectively output. The selection circuits 36a to 36f are supplied with a mode switching signal from the flip-flop 38, and the selection of the selection circuits 36a to 36f is controlled by the mode switching signal.

The flip-flop 38 is connected to the AND gate 24.
, And is reset by the output signal of the NOR gate 26. The NOR gate 26 has a PWM signal of 0
An output determination signal (PWM = 0) which becomes L level at the time of
A 100 rpm signal which becomes H level when the motor rotation speed is 100 rpm or more is supplied, and an AND gate 24 is supplied with an output determination signal and a signal of a rising edge of the 100 rpm signal from L level to H level. In addition,
The rising edge from the L level to the H level of the 100 rpm signal is extracted by the edge extracting circuit 28, and the signal of the rising edge is supplied to the AND gate 24.

The AND gate 24 outputs a rising edge when the 100 rpm signal rises from L to H while the output determination signal is at H level. The NOR gate 26 is high only when both the output determination signal and the 100 rpm signal are low.
Is output. Therefore, the flip-flop 38 is reset only when the output signal is at the L level and the rotational speed is 100 rpm or less, the mode switching signal which is the output signal of the flip-flop 38 is at the L level, and the output determination signal is at the H level. The mode switching signal is set to H only when the rotation speed is changed to 100 rpm or more.
Even if the output determination signal is L, the output becomes H level when the rotation speed is 100 rpm or more. 1 for the mode switching signal
The reason that the 00 rpm signal is not used as it is is that the rotation speed is 1
This is because a hysteresis is provided so that the mode is not frequently switched around 00 rpm.

When the mode switching signal output from the flip-flop 38 is L, the activation mode is set, and the selection circuits 36a to 36f select the outputs of the selection circuits 34a to 34f. In the normal mode, the selection circuits 36a to 36f
ATO, BTO, CTO, ABO, BB
Select O and CBO.

Thus, the starting sensor signal SA
Up to three risings of H, SAL, SBH, SBL, SCH, SCL, the control signals ATS, BTS, CTS, A
BS, BBS, CBS are output as they are, and then 10
Up to 0 rpm, the control signals ATS, BTS, CTS, A
A signal in which an overlap period is added to BS, BBS, and CBS is output, and when the normal mode is set, ATO, BTO, and CT output from the control signal generation circuit 14 are output.
O, ABO, BBO, and CBO are output.

As described above, since the control signal is generated according to the output of the Hall sensor up to 100 rpm, the motor drive current according to the rotor position flows, and there is no possibility of reverse rotation. Further, even when controlled by a signal from the Hall sensor, an overlap period is added, so that appropriate driving can be performed without noise.

Further, when the output determination signal is L (PWM = 0)
The motor speed is 100 rpm
If not, the mode does not shift to the start mode.
Therefore, it is possible to prevent the mode from being left in the start mode.

That is, if the 100 rpm signal is H (100
(rpm or more), the mode shifts to the normal mode, and when the output determination signal shifts to L (PWM = 0), the mode shifts to the start mode. When the signal becomes L (PWM = 0) and the operation mode becomes the start mode, as shown in FIG. 6, when the output determination signal subsequently becomes H, the 100 rpm signal remains H because the 100 rpm signal remains H and the rising edge is not changed. Because there is no, it remains in the start mode as it is. Therefore, the motor drive control in the normal mode based on the digital processing from the control signal generation circuit 14 cannot be performed.

In the present embodiment, it is possible to prevent such a problem from occurring. That is, in the normal operation of FIG. 7A, when PWM = 0 is detected at 100 rpm or less in FIG. 7B, the PWM is detected at 100 rpm or less in FIG.
= 0 is not detected, 100 rpm in FIG.
In any of the above cases where PWM = 0 is detected,
Appropriate mode switching is performed, and it is possible to prevent a problem that the startup mode is fixed as shown in FIG.

[Rotation Number Detecting Circuit] FIG. 9 shows a configuration in which the amount of advance and the amount of overlap are calculated from the number of rotations of the motor and supplied to the control signal generation circuit 14.

Sensor signals SAH, SAL, SBH, SBL, SC obtained by detecting the position of the rotor by the Hall sensor
Any one signal of H, SCL (described as SA, SA, SB) (in this case, one of the sensor signals SAH or SAL) is input to the rotation speed detecting unit 40. The rotation speed detection section 40 detects the rotation speed by counting the sensor signal AH. Then, this rotation speed detecting unit 4
The rotation speed detected by 0 is supplied to the advance ROM 42 and the overlap ROM 44. These advance ROM4
The advance angle amount and the overlap amount according to the rotation speed are stored in advance in the second and overlap ROMs 44. Then, the advance angle amount data and the overlap data are output from the advance ROM 42 and the overlap ROM 44 and supplied to the control signal generation circuit 14.
Therefore, the control signal generation circuit 14 controls the count based on the rising edge of the sensor signal from the Hall sensor in accordance with the supplied advance amount data and overlap amount data to control the control signals ATO, BTO, and CTO. , AB
O, BBO, and CBO (described as AO, BO, and CO) are generated and output.

As described above, the advance amount and the overlap amount corresponding to the rotational speed are stored in the ROM, so that the advance amount data and the overlap amount data can be easily calculated according to the measured rotational speed. be able to.

Here, as a method of detecting the number of revolutions in the revolution number detecting section 40, there is a method of counting one cycle from the rising edge of the sensor signal of the Hall sensor to the next rising edge with a clock, and this is the most practical method. Is a typical way.

The configuration of the rotation speed detecting section 40 will be described with reference to FIG. FIG. 11 shows the relationship between the rotation speed and the count value in this case. In the case of the present embodiment, as described above, the mode is switched when the speed becomes 100 rpm or more. Therefore, it is necessary to detect 100 rpm. At 100 rpm, one rotation corresponds to 600 msec. In the present embodiment, 102.
A clock of 4 μsec and a sensor signal (for example, SAH) are input to a 14-bit counter 40a, and one rotation (one cycle)
Count. Here, the count value at 100 rpm is 5860, and counting can be performed with a 13-bit counter, but in the present embodiment, counting is performed using a 14-bit counter 40a that is a 14-bit counter. Therefore, the detection circuit 48 at 100 rpm or more determines 100 rpm from the count value of the 14-bit counter 40a.

On the other hand, the advance amount is 1800 rpm
It changes within the range of ７7000 rpm according to the number of rotations.
This means that one rotation is 33.33 msec to 8.57 msec.
Changing the amount of advance angle corresponds to the case where it is between c.
On the other hand, outside these ranges, it is fixed. Therefore, the input to the advance angle ROM 42 may be a rotation speed within this range.

This 33.33 msec to 5.57 msec
c is a count value of 326 to 84. Therefore, it is sufficient that the range of the count value 242 is known, and 8 bits are sufficient. Therefore, n (for example, 7
9) is subtracted. Thereby, the advance ROM 4 is set according to the value of the subtraction result represented by 8 bits within the range of 5 to 247.
2 outputs the corresponding advance angle data.

Further, regarding the amount of overlap, 1
It changes within the range of 125 rpm to 1800 rpm according to the number of revolutions. This means that one rotation is 53.33 msec-3.
This corresponds to changing the overlap amount when it is within 3.33 msec. On the other hand, outside these ranges,
To be constant. Therefore, the input to the overlap ROM 44 may be a rotation speed within this range.

This 53.33 ms to 33.33 ms
ec is a count value of 512 to 326. Therefore,
It is only necessary to know the range of the count value 195, and 8 bits are sufficient. Therefore, m (for example, in the -m adder 40c)
296) is subtracted. As a result, the corresponding overlap amount is output from the overlap ROM 44 according to the value within the range of 30 to 225 of the subtraction result represented by 8 bits.

As described above, using the output of the 14-bit counter 40a, 100 rpm, 1125 rpm, 180 rpm
0 rpm and 7000 rpm are detected. In particular, the advance angle RO
The input to the M42 and the overlap ROM 44 may be 8 bits, and the capacity of the ROM may correspond to the address of 8 bits. It is sufficient that the advance angle and the overlap amount are 8 bits, and the outputs of the advance ROM 42 and the overlap ROM 44 are also 8 bits.

Further, as shown in FIG. 12, an advance minimum value detection circuit (MIN) 40d and an advance maximum value detection circuit (M
AX) 40e, overlap minimum value detection circuit (MI
N) 40f, maximum value detection circuit for overlap (MA
X) It is preferable to provide 40 g and control the limiters 40 h and 40 i based on these detection results.

That is, when the advance angle minimum value detection circuit 40d detects that the count value is 82 or less, the limiter 40h
To output 00. Thereby, the advance ROM 42
In the case where the count value is equal to or less than 82, the address 00 is accessed. Therefore, a fixed advance amount may be stored at the address 00. On the other hand, the lead angle maximum value detection circuit 4
When 0e detects that the count value is 326 or more, the limiter 40h outputs FF. Thus, the lead angle R
The OM 42 accesses the address FF when the count value is 326 or more. Therefore, a fixed advance amount may be stored in the address FF.

Further, when the overlap minimum value detection circuit 40f detects the count value of 326 or less, 00 is output by the limiter 40i. Thus, the address 00 is accessed in the overlap ROM 44 when the count value is equal to or less than the count value 326. Therefore, a fixed advance amount may be stored at the address 00. on the other hand,
When the overlap maximum value detection circuit 40g detects the count value of 541 or more, the limiter 40i outputs the FF.
Is output. Thereby, the overlap ROM 44
In the case where the count value is 541 or more, the address FF is accessed. Therefore, a fixed overlap amount may be stored in the address FF.

FIGS. 13 and 14 show specific values (theoretical values) of the advance angle and the overlap amount. The advance ROM 42 and the overlap ROM 44 store values corresponding to the graph. Note that the advance amount changes even at 7000 rpm or more, but in the case of the motor of the present embodiment, 7000 rpm
There is no operation at a rotation speed of m or more, and a value corresponding to 7000 rpm or more is unnecessary.

"Calculation of Advance Angle" In this embodiment, the output signal is obtained from the rising edge of the sensor signal of the Hall sensor. On the other hand, the advance amount needs to be added before the detected rising.

Here, the rising of the output signal AT rises at the fall of the sensor input signal SBH unless the advance is made, but when the advance control is performed, it rises by the advance amount. Therefore, the AT may be started at a timing delayed by (Tr / 12−Tf) with reference to the rising of the sensor detection output signal 30 ° before that. Here, Tr = 1 cycle, and Tf = advance angle amount.

As shown in FIG. 15, one of the sensor signals of the sensor is input to the 1 / 12-pulse generating circuit 60 as a reset signal. The 1/12 pulse generating circuit 60 generates 1/12 pulses rising every 12 periods from the first clock (for example, a clock having a period of 6.4 μsec). The 1/12 pulse is supplied to the first counter 6
2 is input. One of the sensor signals is input to the first counter 62, and the sensor signal is counted using a 1/12 pulse as a clock. Count result is Tr / 1
This Tr / 12 is supplied to the subtraction circuit 64. The subtraction circuit 64 is supplied with advance angle data Tf. Therefore, the output of the subtraction circuit 64 includes (T
r / 12-Tf) is obtained.

On the other hand, the rising pulses of the six sensor signals are supplied to the OR circuit 66. Therefore, a pulse is generated from the OR circuit 66 every 30 degrees. This 30
The pulses every ° are supplied to the second counter 68 as reset pulses. The second counter 68 counts up during a 30 ° period in order to count the first clock.

The (Tr / 12) signal from the subtraction circuit 64
−Tf) and the count result from the second counter 68 are
The data is input to the comparator 70 and compared. The comparator 70 outputs a pulse signal that rises when they match.

The second clock, which is a clock having a cycle twice as long as the first clock, is input to the third counter 72, where it is counted. The output of the comparator 70 is supplied to the third counter 72 as a reset signal. Therefore, the third counter 72 starts counting from the rise of the control signal of a certain phase in which the advance amount is set. The output of the third counter 72 is input to the comparator 74, where it is compared with the overlap amount TO.
Therefore, a signal (output 2) that rises when a time corresponding to the overlap amount has elapsed from the rise of the control signal is obtained at the output of the comparator 74.

That is, as shown in FIG. 16, from the fall of one sensor signal (AH), (Tr / 12-T
When the period f) elapses, the control signal is raised by the output of the comparator 70, whereby the rise of the control signal of one phase (AB) in which the advance amount Tf is set is obtained.
The overlap amount can be set by determining the fall of the control signal (BB) of the other phase when the overlap amount TO has elapsed from the rise of B.

FIG. 17 shows this state. Thus, A
The rise of AB is determined from the fall of H, and the fall of BB is determined from the rise of AB.
The rise of BB and the fall of CB are determined from the fall of BH.

In this way, a control signal is created in consideration of the amount of advance and the amount of overlap.

Here, the sensor signal is generated based on the rotation of the motor, and may vary. Thereby, the output of the second counter 68 and the subtraction circuit 6
It is also conceivable that the next rise of the sensor signal occurs before the outputs of 4 match. In such a case, the second counter 68 is reset by the next rising edge of the sensor signal, and the comparator 70 does not output a coincidence pulse. Therefore, as shown in FIG. 18, the output control signal does not rise and the third counter 72 is not reset, so that the corresponding control signal does not fall. When such a state occurs, the rotation of the motor becomes unstable.

Therefore, in this embodiment, as shown in FIG. 19, the output of the comparator 70 is output via the OR circuit 80. On the other hand, a 6-input rising pulse which is a reset pulse of the second counter 68 is input to the OR circuit via the gate circuit 82. The gate circuit 82 inhibits the output when the output of the comparator 70 is H, and permits the output when the output is L. The output of the comparator 70 becomes H when the count value of the second counter 68 coincides with the delay amount, and becomes H until the second counter 68 is reset.

Therefore, when a coincidence signal is output from the comparator 70 as usual, it is output from the OR circuit 80, and the output 1 rises.

On the other hand, if the second counter 68 is reset before the match signal is output from the comparator 70, the reset signal is output to the gate circuit 82 and the OR circuit 8
Output via 0.

Therefore, as shown in FIG. 20, the output 1 rises by the reset signal. Further, the third counter 72 is reset by the output from the OR circuit 80, so that the output 2 also falls. Thus, it is possible to prevent the control signal from changing in accordance with the rotation of the motor, and thereby making the rotation unstable.

The above-mentioned outputs 1 and 2 are signals indicating the transition points of the six signals of all phases. These signals are combined with the signals of each phase to obtain six signals having different timings. Thus, six necessary control signals can be obtained. In order to obtain the six control signals, the control signals of the respective phases are obtained from the outputs 1 and 2 for the advance angle control and the overlap control and the rising signal of each phase from the Hall sensor. Just do it.

[0069]

As described above, according to the present invention,
At startup, based on the output of the rotational position detection sensor,
In order to obtain the first drive control signal by the analog circuit, appropriate start-up can be performed, and then appropriate rotation control can be performed by the digital second drive control signal based on the count.

Further, a predetermined rotation speed (for example, 100 rpm)
By switching the drive control signal after the rotation speed has increased until m), the occurrence of reverse rotation and the like can be reliably prevented.

Also, after starting, by using a signal obtained by adding an overlap waveform to the first drive until the predetermined rotation speed is reached, the generation of noise is suppressed even at a low rotation speed. be able to.

When the motor drive command is 0 while the motor is being driven by the second drive control signal and the motor speed is equal to or less than the predetermined speed, the first drive control is executed. By selecting the signal, switching of the drive control signal can be reliably performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment.

FIG. 2 is a diagram showing signal waveforms at various points.

FIG. 3 is a diagram illustrating a configuration of a combinational circuit.

FIG. 4 is a diagram showing a configuration of an inverter.

FIG. 5 is a diagram illustrating a configuration of a control signal generation circuit.

FIG. 6 is a diagram showing a mode change operation at the time of an abnormal operation.

FIG. 7 is a diagram showing a mode change operation during a normal operation.

FIG. 8 is a diagram showing a mode change operation during a normal operation.

FIG. 9 is a diagram showing a configuration for outputting an advance amount and an overlap amount.

FIG. 10 is a diagram illustrating a configuration of a rotation speed detection unit.

FIG. 11 is a diagram showing a relationship between a rotation speed and a count value.

FIG. 12 is a diagram illustrating another configuration of the rotation speed detection unit.

FIG. 13 is a diagram showing the relationship between the number of revolutions and the amount of advance.

FIG. 14 is a diagram showing the relationship between the number of rotations and the amount of overlap.

FIG. 15 is a diagram illustrating a configuration of a control signal generation circuit.

FIG. 16 is a diagram illustrating calculation of an advance angle amount.

FIG. 17 is a diagram illustrating addition of an advance amount and an overlap amount.

FIG. 18 is a diagram illustrating an operation of generating a control signal.

FIG. 19 is a diagram showing a configuration for generating a control signal.

FIG. 20 is a diagram illustrating an operation of generating a control signal.

[Explanation of symbols]

10 combination circuit, 12 switch circuit, 14 control signal generation circuit, 163 detection circuit, 18 flip-flop, 20 inverter, 22 motor.

Continued on the front page (72) Inventor Hirotaka Morita 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) in Sanyo Electric Co., Ltd. 5H560 BB04 BB07 BB12 DA02 DA19 DC02 EB01 GG04 TT02 TT04 TT07 TT12 UA02 XA15 XB01 XB04

Claims (5)

[Claims] A position detection sensor that detects a rotor position; a logic circuit that forms a first drive control signal in accordance with an output of the position detection sensor; A signal forming circuit that counts and forms a second drive control signal based on the count result; a selection circuit that receives the first and second drive control signals and selects and outputs one of the first and second drive control signals; A motor drive control circuit that selects the first drive control signal when the motor starts, and selects the second drive control signal after the motor starts rotating. 2. The motor drive control circuit according to claim 1, wherein the selection circuit selects a first drive control signal until the rotation speed reaches a predetermined rotation speed after the motor is started by the selection circuit. 3. The motor drive control according to claim 2, wherein, after starting, a signal obtained by adding an overlap waveform to the first drive control signal until the predetermined rotational speed is reached. circuit. 4. The circuit according to claim 2, wherein the overlap waveform is formed by adding the first drive control signal delayed according to the overlap period to the undelayed first drive control signal. Motor drive control circuit. 5. The circuit according to claim 2, wherein when the motor is driven by the second drive control signal, a motor drive command is 0 and the number of rotations of the motor is reduced. A motor drive control circuit for selecting a first drive control signal when the number of revolutions falls below a predetermined number of revolutions;