JP2002237528A - Semiconductor device, memory system and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high-speed SRAM and whose power consumption can be lowered. SOLUTION: The memory cell of the SRAM has a structure, in which five conductive layers are provided in the upper part of a field. Subword lines 23a, 23b in the first-layer conductive layer are situated, so as to be separated from an active region 13 as the field viewed from a plane. The active region 13 does not extend to the lower part of the subword lines 23a, 23b. Since the overlapping part of the active region 13 with the subword line 23a (or 23b) is not generated, stray capacitance caused by the overlap part can be eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a semiconductor device such as a (static random access memory), a memory system including the same, and an electronic device.

[0002]

2. Description of the Related Art An SRAM, which is a kind of a semiconductor memory device, has a feature that a refresh operation is not required, so that a system can be simplified and power consumption is low. For this reason, the SRAM is suitably used as a memory of an electronic device such as a mobile phone.

There is a demand for high speed and low current consumption of electronic devices.

An object of the present invention is to provide a semiconductor device capable of high speed and low current consumption, a memory system including the same, and an electronic apparatus.

[0005]

(1) A semiconductor device according to the present invention comprises a first load transistor, a second load transistor, a first drive transistor, a second drive transistor,
A semiconductor device including a memory cell including a first transfer transistor and a second transfer transistor, wherein the first active region extends in a first direction and in which the first and second load transistors are formed; A second active region extending in a first direction and in which the first and second drive transistors and the first and second transfer transistors are formed; and a second active region extending in a second direction and Located above the first and second active regions, and spaced apart from the first active region in a plan view, and intersected with the second active region in a planar view; and A first word line including a gate electrode of the first transfer transistor, a first word line extending in a second direction, and located above the first and second active regions; It is located away from the plane And positioned so as to intersect when viewed in the manner second active region and a plane, and comprises a gate electrode of the second transfer transistor comprises a second word line, a.

Here, the “active region” refers to an element forming region defined by an element isolation region.
It includes a region where the impurity diffusion layer is formed and a region where the channel below the gate electrode is formed.

According to the first and second word lines of the present invention,
It is located apart from the active region in plan view. That is, the first
The active region does not extend below the first and second word lines. Therefore, according to the present invention, since the overlapping portion between the first (second) word line and the first active region is not formed,
The stray capacitance due to the overlapping portion can be eliminated. Therefore, according to the present invention, the semiconductor device can be operated at high speed and with low current consumption.

(2) The semiconductor device according to the present invention can be configured as follows.

Extending in the second direction, located on the same layer as the first and second word lines, and intersecting the first and second active regions in a plan view; A first word line that is located between the first word line and the second word line in a plan view and includes a gate electrode of the first load transistor and a gate electrode of the first drive transistor;
A gate-gate electrode layer extending in the second direction, located in the same layer as the first and second word lines, and intersecting the first and second active regions in plan view; And a gate electrode of the second drive transistor and the second load transistor, which is located between the first word line and the second word line when viewed in a plan view and includes a gate electrode of the second load transistor and the second drive transistor. A gate-gate electrode layer.

(3) The semiconductor device according to the present invention can be configured as follows.

The first active region includes the first and second regions.
Extension has stopped before the word line.

As a result, the first and second word lines are
The first active region is separated from the first active region in a plan view.

(4) The semiconductor device according to the present invention can be configured as follows.

The first load transistor extends in a second direction, is located above the first and second gate-gate electrode layers and the first and second word lines, and is connected to the drain of the first load transistor. A first drain-drain connection layer for connecting the drain of the first drive transistor, and a second direction extending in the second direction, and an upper layer of the first and second gate-gate electrode layers and the first and second word lines; And connecting the drain of the second load transistor and the drain of the second drive transistor.
A drain-drain connection layer, the drain-drain connection layer being located above the first and second drain-drain connection layers;
A first drain-gate connection layer, which connects the drain-drain connection layer and the second gate-gate electrode layer, and which is located above the first and second drain-drain connection layers; A second drain-gate connection layer that connects the drain-drain connection layer and the first gate-gate electrode layer.

A predetermined connection is made to the first load transistor, the second load transistor, the first drive transistor, and the second drive transistor, thereby forming a flip-flop. According to the present invention, a flip-flop is formed using three conductive layers (gate-gate electrode layer, drain-drain connection layer, and drain-gate connection layer). Therefore, the pattern of each layer is simplified (for example, compared to the case where a flip-flop is formed using two conductive layers) (for example,
A substantially linear pattern). As described above, according to the present invention, since the pattern of each layer can be simplified, for example, a fine semiconductor device having a memory cell size of 2.5 μm ² or less can be obtained.

(5) The semiconductor device according to the present invention can be configured as follows.

A power supply line extending in a first direction and located in the same layer as the first and second drain-drain connection layers; and a power supply line extending in a second direction and extending in the second direction.
And a second drain-gate connection layer,
Ground line, main word line, BL local wiring layer, and / BL
A local wiring layer, a bit line extending in a first direction and located above the ground line, the main word line, the BL local wiring layer, and the / BL local wiring layer, and / or A bit line.

According to the present invention, a power supply line, a ground line, a main word line, a bit line, and a / bit line can be arranged in a well-balanced manner. Note that the BL local wiring layer is used for connecting the bit line to the first transfer transistor, and the / BL
The local wiring layer is used for connection between the / bit line and the second transfer transistor.

(6) The semiconductor device according to the present invention can be configured as follows.

The first and second active regions, the first and second gate-gate electrode layers, and the first and second word lines have a substantially linear pattern.

These elements constitute a bulk layer. According to the present invention, since these elements have a substantially linear pattern, that is, a simple pattern, the bulk layer can be miniaturized.

(7) The semiconductor device according to the present invention can be configured as follows.

The size of the memory cell is 2.5 μm ²
It is as follows.

(8) The memory system according to the present invention comprises:
The semiconductor device according to any one of the above (1) to (7) is provided.

(9) An electronic device according to the present invention includes the semiconductor device according to any one of (1) to (7).

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described. In the present embodiment, the semiconductor device according to the present invention is represented by S
This is applied to a RAM. First, an outline of the structure of the SRAM according to the present embodiment will be described, and then details of the structure will be described.

[Schematic of SRAM Structure] FIG. 1 is an equivalent circuit diagram of the SRAM according to the present embodiment. The SRAM according to the present embodiment is of a type in which one memory cell is configured by six MOS field effect transistors. That is, the n-channel type driving transistor Q ₃ and p
In the load transistor Q ₅ of channel, one CMO
An S inverter is configured. Further, in the load transistor Q ₆ of the driving transistor Q ₄ and the p-channel n-channel type, a CMOS inverter is formed. A flip-flop is formed by cross-coupling these two CMOS inverters. One memory cell is constituted by the flip-flop and the n-channel transfer transistors Q ₁ and Q ₂ .

As shown in FIGS. 2 to 7, the SRAM memory cell according to the present embodiment has a structure having five conductive layers above a field. Hereinafter, FIGS. 2 to 7 will be briefly described with reference to FIG. Note that the symbol R in these figures indicates a region where one memory cell is formed.

FIG. 2 is a plan view showing a field.
Active regions 11 and 13 having a pattern extending substantially linearly in the Y direction are included. FIG. 3 is a plan view showing the first conductive layer, in which gate-gate electrode layers 21a and 21b and a sub-word line 23 having a pattern extending substantially linearly in the X direction.
a and 23b. Gate - a gate electrode layer 21a includes a gate electrode of the driving transistor Q ₃ and the load transistor Q _5, the gate - a gate electrode layer 21b includes a gate electrode of the driving transistor Q ₄ and the load transistor Q _6, the sub-word line 23a includes the gate electrode of the transfer transistor Q _1, the sub-word line 23b includes a gate electrode of the transfer transistor Q _2. FIG. 4 is a plan view showing the second conductive layer, in which a drain-drain connection layer 31a having a pattern extending substantially linearly in the X direction, a drain-drain connection layer 31b having an L-shaped pattern, and a Y direction _VDD wiring 33 having a pattern extending in a substantially straight line
And so on. FIG. 5 is a plan view showing a third conductive layer.
Drain-gate connection layer 41 having L-shaped pattern
a, includes a drain-gate connection layer 41b having a U-shaped pattern. FIG. 6 is a plan view showing the fourth conductive layer, and has a pattern B extending substantially linearly in the X direction.
L local wiring layer 51a, / BL local wiring layer 51b, main word line 53, and _VSS wiring 55 are included. FIG. 7 is a plan view showing the fifth conductive layer, and includes a bit line 61a and a bit line 61b having a pattern extending substantially linearly in the Y direction.

[Details of Structure of SRAM] Details of the structure of the SRAM according to the present embodiment will be described in order from the lower layer with reference to FIGS. FIG. 8 is a plan view showing a field and a first conductive layer. FIG. 9 is a plan view showing a field, a first conductive layer and a second conductive layer.
11 is a plan view showing a second conductive layer and a third conductive layer, FIG. 11 is a plan view showing a first conductive layer and a third conductive layer, and FIG. 12 is a plan view showing the second conductive layer and a third conductive layer. FIG. 13 is a plan view showing a four-layer conductive layer, and FIG.
14 is a cross-sectional view taken along line A1-A2 in FIGS. 2 to 13, and FIG. 15 is a cross-sectional view taken along line B1-B2 in FIGS. 2 to 13. is there.

{Field, First Conductive Layer} First, the field will be described. As shown in FIG. 2, the field has active regions 11, 13 and an element isolation region 19. The active regions 11 and 13 are formed on the surface of the silicon substrate.

The active region 11 has a pattern extending substantially linearly in the Y direction. The active region 11 extends to another memory cell formation region located above and below the memory cell formation region R in FIG. The active region 11 includes a formation region 11a for the driving transistors Q ₃ and Q ₄ and a formation region 11b for the transfer transistors Q ₁ and Q ₂ . The length of the active region 11 in the Y direction is, for example, 1.6 to 2.0 μm,
The length of the formation region 11a in the X direction is, for example, 0.22 to
The length in the X direction of the formation region 11b is, for example, 0.16 to 0.20 μm.

The active region 13 has a pattern extending substantially linearly in the Y direction, and is formed with an interval from the active region 11. Both ends of the active region 13 stop extending in the memory cell formation region R. The active region 13, the load transistor Q _5, Q ₆ is formed. The length of the active region 13 in the Y direction is, for example, 0.8 to 1.0 μm,
The length in the X direction is, for example, 0.16 to 0.20 μm.

The active region 11 and the active region 13 are separated from each other by an element isolation region 19 (depth, for example, 0.35 to 0.45 μm).
Are separated from each other. The element isolation region 19 includes, for example, STI (shallow trench isolation). The length of the memory cell formation region R in the X direction is, for example, 1.0 to 1.4 μm, and the length in the Y direction is, for example, 1.6 to 2.0 μm.

A1-A2 section of the field shown in FIG.
B1-B2 cross sections are as shown in FIGS. 14 and 15, respectively. In these cross sections, a p-well 12, an n-well 14, and the like formed in a silicon substrate are shown.

Next, the first conductive layer located above the field will be described with reference to FIGS. A pair of gate-gate electrode layers 21a and 21b are arranged in a formation region R of one memory cell in parallel with each other.
The gate-gate electrode layers 21a and 21b are
It intersects 1 and 13 in a plan view. Gate - a gate electrode layer 21a constitutes the gate electrode of the driving transistor Q ₃ and the load transistor Q _5, are further connected to these gate electrodes together. Gate - a gate electrode layer 21b constitutes the gate electrode of the driving transistor Q ₄ and the load transistor Q _6, are further connected to these gate electrodes together. The gate lengths of the driving transistors Q ₃ and Q ₄ are, for example, 0.12 to 0.15 μm.
The gate lengths of the load transistors Q ₅ and Q ₆ are, for example, 0.
14 to 0.17 μm.

The sub-word lines 23a and 23b are connected to the active region 1
3 and is located away from the active region 11 in a plan view. A gate-gate electrode layer 21a between the sub-word line 23a and the sub-word line 23b;
21b is located. Sub-word line 23a becomes a gate electrode of the transfer transistor Q _1, the sub-word line 23b
Serves as a gate electrode of the transfer transistor Q _2. The gate length of the transfer transistors Q ₁ and Q ₂ is, for example, 0.14 to
0.17 μm. Note that 25 is the sub word line 23
14A shows a sidewall insulating layer disposed on the side of 23a and 23b.

The gate-gate electrode layers 21a and 21b and the sub-word lines 23a and 23b have, for example, a structure in which a silicide layer is formed on a polysilicon layer.

A1-A of the first conductive layer shown in FIGS.
14 and FIG. 15 show two cross sections and B1-B2 cross sections, respectively.
As shown in FIG. These sections include the sub word line 2
3a and the gate-gate electrode layer 21a are shown.

Next, n ⁺ -type impurity regions 15a, 15b, 15c, 15d, and 15e formed in active region 11 will be described with reference to FIG. The n ⁺ -type impurity region 15a and the n ⁺ -type impurity region 15b are located so as to sandwich the sub-word line 23a in plan view, and the gate-gate electrode layer 2
1a are sandwiched between n ⁺ -type impurity region 15b and n ⁺ -type impurity region 15c, and gate-gate electrode layer 21b
N ⁺ -type impurity region 15c and n ⁺ -type impurity region 15d are positioned so as to sandwich the sub word line 23b.
An n ⁺ -type impurity region 15d and an n ⁺ -type impurity region 15e are located.

N⁺The type impurity region 15a has a transfer transistor.
Star Q₁Source or drain. n⁺Type impurity area
The area 15b includes the transfer transistor Q₁Sauce or dressing
In, drive transistor Q_ThreeDrain. n⁺Typeless
The pure region 15c is the driving transistor Q_Three, Q_FourCommon
Become a source. n⁺The type impurity region 15d is
Jista Q_FourDrain, transfer transistor Q_TwoThe source
Or drain. n ⁺The type impurity region 15e is transferred
Transistor Q_TwoSource or drain.

Next, p ⁺ -type impurity regions 17a, 17b, and 17c formed in active region 13 will be described with reference to FIG. Gate-gate electrode layer 21 as viewed in plan
The p ⁺ -type impurity region 17a and the p ⁺ -type impurity region 17b are located so as to sandwich a, and the p ⁺ -type impurity region 17b and the p ⁺ -type impurity region 17c are sandwiched so as to sandwich the gate-gate electrode layer 21b. positioned. The p ⁺ -type impurity region 17a
Becomes the drain of the load transistor Q _5, p ⁺ -type impurity regions 17c becomes a drain of the load transistor Q _6,
The p ⁺ -type impurity region 17b is connected to the load transistors Q ₅ and Q ₆
A common source of As shown in FIG. 14, n ⁺ -type impurity regions 15a and 15b and p ⁺ -type impurity region 17a appear in this cross section.

As shown in FIGS. 14 and 15, an interlayer insulating layer 71 such as a silicon oxide layer is formed so as to cover the field and the first conductive layer. The interlayer insulating layer 71 has been planarized by CMP.

{Second-layer conductive layer} Regarding the second-layer conductive layer,
This will be described with reference to FIGS. The second conductive layer is located above the first conductive layer. The second conductive layer is a drain-
Drain connection layers 31a, 31b, _VDD wiring 33, BL
(Bit line) contact pad layer 35a, / BL (/ bit line) contact pad layer 35b, _VSS local wiring layer 3
7 inclusive. The second conductive layer includes a contact conductive portion 73 is a conductive part for connecting the a field second conductive layer (hereinafter, field second layer - that the contact conductive portion 73) through a field of n ⁺ -type Connected to an impurity region or ap ⁺ -type impurity region.

The drain-drain connection layers 31a and 31b are positioned between the drain-drain connection layers 31a and 31b such that the gate-gate electrode layers 21a and 21b are positioned in plan view. are doing. The drain-drain connection layer 31a includes an n ⁺ -type impurity region 15b (drain) and ap ⁺ -type impurity region 17a.
(Drain). The end 31a1 of the drain-drain connection layer 31a is a field / second layer.
-N ⁺ -type impurity region 15 through contact conductive portion 73
The end 31a2 of the drain-drain connection layer 31a is connected to the p ⁺ -type impurity region 17a (drain) via the field / second layer-contact conductive portion 73. The drain-drain connection layer 31b is located above the n ⁺ -type impurity region 15d (drain) and the p ⁺ -type impurity region 17c (drain). End 31b1 of drain-drain connection layer 31b
Is connected to the n ⁺ -type impurity region 15d (drain) via the field / second layer-contact conductive portion 73,
L-shaped corner 31b of drain-drain connection layer 31b
Reference numeral 3 is connected to the p ⁺ -type impurity region 17c (drain) via the field / second layer-contact conductive portion 73. The width of the drain-drain connection layers 31a and 31b is, for example, 0.16 to 0.20 μm.

The _VDD wiring 33 is shared by the memory cells in the formation region R and the memory cells located on the left side of FIG. The width of the _VDD wiring 33 is, for example, 0.16 to 0.20 μm. The convex portion 33a of the _VDD wiring 33 extends in the X direction and is located above the p ⁺ -type impurity region 17b (source). Convex part 3
3a is connected to the p ⁺ -type impurity region 17b via the field / second layer-contact conductive portion 73.

[0047] V _SS local wiring layer 37 is located above the n ⁺ -type impurity regions 15c (source). The _VSS local wiring layer 37 is a field / second layer-contact conductive portion 73.
Is connected to n ⁺ -type impurity region 15c.
The V _SS local wiring layer 37 functions as a wiring layer for connecting the V _SS wiring 55 (FIG. 6) and the n ⁺ -type impurity region 15c serving as the sources of the driving transistors Q ₃ and Q ₄ . V _SS
Local wiring layer 37 includes a memory cell in formation region R, and
The memory cell located on the right side in FIG.

The BL contact pad layer 35a is located above the n ⁺ type impurity region 15a. The BL contact pad layer 35a is connected to the n ⁺ -type impurity region 15a via the field / second layer-contact conductive portion 73. BL contact pad layer 35a includes a bit line 61a (FIG. 7), which functions as a pad layer to connect the n ⁺ -type impurity regions 15a serving as source and drain of the transfer transistor Q _1. The BL contact pad layer 35a is shared by the memory cells in the formation region R and the memory cells located on the upper side in FIG.

/ BL contact pad layer 35b is formed of n ⁺
It is located above the mold impurity region 15e. / BL contact pad layer 35b is connected to n ⁺ -type impurity region 15e via field / second layer-contact conductive portion 73. / BL contact pad layer 35b is
A bit line 61b (FIG. 7), which functions as a pad layer to connect the n ⁺ -type impurity region 15e serving as a source and a drain of the transfer transistor Q _2. The / BL contact pad layer 35b is shared by the memory cells in the formation region R and the memory cells located below the formation region R in FIG.

Next, regarding the cross-sectional structure of the second conductive layer,
This will be described with reference to FIG. The second conductive layer can be composed of, for example, only a nitride layer of a high melting point metal. The thickness of the second conductive layer is, for example, 100 to 200 nm.
The nitride layer of the refractory metal includes, for example, a titanium nitride layer. Further, the second conductive layer may be in the following mode. 1) It may have a structure in which a nitride layer 32 of a high melting point metal is formed on a metal layer 30 made of a high melting point metal. In this case, the metal layer 30 made of the high melting point metal is underlayed, for example, a titanium layer. Examples of the material for the metal layer of the high melting point metal include titanium and tungsten. 2) The configuration of the second conductive layer may be composed of only the metal layer of the high melting point metal.

Next, the sectional structure of the field / second layer-contact conductive portion 73 will be described with reference to FIG. A plurality of through holes 75 exposing n ⁺ -type impurity regions and p ⁺ -type impurity regions in the field are formed in the interlayer insulating layer 71. These through holes 75
, A field / second layer-contact conductive portion 73 is buried. The field / second layer-contact conductive portion 73 is formed by a plug 77 embedded in a through hole 75.
And a barrier layer 79 located on the bottom and side surfaces of the through hole 75. As a material of the plug 77,
For example, there is tungsten. The barrier layer 79 preferably includes a metal layer made of a high melting point metal and a nitride layer of the high melting point metal formed on the metal layer. As a material of the metal layer made of the high melting point metal, for example, titanium is given. As a material of the nitride layer of the refractory metal, for example, there is titanium nitride. The diameter of the upper end of the through hole 75 is, for example, 0.18 to 0.22 μm, and the diameter of the lower end is, for example, 0.14 to 0.18 μm.

As shown in FIGS. 14 and 15, an interlayer insulating layer 81 such as a silicon oxide layer is formed so as to cover the second conductive layer. The interlayer insulating layer 81 is made of CM
The flattening process is performed by P.

{Third-layer conductive layer} Regarding the third-layer conductive layer,
This will be described with reference to FIGS. 5, 10, and 11. The third conductive layer is located above the second conductive layer. The third conductive layer is
Drain-gate connection layers 41a and 41b are included. The width of the drain-gate connection layers 41a and 41b is, for example, 0.1.
16 to 0.20 μm.

The drain-gate connection layer 41a has an L-shaped pattern, and its end 41a1 is located above the end 31a1 of the drain-drain connection layer 31a (FIG. 10). End 41 of drain-gate connection layer 41a
a1 denotes a contact conductive portion 83 (hereinafter, referred to as a second layer / third layer) which is a conductive portion connecting the third conductive layer and the second conductive layer.
(Referred to as “contact conductive portion 83”) and the end 31a1 of the drain-drain connection layer 31a (FIG. 10). End 41 of drain-gate connection layer 41a
a2 is located above the center of the gate-gate electrode layer 21b (FIG. 11). Drain-gate connection layer 41a
An end portion 41a2 of the contact conductive portion 93 (hereinafter referred to as a first conductive portion) is a conductive portion that connects the third conductive layer and the first conductive layer.
Layer / third layer-contact conductive portion 93)
It is connected to the center of the gate-gate electrode layer 21b (FIG. 11).

The drain-gate connection layer 41b has a U-shape, and its end 41b1 is located above the end 31b2 of the drain-drain connection layer 31b (FIG. 1).
0). End 41b1 of drain-gate connection layer 41b
Is via the second layer / third layer-contact conductive part 83,
It is connected to the end 31b2 of the drain-drain connection layer 31b (FIG. 10). Drain-gate connection layer 41b
Is located above the central portion of the gate-gate electrode layer 21a (FIG. 11). The end 41b2 of the drain-gate connection layer 41b is connected to the gate-gate electrode layer 21a via the first layer / third layer-contact conductive portion 93.
(FIG. 11).

Next, regarding the cross-sectional structure of the third conductive layer,
This will be described with reference to FIGS. The third conductive layer can be composed of, for example, only a nitride layer of a high melting point metal. The thickness of the third conductive layer is, for example, 100 to 200 n.
m. The nitride layer of the refractory metal includes, for example, a titanium nitride layer. Further, the third conductive layer may be in the following mode. 1) It may have a structure in which a high melting point metal nitride layer 42 is formed on a high melting point metal layer 40. In this case, the metal layer 40 made of a high melting point metal is used.
Is an underlay, for example, there is a titanium layer. Examples of the material for the metal layer of the high melting point metal include titanium and tungsten. 2) The configuration of the third conductive layer may be composed of only a metal layer of a high melting point metal.

Next, a cross-sectional structure of the second-layer / third-layer contact conductive portion 83 will be described with reference to FIG. A second layer / third layer-contact conductive portion 83 is buried in a through hole 85 penetrating the interlayer insulating layer 81.
The second layer / third layer-contact conductive portion 83 includes a plug 87 embedded in the through hole 85 and a through hole 85.
And a barrier layer 89 located on the bottom surface and the side surface of the substrate. As a material of the plug 87, for example, there is tungsten. The barrier layer 89 preferably includes a metal layer made of a high melting point metal and a nitride layer of the high melting point metal formed on the metal layer. As a material of the metal layer made of the high melting point metal, for example, titanium is given. As a material of the nitride layer of the refractory metal, for example, there is titanium nitride. The diameter of the upper end of the through hole 85 is, for example, 0.18 to 0.22 μm, and the diameter of the lower end is, for example, 0.14 to 0.18 μm.

Next, the sectional structure of the first-layer / third-layer conductive section 93 will be described with reference to FIG. The first layer / third layer-contact conductive portion 93 is embedded in a through hole 95 penetrating the two interlayer insulating layers 71 and 81. In this cross section, the first layer / third layer-contact conductive portion 93 is connected to the gate-gate electrode layer 21a. First layer / third layer-contact conductive part 93
Include a plug 97 buried in the through hole 95 and a barrier layer 99 located on the bottom surface and the side surface of the through hole 95. As a material of the plug 97, for example, there is tungsten. Preferably, the barrier layer 99 includes a metal layer made of a high melting point metal and a nitride layer of the high melting point metal formed on the metal layer. As a material of the metal layer made of the high melting point metal, for example, titanium is given. As a material of the nitride layer of the refractory metal, for example, there is titanium nitride. The diameter of the upper end of the through hole 95 is, for example, 0.18 to 0.22 μm,
The diameter of the lower end is, for example, 0.14 to 0.18 μm.

As shown in FIGS. 14 and 15, an interlayer insulating layer 101 such as a silicon oxide layer is formed so as to cover the third conductive layer. The interlayer insulating layer 101
A flattening process is performed by CMP.

{Fourth conductive layer} Regarding the fourth conductive layer,
This will be described with reference to FIGS. The fourth conductive layer is a third conductive layer.
It is located above the conductive layer. The fourth conductive layer is a BL local wiring layer 5 having a pattern extending substantially linearly in the X direction.
1a, / BL local wiring layer 51b, main word line 53, V _SS
The wiring 55 is included. The main word line 53 and the _VSS wiring 55 are provided between the BL local wiring layer 51a and the / BL local wiring layer 51b.
Is located.

The V _SS wiring 55 is located above the V _SS local wiring layer 37, and is a contact conductive part 113 (hereinafter referred to as a second conductive layer) which is a conductive part connecting the fourth conductive layer and the second conductive layer.・
Via the fourth layer-contact conductive portion 113),
_It is connected to the _SS local wiring layer 37 (FIG. 12). The width of V _SS line 55 is, for example, 0.4～1.0Myuemu.

The main word line 53 is located above the drain-drain connection layer 31a. Main word line 53 activates and deactivates sub word lines 23a and 23b (FIG. 8). The width of the main word line 53 is, for example, 0.
18 to 0.24 μm. In the present embodiment, the word line has a structure including a sub-word line and a main word line, but may have a structure without a main word line.

The BL local wiring layer 51a is located above the BL contact pad layer 35a. BL local wiring layer 51
a indicates the bit line 61a (FIG. 7) and the transfer transistor Q
N ⁺ -type impurity region 15a serving as source and drain of ₁
(FIG. 8). B
The end 51a1 of the L local wiring layer 51a is a second layer / fourth layer.
-It is connected to the BL contact pad layer 35a via the contact conductive portion 113. BL local wiring layer 51a
Are shared by the memory cells in the formation region R and the memory cells located above in FIG. The width of the BL local wiring layer 51a is, for example, 0.2
０．４0.4 μm.

The / BL local wiring layer 51b is located above the / BL contact pad layer 35b. / BL local interconnection layer 51b is provided with a bit line 61b (FIG. 7), which functions as a wiring layer for connecting the the source and drain of the transfer transistor Q ₂ n ⁺ -type impurity region 15e (FIG. 8). The end 51b1 of the / BL local wiring layer 51b is connected to the / BL contact pad layer 35b via the second-layer / fourth-layer contact conductive portion 113. The / BL local interconnect layer 51b is shared by the memory cells in the formation region R and the memory cells located below the formation region R in FIG. / BL local wiring layer 51b has a width of
For example, it is 0.2 to 0.4 μm.

Next, the sectional structure of the fourth conductive layer will be described.
This will be described with reference to FIG. The fourth conductive layer has, for example, a structure in which a nitride layer 52 of a high melting point metal, a metal layer 54, and a nitride layer 56 of a high melting point metal are stacked in this order from the bottom. Specific examples of each layer are as follows. As the nitride layer 52 of the refractory metal, for example, there is a titanium nitride layer. Examples of the metal layer 54 include an aluminum layer, a copper layer, and an alloy layer thereof. As the nitride layer 56 of the refractory metal, for example, there is a titanium nitride layer. Further, the fourth conductive layer may be in the following mode.
1) An embodiment comprising only a nitride layer of a high melting point metal.
2) An embodiment composed of only a metal layer.

A hard mask layer 59 made of a silicon oxide layer is formed on the fourth conductive layer. Using the hard mask layer 59 as a mask, the fourth conductive layer is patterned. This is because it is difficult to pattern the fourth conductive layer using only the resist as a mask due to the miniaturization of the memory cell.

Next, a sectional structure of the second / fourth layer-contact conductive portion 113 will be described with reference to FIG.
The second layer / fourth layer-contact conductive part 113 is embedded in a through hole 115 penetrating the two interlayer insulating layers 81 and 101. In this section, the second and fourth layers
-The contact conductive portion 113 connects the BL contact pad layer 35a and the BL local wiring layer 51a. Second
The layer / fourth layer-contact conductive portion 113 includes a plug 117 embedded in the through hole 115 and a through hole 1
The barrier layer 119 located on the bottom surface and the side surface of the substrate 15
And As a material of the plug 117, for example, there is tungsten. Preferably, the barrier layer 119 includes a metal layer made of a high melting point metal and a nitride layer of the high melting point metal formed on the metal layer. As a material of the metal layer made of the high melting point metal, for example, titanium is given. As a material of the nitride layer of the refractory metal, for example, there is titanium nitride. The diameter of the upper end of the through hole 115 is, for example, 0.18 to 0.22 μm, and the diameter of the lower end is, for example, 0.14 to 0.18 μm.

As shown in FIGS. 14 and 15, an interlayer insulating layer 121 such as a silicon oxide layer is formed so as to cover the fourth conductive layer. The interlayer insulating layer 121
A flattening process is performed by CMP.

{Fifth conductive layer} Regarding the fifth conductive layer,
This will be described with reference to FIGS. The fifth conductive layer is the fourth conductive layer.
It is located above the conductive layer. The fifth conductive layer includes a bit line 61a having a pattern extending substantially linearly in the Y direction,
/ Bit line 61b. A signal complementary to the signal flowing through the bit line 61a flows through the / bit line 61b. The width of the bit lines 61a and / b is, for example, 0.20
０．２0.26 μm.

The bit line 61a is a contact conductive portion 13 which is a conductive portion connecting the fifth conductive layer and the fourth conductive layer.
3 (hereinafter, referred to as a fourth layer / fifth layer-contact conductive portion 133), an end portion 51a1 of the BL local wiring layer 51a.
Connected to / Bit line 61b is connected to the fourth and fifth layers.
Via the contact conductive portion 133, the / BL local wiring layer 5
1b is connected to the end 51b2.

Next, the sectional structure of the fifth conductive layer will be described.
This will be described with reference to FIGS. The fifth conductive layer has, for example, a structure in which a nitride layer 62 of a high melting point metal, a metal layer 64, and a nitride layer 66 of a high melting point metal are stacked in this order from the bottom. Specific examples of each layer are as follows. As the nitride layer 62 of the refractory metal, for example, there is a titanium nitride layer. Examples of the metal layer 64 include an aluminum layer, a copper layer, and an alloy layer thereof. As the nitride layer 66 of the high melting point metal, for example, there is a titanium nitride layer. Further, the fifth conductive layer may have the following mode. 1) An embodiment comprising only a nitride layer of a high melting point metal. 2) An embodiment composed of only a metal layer.

On the fifth conductive layer, a hard mask layer 69 made of a silicon oxide layer is formed. Using the hard mask layer 69 as a mask, patterning of the fifth conductive layer is performed. This is because it is difficult to pattern the fifth conductive layer using only the resist as a mask due to the miniaturization of the memory cell.

The above is the details of the structure of the SRAM according to the present embodiment.

[Main Effects of the SRAM According to the Present Embodiment] The main effects of the SRAM according to the present embodiment are as follows.

{Effect 1} According to the present embodiment, no overlapping portion is formed between the sub-word line and the active region where the load transistor is formed, so that the stray capacitance due to this overlapping portion can be eliminated. Further, the floating capacitance formed by the active region, the side wall insulating layer of the sub-word line and the sub-word line can be eliminated. The details will be described below.

As shown in FIG. 8, the sub word lines 23a, 23a
3b, the extension is stopped short of the active region 13 (where the load transistor is formed).
a and 23b are located apart from the active region 13 in plan view. FIG. 16 is a sectional view taken along line C1-C2 in FIG. The side wall insulating layer 25 is located on the side of the sub word line 23a. A thin insulating layer 27 formed at the time of forming the gate insulating film is located below the sub word line 23a. Sub word line 23a and sidewall insulating layer 2
5 is located away from the active region 13 in plan view. That is, the active region 13 does not extend below the sub-word line 23 a or the sidewall insulating layer 25.

Therefore, active region 13 and sub-word line 23a
Since there is no overlapping portion with (23b), the stray capacitance caused by the overlapping portion, that is, the stray capacitance constituted by the active region 13, the thin insulating layer 27, and the sub-word line 23a (23b) can be eliminated. . Further, the active region 13, the side wall insulating layer 25 and the sub-word line 23a (23
The stray capacitance constituted by b) can be eliminated.

FIG. 17 shows a comparative example.
Active region 13 extends below sub word line 23a. Therefore, an overlapping portion 29 between the active region 13 and the sub-word line 23a is formed, so that a stray capacitance composed of the active region 13, the thin insulating layer 27 and the sub-word line 23a is generated. Further, the active region 13 and the sidewall insulating layer 2
5 and a sub-word line 23a. These stray capacitances hinder high speed operation and low current consumption of the SRAM.

According to the present embodiment, since the formation of the stray capacitance as described above can be prevented, the SRAM can be operated at high speed and with low current consumption.

{Effect 2} According to the present embodiment, the SRAM
Can be downsized. The details will be described below. In this embodiment, information is stored by the flip-flop of the memory cell. The flip-flop connects the input terminal (gate electrode) of one inverter to the output terminal (drain) of the other inverter, and connects the input terminal (gate electrode) of the other inverter to the output terminal (drain) of one inverter. It is configured by connecting. That is, the flip-flop is obtained by cross-connecting the first inverter and the second inverter. In the case where a flip-flop is formed using two conductive layers, for example, a drain-drain connection layer connecting the drains of the inverters and a drain-gate connection layer connecting the gate of the inverter and the drain of the inverter are combined. By using one conductive layer, cross-couple connection can be achieved.

However, according to this structure, the conductive layer is formed over a region where the drain of one inverter is located, a region where the gate of the other inverter is located, and a region connecting these. Therefore, this conductive layer becomes a pattern having three ends (for example, a pattern having a branch portion such as a T-shape or an h-shape) or a spiral pattern in which the arms intersect with each other. In addition, as the T-shaped pattern, for example,
This is disclosed in FIG. As the h-shaped pattern, for example, M. Ishida, et.al., IEDM
4 (b) on page 203 of Tech. Digest (1998). As a spiral pattern, for example,
M. Ishida, et.al., IEDM Tech. Digest (1998), page 203, FIG. 3 (b). When such a complicated pattern is miniaturized, it becomes difficult to accurately reproduce the shape in a photoetching process, so that a desired pattern cannot be obtained, which hinders miniaturization of the memory cell size.

According to the present embodiment, as shown in FIGS. 3, 4 and 5, the gate which becomes the gate of the CMOS inverter
A gate electrode layer (21a, 21b), a drain-drain connection layer (31a, 31b) connecting the drains of the CMOS inverters, and a drain-gate connection connecting the gate of one CMOS inverter and the drain of the other CMOS inverter The layers (41a, 41b) are formed in different layers. As described above, in the present embodiment, since the flip-flop is configured using three conductive layers, the pattern of each layer is simplified (for example, compared to the case where the flip-flop is configured using two conductive layers) (for example, ,
(Substantially linearly). Therefore, according to the present embodiment, since the pattern of each layer can be simplified, for example, in the 0.12 μm generation, the memory cell size is
A fine SRAM of 2.5 μm ² or less can be obtained.

[Application Example of SRAM to Electronic Apparatus] The SRAM according to the present embodiment can be applied to an electronic apparatus such as a portable apparatus. FIG. 18 is a block diagram of a part of the mobile phone system. CPU, SRA
M and DRAM are mutually connected by a bus line. Further, the CPU is connected to a keyboard and an LCD driver by a bus line. The LCD driver is connected to a liquid crystal display unit by a bus line. A memory system is composed of a CPU, an SRAM and a DRAM.

FIG. 19 is a perspective view of a portable telephone 600 provided with the portable telephone system shown in FIG. The mobile phone 600 includes a keyboard 612, a liquid crystal display 614,
Main unit 61 including earpiece 616 and antenna 618
0, and a cover 620 including a transmitter 622.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of an SRAM according to an embodiment.

FIG. 2 is a plan view showing fields of a memory cell array of the SRAM according to the embodiment;

FIG. 3 is a plan view showing a first conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 4 is a plan view showing a second conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 5 is a plan view showing a third conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 6 is a plan view showing a fourth conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 7 is a plan view showing a fifth conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 8 is a plan view showing a field and a first conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 9 is a plan view showing a field, a first conductive layer, and a second conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 10 is a plan view showing a second conductive layer and a third conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 11 is a plan view showing a first conductive layer and a third conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 12 is a plan view showing a second conductive layer and a fourth conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 13 is a plan view showing a fourth conductive layer and a fifth conductive layer of the memory cell array of the SRAM according to the embodiment;

FIG. 14 is a sectional view taken along the line A1-A2 in FIGS.

FIG. 15 is a sectional view taken along the line B1-B2 of FIGS. 2 to 13;

FIG. 16 is a sectional view taken along line C1-C2 in FIG. 8;

17 is a cross-sectional view as a comparative example of FIG.

FIG. 18 is a block diagram of a part of a mobile phone system including the SRAM according to the embodiment.

FIG. 19 is a perspective view of a mobile phone including the mobile phone system shown in FIG. 18;

[Explanation of symbols]

Reference Signs List 11 active region 11a, 11b forming region 12 p-well 13 active region 14 n-well 15a, 15b, 15c, 15d, 15en ⁺ type impurity region 17a, 17b, 17cp ⁺ type impurity region 19 element isolation region 21a, 21b gate- Gate electrode layer 23a, 23b Sub word line 25 Side wall insulating layer 27 Thin insulating layer 29 Overlapping part 30 Metal layer 31a, 31b Drain-drain connection layer 31a1, 31a2, 31b1, 31b2 End 31b3 L-shaped 32 Refractory metal nitride layer 33 _VDD wiring 33a Convex part 35a BL contact pad layer 35b / BL contact pad layer 37V _SS local wiring layer 40 Metal layer 41a, 41b made of high melting point metal Drain-gate connection Layers 41a1, 41a2, 41b1, 41b2 End 42 Nitride layer of refractory metal 51a BL local wiring layer 51a1 End 51b / BL local wiring layer 51b1 51b2 End 52 Refractory metal nitride layer 53 Main word line 54 Metal layer 55 V _SS wiring 56 High melting point Metal nitride layer 59 Hard mask 61a Bit line 61b / bit line 62 Refractory metal nitride layer 64 Metal layer 66 Refractory metal nitride layer 69 Hard mask 71 Interlayer insulating layer 73 Field / second layer-contact conductive Part 75 Through hole 77 Plug 79 Nitride layer of high melting point metal 81 Interlayer insulating layer 83 Second / third layer-contact conductive part 85 Through hole 87 Plug 89 Nitride layer of high melting point metal 93 First layer / third layer Layer-contact conductive part 95 through hole 97 plug 99 nitride layer of refractory metal 101 interlayer insulating layer 113 second layer Fourth layer-contact conductive part 115 Through hole 117 Plug 119 Refractory metal nitride layer 121 Interlayer insulating layer 133 Fourth / fifth layer-Contact conductive part R One memory cell formation region

Claims (9)

[Claims] 1. A semiconductor device including a memory cell including a first load transistor, a second load transistor, a first drive transistor, a second drive transistor, a first transfer transistor, and a second transfer transistor, wherein the semiconductor device includes: A first active region that extends and in which the first and second load transistors are formed; and a first and second drive transistor that extends in a first direction and the first and second drive transistors. A second active region in which a transfer transistor is formed; a second active region extending in the second direction; being located above the first and second active regions; and being planar with the first active region. A first word line including a gate electrode of the first transfer transistor, the first word line including a gate electrode of the first transfer transistor, and extending in the second direction; And located at an upper layer of the first and second active regions, separated from the first active region in plan view, and intersected with the second active region in plan view. And a second word line including a gate electrode of the second transfer transistor. 2. The device according to claim 1, which extends in the second direction, is located on the same layer as the first and second word lines, and is planar in view of the first and second active regions. And the gate electrode of the first load transistor and the gate electrode of the first drive transistor are located between the first word line and the second word line when viewed in a plan view. A first gate-gate electrode layer, extending in the second direction, and located in the same layer as the first and second word lines, and viewed in plan with the first and second active regions. And the gate electrode of the second load transistor and the second drive transistor is located between the first word line and the second word line when viewed in plan, and includes the gate electrodes of the second load transistor and the second drive transistor. And a second gate-gate electrode layer. Location. 3. The semiconductor device according to claim 1, wherein the first active region stops extending in front of the first and second word lines. 4. The semiconductor device according to claim 1, wherein the first and second gate-gate electrode layers extend in the second direction and are located above the first and second word lines. A first drain-drain connection layer connecting the drain of the first load transistor and the drain of the first drive transistor; and a first and second gate-gate electrode extending in a second direction. A second drain-drain connection layer, which is located on a layer and above the first and second word lines, and connects a drain of the second load transistor and a drain of the second drive transistor; And a first drain-gate connection located above the second drain-drain connection layer and connecting the first drain-drain connection layer and the second gate-gate electrode layer And a second drain-gate connection layer located above the first and second drain-drain connection layers and connecting the second drain-drain connection layer and the first gate-gate electrode layer. A semiconductor device, comprising: 5. The power supply line according to claim 1, wherein the power supply line extends in the first direction and is located in the same layer as the first and second drain-drain connection layers. And a ground line, a main word line, a BL local wiring layer, and a / BL local wiring layer, which are located above the first and second drain-gate connection layers, and extend in the first direction. And a bit line and a / bit line located above the ground line, the main word line, the BL local wiring layer, and the / BL local wiring layer. 6. The semiconductor device according to claim 1, wherein the first and second active regions, the first and second gate-gate electrode layers, and the first and second word lines are substantially linear. A semiconductor device having a pattern. 7. The memory cell according to claim 1, wherein the size of the memory cell is 2.5 μm ² or less.
Semiconductor device. 8. A memory system comprising the semiconductor device according to claim 1. 9. An electronic apparatus comprising the semiconductor device according to claim 1.