JP2002237180A - Memory module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory module which can hold stable waveform quality independently of conditions of capacity of a memory module or the like. SOLUTION: A load circuit having a resistor 3 and a capacitor 4 is branched from a signal line connecting a part at which a signal is inputted to a memory module and a memory element (DRAM2a), and a branch line is set. Chip resistance sockets (6a, 6b) are set for the signal line by the branch line connected to the load circuit and the signal line connected to the memory module. When a memory module element is not incorporated, a chip resistor of 0 Ω is inserted in the chip resistance socket 6b, and a signal inputted to the memory module is inputted to the load circuit. Thereby, the same situation as the situation in which a memory element is incorporated in a pseudo state is obtained in the case of considering it as a whole module.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory module capable of maintaining stable waveform quality irrespective of the capacity of the memory module (such as the mounting state of a memory unit such as a DRAM).

[0002]

2. Description of the Related Art In recent years, DRAMs (Dynamic Random Access Memory) used for memory modules such as DIMMs have been developed.
Access memories such as SDRAMs (Synchronous DRAMs) function in synchronization with a clock without changing the basic memory method.
And DR-DRAM (Direct RambusDR)
AM) DDR-SDRAM (Double Da)
(Ta Rate SDRAM) and the like, the speed has been increased.

A memory module equipped with an SDRAM or the like is combined with a system controller to
It is possible to dramatically improve the performance of the system controller while increasing the memory of the entire system. For this purpose, it is necessary to maintain stable waveform quality for the memory to be added and to secure timing.

On the other hand, the number of memories mounted on a memory module varies depending on the type of DRAM or the like. Therefore, the load applied to the signal line may be different for each DRAM mounted on the memory module. In addition, in a slot of a memory module in which a DRAM or the like is not mounted, for a signal line to be originally connected to the DRAM or the like, a circuit ahead of the signal line is opened and a load is not applied at all. Therefore, the waveform quality of the memory module changes according to the situation.

Conventionally, for all these cases,
On the system controller board side, it has been necessary to design printed circuit boards that take measures to ensure waveform quality and timing.

[0006]

However, in consideration of the fact that this design requires extremely complicated processing and that the speed of technological innovation such as the speeding up of the system clock on the system side is high, only the controller board side is required. Therefore, it is difficult to take the above measures.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a memory module capable of maintaining a stable waveform quality regardless of the capacity of the memory module (such as the mounting status of a memory unit). I do.

[0008]

In order to achieve the above object, a memory module according to claim 1 comprises a load circuit having a capacitor and a resistor according to the capacity of the memory module and the mounting contents of the memory element. And a switching unit for switching connection between a load circuit and a signal line connected to the memory element.

According to a second aspect of the present invention, there is provided the memory module according to the first aspect, wherein the amount of change in load applied to the circuit depends on whether the memory module is installed in a predetermined circuit or not. Is greater than or equal to a predetermined value, and if the change in the waveform quality changes by a predetermined value or more depending on whether or not the load circuit is connected to a predetermined signal line of the memory module, the switching means only applies to that signal line. It is characterized by being provided.

According to a third aspect of the present invention, there is provided the memory module according to the first aspect, wherein the memory module is capable of changing the number of mounted memory elements and includes a permanent memory element which is always mounted. Module, wherein the switching means comprises: a signal line for notifying an input signal input to the memory module, wherein a signal line for notifying the permanent memory element and an emergency memory signal for an element other than the permanent memory element. After being branched to a line, if it is connected to a predetermined memory element, it is provided for the emergency memory signal line.

According to a fourth aspect of the present invention, in the memory module according to the third aspect, the switching means is effective for the permanent memory signal line.

[0012]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The memory module includes a DRAM, an SDRAM, a DR-DR
Various types of memories such as AM and DDR-DRAM are mounted. As an embodiment of the present invention, a memory module having a DRAM mounted on a memory section will be described.

(First Embodiment) A first memory module will be described. First, the first memory module has a resistor, a capacitor, a DRAM, a chip resistor socket, and a signal line. The DRAM has a function as a memory unit of the memory module.

The capacitor has a capacity corresponding to the capacity of the DRAM in the first memory module. The resistor is connected to the capacitor to form a load circuit for providing a load state similar to the load state on the signal line connected to the DRAM. That is, when the signal line is connected to the DRAM and when the signal line is connected to the load circuit, the voltage applied to the signal line is made equal.

In the chip resistor socket, a chip resistor is inserted as needed. The chip resistor socket is connected to the signal input portion of the memory module and the load circuit, and the signal input portion of the memory module and the signal line of the memory module.
It is installed in each part connecting AM.

Here, the chip resistor is inserted into a chip resistor socket between the load circuit and the signal line when the DRAM is not mounted ahead of the predetermined signal line, and when the DRAM is mounted, the signal line and the DRAM are mounted. Inserted into the chip resistor socket between. Thus, when the DRAM is mounted, the input signal goes to the DRAM, and when the DRAM is not mounted, the input signal goes to the load circuit. It may also be a 0Ω chip resistor.

The load circuit may be mounted for each signal line.

The signal flowing through the signal line takes the following path. When the DRAM is mounted on the first memory module, and the signal line is connected to the DRAM, the signal current input to the first memory module follows the signal line, and It flows to a predetermined address. In the first memory module, when a signal line is connected to the load circuit, a signal current input to the first memory module flows through the load circuit along the signal line.

In any of the above cases, the electrical state of the signal line generated by a signal input from outside the memory module is the same. Therefore, when the first memory module is mounted on the system controller,
The waveform quality of the first memory module is maintained regardless of any of the above states. That is, the load circuit
By exerting the function of virtually creating the same state as the state in which the DRAM is mounted, the load state of the entire memory module is maintained regardless of the change in the mounting state of the memory unit inside the memory module.

Therefore, in the structure of a DRAM module in which the capacity can be changed by changing the number of DRAM chips, a chip capacitor chip when no DRAM is mounted on each signal line of each DRAM chip which is not mounted when the capacity is changed. A DRAM module having a structure in which a layout for connecting to a load circuit having a resistance is provided is provided.

(Second Embodiment) Next, a second memory module will be described. The second memory module has a capacitor, a resistor, a DRAM, a chip resistor socket, and a signal line. Capacitor, resistor, signal line, DR
The functions of the AM and the chip resistor are the same as those of the first memory module. However, the second memory module is DR
Two or more AMs can be mounted.

A method for setting the mounting location of the load circuit in the second memory module will be described. First, a memory module N in which the mounting state of the DRAM is the same as that of the second memory module and which has no load circuit is considered. It is assumed that the amount of change in the circuit load is R between when the memory module N is mounted on a predetermined circuit such as a controller board and when it is not mounted. The change in the waveform quality of the signal flowing through each signal line Li (i is a positive integer and the maximum value n (n indicates the number of signal lines of the memory module N)) of the memory module N is shown. Wi (i is a positive integer and the maximum value is n).

At this time, the change Wk in the waveform quality of the signal flowing through the signal line Lk (k is a positive integer and the maximum value n) when the amount of change R in the load is equal to or greater than the predetermined value P. (K
Is a positive integer, and when the maximum value n) is equal to or greater than the predetermined value W, a load circuit is installed for the signal line Lk. Thereby, the load circuit of the second memory module is set. Note that P and W may be determined according to the relationship between the memory module and a predetermined circuit.

Further, the load circuit mounted on the memory has a function of connecting to a signal line connected to the memory. At this time, the path of the signal flowing through the signal line and the structure of the load circuit main body may be the same as those of the first memory module.

That is, the load differs greatly depending on whether a module is mounted or not, and the first memory is used only for signal lines (address control signals, etc.) requiring waveform quality accuracy. DRA based on the same layout as the module
An M module is provided.

(Third Embodiment) Next, a third memory module will be described. FIG. 3 is a schematic configuration diagram of the third memory module. The third memory module (memory module 5) is a DRAM (1a, 1b),
It has a DRAM (2a, 2b), a capacitor 3, a resistor 4, a chip resistor socket (6a, 6b) and a signal line. D
RAM (1a, 1b), DRAM (2a, 2b), capacitor 3, resistor 4, chip resistor socket (6a, 6b)
The function of the signal line may be the same as that of the first memory module.

Also, a DRAM (1a, 1b) and a DRAM
The differences between (2a, 2b) are as follows. That is, in the third memory module, the DRAM (1
a, 1b) are always mounted. Meanwhile, DRAM
(2a, 2b) in the third memory module,
It is not always installed.

Next, the mounting state of the load circuit in the third memory module will be described. This can be explained with reference to FIG. A signal line for notifying that a predetermined signal has been input is divided into a case where the signal is addressed to the address of the DRAM (1a, 1b) and a case where the signal is addressed to the address of the DRAM (2a, 2b). DRAM (1a, 1
b) Alternatively, it is connected to the DRAM (2a, 2b).
A signal line going to the DRAM (1a, 1b) is a permanent memory signal line, and a signal line going to the DRAM (2a, 2b) is an emergency memory signal line. At this time, a load circuit is provided for the emergency memory signal line. Also,
The load circuit mounted on the memory has a function of connecting to a signal line connected to the memory. At this time, the path of the signal flowing through the signal line and the structure of the load circuit main body may be the same as those of the first memory module.

That is, in the structure of a DRAM module in which the capacity can be changed by changing the number of DRAM chips, the input signal of the DRAM module is first used for the address where the DRAM chip is always mounted and for the address where the DRAM chip is not always mounted. DRAM after each branch
Make chip wiring. Furthermore, for addresses for which a DRAM chip may not be mounted, connect to each DRAM chip immediately after branching, or use a chip capacitor or chip capacitor.
A DRAM module laid out so that it can be connected to a load circuit having a chip resistor can be provided.

(Fourth Embodiment) Next, a fourth memory module will be described. FIG. 4 is a schematic configuration diagram of the fourth memory module. The third memory module (memory module 5) is a DRAM (1a, 1b),
It has a DRAM (2a, 2b), a capacitor 3, a resistor 4, a chip resistor socket (6a, 6b, 6c) and a signal line. DRAM (1a, 1b), DRAM (2a, 2
b), capacitor 3, resistor 4, chip resistor socket (6)
a, 6b, 6c) and the functions of the signal lines may be the same as those of the third memory module.

A DRAM (1a, 1b) and a DRAM
The difference between (2a, 2b) may be the same as that of the third memory module.

Next, the mounting state of the load circuit in the fourth memory module will be described. This can be explained with reference to FIG. That is, in addition to the emergency memory signal lines, the permanent memory signal lines are in a state similar to that in which a load circuit is installed.

Next, the path of a signal flowing through a signal line will be described. It becomes a path according to the installation status of the chip resistor in the chip resistor socket.

Chip resistor socket (6a, 6b, 6c)
Have chip resistors inserted as necessary. Also,
The chip resistor sockets (6 a, 6 b, 6 c) are provided on signal lines at portions connecting the signal input portion of the memory module and the load circuit and between the signal input portion of the memory module and the DRAM.

The placement of the chip resistor is divided as follows. DRAM (1a, 1b) and DRAM (2a, 2
b) is mounted, the chip resistor socket (6
a, 6c) A chip resistor is installed. DRAM (1a,
1b) is mounted and the DRAM (2a, 2b) is not mounted, the chip resistor sockets (6b, 6b) are not mounted.
Place a chip resistor in c). DRAM (1a, 1b)
When the DRAM (2a, 2b) is not mounted, a chip resistor is installed in the chip resistor socket 6c.
Thus, when the DRAM is mounted, the input signal goes to the DRAM, and when the DRAM is not mounted, the input signal goes to the load circuit. The chip resistance is 0
A chip resistor of Ω may be used.

That is, in the layout structure of the third memory module, the DRAM is connected to each DRAM chip immediately after a signal line branches for an address where the DRAM chip is always mounted, or a load circuit having a chip capacitor and a chip resistor. A DRAM module laid out so as to be connectable to a DRAM module.

It is to be noted that a circuit for controlling the input state of the signal is not limited to the chip resistor, and may be provided. It is, for example, a switch.

For example, in a system controller capable of mounting a DRAM module, when a memory module having four chips and a memory module having eight chips coexist, a third memory module is replaced with a memory module having four chips. It is possible to adopt things. As a result, all the pseudo extension RAM modules have a constant load, and a signal having a constant waveform quality and operation timing can be obtained regardless of the memory capacity of the system.

Further, regarding the fourth memory module,
In a system controller capable of memory expansion, when a RAM module for expansion is not originally inserted into a slot, a circuit where the circuit is opened is replaced with a DIMM for an empty slot which requires the same load as when a DRAM module is inserted. By installing it, RA for expansion
The same load is applied to the signal line both when the M module is inserted and when the empty slot DIMM is inserted, and a constant waveform quality and operation timing are maintained regardless of the memory capacity of the system. You can get the signal you have.

Further, since it is only necessary to design a circuit considering only the case where the additional RAM module is inserted in a simulated manner, the subsequent approach (for example, increasing the clock frequency, etc.) Design). This reduces board design errors and leads to a higher quality system controller board design.

[0041]

As is apparent from the above description, according to the first aspect of the present invention, the capacity of the memory module (DR)
Regardless of the mounting status of the memory unit such as AM, etc.), a memory module that can maintain stable waveform quality can be provided, and it is possible to overcome the situation where the control board had to take measures to maintain waveform quality. It becomes possible.

According to the second aspect of the present invention, it is not necessary to provide a load circuit for the signal lines of all the memory elements, and the space occupied by the load circuit can be reduced.

According to the third aspect of the present invention, it is not necessary to install a load circuit for all the signal lines by classifying the memory element based on the possibility that the memory element may not be mounted. The number of parts can be reduced.

For example, in a memory module in which a maximum of eight memory elements are mounted on both sides (4 on each side), if the memory elements are mounted on only one side, the memory elements can be mounted on one side. Nevertheless,
The location is empty (not mounted). This 4
It is necessary to connect a load circuit to the signal lines (signal lines for the address signal and the control signal) of each memory element in order to make the state where the memory element is quasi-mounted at a place where the memory element is not mounted. Occurs. In this case, a number of parts corresponding to the product of "the number of signal lines for address signals / control signals for each memory element", "the number of unmounted memory elements", and "resistance / capacitor required for load" is required.

At this time, if the number of unmounted memory elements is not determined in advance, it is necessary to consider the possibility of all unmounted memory elements. Since the number is determined in advance, the number of parts can be reduced.

According to the fourth aspect of the present invention, it is particularly effective for a circuit such as a control board of a system having a slot in which a plurality of memory modules can be mounted.

For example, when the system has a memory configuration,
There is a case where a slot is empty even though there are a plurality of slots in which a memory module can be mounted. In this case, the circuit is opened from the place where the slot becomes an empty slot, and the load on the signal line is greatly different from the case where the memory elements are mounted in all the slots. In order to prevent this, an empty slot module having a predetermined load is mounted on the empty slot. This means that when designing the circuit, it is only necessary to consider the case where the load on the signal line is the largest.

At this time, by using the configuration of the memory module according to the present invention, the PWB of the module for the empty slot and the memory module according to the present invention can be shared. That is, for example, in the fourth memory module, a memory module without a DRAM is used as a memory module for an empty slot.

That is, according to the present invention, when the load on the signal line greatly changes depending on the number of memory modules mounted in the system controller capable of adding memory, the signal line is applied to the signal line regardless of the memory capacity of the system. A memory module having a structure in which the load is constant (a memory module according to claim 1 or the like) is used.

As a result, since the load on the signal line has always been constant depending on the number and types of the additional RAM modules, the waveform quality and operation timing have been fixed, and the speed has been increased in recent years. Design errors are reduced for a given bus frequency, and the effect that a high-quality system controller can be designed can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram for explaining an embodiment of a third memory module according to the present invention.

FIG. 2 is a schematic configuration diagram for explaining an embodiment of a fourth memory module according to the present invention.

[Explanation of symbols]

 1a, 1b DRAM 2a, 2b DRAM 3 resistor 4 capacitor 5 memory module 6a, 6b, 6c chip resistor socket

Claims (4)

[Claims] 1. A load circuit having a capacitor and a resistor according to the capacity of a memory module and the content of a memory element, and switching means for switching connection between the load circuit and a signal line connected to the memory element. A memory module characterized by the above-mentioned. 2. The method according to claim 1, wherein a change amount of a load applied to the memory module is equal to or more than a predetermined value depending on whether or not the memory module is installed in a predetermined circuit, and the load circuit is connected to a predetermined signal line of the memory module. 2. The memory module according to claim 1, wherein when the change in the waveform quality changes by a predetermined value or more depending on whether or not the signal line is connected, the switching unit is provided only on the signal line. 3. 3. The memory module according to claim 1, wherein the memory module has a variable number of memory elements mounted thereon, and has a permanent memory element that is always mounted, wherein the switching means includes an input signal input to the memory module. Is branched into a permanent memory signal line heading to the permanent memory element and an emergency memory signal line heading to an element other than the permanent memory element, and then connected to a predetermined memory element, The memory module according to claim 1, wherein the memory module is provided for the emergency memory signal line. 4. The memory module according to claim 3, wherein said switching means is also effective for said permanent memory signal line.