JP2002232277A - Current switch circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To operate ON/OFF of an output side transistor in a current mirror circuit at high speed without increasing a constant current. SOLUTION: A transfer gate 5 is conducted by impressing a high voltage to a first terminal 5a and impressing a low voltage to a second terminal 5b, and the gates of NMOS transistors 2 and 3 are connected. The NMOS transistor 4 is changed from ON to OFF, the output of an inverter circuit 11 is changed from low to high, one part of a constant current Io is impressed to the gate of the NMOS transistor 3 by superimposing a current from the transfer gate 5 and a current from the inverter circuit 11 through a capacitor 10, and a gate voltage is speedily increased. Thus, a switching speed in the case of changing the NMOS transistor 3 from OFF to ON can be accelerated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current switch circuit of a semiconductor integrated circuit, and more particularly to a current switch circuit capable of performing a high-speed switching operation.

[0002]

2. Description of the Related Art A conventional current switch circuit of this type is configured as shown in FIG. In FIG. 3, the gates of the NMOS transistor 2 and the NMOS transistor 3 that constitute the current mirror circuit 1 are connected by a switch circuit. The first part of the switch circuit
The input signal Vin of the terminal (input terminal) 5a is at a high level,
When the input signal Vin of the second terminal (inverting input terminal) 5b is at a low level, the transfer gate 5 is turned on, the NMOS transistor 4 is turned off, and the constant current Io obtained from the constant current source 6 by the current mirror circuit 1 is supplied. The current flows at the output terminal 7 as the output current Iout.

When the input signal Vin of the first terminal 5a is at a low level and the input signal Vin of the second terminal 5b is at a high level, the transfer gate 5 is open and N
The current switch circuit is realized by turning on the MOS transistor 4 and turning off the NMOS transistor 3 to change the presence or absence of the output current Iout.

[0004]

In the current switch circuit having such a configuration, when the NMOS transistor 3 changes from on to off, the NMOS transistor 4 transfers the electric charge stored in the gate input capacitance of the NMOS transistor 3. Since the discharge can be performed in a short time by turning on, the NMOS transistor 3 can change from on to off at high speed.

However, when the NMOS transistor 3 is turned on from off, it is necessary to change the gate voltage of the NMOS transistor 3 from a low level to a high level by a part of the constant current Io flowing through the transfer gate 5. It takes time for the transistor 3 to change from off to on.

The current flowing through the transfer gate 5 is increased by increasing the constant current Io.
The time required for the MOS transistor 3 to change from off to on can be shortened to some extent, but this causes a problem that the current flowing constantly increases and that the mirror ratio with the output current Iout becomes difficult to obtain. I do.

Therefore, although there is no problem in the switching operation of the low-frequency current, the time required for the NMOS transistor 3 to be turned on from the off-state cannot be ignored as the frequency increases, so that the switching operation of the high-frequency current is limited. there were.

The present invention is directed to solving the above-mentioned problem of the prior art, and by changing the output side transistor of the current mirror circuit from off to on at high speed without increasing the constant current Io, An object of the present invention is to provide a current switch circuit capable of high-speed switch operation.

[0009]

In order to achieve the above object, a current switch circuit according to the present invention comprises a first MOS transistor having a drain connected to a gate and a gate of a second MOS transistor. A current mirror circuit connected by the switch circuit, a circuit connecting the gate and the source of the second MOS transistor when the switch circuit is opened, and a capacitor connected to the gate of the second MOS transistor when the switch circuit is closed. And a circuit for charging or discharging.

Further, a resistor is inserted between the charging or discharging circuit and the capacitor to adjust the on / off switching speed of the second MOS transistor.

According to the above configuration, the on / off switching of the output side MOS transistor of the current mirror circuit can be changed at a high speed by the circuit for charging or discharging the capacitor connected to the gate, and the current switch for the high speed switching operation A circuit can be realized.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a current switch circuit according to the first embodiment of the present invention. Here, components having substantially the same functions and corresponding to the components described in FIG. 3 showing the conventional example are denoted by the same reference numerals, and the same applies to the following drawings. As shown in FIG. 1, the gates of the NMOS transistor 2 and the NMOS transistor 3 whose drain and gate are connected are connected via a transfer gate 5 which is a switch circuit.

The gate of the NMOS transistor 3 is connected to the drain of the NMOS transistor 4 connecting the gate and the source of the NMOS transistor 3.
To the output of the inverter circuit 11.

The transfer gate 5 has a first input terminal 5a, an input of the inverter circuit 11 and an NMO
A second terminal 5b, which is an inverting input terminal to which the gate of the S transistor 4 is connected, is formed. Switching control voltages having phases different by 180 degrees are applied to the first terminal 5a and the second terminal 5b, respectively. NMOS transistor 2
, A constant current Io is constantly flowing from the constant current source 6, and depending on the input level of the switching control voltage inputted to the first terminal 5 a and the second terminal 5 b of the transfer gate 5, The constant current Io flows to the output terminal 7 as the output current Iout.

The operation of the current switch circuit of the first embodiment configured as described above will be described with reference to FIG. Consider a case where the transfer gate 5 is conducting and the NMOS transistor 3 is on as an initial value. From this state, at the moment when a low-level voltage is applied to the first terminal 5a and a high-level voltage is applied to the second terminal 5b as a switching control voltage, the transfer gate 5 is opened, and the NMOS transistor 2 and the NMO
The gate of the S transistor 3 is disconnected.

Further, the NMOS transistor 4 is turned on, a drain current flows through the NMOS transistor 4, and the gate voltage of the NMOS transistor 3 and the voltage of the connected capacitor 10 are changed to the ground potential. At the same time, the output of the inverter circuit 11 also changes to low level, so that the discharge of the capacitor 10 is finally completed, the voltage between both terminals of the capacitor 10 approaches 0 V, and the NMO
The S transistor 3 is turned off.

By increasing the current drive capability of the NMOS transistor 4, the charge stored in the gate input capacitance of the NMOS transistor 3 and the capacitor 10 can be rapidly discharged.
The gate voltage of the MOS transistor 3 quickly changes from a high level (gate potential of the NMOS transistor 2) to a low level (ground potential).

Next, at the moment when a high-level voltage is applied to the first terminal 5a and a low-level voltage is applied to the second terminal 5b as the switching control voltage, the transfer gate 5 changes from the open state to the conductive state, and the NMOS transistor 2 and the NMOS transistor The current mirror circuit 1 is formed by connecting the gates of the transistors 3. At the same time, the NMOS transistor 4 changes from on to off, and the inverter circuit 11
Changes from the low level to the high level, a part of the constant current Io is superimposed on the current flowing from the transfer gate 5 and the current supplied from the inverter circuit 11 through the capacitor 10, and the NMOS transistor 3
, The gate voltage of the NMOS transistor 3 starts to rise quickly.

As the gate voltage of the NMOS transistor 3 increases, the current supplied from the capacitor 10 decreases, and the gate voltage of the NMOS transistor 3 finally settles to the gate voltage of the NMOS transistor 2. Therefore, the switching speed can be increased even when the NMOS transistor 3 is turned on from off.

The switching speed can be varied by increasing or decreasing the high-level drive current of the inverter circuit 11 or by changing the capacitance of the capacitor 10. It can be adjusted by inserting a resistor between them.

Specifically, when the constant current Io = 10 μA while the NMOS transistor 3 is on, if the size ratio between the NMOS transistor 2 and the NMOS transistor 3 is 1: 100, the output current Iout = 10 μ × 100
A current of = 1 mA flows.

Most of the current required to quickly change the gate potential of the NMOS transistor 3 to the high level is supplied from the capacitor 10 through the inverter circuit 11, so that the current flows to the drain-gate connection of the NMOS transistor 2. It has almost no relation to the constant current Io.

As described above, without setting the constant current Io to a particularly large value, the constant current Io changes not only when the NMOS transistor 3 changes from on to off but also when it changes from off to on. Current switching operation becomes possible.

FIG. 2 is a circuit diagram showing a current switch circuit according to the second embodiment of the present invention. In the second embodiment,
The output current Io is basically the same as that of the first embodiment, as shown in FIG.
ut is taken out. In order to change the gate voltage of the current mirror circuit 1 ′ and the PMOS transistor 3 ′ to the source voltage, P
It is configured using a MOS transistor 4 '.

The operation will be described below with reference to FIG. Consider a case where transfer gate 5 is conductive and PMOS transistor 3 'is on as an initial value. From this state, at the moment when a low-level voltage is applied to the first terminal 5a and a high-level voltage is applied to the second terminal 5b as a switching control voltage, the transfer gate 5 is opened, and the PMOS transistor 2 'and the PMOS transistor 3' The gate is disconnected.

When the PMOS transistor 4 'is turned on and the PM
A drain current flows through the OS transistor 4 ', and changes the gate voltage of the PMOS transistor 3' and the voltage of the connected capacitor 10 to the VDD potential. At the same time, the output of the inverter circuit 11 changes to a high level, so that the capacitor 10 is finally charged, the voltage between both terminals of the capacitor 10 approaches 0 V, and the PMOS transistor 3 'is turned off.

By increasing the current drive capability of the PMOS transistor 4 ', the gate input capacitance of the PMOS transistor 3' and the charge stored in the capacitor 10 can be rapidly charged.
The gate voltage of the MOS transistor 3 'quickly changes from a low level (gate potential of the PMOS transistor 2') to a high level (VDD potential).

Next, at the moment when a high-level voltage is applied to the first terminal 5a and a low-level voltage is applied to the second terminal 5b as the switching control voltage, the transfer gate 5 changes from the open state to the conductive state, and the PMOS transistor 2 '
And the gate of the PMOS transistor 3 'are connected to form a current mirror circuit 1'. At the same time, the PMOS transistor 4 'changes from on to off, and the inverter circuit 11
Changes from high level to low level.

Therefore, the current flowing through the transfer gate 5 as a part of the constant current Io and the capacitor 1
0, and the current flowing out of the inverter circuit 11 through the inverter circuit 11 is superimposed and applied to the gate of the PMOS transistor 3 '.
The gate voltage of the MOS transistor 3 'starts to decrease immediately. As the gate voltage of the PMOS transistor 3 'decreases, the outflow current of the capacitor 10 decreases and the gate voltage of the PMOS transistor 3' finally settles to the gate voltage of the PMOS transistor 2 '. Therefore, the switching speed can be increased even when the PMOS transistor 3 'is turned on from off.

As described above, also in the second embodiment, as in the first embodiment, a high-speed current switching operation can be performed without setting the constant current Io to a particularly large value.

[0032]

As described above, according to the present invention,
In a switch circuit composed of a current mirror circuit and a transfer gate, not only when the output transistor of the current mirror circuit is changed from on to off without increasing the constant current Io which is the reference current of the current mirror circuit, Even when changing from off to on, the change can be made at a high speed, and an effect of realizing a current switch circuit that operates with low power consumption and at a high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a current switch circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a current switch circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional current switch circuit.

[Explanation of symbols]

 1, 1 'current mirror circuit 2, 3, 4 NMOS transistor 2', 3 ', 4' PMOS transistor 5 transfer gate 5a first terminal 5b second terminal 6 constant current source 7 output terminal 8 power supply terminal 10 capacitor 11 inverter circuit

Claims (2)

[Claims] A first transistor having a drain connected to the gate;
A current mirror circuit connecting the gate of the OS transistor and the gate of the second MOS transistor by a switch circuit; a circuit connecting the gate and the source of the second MOS transistor when the switch circuit is opened; A circuit for charging or discharging a capacitor connected to the gate of the second MOS transistor when the circuit is closed. 2. The current switch according to claim 1, wherein a resistor is inserted between the charging or discharging circuit and the capacitor to adjust an on / off switching speed of the second MOS transistor. circuit.