JP2002229518A - Liquid crystal display device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device and its manufacturing method in which EMI level is reduced and visual angle characteristic is improved. SOLUTION: The liquid crystal display device has a data driving section 29 which includes a plurality of data drivers that supply image data to a liquid crystal panel 30 displaying an image. When image data being supplied to at least two data drivers are same, a control section 21 is provided to control the liquid crystal display device so that the image data are simultaneously taken in by at least the two data drivers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 1 is a block diagram showing a configuration of a data driver in a conventional liquid crystal display device. As shown in FIG. 1, a data driver in a conventional liquid crystal display device includes data drivers DV1 to DVn. Then, each of the data drivers DV1 to DVn captures the data signal DATA in accordance with the supplied display start signal, and then activates the display start signal EO which is activated by the next-stage data driver.
Supply UT. Thus, the data signal DATA is sequentially taken into the data drivers DV1 to DVn arranged in parallel. As shown in FIG. 1, each data driver D
A clock signal CLK and a latch pulse LP are provided to V1 to DVn.
And a reference voltage Vref.

FIG. 2 is a block diagram showing a configuration of the data driver DV1 shown in FIG. The data drivers DV2 to DVn shown in FIG. 1 have the same configuration as the data driver DV1.

[0004] As shown in FIG.
V1 includes an output amplifier 1, a D / A converter 3, a latch circuit 5, a shift register 7, and a clock controller 9. Here, the source line SL is connected to the output amplifier 1, and the D / A converter 3 is connected to the output amplifier 1.
The latch circuit 5 is connected to the D / A converter 3,
The shift register 7 is connected to the latch circuit 5. Also,
The clock controller 9 is connected to the shift register 7. Then, the reference voltage Vref is supplied to the D / A converter 3, and the data signal DATA is supplied to the shift register 7. Further, the clock controller 9 is supplied with a display start signal EI, a clock signal CLK and a latch pulse, and outputs a display start signal EOUT.

Therefore, in the conventional liquid crystal display device having the above-described configuration, the clock signal CLK is supplied to each of the data drivers DV1 to DVn irrespective of the data signal DATA. There has been a problem that the level of noise and the power consumption increase.

[0006] In recent years, the technology of electric and electronic equipment has been rapidly developing. However, in the low frequency area, heating and fire of electric equipment due to harmonics, and in the high frequency area, noise mixing into televisions and the like have occurred. Disturbances have occurred and such electromagnetic interference has become a common problem worldwide. Therefore, at present, the need for measures against electromagnetic interference (EMI measures) is increasing.

On the other hand, in recent years, TFT liquid crystal displays have been used as monitors for personal computers or TV image display devices because of their large size, gradation display, and high contrast. Such applications require that the liquid crystal display be visible from all directions.

Here, as a technique for realizing a liquid crystal display having a wide viewing angle, MVA (Multi-domain Verti
cal Alignment) type liquid crystal display devices have been devised. That is, in the MVA type liquid crystal display device, as shown in FIG. 3, the transparent electrodes 11 on which the bank-shaped dielectric structures 13 are formed are provided to face each other, and the liquid crystal molecules 15 are placed between the two transparent electrodes 11. The liquid crystal layer including the liquid crystal layer is sandwiched.

As shown in FIG. 3A, when a voltage is not applied between the transparent electrodes 11 facing each other, the liquid crystal molecules 15 are vertically aligned. As shown in FIG. 3 (b), each of the four regions is inclined in a predetermined direction. Thereby, the viewing angle characteristics of the four regions are mixed, so that a wide viewing angle can be obtained.

Here, in the MVA type liquid crystal display device, as shown in the contrast diagram of FIG. 4, the black-and-white viewing angle has a contrast (CR) of 10 or more even at a tilt angle of 80 degrees in the vertical and horizontal viewing angles. Has been realized.

In the structure of the MVA type liquid crystal display device, a slit may be formed on the electrode instead of the dielectric structure, and the dielectric structure is formed on one substrate and the slit is formed on the other substrate. It is good also as a structure which formed and combined.
Further, the dielectric structure and the slit may be combined and formed on one substrate.

However, halftone display, for example, FIG.
When a picture of a woman as shown in FIG. 6 is displayed, there arises a problem that the whole image becomes white and the contrast decreases at a lower viewing angle as shown in FIG.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a liquid crystal display device having a reduced EMI level and improved viewing angle characteristics, and a method of manufacturing the same. With the goal.

[0014]

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device including a plurality of data driving means for supplying image data to a liquid crystal display means for displaying an image. In the case where the same image data is used, it is attained by providing a liquid crystal display device comprising a control means for simultaneously taking in the image data to at least two data driving means.

According to such means, the clock signal for transferring the image data can be temporarily stopped or the frequency of the clock signal can be reduced.

Another object of the present invention is to provide a liquid crystal display device including data driving means for taking in image data according to a supplied clock signal and supplying the image data to liquid crystal display means for displaying an image, The data driver captures the image data at a timing when the clock signal transitions from the first logic level to the second logic level, or at a second timing when the clock signal transitions to a different logic level. This is achieved by providing a liquid crystal display device comprising a control means for arbitrarily switching and setting.

According to such means, the peak frequency of EMI noise generated from the clock signal can be dispersed.

Another object of the present invention is to provide a liquid crystal display device including data driving means for taking in image data according to a supplied clock signal and supplying the image data to liquid crystal display means for displaying an image, The present invention is attained by providing a liquid crystal display device including a control unit that generates a clock signal whose duty ratio changes and supplies the clock signal to a data driving unit.

According to such a means, it is possible to disperse harmonics generated when displaying an image on the liquid crystal display means.

Here, more specifically, the control means can change the duty ratio and generate a clock signal synchronized with the image data and supply it to the data driving means.

It is another object of the present invention to provide a method of manufacturing a liquid crystal display device for displaying an image on a liquid crystal panel including a liquid crystal cell, wherein the thickness of the liquid crystal cell or the birefringence of a liquid crystal layer included in the liquid crystal cell is determined. This is achieved by providing a method for manufacturing a liquid crystal display device having a step of determining a γ value that is an index of the gradation-luminance characteristic according to the magnitude of the gray level. here,
The “birefringence of the liquid crystal layer” means the product Δn · d of the refractive index anisotropy Δn of the liquid crystal and the thickness d of the liquid crystal cell.

According to such means, the display / viewing angle characteristics of the liquid crystal panel can be improved.

Another object of the present invention is to provide a liquid crystal display device for displaying an image by controlling the orientation of a plurality of liquid crystal molecules, wherein the liquid crystal molecules are oriented in a first direction when a voltage is applied. The liquid crystal molecules are aligned in a second direction opposite to the first direction when a voltage is applied, and include a second alignment region having a width different from that of the first alignment region. This is achieved by providing a liquid crystal display device characterized by the above.

According to such means, a liquid crystal display device having desired viewing angle characteristics can be easily obtained.

Another object of the present invention is to provide a liquid crystal display device for displaying an image by aligning liquid crystal molecules contained in a liquid crystal layer provided between a pixel electrode substrate and a counter substrate. A first electrode formed on the entire surface of the substrate, a resin layer formed on the first electrode, having a first slit portion, and formed on the pixel electrode substrate so as to face the first electrode; This is achieved by providing a liquid crystal display device comprising: one slit portion; and a second electrode having a second slit portion facing the slit portion.

According to such means, the liquid crystal molecules can be selectively driven.

Here, a liquid crystal display device for displaying an image by orienting liquid crystal molecules contained in a liquid crystal layer provided between a pixel electrode substrate and a counter substrate is provided on the counter substrate. Bank-shaped first dielectric structure, a first electrode formed to cover the opposing substrate and the dielectric structure, and a slit portion formed on the pixel electrode substrate and facing the dielectric structure. A liquid crystal display device comprising a second electrode having, or a first electrode formed on the entire surface of the counter substrate, and a first dielectric structure formed on the counter substrate, or A slit portion formed in the first electrode, a second electrode provided on the pixel electrode substrate so as to face the first electrode, a first electrode in the vicinity of the first dielectric structure, Or a dielectric covering the second electrode near the slit By a liquid crystal display device characterized by comprising a preparative, it is possible to selectively drive the liquid crystal molecules.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts. [First Embodiment] FIG. 7 is a diagram showing a configuration of a liquid crystal display device according to a first embodiment of the present invention. As shown in FIG. 7, the liquid crystal display device 20 according to the first embodiment includes a control unit 21, a reference voltage generation unit 23, a power supply voltage generation unit 25, a gate drive unit 27, a data drive unit 29, and a liquid crystal panel 30.
Is provided. Here, the control unit 21 generates various control signals described later according to the supplied input signal. The reference voltage generator 23 is connected to the power supply voltage generator 25, generates a reference voltage (grayscale voltage), and supplies the reference voltage to the data driver 29.

Further, the power supply voltage generator 25 stores an internal power supply voltage and a reference voltage according to an external power supply voltage supplied from the outside.
Vref is generated, and the gate driver 27 and the data driver 29
Supply to In addition, the gate driving unit 27 selects a liquid crystal to which data is to be written from among the liquid crystal cells constituting the liquid crystal panel 30 according to the control signal supplied from the control unit 21 and the voltage supplied from the power supply voltage generation unit 25. Select a cell. The data driver 29 supplies a data signal to the liquid crystal cell according to a control signal and a data signal supplied from the controller 21 and voltages supplied from the reference voltage generator 23 and the power supply voltage generator 25. I do.

FIG. 8 is a block diagram showing a first configuration of the control unit 21 shown in FIG. As shown in FIG. 8, the control unit 21 includes shift registers 31 and 32, AND circuits 33 and 34, an exclusive OR circuit (XOR) 35, a delay flip-flop (D-FF) 37, a mask signal creation circuit 39, It includes one driver counter 41 and a start pulse creation circuit 43.

Here, the data signal DATA and the clock signal CLK are supplied to the shift register 31, and the shift register 32 is connected to the shift register 31. The input node of the exclusive OR circuit (XOR) 35 is connected to the output node and the input node of the shift register 31. The delay flip-flop (D-FF) 37 is XOR3
5 is supplied with a clock signal CLK. Also,
The mask signal creation circuit 39 is connected to the D-FF 37 and one driver counter 41.

The AND circuit 33 includes a shift register 3
2 and a mask signal generation circuit 39,
Outputs DATAOUT. The AND circuit 34 is supplied with the clock signal CLK and the signal Se output from the mask signal creation circuit 39, and outputs a clock signal CKOUT.

The one driver counter 41 is supplied with a clock signal CLK and a horizontal synchronization signal HSYNC. And
The start pulse generation circuit 43 is connected to the D-FF 37 and the one-driver counter 41, and also receives a clock signal CL.
K and the horizontal synchronization signal HSYNC are supplied, and data capture start signals (start pulses) C1 to Cn are generated and supplied to each data driver included in the data driver 29.

Here, the start pulse C1 is supplied to the first data driver, the start pulse C2 is supplied to the second data driver, the start pulse C3 is supplied to the third data driver, and the start pulse C4 is supplied to the third data driver. And supplied to the fourth data driver.

In the above description, the shift registers 31 and 32
Is large enough to hold data output by one driver at a time.

The operation of the control unit shown in FIG. 8 will be described below with reference to FIG. Note that, as shown in FIG. 9, a time T2 from time T1 and a time T2 from time T2.
3. During each period (also referred to as a “driver reading period”) from time T3 to time T4, time T4 to time T5, and time T5 to time T6, a data group supplied to each corresponding data driver is a data signal. The same data signal A is supplied to the control unit as DATA, for example, the same data signal A is supplied to the first data driver and the second data driver, the data signal B is supplied to the third data driver, and the data signal C is supplied to the fourth data driver. The case where each is supplied will be described.

First, as shown in FIG. 9A, between time T1 and time T2, the data signal A supplied to the first data driver is stored in the shift register 31. When the same data signal A as the data signal DATA supplied to the second data driver is input to the shift register 31 during the next driver reading period, the data signal A supplied to the first data driver is 32.

At this time, the exclusive OR circuit 35 outputs the signal Sa shown in FIG. 9C output from the shift register 31 and the data signal DA input to the shift register 31.
Compared with TA, since the data signal A is the same, a high-level signal is output. And this signal is D-FF3
7 and the time T as shown in FIG.
A signal Sc which becomes high level during one driver read period from time 2 to time T3 is generated.

Next, the mask signal generation circuit 39 latches the signal Sc by the clock signal Sd shown in FIG.
Then, the mask signal creation circuit 39 outputs the clock signal Sd supplied first after the signal Sc transitions to the low level.
, A signal Se which is at a low level during one driver read period is generated and output.

Thus, the AND circuit 33 calculates the logical product of the signal Se shown in FIG. 9G and the signal Sb shown in FIG. The output data signal DATAOUT is output to the driver, and AND
The circuit 34 includes the clock signal CLK shown in FIG.
By taking the logical product with the signal Sb shown in FIG. 9D, the clock signal CKOUT shown in FIG. 9I is output to the driver.

On the other hand, as shown in FIG. 9 (j) and FIG. 9 (k), the start pulse generating circuit 43 changes the time T3 when the supplied signal Sc transitions from the high level to the low level.
Start pulses C1 and C2 simultaneously activated in
Is supplied to the first data driver and the second data driver, respectively. As a result, the first and second data drivers simultaneously take in the same data signal A supplied between time T3 and time T4 according to the start pulses C1 and C2, respectively.

As shown in FIGS. 9 (l) and 9 (m), the start pulse C3 generated by the start pulse generation circuit 43 is activated at time T5.
Since the start pulse C4 is activated at the time T6, as shown in FIG. 9H, the third data driver takes in the data signal B in response to the start pulse C3, and the fourth data driver inputs the start signal C4. Fetches the data signal C according to.

As described above, for example, when supplying the data signal A to the first data driver, the start pulse C
By activating the start pulse C2 to the high level at the same time as the step 1, the data signal A can be simultaneously supplied to the second data driver. Therefore, in this case, it is not necessary to supply the data signal to the second data driver during the one-driver reading period immediately after the data signal is supplied to the first data driver. As shown in (1), there is no need to supply the clock signal CKOUT to the data driver, and the clock signal CKOUT can be stopped. Thus, the EMI level due to the clock signal CKOUT can be reduced.

Here, instead of temporarily stopping the clock signal CKOUT supplied to the data driver as described above, as shown in FIG. 10, a clock signal CKOUT obtained by dividing the clock signal CLK by, for example, 2 is generated. Along with
A data signal A 'having a double cycle of the data signal A is supplied to the first and second data drivers from the time T3 to the time T5, and the first and second data drivers are synchronized with the clock signal CKOUT. Data signal A 'to driver at the same time
EMI level can be reduced in the same manner as described above.

The following is a more detailed description. Figure 1
FIG. 1 is a block diagram illustrating a second configuration of the control unit illustrated in FIG. 7. The control unit shown in FIG. 11 has the same configuration as the control unit shown in FIG.
(First-Out) circuit 45, a divide-by-2 circuit 55, a divide-by-2 clock select circuit 53, and a select circuit 51.

Here, the FIFO circuit 45 is connected to the shift register 32, and the clock signal CL is supplied to the divide-by-2 circuit 55.
K is supplied. In addition, the divided-by-2 clock select circuit 5
3 is connected to the 1-driver counter 41 and the selection circuit 51
Are connected to an AND circuit 34.

In the control unit having the above configuration, the divide-by-2 circuit 55 divides the frequency of the clock signal CLK shown in FIG. 12 (b) by 2, and the clock signal CLK shown in FIG. 12 (c). Generate 2XCLK. The frequency-divided-by-2 clock select circuit 53 outputs the signal Sc shown in FIG.
2 and a time T3, the signal Sf (see FIG. 5) which becomes a high level during a period (from time T3 to time T5) in which the same data signal A is supplied to the first and second data drivers. 12 (i)).

As shown in FIG. 12 (k), the selection circuit 51 responds to the supplied signal Sf between the time T3 and the time T5 to select the clock signal 2X shown in FIG. 12 (c).
CLK is selectively output as the clock signal CKOUT from the clock signal CLK shown in FIG. 12B after the time T5.

On the other hand, the FIFO circuit 45 is connected to the AND circuit 34.
In response to the clock signal CLK supplied to the w terminal from the time T3, the data signal A supplied from the shift register 32 is taken in between the time T3 and the time T4, and at the time T3
The data signal A is output as the data signal A 'shown in FIG. 12 (j) in response to the clock signal CKOUT (FIG. 12 (k)) supplied from the selection circuit 51 during the period from to T5.

The data driver 29 according to the first embodiment can be constituted by data drivers 59 to 63 arranged side by side as shown in FIG. here,
The corresponding display start signals C1 to Cn are supplied to the data drivers 59 to 63 shown in FIG.
The timing of taking in the data signal DATA is controlled for each of the data drivers 59 to 63.

The display start signals C1 to Cn
Can be generated, for example, by a decoder 65 connected to an address line, as shown in FIG. Here, the decoder 65 generates the display start signals C1 to Cn by decoding the supplied addresses D1 to D4, as shown in FIGS. 15A and 15B. According to such a data driving unit 29, the display start signals C1 to C
n can be controlled.

As shown in FIG. 16, instead of providing the decoder 65 shown in FIG. 14, a decoder 80 is incorporated in each data driver 66, and as shown in FIG. They may be juxtaposed.

As described above, according to the liquid crystal display device of the first embodiment of the present invention, when the same data signal is supplied to a plurality of data drivers, the clock signal for transferring the data signal is stopped. Alternatively, since the frequency of the clock signal can be reduced, the EMI level and power consumption can be reduced. [Embodiment 2] In a conventional liquid crystal display device, single edge driving or double edge driving is generally adopted. Here, "single-edge driving", as shown in FIG. 18, uses one edge of a clock signal having a period T, that is, for example, a timing of transition from a low level to a high level, and causes a data driver to capture a data signal. Refers to the driving method. Further, as shown in FIG. 19, "double edge driving" refers to a driving method in which a data signal is taken into a data driver using both edges of a clock signal having a period of 2T, that is, a timing at which a logic level changes.

As shown in FIG. 20, a clock signal (double edge clock signal) having a period of 2T is provided by a delay flip-flop (D-FF) circuit 81 and an inverting circuit 83.
Is generated by a circuit composed of Here, the input node of the inverting circuit 83 is connected to the output node of the D-FF circuit 81, and the output node of the inverting circuit 83 is connected to the D terminal of the D-FF circuit 81.

In a circuit having such a configuration, D
A signal (single edge clock signal) having a period T shown in FIG. 21A is supplied to a CK terminal of the FF circuit 81, and a double edge signal shown in FIG. A clock signal is output.

Here, conventionally, even in a circuit which can execute the two types of driving, the single edge driving and the double edge driving, only one of the driving methods is fixedly employed. A method of eliminating noise of a clock signal using beads (coils) or the like has been adopted.

However, the method using a filter or a bead as described above also affects the phase relationship between the clock signal and the data signal, so that the EMI level cannot always be reduced to a good value. .

In recent years, a method of finely changing the frequency of a clock signal to disperse noise peaks of harmonics has been adopted. In this method, a clock signal whose frequency fluctuates is asynchronous with the original clock signal. Therefore, there is a problem that it is not possible to synchronize with the data signal, and there is also a problem that the cost increases due to the necessity of using a dedicated IC.

Hereinafter, a liquid crystal display device according to a second embodiment of the present invention, which solves the above problem by dispersing the peak frequency of EMI noise generated from a clock signal, will be described.

The liquid crystal display according to the second embodiment of the present invention has the same configuration as the liquid crystal display according to the first embodiment shown in FIG. 7, but each data driver included in the data driver is It can be driven by any driving method of single edge driving and double edge driving,
The difference is that which driving method is selected according to the supplied control signal. This will be described more specifically below.

FIG. 22 is a diagram showing a selection circuit included in the control unit constituting the liquid crystal display according to the second embodiment of the present invention. As shown in FIG.
A single edge clock signal is supplied to the terminal, a double edge clock signal is supplied to the B terminal, and a control signal is supplied to the S terminal.

Here, the selection circuit 84 selectively outputs either a single edge clock signal or a double edge clock signal according to the control signal. Here, the control signal can be arbitrarily created in the control unit.
As shown in FIG. 3, if the data driver inverts the display data at the time T _INV after latching the valid display data, it is possible to avoid a failure in capturing the data signal.

FIG. 24 is a diagram showing a configuration of the data driver 95 in the liquid crystal display device according to the second embodiment. As shown in FIG. 24, the data driver 95 includes a first data register 91 and a second data register 93, and a selection circuit 89 and an inversion circuit 87. Here, the data signal DATA is sent to the first and second data registers 91 and 93.
However, the clock signal CLK is supplied to the first data register 91 and the A terminal of the selection circuit 89 and the inversion circuit 87.
A control signal is supplied to the S terminal of
Is supplied via The output node of the inverting circuit 87 is connected to the B terminal of the selecting circuit 89, and the output node of the selecting circuit is connected to the second data register 93.

Data driver 9 having such a configuration
5, the first and second data registers 91, 93
In both cases, the data signal DATA is taken in only at the so-called rising timing when the input clock signal transitions from the low level to the high level.

On the other hand, the data signal shown in FIG.
FIG. 25B shows a single edge clock signal for DATA.
25, the double edge clock signal shown in FIG. 25C is generated based on the single edge clock signal, and the inverted circuit 87 generates the double edge clock signal shown in FIG.
5 (d) is generated.

When the data driver 95 is driven by the double edge, even-numbered data signals are taken into the corresponding register even if the double edge clock signal shown in FIG. 25C is supplied. Therefore, the selection circuit 89 is controlled by the control signal so that the inverted double edge clock signal shown in FIG. 25D is supplied to the even-numbered registers. That is, in the selection circuit 89 corresponding to the even-numbered register, the signal output from the inversion circuit 87 is selectively output according to the supplied control signal.

As described above, according to the liquid crystal display device according to the second embodiment of the present invention, single-edge driving and double-edge driving can be arbitrarily switched with a simple configuration, so that EMI noise generated from a clock signal can be reduced. By dispersing the peak frequency, the EMI level can be reduced. [Embodiment 3] The system drive clock of information equipment has been sped up by high-speed processing of data by the system. Accordingly, the circuit is driven by a high-frequency clock, so that the need to suppress the EMI noise level is increasing.

Here, conventionally, measures such as using beads or filters or strengthening the shield structurally have been taken. However, in the current situation where the driving frequency is increasing, it is only necessary to eliminate the noise of the clock waveform. There is a problem that cannot be dealt with by the above method.

One solution is to fluctuate the clock frequency to disperse the peaks of the harmonics.
This method has a problem in that the clock whose frequency has changed has an asynchronous relationship with the original clock, and thus cannot be synchronized with the data.

Therefore, in the liquid crystal display device according to the third embodiment of the present invention, the noise level concentrated at one point is scattered to another point by changing the change timing of the waveform determining the EMI noise level. , The noise level is reduced.

The n-th harmonic of the Fourier component in a general high-frequency pulse can be expressed by the following equation. aA + A / nπ × [√2 (1-cos2πan)] × sin (nωt +
φ) In the above equation, A indicates the amplitude, and a indicates the duty. Therefore, it can be understood from this that when the duty ratio changes, the harmonic changes. Hereinafter, the liquid crystal display device according to the third embodiment will be specifically described.

FIG. 26 is a block diagram showing a configuration of a liquid crystal display device according to Embodiment 3 of the present invention. As shown in FIG. 26, the liquid crystal display device according to the third embodiment includes:
Gate driver 27, data driver 29, liquid crystal panel 30
And a control unit 100. Here, the gate drive unit 2
7 and the data driving unit 29 are connected to the control unit 100, and the liquid crystal panel 30 is connected to the gate driving unit 27 and the data driving unit 29.
Connected to.

Further, the control unit 100 includes a gradation power supply
And a power supply generator 25, a driver control signal generator 97, and a data timing controller 99. Then, the driver control signal creation unit 97 creates signals for driving the gate drive unit 27 and the data drive unit 29, such as the gate clock GCLK and the data clock. The data timing control unit 99 synchronizes data with the data clock generated by the driver control signal generation unit 97.

FIG. 27 shows a structure of a circuit included in driver control signal generating section 97 and data timing control section 99 shown in FIG. As shown in FIG. 27, this circuit includes a delay circuit 101, delay flip-flops 103 and 111, AND circuits 105 to 107, an OR circuit 108, and a buffer 109. Then, a clock signal INCLK is supplied to the delay circuit 101 and the delay flip-flop 103 from outside the liquid crystal display device. Also,
The clock signal DCK0 and the clock signal INCLK output from the delay circuit 101 are supplied to the AND circuit 105.
The clock signal DCK1 output from the AND circuit 105 and the clock signal 2CK output from the delay flip-flop 103 are supplied to the ND circuit 106. The AND circuit 107 is supplied with the clock signal INCLK and the inverted clock signal / 2CK output from the delay flip-flop 103.

The OR circuit 108 has the AND circuit 1
The two signals output from 06 and 107 are supplied, the logical sum is calculated, and the duty clock signal DTYCK1 is generated. The duty clock signal DTYCK1 is buffered by the buffer 109. Further, a signal output from the buffer 109 and a signal INDATA supplied from outside the liquid crystal display device are input to the delay flip-flop 111, and a duty data signal DTYDT1 is generated.

Here, delay circuit 101 shown in FIG.
Is, for example, as shown in FIG. 28, a resistor R connected in series with a Schmitt trigger circuit 113 and a buffer 1
15. The delay circuit 10
29, a delay circuit 101a in which a capacitor C having one electrode grounded is provided in place of the resistance element R as shown in FIG. 29 may be used. The input clock signal is generated by the resistor R and the capacitor C.
The INCLK waveform is blunted. Further, the delay circuit 101
Is the input clock signal as shown in FIG.
The buffer 117 having a lower voltage level than INCLK and a buffer 118 for converting the level of an input signal to the same voltage level as the clock signal INCLK may be replaced by a delay circuit 101b configured in series.

The operation of the circuit shown in FIG. 27 will be described below with reference to the timing chart of FIG. First, as shown in FIG. 31 (1) and FIG. 31 (3), a clock signal externally input to the liquid crystal display device.
INCLK is delayed by the delay circuit 101 for a predetermined time to generate a clock signal DCK0. And the AND circuit 105
Is the clock signal INCLK shown in FIG.
An AND operation with the clock signal DCK0 shown in FIG. 31 (3) is performed to generate the clock signal DCK1 shown in FIG. 31 (3). Here, the clock signal DCK1 corresponds to a clock signal obtained by delaying only a so-called rising edge that transits from a low level (L) to a high level (H) with respect to the clock signal INCLK shown in FIG.

On the other hand, as shown in FIG. 31 (4) and FIG. 31 (5), the clock signal 2CK is generated by the delay flip-flop 103.
The logic level changes at each rising timing of the clock signal INCLK shown in (1), and the clock signal has a cycle twice as long as the clock signal INCLK. The inverted flip-flop 103 generates the inverted clock signal / 2CK shown in FIG. 31 (5) in which the clock signal 2CK is inverted.

The AND circuit 106 operates as shown in FIG.
The logical product of the clock signal DCK1 shown in (3) and the clock signal 2CK shown in FIG.
The circuit 107 receives the clock signal IN shown in FIG.
CLK and the inverted clock signal / 2CK shown in FIG.
And is calculated.

As a result, the OR circuit 108 outputs the signal shown in FIG.
The duty clock signal DTYCK1 shown in (6) is generated. That is, the duty clock signal DTYCK1
31 corresponds to the clock signal DCK1 shown in FIG.
The clock signal INCLK shown in (1) is a signal that is alternately repeated every clock, and is a signal whose duty ratio changes every other clock.

Then, the delay flip-flop 111
The data signal INDATA is converted to the duty clock signal DTYCK1
And generates and outputs the duty data signal DTYDT1 shown in FIG. 31 (7). Here, this duty data signal DTYDT1 is obtained by comparing FIG. 31 (6) and FIG.
As shown in (7), the duty clock signal DTYC
The data is synchronized with the so-called rising timing of K1.

The duty clock signal DTYCK1
The duty data signal DTYDT1 is supplied to the data driver 29 shown in FIG. At this time, the respective data drivers included in the data driver 29 transmit the duty data signal DTYDT1 at times T1 to T5 when the duty clock signal DTYCK1 transitions from the high level to the low level.
Respectively.

In the above description, the clock signal INCLK
Has been described for a predetermined time by the delay circuit 101 shown in FIG. 27, but the clock signal INCLK is delayed in parallel by a plurality of delay elements having different delay constants, and a plurality of generated signals having different phases are generated. The duty clock signal may be alternately supplied to the AND circuit 105 at an arbitrary time.

As described above, according to the liquid crystal display device of the third embodiment of the present invention, a clock signal in which only the rising edge of clock signal INCLK supplied from the outside of the liquid crystal display device is generated is generated and transmitted to the data driver. Therefore, data can be taken into the data driver by the duty clock signal DTYCK1 synchronized with the clock signal INCLK and the data signal, and the generated harmonics can be dispersed to lower the EMI peak. [Embodiment 4] In the display of a half tone, the problem that the whole image becomes white and the contrast is reduced as shown in FIG. 6 is a problem peculiar to the MVA type liquid crystal display device or the liquid crystal panel in which the alignment is divided. It turned out to be.

FIG. 32 shows a TV characteristic (applied voltage of transmittance) in the lower viewing angle direction of the MVA type liquid crystal panel (the liquid crystal molecules respond in such a manner as to tilt in four directions of upper right, lower right, upper left and lower left). Dependency). As shown in FIG. 32, the TV characteristic undulates in the portion 17 corresponding to the halftone. This is because the substantial birefringence of the liquid crystal molecules tilted toward the viewer of the liquid crystal panel becomes small. Responsible.

On the other hand, FIG. 33 is a histogram showing the relationship between the gradation of the image shown in FIG. 5, which is a typical picture in which the entire image becomes white, and the number of dots on the display surface. FIG.
As can be seen from FIG. 7, the number of dots near black is not so large, but the number of dots is large in the portion 19 indicating an intermediate tone. Since the halftone having such a large ratio of the number of dots undulates as seen in the portion 17 in FIG. 32, the contrast between the halftones is greatly reduced, and as a result, the display becomes light overall as a whole. It is thought that it looks whitish.

The refractive index anisotropy of the liquid crystal panel is Δ Δ
n, and when the thickness of the liquid crystal cell (cell thickness) is d, when the product of these is changed to 245 nm, 287 nm, or 345 nm, the TV characteristics observed from the front and lower viewing angles are shown in FIG. As shown in FIG. Incidentally, the above refractive index anisotropy [Delta] n, when n ₁ the refractive index components in the major axis direction of liquid crystal _molecules, the refractive index components in the major axis perpendicular to the direction of liquid crystal molecules was n _2, (n ₁ - n ₂ ).

That is, specifically, the refractive index anisotropy is
When 0.082, set the cell thickness to 3μm, 3.5μm or 4.2μm
35 to FIG. 37 respectively show the TV characteristics when changing.

Here, as shown in FIG. 35, when the cell thickness is 3 μm, the TV characteristic is almost monotonous, whereas when the cell thickness is 4.2 μm, it is shown in FIG. Thus, it can be seen that the TV characteristic undulates at the viewing angles of 60 degrees and 80 degrees in the halftone. As shown in FIG. 36, when the cell thickness is 3.5 μm, the case where the cell thickness shown in FIG.
It can be seen that the cell takes an intermediate state when the cell thickness is 4.2 μm.

From the above, it is understood that the larger the product of the refractive index anisotropy Δn of the liquid crystal panel and the cell thickness d, the greater the swell of the TV characteristics, and the above-mentioned phenomenon of the image becoming whitish is likely to occur. I understand.

Therefore, in the liquid crystal display device according to Embodiment 4 of the present invention, the larger the product of the refractive index anisotropy Δn and the cell thickness d in the liquid crystal panel, the larger the γ value in the TV characteristics. In the graph of grayscale-luminance characteristics shown in FIG. 34 where the display luminance when white is set to 100 is the vertical axis (log scale) and the display grayscale is the horizontal axis (log scale), The slope of the graph at the high part is defined as the γ value. FIG. 34 shows graphs of γ values of 2 and 3, respectively.

Here, in the liquid crystal display device according to Embodiment 4 of the present invention, the γ value is set so as to satisfy the following condition (1). γ = Δnd (unit of nm) × 0.008 ± 30%, and γ> 1.9 (1) And, more specifically, the product Δnd · d of the liquid crystal panel is
When 280 nm is set, γ is 2.0 to 2.3, and when the product Δn · d of the liquid crystal panel is set to 345 nm, γ is 2.15 to 3
It was adjusted appropriately by about ± 30%.

The principle of the liquid crystal display according to the fourth embodiment of the present invention will be described below. When a large value is set as the γ value, the display luminance at a large gradation becomes a value lower than the maximum luminance. For example, as shown in FIG. 34, when the γ value is 2, the display luminance at the 100th gradation is about 15% of the maximum white luminance (100 × (100/2
56) Where ² ≒ 15.2), 6% when γ is 3
(100 x (100/256) ³ $ 5.96). This means that the larger the γ, the lower the luminance when displaying the same gray scale becomes, and as a result, the voltage applied to the liquid crystal panel becomes a relatively low value.
That is, when γ is large, when displaying a certain image, the image is displayed by applying a relatively low voltage.

In the liquid crystal display device according to the fourth embodiment, when the product Δn · d in the liquid crystal panel has a relatively large value, the γ value has a large value. this is,
When the product Δn · d is a large value as described above, this corresponds to expressing an image with a relatively low driving voltage.

When the γ value is set as described above,
As the TV characteristics shown in FIG. 32, a halftone is displayed at a drive voltage lower than the undulating drive voltage at the TV characteristics at the up, down, left, and right viewing angles. In this case, when viewing the TV characteristics in the vertical, horizontal, and horizontal viewing azimuths in the region used for display, since the brightness changes in accordance with the voltage change, the decrease in contrast at an oblique viewing angle in halftone is suppressed. Can be Therefore, in the liquid crystal display device according to the fourth embodiment, black-and-white contrast and white luminance are maintained.

Further, by allocating fine gradations to the black-side halftone, it is possible to avoid black crushing, and to use only the black-side halftone before the TV characteristic swells as the halftone, thereby using the black-side halftone. The halftone contrast can also be maintained. In addition, each color is emphasized so that the reddish skin color is more reddish, the bluish color is more blue, and the leaves of greenish trees are more green.

By the way, in the liquid crystal display device according to the fourth embodiment, the γ value is changed, but it is important that the actual γ value itself is about 2 in accordance with the CRT. Here, in an MVA-type LCD (liquid crystal display device) in which the γ value is set to a relatively large value in order to realize a bright display, if the γ value is set to 2, a whitish image occurs in the vertical and horizontal viewing angles of the image. Is useless, but the product Δ
In an MVA type LCD having a small n · d, a natural color tone in front display can be realized by setting the γ value to about 2.

FIGS. 38 and 39 are graphs showing the simulation results of the gradation-luminance characteristics when the γ value is actually adjusted. Here, the vertical axis represents white luminance of 100.
And the horizontal axis represents the maximum gray scale as 1
The gray scale when normalized to 00 is shown on a log scale. The solid line shows the gradation-luminance characteristic at the lower viewing angle of 60 degrees, and the broken line shows the characteristic in the front. In this simulation, the MVA LC
It was assumed that D quadrant panels were used.

FIG. 38 shows the characteristic when the γ value is 2, and it can be seen that the change of the luminance with respect to the gradation in the halftone in the portion 119 is small. This is because the undulating portion of the TV characteristic is mainly used in the halftone. On the other hand, FIG. 39 shows the characteristics when the γ value is corrected to a relatively large value of about 3. As shown in a portion 121, even in the halftone, the luminance increases with a predetermined gradient with respect to the gradation. It can be seen that the relationship is as follows. This is because a portion of the TV characteristic accompanied by undulation is set to a higher gradation side.

As described above, the γ value itself is 2
The degree is important for realizing the natural color of the display in front. From this, the product Δn · d is
With the current MVA type LCD of 345 nm, the γ value from 2.2
Approximately 3 and the γ value for LCDs with a product Δn · d of 280 nm, etc.
It is important to set it to around 2 or 2.2.

FIG. 40 shows the result of verification while comparing the actual display state. The vertical axis is the optimal γ
The horizontal axis represents the product Δnd · (n
m). Here, as shown in FIG. 40, good image display can be realized in the vertical line portion satisfying the above condition (1), and further, the best image can be obtained at each point constituting the dashed line shown in FIG. The display was realized.

In general, when the γ value is set to a large value, a clearer image display can be obtained, but the naturalness as seen in a natural image tends to be impaired. Or adjust it.

The adjustment of the γ value in the above is performed by, for example, as shown in FIG. 41, a plurality of variable resistors 125 connected in series between a 5-volt power supply node and a ground node.
In this case, the gray scale voltages v1 to v4 supplied to the data driver can be adjusted by appropriately changing the resistance values.

As described above, according to the liquid crystal display device of Embodiment 4 of the present invention, the display / viewing angle characteristics of the MVA type LCD can be improved. In particular, good viewing angle characteristics can be realized even when the product Δn · d is large, and as a result, an MVA liquid crystal display with higher display luminance can be realized. [Fifth Embodiment] The liquid crystal display device according to the fifth embodiment of the present invention solves the problem described in the fourth embodiment, that is, the problem that the whole image becomes white and the contrast is reduced in displaying a halftone image. Things.

FIG. 42 is a plan view showing a layout of a display area in a conventional MVA type liquid crystal display device. FIG.
As shown in FIG. 2, the display area in the conventional MVA type liquid crystal display device is a bank-shaped dielectric structure 127 formed on a pixel electrode substrate provided on the lower side as viewed in FIG.
An image (line) when orthogonally projected on the same plane between the dielectric structure 203 formed on the common electrode substrate disposed on the front side of FIG. It is juxtaposed to have. In addition, as shown in FIG. 42, the above lines form a group of parallel lines rising to the right in the upper half of the display area and a group of parallel lines falling to the right in the lower half. It should be noted that the upper half and the lower half of the display area may have opposite directions.

In the display region having the above structure, the liquid crystal molecules are oriented in the direction shown by the arrow.

Here, in the display region of the liquid crystal display device according to the fifth embodiment, the structure is such that the ratio of the region where the liquid crystal molecules are inverted at the upper viewing angle is reduced. That is, a region in which the liquid crystal molecules are oriented to be inclined upward in the drawing is reduced, and a region in which the liquid crystal molecules are oriented to be inclined downward is increased.

FIG. 48 shows a conventional MVA type LCD, that is, an area ratio of a region where liquid crystal molecules are inclined to the upper right or upper left (inverted region) to a region where the liquid crystal molecules are inclined to the lower right or lower left (non-inverted region) is 1: 1. FIG. 49 shows the TV characteristics of the liquid crystal display device having the ratio of 1: 1.5.
FIG. 50 shows simulation results showing the TV characteristics of the liquid crystal display device in which the above ratio is 1: 4.

Here, as shown in FIG. 43, as a method for increasing the region where the liquid crystal molecules are tilted to the lower right or lower left in the figure, as shown in FIG. The dielectric structures 127 and 203 are juxtaposed while changing the intervals of every other so that the inclined region is wide and the region inclined to the upper left is narrow. In the lower half of the display area, the area where the liquid crystal molecules are inclined to the lower left is wide, and the area where the liquid crystal molecules are inclined to the upper right is narrower. I do. In the conventional display area shown in FIG. 42, each of the dielectric structures 127 and 203 is formed continuously between the upper half area and the lower half area, but is shown in FIG. As described above, in the display region according to the fifth embodiment, both portions are formed discontinuously.

According to the layout as shown in FIG. 43, the contrast tends to decrease in the lower viewing angle direction, but when the monitor is placed on the desk, the lower viewing angle direction is preferable. It is unlikely to see from. On the other hand, there are many cases where the monitor is observed from the direction of the upper viewing angle while standing, but in this case, an image display in which the contrast does not decrease is realized.

As shown in FIG. 48, in the conventional MVA type LCD, it can be seen that the TV characteristic is wavy as the viewing angle is increased. Note that, as described above, the undulation of the TV characteristics causes a decrease in the contrast of the displayed image. From this, when the ratio of the liquid crystal molecules tilting to the upper right or upper left, which is the cause of the ripple of the TV characteristic as described above, is reduced, the region where the liquid crystal molecules tilt upward in FIG. FIG. 50 (when the ratio of the region where the liquid crystal molecules are tilted upward to the region where the liquid crystal molecules are tilted downward is 1: 4 in the drawing). As shown in FIG. This is because the characteristics of the liquid crystal molecules inclined to the lower right or lower left appear preferentially.

The case where the present invention is applied to an MVA type liquid crystal display device will be described below. FIG. 44 is a plan view showing a layout of a display area in a conventional MVA liquid crystal display device. As shown in FIG. 44, a TFT substrate constituting a conventional MVA type liquid crystal display device has an IT substrate.
An O pixel electrode 201, a data electrode DE for transmitting a data signal to the ITO pixel electrode 201, a gate electrode GE forming a gate of the TFT, an auxiliary capacitance electrode GL for forming an auxiliary capacitance, and a slit portion 205 are formed. .

On the other hand, a bank-shaped dielectric structure 203 is formed on a counter substrate (also referred to as a common electrode substrate or CF substrate) facing the TFT substrate. Note that a similar effect can be obtained even if a slit is formed instead of the dielectric structure 203.

On the other hand, in the display area of the liquid crystal display according to the fifth embodiment, as shown in FIG.
A slit 206 is formed in the ITO pixel electrode 202 on the T substrate, and the tilt direction of the liquid crystal molecules is defined by an oblique electric field generated in this portion. Here, as shown in FIG. 47, bank-shaped dielectric structures 209 and 203 are provided on both the TFT substrate and the counter substrate, and the electric field from the ITO pixel electrode 202 is inclined so that the inclination direction of the liquid crystal molecules is increased. May be defined. This will be described more specifically below.

Although the layout of the display area shown in FIG. 47 is relatively simple, the dielectric structure 209,
When each of the dielectric structures 209 and 203 is provided on the TFT substrate or the opposite substrate, the distance between the dielectric structures 209 and 203 is increased every other line. Further, in order to increase the ratio of the liquid crystal molecules inclined in the lower viewing angle direction, the dielectric structure 209 formed on the TFT substrate and the dielectric structure 203 formed on the opposing substrate are arranged in an upper half and a lower half in the drawing. It is provided so as to form the shape of "ku". That is, in the conventional liquid crystal display device shown in FIG. 44, the dielectric structure 203 formed on the opposing substrate is continuously provided so that the upper half and the lower half of the drawing form a "<". However, in the display region according to the fifth embodiment shown in FIG. 47, the substrate on which the dielectric structure having the “<” shape is to be formed is composed of the upper half and the lower half of the display region. Is replaced with

By adopting such a layout, a favorable range of the viewing angle can be increased only in the upper viewing angle. That is, in the regions B and C shown in FIG. 47, the liquid crystal molecules are inclined downward. However, since these regions are wide, the viewing angle characteristics in the upper viewing angle direction are improved.

On the other hand, the layout shown in FIG. 45 is basically the same as the layout shown in FIG. 47, except that the dielectric structure 2 formed on the TFT substrate is formed.
09 and a slit 206 in the ITO pixel electrode 202
Is formed. In the layout shown in FIG. 47, the dielectric structure 209 can be formed at an arbitrary position, whereas in the layout shown in FIG. 45, a slit is formed up to the end where the electrode is laid. Cannot be stretched. At this time, as shown in a portion 207 in FIG. 45, the slit 206 may connect the slits within the pixel and partially close the slits in the middle.

In the layout shown in FIG. 46, the layout of the slit 205 is prioritized.
The dielectric structure 203 and the slit 205 formed in the upper half and the lower half of the display area shown in the figure are connected together and formed integrally. According to this layout, continuity between adjacent pixels can be maintained, and the orientation of liquid crystal molecules can be evenly distributed in the vertical direction. Thus, the left and right viewing angle characteristics can be made symmetric.

As described above, according to the liquid crystal display of Embodiment 5 of the present invention, the viewing angle characteristics of the MVA liquid crystal display can be significantly improved. In particular, it is possible to improve the viewing angle characteristics in a specific azimuth such as the upper viewing azimuth, which is important as a monitor. [Embodiment 6] In the MVA liquid crystal display device described above, there is a problem that the response speed in displaying a halftone image is slow. For example, in an image in which a person moves under a background such as dim light, there has been a problem that the hair has a tail. This is, as shown in FIG.
Dielectric structure 13 and slit 20 of MVA type liquid crystal panel
This is because all of the liquid crystal molecules 15 between them move. FIG. 51A is a graph showing the light transmittance of each portion of the liquid crystal panel having the structure shown in FIG. 51B.

Here, all the liquid crystal molecules 15 move because:
This is because in the MVA type liquid crystal display device, although the liquid crystal molecules 15 near the slit 205 or the bank move first, the entire threshold voltage is the same. This is because the electric field is uniformly applied to the entire liquid crystal panel.

As described above, in displaying a halftone image, there is a problem that the displayed image becomes whitish. However, as shown in FIG. This is because the V characteristic undulates.

Therefore, in the liquid crystal display device according to the sixth embodiment of the present invention, the electric field applied to the liquid crystal molecules 15 is partially concentrated, so that the liquid crystal molecules 15 are driven at a low voltage and the liquid crystal molecules 15 are partially driven. Only the molecule 15 is made to respond. This will be specifically described below.

FIG. 52 is a view for explaining a first structural example in the liquid crystal display device according to the sixth embodiment of the present invention.
FIG. 52 (a) is a graph showing light transmittance at each location of the liquid crystal panel having the structure shown in FIG. 52 (b).

As shown in FIG. 52, the glass substrate 30
6, an electrode 211 and a SiN layer 308 are formed on the ITO pixel electrode 2 on which a slit 205 is provided.
04 is formed. On the other hand, an ITO pixel electrode 201 is formed on one surface of an opposing glass substrate 307, and a resin layer 302 is formed thereon. Here, the resin layer 302 includes
Almost immediately above the slit 205 formed in the ITO pixel electrode 204, a slit 208 slightly narrower than the slit 205 is formed. In addition, for example, the slit 20
The width of 5,208 can be between 3 μm and 20 μm. A color filter is formed on the glass substrate 307, but is omitted in FIG.

A bank-shaped dielectric structure 203 is formed on the resin layer 302. Here, the slits 205 and 208, the dielectric structure 203, and the gate electrode G
E, data electrode DE, and electrode 30 for forming auxiliary capacitance
5 are arranged according to the layout shown in FIG.
That is, the slits 205 and 208 and the dielectric structure 203 are laid out so as to be bent in a “<” shape in each pixel forming the display area, and the liquid crystal molecules 15
It is structured to be oriented in the direction.

As shown in FIG. 53, the slit 205 is provided so as to stop at the end of the ITO pixel electrode 201 in the pixel area, but the slit 208 can be formed across pixels.

According to the above structure, the resin layer 302
And the ITO pixel electrode 204
Since the slits 205 formed in the opposite directions are opposed to each other, an electric field particularly in an oblique direction is concentrated between them. That is, even if only the slit 205 is formed and the slit 208 is not formed in the resin layer 302, the electric field applied to the liquid crystal molecules 15 is oblique, but by providing the slit 208, the electric field is reduced. The tendency to generate obliquely increases.

Due to the effect of the oblique electric field generated as described above, as shown in a portion 301 of FIG. 52A, only the liquid crystal molecules 15 near the slits 205 and 208 are applied to the voltage applied. Response is preferentially increased to increase transmittance. At this time, the other liquid crystal molecules 15 also try to respond, but the threshold voltage increases due to the influence of the resin layer 302. Therefore, when the applied voltage is low, only the liquid crystal molecules 15 in the vicinity of the slits 205 and 208 respond, and the response does not spread to the surrounding liquid crystal molecules 15. Therefore, the response speed of the liquid crystal molecules 15 in the halftone is increased. Can be

Note that the dielectric structure 203 is formed of the liquid crystal molecules 15.
Is provided to define the direction of inclination of
In cooperation with the slits 205 and 208, the liquid crystal molecules 15 existing in the region LR are oriented leftward in the drawing, and the liquid crystal molecules 15 existing in the region RR are oriented rightward in the drawing.

Further, as the glass substrate 306, I
Since the slit 205 can be provided without adding a process when the TO pixel electrode 204 is generated, a TFT substrate on which a TFT is formed can be provided. Note that the glass substrate 306 shown in FIG. 52 can be used as a counter substrate.

The material of the resin layer 302 and the dielectric structure 203 is a positive resist.
Has a thickness of 0.1 μm to 2 μm, and the height of the dielectric structure 203 is 0.5 μm to 4 μm. On the other hand, the electrode 21
1 can be formed by extending an auxiliary capacitance electrode below the slit 205, and the width of the electrode 211 is substantially the same as the width of the slit 205.

FIG. 54 is a diagram illustrating a second structural example of the liquid crystal display according to the sixth embodiment of the present invention.
As shown in FIG. 54, the second example is the same as the first example, except that a bank-shaped dielectric structure 403 is formed on the glass substrate 307 or a color filter formed on the glass substrate 307. The difference is that the ITO pixel electrode 402 is provided so as to cover the dielectric structure 403. Here, the dielectric structure 403 is the slit 20
5, a bank-shaped dielectric structure 410 is formed on the ITO pixel electrode 402 and at an intermediate point between adjacent dielectric structures 403. In addition,
FIG. 55 is a plan view showing a layout of the liquid crystal panel shown in FIG.

According to such a structure, the dielectric structure 4
Since a large oblique electric field can be applied between the ITO pixel electrode 402 that covers the area 03 and the ITO pixel electrode 204 near the slit 205, the liquid crystal molecules in this area as shown in a portion 414 in FIG. Only 15 can respond preferentially by applying a low voltage to increase the transmittance. The electrode 211 has a function of concentrating the above-mentioned oblique electric field, and it is effective to make the same potential as the ITO pixel electrode 402.

Further, similarly to the first structure example, the glass substrate 306 can be a TFT substrate. And
The height of the dielectric structure 403 is 1.5 μm to 4 μm, preferably about 3 μm, and the width is 3 μm to 15 μm, preferably about 10 μm.

On the other hand, the height of the dielectric structure 410 is 0.3 μm.
m to 2 μm and a width of about 3 μm to 15 μm. Further, the distance between the dielectric structures 403 and 410 is about 10 μm to 40 μm.

FIG. 56 is a view for explaining a third structural example in the liquid crystal display device according to the sixth embodiment of the present invention.
As shown in the right half of FIG. 56, the liquid crystal display device according to the sixth embodiment differs from the second structure example shown in FIG. 54 in that a dielectric structure 617 is formed on the SiN layer 308. Further, a liquid crystal panel having an ITO pixel electrode 606 formed thereon may be provided. Note that such a structure is different from the dielectric structure 61 in place of the slit 205.
0, the glass substrates 306, 307
205 and dielectric structure 4 respectively formed in
03 corresponds to an upside down arrangement.

According to the above structure, the three dielectric structures 403, 610, 617 and the slit 20 are formed.
5, the response speed is fast and good alignment of the liquid crystal molecules 15 can be realized.

As shown in the left half of FIG. 56,
The liquid crystal display device according to the sixth embodiment differs from the structure example shown in the right half of FIG. 56 in that a thin resin layer 615 is further provided on the ITO pixel electrode 402, and a dielectric structure 616 is provided thereon. Provided with a liquid crystal panel on which is formed. According to such a structure, the resin layer 6
15 has the same effect as the resin layer 302 shown in FIG. 52, so that the difference between the threshold voltages of the liquid crystal molecules 15 in the display region is increased, and the response of the liquid crystal molecules near the dielectric structure 403 is increased. Speed can be increased more.
As shown in FIG. 56A, also in the structure shown in FIG. 56B, the liquid crystal molecules 15 near the dielectric structure 403 respond preferentially when a low voltage is applied.

Also, as shown in FIG. 57, the dielectric structure 403 in the structure shown in FIG. 54B is replaced with the dielectric structure 7 on which color filters (G, B) are superimposed.
03, the liquid crystal display device according to the sixth embodiment can be formed without increasing the number of manufacturing steps.

On the other hand, with respect to the phenomenon that the image becomes whitish as described above, the threshold characteristics of the liquid crystal molecules are made different in a part of the screen, and the viewing angle characteristics are improved by overlapping the different characteristics. It is effective to do this, but it will be specifically described below.

FIG. 59 is a diagram illustrating a fifth structural example of the liquid crystal display device according to the sixth embodiment of the present invention.
As shown in FIG. 59, in the fifth structure example, a dielectric layer 801 made of a resin is formed on an ITO pixel electrode 201 formed on a color filter substrate or a counter substrate, and a dielectric structure 803 is formed thereon. Is provided. Here, the dielectric layer 801 has a thickness of about 0.1 μm to 3 μm, and is formed of a resist material or the like.

In the process of forming such a structure, the portion where the dielectric structure 803 is to be formed is not irradiated with ultraviolet light at all, and the portion where the dielectric layer 801 is to be formed is slightly irradiated with ultraviolet light. The portion where the body layer 801 is not formed is sufficiently irradiated with ultraviolet rays. The ultraviolet light is
Irradiation can be performed several times using a plurality of masks.

Here, a fine pattern is provided on the mask,
By irradiating a substantially intermediate amount of ultraviolet rays, the tall dielectric structure 803 and the surrounding dielectric layer 801 can be formed simultaneously by one irradiation of ultraviolet rays. Further, the ratio of the dielectric layer 801 in the pixel portion is 10% or more and 90% or less, and the region where the threshold voltage is 1.2 times or more, particularly 1.5 times or less, is less than half (3 ± 2%) of the entire pixel region. %), Especially when only 30% are provided, the best image display can be realized.

FIG. 63 is a plan view showing the fifth structural example shown in FIG. As shown in FIG. 63, in order to maintain the symmetry of the viewing angle, the dielectric structure 803 is laid out vertically symmetrically around the center of the pixel. Are the same. The height of the dielectric structure 803 is 0.5 μm or more and 6 μm or more.
μm or less, and the height of the dielectric layer 801 is 0.1 μm or more and 3 μm or less.

In the above configuration, the dielectric layer 8
Since it is difficult for a voltage to be applied to the liquid crystal just below 01 and the threshold voltage increases, the transmittance in this portion decreases as shown in FIG.

Here, the TV of the portion where the threshold voltage is high is
The characteristics and the TV characteristics of the other parts are shown in FIG. The graphs G1a to G3a shown in FIG.
The viewing angle characteristics of the MVA type liquid crystal display device at an upper viewing angle of 80 degrees are shown. The graph G1a shows the TV characteristics of the other portions, the graph G2a shows the TV characteristics of a high threshold region,
The graph G3a shows the TV characteristics when 30% of the pixel area is provided with a high threshold area. As shown in the graphs G2a and G1a of FIG. 60, when viewed from an oblique direction, the region having a high threshold voltage has a TV voltage similar to other portions.
It can be seen that the characteristics undulate. Here, if 30% of the region having a high threshold voltage is provided, the swell becomes small as shown in the graph G3a, and the TV that monotonically increases is increased.
Properties can be obtained. Note that the graph G3a shown in FIG. 60 is such that the TV characteristic in the high threshold voltage portion increases near the voltage 2V where the transmitted light amount decreases in the TV characteristic in the other portion. Is the case.

As in FIG. 60, FIG. 61 shows the viewing angle improvement front characteristics of the MVA type liquid crystal display device, and the graph G1b
Shows the TV characteristics of the other portions, graph G2b shows the TV characteristics of the region with a high threshold, and graph G3b shows the TV characteristics when the region with a high threshold is provided 30% of the pixel region. Shown respectively. From FIG. 61, it can be seen that the viewing angle improving front characteristic when a region with a high threshold value is provided 30% of the pixel region is similar to the TV characteristics of the other parts.

FIG. 62 shows M at an upper right viewing angle of 80 degrees.
The viewing angle characteristics of the VA-mode liquid crystal display device are shown. The graph G1c shows the TV characteristics of the other portions, the graph G2c shows the TV characteristics of the high threshold region, and the graph G3c shows the high threshold region. The TV characteristics when 30% of the area is provided are shown. According to FIG. 62, the viewing angle characteristics when 30% of the pixel region is provided with a region having a high threshold value are the T.sub.
It can be seen that the characteristic approximates to the -V characteristic.

As shown in FIG. 64, in the liquid crystal display device according to the sixth embodiment, the dielectric layer 901 is formed not on the counter substrate but on the ITO pixel electrode formed on the TFT substrate (glass substrate 306). 204 may be provided. Here, the dielectric layer 901 is formed of resist or SiN. Since the dielectric constant of the resist is about 3 and the dielectric constant of SiN is about 7, when forming the dielectric layer 901 with SiN, the thickness is in the range of 0.1 μm to 5 μm. You.

In the above description, a similar effect can be obtained by a structure in which a slit is provided in the ITO pixel electrode, in contrast to a structure in which a bank-shaped dielectric structure is provided on the ITO pixel electrode. .

As described above, according to the liquid crystal display device of Embodiment 6 of the present invention, the response speed of the liquid crystal molecules 15, particularly the response speed in the half tone, can be greatly increased, and the viewing angle characteristics can be improved. (Supplementary Note 1) A liquid crystal display device including a plurality of data driving units that supply image data to a liquid crystal display unit that displays an image, wherein the image data supplied to at least two of the data driving units is the same. The liquid crystal display device further comprises control means for causing the at least two data driving means to simultaneously take in the image data. (Supplementary Note 2) A signal is provided on the substrate on which the plurality of data driving units are formed, and generates a signal for determining a timing of capturing the image data according to a signal supplied from the control unit. 2. The liquid crystal display device according to claim 1, further comprising a capture timing signal generation means for selectively supplying. (Supplementary Note 3) The liquid crystal display device according to Supplementary Note 1, further comprising a capture timing determination unit built in each of the data driving units and determining a timing of capturing the image data according to a signal supplied from the control unit. . (Supplementary Note 4) The control unit stops supplying a clock signal for determining the timing of capturing the image data to the data driving unit during a period in which the at least two data driving units do not need to capture the image data. 2. The liquid crystal display device according to claim 1, further comprising a clock signal supply unit. (Supplementary Note 5) The control unit includes a frequency dividing unit that reduces a frequency of an external clock signal that determines the timing of capturing the image data, and the control unit performs the at least one of the at least 2. The liquid crystal display device according to claim 1, wherein the same image data is transferred to two data driving units. (Supplementary Note 6) A liquid crystal display device including a data driving unit that captures image data in accordance with the supplied clock signal and supplies the image data to a liquid crystal display unit that displays an image, wherein the data driving unit is configured to execute the data driving. The timing of capturing the image data is either the first timing at which the clock signal transitions from the first logic level to the second logic level, or the second timing at which the clock signal transitions to a different logic level. A liquid crystal display device comprising control means for arbitrarily switching and setting. (Supplementary Note 7) A liquid crystal display device including a data drive unit that captures image data in accordance with the supplied clock signal and supplies the image data to a liquid crystal display unit that displays an image, wherein the duty ratio changes. A liquid crystal display device comprising: a control unit that generates a clock signal and supplies the clock signal to the data driving unit. (Supplementary note 8) The liquid crystal display device according to supplementary note 7, wherein the control unit changes the duty ratio, generates the clock signal synchronized with the image data, and supplies the clock signal to the data driving unit. (Supplementary Note 9) A method of manufacturing a liquid crystal display device for displaying an image on a liquid crystal panel including a liquid crystal cell, wherein the method is based on the thickness of the liquid crystal cell or the magnitude of birefringence of a liquid crystal layer included in the liquid crystal cell. And determining a γ value as an index of the gradation-luminance characteristics. (Supplementary Note 10) In a liquid crystal display device for displaying an image on a liquid crystal panel including a liquid crystal cell, a γ value which is an index of a gradation-luminance characteristic of the liquid crystal panel is a refractive index anisotropy of the liquid crystal cell. Wherein the thickness of the liquid crystal cell is d, the value is set to a value within a range of 0.008 times ± 30% of the product Δn · d and 1.9 or more. (Supplementary note 11) The liquid crystal display device according to supplementary note 10, wherein the product Δn · d is a value within a range of 350 nm ± 50 nm, and the γ value is set to be equal to or greater than 2.15 and equal to or less than 3. (Supplementary Note 12) The liquid crystal display device according to Supplementary Note 10, wherein the product Δn · d is a value within a range of 280 nm ± 50 nm, and the γ value is set to 2.0 or more and 2.3 or less. (Supplementary Note 13) A liquid crystal display device that displays an image by controlling the orientation of a plurality of liquid crystal molecules, wherein a first alignment region in which the liquid crystal molecules are oriented in a first direction when a voltage is applied, The liquid crystal molecules are oriented in a second direction opposite to the first direction when the voltage is applied, and a second alignment region having a width different from the first alignment region is provided. A liquid crystal display device characterized by the above-mentioned. (Supplementary note 14) The liquid crystal display device according to supplementary note 13, wherein a slit or a bank-shaped dielectric structure is formed, and further comprising an electrode for applying the voltage to the first alignment region and the second alignment region. (Supplementary Note 15) Further provided is a pair of substrates on each of which a slit or a bank-shaped dielectric structure is formed, and a liquid crystal layer including the first alignment region and the second alignment region is sandwiched therebetween. The gap between the first slit or bank-shaped dielectric structure formed on the substrate and the second slit or bank-shaped dielectric structure formed on the other substrate is alternately formed as 14. The liquid crystal display device according to supplementary note 13, wherein the liquid crystal display device has one length and a second length. (Supplementary Note 16) The first slit or the bank-shaped dielectric structure and the second slit or the bank-shaped dielectric structure are respectively on the same plane for each pixel displaying the image. 16. The liquid crystal display device according to supplementary note 15, wherein the orthographic projection is connected at one end to form two line segments forming a predetermined angle. (Supplementary Note 17) The first or second slit or the bank-shaped dielectric structure is connected at one end to at least one of the one or the other substrate for each pixel displaying the image. 16. The liquid crystal display device according to supplementary note 15, wherein a pattern formed by two line segments forming a predetermined angle is formed. (Supplementary Note 18) By aligning liquid crystal molecules contained in a liquid crystal layer narrowly disposed between the pixel electrode substrate and the counter substrate,
A liquid crystal display device for displaying an image, a first electrode formed on the entire surface of the counter substrate, a resin layer formed on the first electrode and having a first slit portion, A second electrode formed on the pixel electrode substrate so as to face the first electrode and having a second slit facing the first slit. (Supplementary note 19) The liquid crystal display device according to supplementary note 18, wherein the width of the first slit portion is smaller than the width of the second slit portion. (Supplementary note 20) The liquid crystal display device according to supplementary note 18, further comprising a bank-shaped dielectric structure formed on the resin layer. (Supplementary Note 21) By aligning liquid crystal molecules contained in a liquid crystal layer narrowly provided between the pixel electrode substrate and the counter substrate,
A liquid crystal display device for displaying an image, wherein a first dielectric structure having a bank shape provided on the counter substrate, and a first electrode formed so as to cover the counter substrate and the dielectric structure And a second electrode formed on the pixel electrode substrate and having a slit facing the dielectric structure. (Supplementary note 22) The liquid crystal display device according to supplementary note 21, further comprising a second dielectric structure provided on the first electrode and between the first dielectric structures. (Supplementary Note 23) The image forming apparatus further includes a third dielectric structure provided on the pixel electrode substrate and at a position facing the second dielectric structure, wherein the second electrode is provided with the third dielectric structure. 23. The liquid crystal display device according to supplementary note 22, formed to cover the body structure. (Supplementary note 24) The liquid crystal display device according to supplementary note 23, further comprising a dielectric layer formed between the second dielectric structure and the first electrode. (Supplementary note 25) The liquid crystal display device according to supplementary note 21, wherein the first dielectric structure includes a plurality of stacked color filter layers. (Supplementary Note 26) By aligning liquid crystal molecules contained in a liquid crystal layer narrowly disposed between the pixel electrode substrate and the counter substrate,
A liquid crystal display device that displays an image, wherein a first electrode formed on the entire surface of the counter substrate, a first dielectric structure formed on the counter substrate, or a first electrode formed on the first electrode A slit portion, a second electrode provided on the pixel electrode substrate to face the first electrode, and the first electrode or the slit near the first dielectric structure. And a dielectric layer covering the second electrode in the vicinity of the portion. (Supplementary Note 27) By aligning liquid crystal molecules contained in a liquid crystal layer narrowly provided between the pixel electrode substrate and the counter substrate,
A liquid crystal display device that displays an image, wherein a first electrode formed on the entire surface of the counter substrate, a dielectric structure formed on the first electrode, and the pixel electrode substrate, A second electrode provided to face the first electrode and the dielectric structure, and a dielectric layer formed on the second electrode and facing the dielectric structure. A liquid crystal display device comprising: (Supplementary Note 28) A first threshold voltage when driving the liquid crystal molecules facing the dielectric layer is a second threshold when driving the liquid crystal molecules not facing the dielectric layer. The first region in which the threshold voltage is 1.2 times or more the value voltage and the threshold voltage when driving the liquid crystal molecules is the first threshold voltage is the second threshold voltage. 28. The liquid crystal display device according to Supplementary Note 26 or 27, which is equal to or less than half of the second region.

As described above, according to the liquid crystal display device of the present invention, the clock signal for transferring the image data can be temporarily stopped or the frequency of the clock signal can be reduced. , EMI level and power consumption can be reduced.

Further, by dispersing the peak frequency of the EMI noise generated from the clock signal or the harmonic generated when displaying an image on the liquid crystal display means, the E
The MI level can be reduced.

According to the liquid crystal display device of the present invention, by selectively driving the liquid crystal molecules, the viewing angle characteristics can be improved and desired viewing angle characteristics can be easily realized.

Further, according to the method for manufacturing a liquid crystal display device according to the present invention, the display / viewing angle characteristics of the liquid crystal panel can be easily improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data driver in a conventional liquid crystal display device.

FIG. 2 is a block diagram showing a configuration of a data driver shown in FIG.

FIG. 3 is a perspective view illustrating a basic configuration of a conventional MVA liquid crystal display device.

FIG. 4 is a graph showing visual characteristics of black and white contrast in the liquid crystal display device shown in FIG.

5 is a diagram showing an example of a front display image displayed by the liquid crystal display device shown in FIG.

6 is a diagram illustrating a problem of the liquid crystal display device shown in FIG.

FIG. 7 is a block diagram illustrating a configuration of a liquid crystal display device according to Embodiment 1 of the present invention.

FIG. 8 is a block diagram showing a first configuration of a control unit shown in FIG. 7;

9 is a timing chart showing a first operation of the control unit shown in FIG.

FIG. 10 is a timing chart showing a second operation of the control unit shown in FIG.

FIG. 11 is a block diagram showing a second configuration of the control unit shown in FIG.

FIG. 12 is a timing chart showing an operation of the control unit shown in FIG.

FIG. 13 is a block diagram illustrating a configuration of a data driver illustrated in FIG. 7;

FIG. 14 is a block diagram showing another configuration of the data driver shown in FIG. 7;

FIG. 15 is a diagram illustrating the decoder shown in FIG.

FIG. 16 is a block diagram showing a configuration of a data driver according to the first embodiment of the present invention.

17 is a block diagram showing a configuration of a data driver configured by the data driver shown in FIG.

FIG. 18 is a timing chart showing a data fetch timing by a conventionally used single edge clock signal.

FIG. 19 is a timing chart showing a data fetch timing by a conventionally used double edge clock signal.

20 is a circuit diagram showing a circuit for generating the double edge clock signal shown in FIG.

21 is a timing chart showing the operation of the circuit shown in FIG.

FIG. 22 is a diagram illustrating a selection circuit included in a control unit according to the second embodiment of the present invention.

FIG. 23 is a timing chart showing an operation of the selection circuit shown in FIG. 22;

FIG. 24 is a diagram showing a configuration of a driver according to Embodiment 2 of the present invention.

FIG. 25 is a timing chart showing the operation of the driver shown in FIG. 24.

FIG. 26 is a diagram showing a configuration of a liquid crystal display device according to Embodiment 3 of the present invention.

FIG. 27 is a diagram illustrating a configuration of a circuit included in the control unit illustrated in FIG. 26;

28 is a diagram illustrating a first configuration example of the delay circuit illustrated in FIG. 27;

FIG. 29 is a diagram illustrating a second configuration of the delay circuit illustrated in FIG. 27;

FIG. 30 is a diagram illustrating a third configuration of the delay circuit illustrated in FIG. 27;

FIG. 31 is a timing chart showing the operation of the circuit shown in FIG. 27;

FIG. 32 is a graph showing TV characteristics of a conventional MVA liquid crystal display device.

FIG. 33 is a graph showing the gradation of an image in which the problem of the viewing angle characteristic becomes remarkable among the images displayed on the conventional MVA liquid crystal display device
It is a graph which shows a brightness histogram.

FIG. 34 is a graph illustrating the definition of the gradation luminance characteristic γ.

FIG. 35 shows a TV in a conventional MVA liquid crystal display device.
9 is a first graph showing the dependence of a characteristic on a product Δn · d.

FIG. 36 shows TV in a conventional MVA liquid crystal display device.
9 is a second graph showing the dependence of the characteristic on the product Δn · d.

FIG. 37 shows a TV in a conventional MVA liquid crystal display device.
11 is a third graph showing the dependence of the characteristic on the product Δn · d.

FIG. 38 is a first graph illustrating gradation-luminance characteristics in the liquid crystal display device according to Embodiment 4 of the present invention.

FIG. 39 is a second graph illustrating gradation-luminance characteristics in the liquid crystal display device according to Embodiment 4 of the present invention.

FIG. 40 is a third graph illustrating gradation-luminance characteristics in the liquid crystal display device according to Embodiment 4 of the present invention.

FIG. 41 is a diagram illustrating a method of adjusting the gradation-luminance characteristic γ in the liquid crystal display device according to the fourth embodiment of the present invention.

FIG. 42 is a plan view showing a layout of a display area in a conventional MVA liquid crystal display device.

FIG. 43 is a plan view showing a layout of a display area in the liquid crystal display device according to Embodiment 5 of the present invention.

FIG. 44 is a plan view showing a layout of a display area in a conventional MAV type liquid crystal display device.

FIG. 45 is a plan view showing an example of a layout of a display area in the liquid crystal display device according to Embodiment 5 of the present invention.

FIG. 46 is a plan view showing another example of the layout of the display area in the liquid crystal display device according to Embodiment 5 of the present invention.

FIG. 47 is a plan view showing still another example of the layout of the display area in the liquid crystal display device according to Embodiment 5 of the present invention.

FIG. 48 is a graph showing TV characteristics of the conventional liquid crystal display device shown in FIGS. 42 and 44.

FIG. 49 is a first graph showing TV characteristics of the liquid crystal display device according to Embodiment 5 of the present invention.

FIG. 50 is a second graph showing TV characteristics of the liquid crystal display device according to the fifth embodiment of the present invention.

FIG. 51 is a diagram illustrating a problem of a conventional MVA liquid crystal display device.

FIG. 52 is a diagram illustrating a first structural example of the liquid crystal display device according to the sixth embodiment of the present invention.

FIG. 53 is a plan view showing a layout of the liquid crystal display device shown in FIG. 52.

FIG. 54 is a diagram illustrating a second structure example of the liquid crystal display device according to the sixth embodiment of the present invention.

FIG. 55 is a plan view showing a layout of the liquid crystal display device shown in FIG. 54.

FIG. 56 is a diagram illustrating a third structural example of the liquid crystal display device according to the sixth embodiment of the present invention.

FIG. 57 is a cross-sectional view illustrating a fourth structure example of the liquid crystal display device according to the sixth embodiment of the present invention.

FIG. 58 is a graph showing TV characteristics at an upper viewing angle in a conventional MVA liquid crystal display device.

FIG. 59 is a diagram illustrating a fifth structure example of the liquid crystal display device according to the sixth embodiment of the present invention.

60 is a graph showing TV characteristics at an upper viewing angle in the liquid crystal display device shown in FIG. 59.

61 is a graph showing TV characteristics of the liquid crystal display device shown in FIG. 59 at a front viewing angle.

62 is a graph showing TV characteristics at the upper right viewing angle in the liquid crystal display device shown in FIG. 59.

FIG. 63 is a plan view showing a fifth example of the structure shown in FIG. 59;

FIG. 64 is a diagram illustrating a sixth structure example of the liquid crystal display device according to the sixth embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 1 output amplifier 3 D / A converter 5 latch circuit 7 shift register 9 clock controller 11 transparent electrode 13, 127, 203, 209, 403, 410, 61
0, 616, 617, 703, 803 Dielectric structure (bank) 15 Liquid crystal molecules 17, 19, 119, 121, 207, 301, 41
4,614 part 20 liquid crystal display device 21,100 control unit 23 reference voltage (gradation power supply) creation unit 25 power supply voltage creation unit 27 gate drive unit 29 data drive unit 30 liquid crystal panel 31,32 shift register 33,34,105- 107 AND circuit 35 Exclusive OR circuit (XOR) 37, 81, 103, 111 Delay flip-flop (D-FF) 39 Mask signal creation circuit 41 1 driver counter 43 Start pulse creation circuit 45 FIFO circuit 47 Mask signal creation circuit 51 , 84, 89 selection circuit 53 divided-by-2 clock selection circuit 55 divided-by-2 circuit 57 start pulse creation circuit 59-63, 66, 95, DV1-DVn data driver 65, 80 decoder 83, 87 inversion circuit 85 interface section (I / F) 91 First data register 93 Second data register 97 Driver control signal creation unit 99 Data timing control unit 101, 101a, 101b Delay circuit 108 OR circuit 109, 115, 117, 118 Buffer 113 Schmitt trigger circuit 125 Variable resistor 201, 202, 204, 402, 606 ITO pixel electrode 205, 206, 208 Slit 211, 305 Electrode 302, 615 Resin layer 306, 307 Glass substrate 308 SiN layer 404 Liquid crystal layer 801, 901 Dielectric layer SL Source line GL Auxiliary capacitance electrode GE Gate electrode DE Data electrode R Resistance Element C Capacitor LR, RR region G1a to G3a, G1b to G3b, G1c to G3c Graph

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 633 G09G 3/20 633G 633P (72) Inventor Tetsu Sekido 4 Kamikadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 1-1 1-1 Fujitsu Co., Ltd. (72) Inventor Hidefumi Yoshida 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Co., Ltd. (72) Inventor Takashi Sasababayashi 4 Ueodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 1-1 1-1 Fujitsu Limited (72) Inventor Koichi Katakawa 4-1-1 Kamiodanaka Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Katsuhiko Kishida Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture 4-1-1 1-1 Fujitsu Limited (72) Inventor Shinpei Nagatani 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. Fujitsu Limited (72) Inventor Yuichi Inoue 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Mikio Oshiro 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. Fujitsu Limited (72) Inventor Katsunori Tanaka 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Toshimitsu Minemura 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No.F-term in Fujitsu Limited (Reference) 2H090 HA16 KA04 MA01 MA13 2H093 NA16 NC13 NC23 ND13 ND31 ND60 NE10 5C006 AA01 AF46 AF72 BB12 BC12 BF03 BF06 BF07 BF09 BF22 BF23 BF24 BF26 BF43 FA32 FA54 FA10 EB05 A03 DD03 JJ06

Claims (10)

[Claims] 1. A liquid crystal display device comprising a plurality of data driving means for supplying image data to a liquid crystal display means for displaying an image, wherein the image data supplied to at least two of the data driving means is the same. In this case, the liquid crystal display device further comprises control means for causing the at least two data driving means to simultaneously take in the image data. 2. The control unit according to claim 1, wherein the control unit supplies a clock signal to the data driving unit for determining a timing of capturing the image data during a period in which the at least two data driving units do not need to capture the image data. 2. The liquid crystal display device according to claim 1, further comprising a clock signal supply unit that stops. 3. A liquid crystal display device comprising: data driving means for fetching image data according to a supplied clock signal and supplying the image data to liquid crystal display means for displaying an image, wherein the data driving means is The timing of capturing the image data is either the first timing at which the clock signal transitions from a first logic level to a second logic level or the second timing at which the clock signal transitions to a different logic level. A liquid crystal display device comprising control means for arbitrarily switching and setting. 4. A liquid crystal display device including data driving means for supplying image data to a liquid crystal display means for displaying an image while capturing image data in accordance with a supplied clock signal, wherein a duty ratio changes. A liquid crystal display device comprising: a control unit that generates the clock signal and supplies the clock signal to the data driving unit. 5. The liquid crystal display device according to claim 4, wherein said control means changes said duty ratio and generates said clock signal synchronized with said image data and supplies it to said data driving means. 6. A method for manufacturing a liquid crystal display device for displaying an image on a liquid crystal panel including a liquid crystal cell, wherein the thickness of the liquid crystal cell or the magnitude of birefringence of a liquid crystal layer included in the liquid crystal cell is adjusted. A method for manufacturing a liquid crystal display device, comprising the step of determining a γ value as an index of gradation-luminance characteristics in accordance therewith. 7. A liquid crystal display device for displaying an image by controlling the alignment of a plurality of liquid crystal molecules, comprising: a first alignment region in which the liquid crystal molecules are aligned in a first direction when a voltage is applied. The liquid crystal molecules are aligned in a second direction opposite to the first direction when the voltage is applied, and a second alignment region having a different width from the first alignment region. A liquid crystal display device characterized by the above-mentioned. 8. A liquid crystal display device for displaying an image by aligning liquid crystal molecules contained in a liquid crystal layer provided between a pixel electrode substrate and a counter substrate, the liquid crystal layer being formed on the entire surface of the counter substrate. A first electrode, formed on the first electrode, a resin layer having a first slit portion, formed on a pixel electrode substrate to face the first electrode, the first electrode A liquid crystal display device comprising: a slit portion; and a second electrode having a second slit portion facing the slit portion. 9. A liquid crystal display device for displaying an image by aligning liquid crystal molecules contained in a liquid crystal layer narrowly disposed between a pixel electrode substrate and a counter substrate, the liquid crystal display device being provided on the counter substrate. A bank-shaped first dielectric structure, a first electrode formed to cover the counter substrate and the dielectric structure, and a first electrode formed on the pixel electrode substrate and facing the dielectric structure. And a second electrode having a slit portion. 10. A liquid crystal display device for displaying an image by aligning liquid crystal molecules contained in a liquid crystal layer provided between a pixel electrode substrate and a counter substrate, the liquid crystal layer being formed on the entire surface of the counter substrate. A first electrode, a first dielectric structure formed on the counter substrate, or a slit formed on the first electrode, and on the pixel electrode substrate, the first electrode A second electrode provided so as to face, a dielectric layer covering the first electrode in the vicinity of the first dielectric structure, or the second electrode in the vicinity of the slit portion; A liquid crystal display device characterized by the above-mentioned.