JP2002216480A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device provided with a data bus which can efficiently transmit data at high speed. SOLUTION: A data bus amplifier circuit 44 amplifying voltage difference is provided on data buses DB, /DB delivering and receiving data between a memory cell and an input/output circuit. As the data buses DB, /DB has large parasitic capacity, complementary data of small amplitude can efficiently be transmitted at high speed at the time of read-out and write-in of data by providing such a data bus amplifier at the middle part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having an internal data bus for transmitting data with a small amplitude signal.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device, when data is written, data provided from an external pin such as a DQ pin is propagated through an internal data bus and reaches a memory cell in a memory cell array. On the other hand, at the time of reading,
When the data held in the memory cell is read from the memory cell array, it is propagated by the data bus, reaches an external pin such as a DQ pin, and is read to the outside.

In recent years, from the viewpoint of speeding up and reducing power consumption, it has been practiced to reduce the amplitude of a signal transmitted when data is transmitted through an internal data bus and amplify the amplitude on the data receiving side. For example, conventionally, data transmission has been performed at a so-called CMOS level amplitude in which the H level is at the power supply potential level and the L level is at the ground level. In recent years, data transmission has often been performed with a small amplitude in which the H level is an arbitrary level lower than the power supply potential level.

FIG. 15 is a circuit diagram showing a configuration for transmitting data through a conventional data bus.

Referring to FIG. 15, a conventional semiconductor memory device includes a memory cell array 512 and a write amplifier 514.
A gate circuit 516 for connecting the memory cell array to the data bus; a gate circuit 518 for connecting the data bus to the input / output circuit 508;
06, an input / output circuit 508, and a data terminal 510 for transmitting / receiving external signals DQ0 to DQn to / from the input / output circuit 508.

That is, in the conventional configuration, the data bus between the memory cell array and the input / output circuit does not have a signal amplification function, and the amplifier is provided and operated only on the data receiving side.

More specifically, in data reading, signal WRITE goes low and signal / WRITE goes high, and gate circuits 524 and 528 included in gate circuits 516 and 518 are activated, respectively. Therefore, the data read from the memory cell is
The data is first transmitted from the memory cell array 512 to the gate circuit 524. The read data is supplied to the gate circuit 524.
And transmitted to the data bus, and the gate circuit 5
The signal arrives at the read amplifier 506 via the. The read amplifier 506 amplifies the amplitude of the transmitted signal and transmits the amplified signal to the input / output circuit 508. Then, data is read to the outside via terminal 510.

[0008]

In the configuration as shown in FIG. 15, since no amplifying circuit is arranged between the gate circuit 524 and the gate circuit 528, interference between data buses and other signals may occur. There is a problem in operation, such as a margin of noise immunity is poor.

An object of the present invention is to provide a semiconductor memory device having a data bus in which an operation margin is improved and a speed is increased on a line for transmitting data with a small amplitude.

[0010]

According to a first aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a matrix; and an input / output circuit for exchanging data with the memory cell array from outside. A data bus pair including first and second data buses complementary to each other for transmitting data between the input / output circuit and the memory cell array; and a first data bus from the input / output circuit of the data bus pair to the memory cell array. , A data bus amplifier circuit for amplifying a potential difference generated between the first and second data buses, and a timing control for activating the data bus amplifier circuit in accordance with data write and read instructions for the memory cell array And a circuit.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the data bus amplifier circuit sets the potentials of the first and second data buses to equalize potentials. An equalizing circuit to be set; a potential setting unit to set a first internal node to a potential lower than the equalizing potential according to an output of the timing control circuit;
A first N-channel MOS transistor having a gate connected to the second data bus and a first N-channel MOS transistor connected between the first internal node and the second data bus. , And a second N-channel MOS transistor having a gate connected to the first data bus.

According to a third aspect of the present invention, in addition to the configuration of the first aspect, the data bus amplifier circuit sets the potentials of the first and second data buses to equalize potentials. An equalizing circuit to be set; a potential setting unit to set a first internal node to a potential higher than the equalizing potential in accordance with an output of the timing control circuit;
And a first P-channel MOS transistor having a gate connected to the second data bus and a first P-channel MOS transistor connected between the internal node and the first data bus, and between the first internal node and the second data bus. And a second P-channel MOS transistor having a gate connected to the first data bus.

According to a fourth aspect of the present invention, in addition to the configuration of the first aspect, the data bus amplifier circuit sets the potentials of the first and second data buses to equalize potentials. An equalizing circuit to be set; a first potential setting unit that sets a first internal node to a potential lower than an equalizing potential in accordance with an output of the timing control circuit; And a gate connected to a first data bus having a gate connected to a second data bus.
A channel MOS transistor, a second N-channel MOS transistor connected between the first internal node and the second data bus and having a gate connected to the first data bus, and an output of the timing control circuit. A second potential setting unit for setting the second internal node to a potential higher than the equalizing potential, a connection between the second internal node and the first data bus, and a gate connected to the second data bus. And a second P-channel MOS transistor connected between the second internal node and the second data bus and having a gate connected to the first data bus. .

According to a fifth aspect of the present invention, in the configuration of the semiconductor memory device according to the fourth aspect, the timing control circuit activates the second potential setting section after activating the first potential setting section.
Is activated.

According to a sixth aspect of the present invention, there is provided a semiconductor memory device comprising: a memory cell array including a plurality of memory cells arranged in a matrix; an input / output circuit for exchanging data with the memory cell array from outside; A data bus pair including first and second data buses complementary to each other for transmitting data to and from the memory cell array, and timing for controlling data transfer timing in accordance with data write and read instructions for the memory cell array A control circuit; and a data bus amplifier circuit for amplifying a potential difference generated between the first and second data buses in accordance with an output of the timing control circuit. An equalizing circuit for setting both of the bus potentials to the equalizing potential; and an equalizing circuit activated in response to the output of the timing control circuit to form a data bus pair. Provided corresponding to the point number, comprising a plurality of amplifier section for amplifying a potential difference between the first and second data bus.

According to a seventh aspect of the present invention, in the semiconductor memory device according to the sixth aspect, the data bus includes a plurality of branch portions for selectively receiving data from the memory cell array in accordance with an address signal. And a selector circuit for selecting and activating a part of the plurality of amplifier units corresponding to the branch portion selected from the plurality of branch portions.

According to an eighth aspect of the present invention, in addition to the configuration of the semiconductor memory device of the sixth aspect, each amplifier section equalizes the first internal node with an equalizing potential according to the output of the timing control circuit. A potential setting unit for setting a lower potential than the first internal node and the first data bus, and a gate connected to the second data bus.
, And a second N-channel MOS transistor connected between the first internal node and the second data bus and having a gate connected to the first data bus.

In the semiconductor memory device according to the ninth aspect, in addition to the configuration of the semiconductor memory device according to the sixth aspect, each amplifier section equalizes the first internal node with an equalizing potential according to the output of the timing control circuit. A potential setting unit for setting a higher potential than the first internal node and the first data bus, and a gate connected to the second data bus.
And a second P-channel MOS transistor connected between the first internal node and the second data bus and having a gate connected to the first data bus.

According to a tenth aspect of the present invention, in addition to the configuration of the semiconductor memory device of the sixth aspect, each amplifier section sets the first internal node to an equalizing potential according to the output of the timing control circuit. Set to a lower potential than the first
A first N-channel MOS transistor connected between the first internal node and the first data bus and having a gate connected to the second data bus; A second N-channel MO connected between the second data bus and a gate connected to the first data bus.
An S transistor, a second potential setting unit that sets a second internal node to a potential higher than an equalizing potential according to an output of the timing control circuit, and a connection between the second internal node and the first data bus A first P-channel MOS transistor having a gate connected to the second data bus;
A second P-channel MOS transistor connected between the second internal node and the second data bus and having a gate connected to the first data bus;

In a semiconductor memory device according to an eleventh aspect, in the configuration of the semiconductor memory device according to the tenth aspect, the timing control circuit activates the first potential setting unit and then activates the second potential setting unit. Activate.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

[First Embodiment] FIG. 1 is a diagram schematically showing an overall configuration of a semiconductor memory device 1 according to the present invention.

Referring to FIG. 1, semiconductor memory device 1 includes four memory banks BankA to BankD each including a plurality of memory cells arranged in a matrix.

The semiconductor memory device 1 further includes a timing control circuit 2 for receiving an address signal ADR and a command signal COM from the outside and outputting an operation timing signal;
Data bus driver circuits A0 to A0 provided corresponding to memory bank BankA to transmit and receive data between a memory cell and a data bus in accordance with the output of timing control circuit 2
A3.

The semiconductor memory device 1 further includes data bus driver circuits B0 to B3 provided corresponding to the memory bank BankB for transmitting and receiving data between the memory cells and the data bus in accordance with the output of the timing control circuit 2. , A timing control circuit 2 for transmitting and receiving data between a memory cell and a data bus provided corresponding to memory bank BankC.
Data bus driver circuits C0 to C
3 and data bus driver circuits D0 to D3 provided corresponding to the memory bank BankD and transmitting and receiving data between the memory cells and the data bus in accordance with the output of the timing control circuit 2.

The semiconductor memory device 1 further includes a data bus pair DBP, a data bus amplifier 4 for amplifying data read to the data bus pair DBP in accordance with the output of the timing control circuit 2, and an amplification by the data bus amplifier 4. Read amplifier 6 which receives the amplified data and further amplifies the data, and externally receives data output signal DAT
And an input / output circuit 8 for outputting the same. The input / output circuit 8 outputs externally applied data to the data bus amplifier 4 when writing data.

FIG. 2 shows the data bus amplifier 4 shown in FIG.
FIG. 4 is a circuit diagram showing a configuration of data transmission regarding the present invention in more detail.

Referring to FIG. 2, the semiconductor memory device 1 includes a memory cell array 12, a write amplifier 14, gate circuits 16, 18, a data bus amplifier 4, a read amplifier 6, an input / output circuit 8, And a data terminal 10.

Gate circuit 16 transmits a data output from memory cell array 12 to the data bus when reading data, and transmits data on the data bus to write amplifier 14 when writing data. And a gate circuit 22. Gate circuit 18 includes a gate circuit 26 for transmitting externally applied data to a data bus via input / output circuit 8 at the time of writing data,
A gate circuit 28 for transmitting a signal transmitted by the data bus to read amplifier 6 at the time of data reading.

The gate circuits 22, 24, 26, 28
Are supplied with complementary control signals WRITE and / WRITE. When control signals WRITE and / WRITE are at H level and L level, respectively, gate circuits 22 and 26 are activated. On the other hand, the control signal WRITE
Is at L level, gate circuits 24 and 28 are activated.

The data bus amplifier 4 has an enable signal D
Activated in response to BAEN to perform an operation of enlarging a potential difference generated in a data bus pair. Enable signal DBAE
N is one of the control signals output from the timing control circuit 2, and the timing is determined based on the address signal ADR and the command signal COM.

Data bus amplifier 4 amplifies data on the data bus both when reading data and when writing data. Therefore, when reading data, the timing control circuit 2 sets the enable signal DBAEN corresponding to the timing at which data is output from the memory cell to the data bus.
Activate. On the other hand, at the time of data writing, the timing control circuit 2 outputs an enable signal DBAEN corresponding to the timing at which data is transmitted from the DQ terminal to the data bus.
Activate.

Since the operation of the data bus amplifier is basically the same in both data reading and data writing, the operation in reading will be described below, and the description in writing will be repeated. Absent.

FIG. 3 is a circuit diagram showing the details of the contents of the data bus amplifier and explaining the operation at the time of reading data.

Referring to FIG. 3, a semiconductor memory device transfers data from a memory cell to data buses DB and / which are complementary to each other.
A bus driver circuit 32 for outputting to the DB, and a data bus amplifier 34 for amplifying data on the data bus
A gate circuit 36 for connecting the data buses DB and / DB to the read amplifier 38; a read amplifier 38 for amplifying and outputting the potential difference between the data buses DB and / DB when the gate circuit 36 is activated; And an output circuit 40 for outputting data to a data terminal according to the output of the output terminal 38. The data bus amplifier 34 equalizes the potential of the complementary data bus to the ground potential in response to the activation of the data bus equalize signal DBEQ when the data bus is not transmitted, and the data bus DB and the data bus DB in response to the control signal DBAEN. Data bus amplifier 44 that amplifies the potential difference of / DB
And

Equalize circuit 42 is connected between data bus DB and a ground node, and has an N-channel MOS transistor 46 receiving a data bus equalize signal DBEQ at its gate. And an N channel MOS transistor 48 receiving data bus equalize signal DBEQ.

The data bus amplifier 44 has a control signal DBA
An inverter 45 that inverts EN and outputs a signal ZDBAEN, and receives the signal ZDBAEN at its gate to receive a potential VDB
A P-channel MOS transistor 50 connected between the node to which A is applied and node N1, and a gate connected between node N1 and data bus DB and having a data bus / D
A P-channel MOS transistor 52 connected to B;
P-channel MOS transistor 54 connected between node N1 and data bus / DB and having a gate connected to data bus DB.

Data bus amplifier 44 further includes an N-channel MOS transistor 56 connected between data bus DB and node N2 and a gate connected to data bus / DB, and a data bus between data bus / DB and node N2. Channel MO whose gate is connected to data bus DB
S-transistor 58 and an N-channel MOS transistor 60 connected between node N2 and a ground node to receive signal DBAEN at its gate. Note that N channel M
OS transistors 56 to 60 have a small threshold voltage N
2 shows a channel MOS transistor.

The gate circuit 36 connects the data buses DB and / DB to the read amplifiers 38 according to the signal ZRDAI, respectively.
And N-channel MOS transistors 62 and 66 coupled to each other.

FIG. 4 shows the data bus amplifier 3 shown in FIG.
4 is an operation waveform diagram for explaining the operation of FIG.

Referring to FIGS. 3 and 4, at time t1, data read from the memory cell first drives only one side of data buses DB and / DB to H level via bus driver circuit 32. . Data bus D at this time
Which of B and / DB is driven to the H level side is determined by the data read from the memory cell.

The voltage level when driving to the H level side is controlled by the bus driver circuit 32.
Usually, it is determined by controlling the drive time and controlling the voltage level of the driver. Controlling the drive time means controlling the charge to be charged based on the pulse width, and controlling the voltage level of the driver means controlling by changing the potential level of the source voltage of the driver.

Subsequently, at time t2, data bus D
In response to the occurrence of a potential change corresponding to data in one of B and / DB, the data bus amplifier 44 arranged on the data bus is activated to reduce the amplitude of the small-amplitude signal on the data bus. Amplify.

More specifically, first, the signal DBAEN output from the timing control circuit 2 shown in FIG.
The level changes from the level to the H level, and the node N2 in the data bus amplifier is pulled down to the ground potential side. And the signal ZDBE
AN changes from the H level to the L level to activate the potential of the node N1 to the potential VDBA which is the activation potential of the P-channel MOS transistor. Such an operation amplifies the potential difference between data buses DB and / DB.

Next, at time t3, the data bus D
N-channel MOS transistors 62 and 66 connecting B, / DB and read amplifier 38 are deactivated, and data bus amplifier 44 is deactivated. Thereafter, the read amplifier 38 is activated, that is, the signal RDAEN is activated from the L level to the H level, and the data transmitted from the data bus is transmitted to the output circuit 40. At this time, since data buses DB and / DB are already separated from read amplifier 38, data bus equalize signal DBEQ
Is activated to the H level to start equalization of the data bus.

Subsequently, at time t4, after data is propagated to output circuit 40, signal ZRDAI is raised from L level to H level, and data bus equalize signal DBEQ is output.
Is changed from the H level to the L level, and preparations for fetching the next data are started.

By operating as described above, the drive time to the data bus is the same as before, and a large amplitude of the data bus can be obtained, thereby enabling high-speed operation.
Further, since the amplitude of the data bus itself can be secured, the operation margin of the data receiving side, that is, the read amplifier or the write amplifier is also improved.

[Embodiment 2] As shown in FIG. 1, a data bus is often constituted by long wires on a chip. Therefore, in order to efficiently amplify the data output to the data bus, it is more efficient to arrange a plurality of data bus amplifiers so that the circuit for driving the data bus is located at any position and the effect is sufficient. Is good.

In the first embodiment, one data bus pair has one data bus amplifier. In the second embodiment, the data bus driver circuit A shown in FIG.
No. 0 to A3, B0 to B3, C0 to C3, and D0 to D3, a plurality of data bus amplifiers are provided so that the data bus amplifying effect can be sufficiently obtained even when data is output from any of the data bus driver circuits. Place on data bus.

FIG. 5 is a diagram showing a configuration related to data transmission in the semiconductor memory device of the second embodiment.

Referring to FIG. 5, the semiconductor memory device includes data buses DB and / DB, an equalizing circuit 42 for equalizing the potentials of data buses DB and / DB according to data bus equalizing signal DBEQ, and a memory cell. Data bus driver circuits 72 # each receiving the data of
0 to 72♯n and the activation potential VDBA and the signal DBA
EN and ZDBAEN are activated according to the data bus DB,
Data bus amplifiers 74 for amplifying the potential difference of / DB
{0-74} N.

Semiconductor memory device 1 further includes a gate circuit 36 for transmitting data buses DB and / DB to read amplifier 38, and an output circuit 40 for outputting data to terminals according to the output of read amplifier 38.

Equalize circuit 42 is connected between data bus DB and the ground node, receives N-channel MOS transistor 46 at its gate and receives signal DBEQ, and is connected between data bus / DB and the ground node at its gate to receive signal DBE.
N channel MOS transistor 48 receiving EQ. Gate circuit 36 has N-channel MOS transistors 62 and 6 for receiving signal ZRDAI at its gate and connecting data buses DB and / DB to read amplifier 38, respectively.
6 is included.

FIG. 6 shows the data bus amplifier 7 in FIG.
FIG. 4 is a circuit diagram showing a configuration of 4♯0 to 74♯N.

Referring to FIG. 6, data bus amplifier 74
Is connected between a node receiving the signal ZDBAEN at its gate and the potential VDBA and the node N11.
Channel MOS transistor 80 is connected between node N11 and data bus DB and has a gate connected to data bus / D.
A P-channel MOS transistor 82 connected to B;
P-channel MOS transistor 84 connected between node N11 and data bus / DB and having a gate connected to data bus DB.

Data bus amplifier 74 further includes an N-channel MOS transistor 86 connected between data bus DB and node N12 and a gate connected to data bus / DB, and a data bus between data bus / DB and node N12. And a gate connected to data bus DB, and an N-channel MOS transistor 90 connected between node N12 and the ground node to receive signal DBAEN at the gate. N channel MOS transistors 86 to 90 are N channel MOS transistors having a small threshold voltage.

As described above, by arranging a plurality of data bus amplifiers on the data bus, even if data is output from data bus driver circuit A0 in FIG. 1, for example, as shown in FIG. Since the data bus amplifier is arranged near the data bus driver, it is possible to effectively amplify the signal on the data bus without depending on the place where the data is output to the data bus. .

[Third Embodiment] In a normal semiconductor memory device, a plurality of data bus driver circuits for outputting data to a data bus are arranged in a chip as shown in FIG. The data bus driver circuit to be used is determined depending on which cell is read.

In the second embodiment, the case where the amplification efficiency is improved by arranging a plurality of data bus amplifiers on the data bus has been described. However, all data bus amplifiers operate even when any data bus drive circuit is used. Therefore, there is a disadvantage that the operating current increases.

FIG. 7 is a circuit diagram showing a configuration of data transmission in the semiconductor memory device of the third embodiment.

Referring to FIG. 7, the semiconductor memory device according to the third embodiment includes a data bus DB, / DB and a selection signal SEL.
A selector circuit 92 that outputs <0> to SEL <3>;
Data bus driver circuits 94 # 0-94 # 3 which receive data read from a memory array (not shown) and are activated in response to select signals SEL <0> -SEL <3> to transmit data, respectively; Receiving potential VDBA and activating in accordance with selection signals SEL <0> to SEL <3>,
At the timing indicated by signal DBAEN, data bus DB, /
Data bus amplifier 96 # 0-9 for amplifying the potential difference of DB
6♯3.

The semiconductor memory device of the third embodiment further includes an equalizing circuit 42 for equalizing data buses DB and / DB, and a gate circuit 36 for transmitting data on data buses DB and / DB to a read amplifier (not shown). including.

The structures of equalizing circuit 42 and gate circuit 36 are the same as those shown in FIG. 5, and description thereof will not be repeated.

FIG. 8 shows the data bus amplifier 9 in FIG.
FIG. 3 is a circuit diagram showing a configuration of 6♯2.

Referring to FIG. 8, data bus amplifier 96 #
2 receives the signal ZDBAEN at the gate and outputs the potential VDBA
A P-channel MOS transistor 100 connected between a node supplied with a node N21 and a node N21.
-Channel MOS transistor 10 connected between data bus DB and a gate connected to data bus / DB
2 and a P-channel MO connected between node N21 and data bus / DB and having a gate connected to data bus DB.
And an S transistor 104.

Data bus amplifier 96 # 2 further includes an N-channel MOS transistor 106 connected between data bus DB and node N22 and a gate connected to data bus / DB, a data bus / DB and node N22. And an N-channel MOS transistor 108 having a gate connected to data bus DB and an N-channel MOS transistor 110 connected between node N22 and a ground node to receive signal DBAEN at the gate. Note that N-channel MOS transistors 106 to 108 are N-channel MOS transistors having a small threshold voltage.

Data bus amplifier 96 # 2 further receives a select signal SEL <2> and a signal DBEAN.
It includes an ND circuit 114 and an inverter 112 which receives and inverts the output of the NAND circuit 114.

The data bus amplifier 96 shown in FIG.
{0, 96, 1, 96} are also data bus amplifiers 96,
It has the same configuration as that of No. 2, and description thereof will not be repeated.

The operation will be briefly described with reference to FIGS. First, the selector circuit 92 selects a data bus driver circuit and a data bus amplifier near the data bus driver circuit. In the example shown in FIG. 7, the selection signal SEL <2> is activated and the data bus driver circuit 9
It is assumed that 4 @ 2 and data bus amplifier 96 # 2 have been selected.

The signal used for selection at this time is formed by a signal obtained by decoding information corresponding to an address or a terminal DQ to be used. This signal is generated, for example, by the timing control circuit 2 shown in FIG.

Next, after driving of data buses DB and / DB is completed, a signal D for activating a data bus amplifier is generated.
The amplification operation is started when BAEN is raised from the L level to the H level.

As described above, using the selection signal,
By controlling the number of the plurality of data bus amplifiers for amplifying the data on the data bus, the operating power supply current can be reduced. Further, in order to activate the nearby data bus amplifier, it is possible to eliminate a delay in the time from when data is driven on the data bus to when the amplifier is started. Therefore, efficient data amplification with reduced time loss is possible.

[Fourth Embodiment] From the fourth embodiment, variations of the configuration of the data bus amplifier used in the first to third embodiments will be described.

FIG. 9 is a circuit diagram showing a configuration of a data bus amplifier and an equalizing circuit used in the fourth embodiment.

Referring to FIG. 9, equalizing circuit 122
Is connected between a data bus DB and a node receiving potential VDBEQ, and has a data bus equalize signal DB at its gate.
An N-channel MOS transistor 126 receiving the EQ;
Data bus equalize signal DBE is connected between data bus / DB and a node receiving potential VDBEQ and connected to the gate.
And an N-channel MOS transistor 128 receiving Q.

Data bus amplifier 124 is connected to node N31
Signal DBAEN is connected between the gate and the ground node.
N-channel MOS transistor 134 receiving an N-channel MOS transistor 134, N-channel MOS transistor 130 connected between node N31 and data bus DB and having a gate connected to data bus / DB, and connected between node N31 and data bus / DB. And an N-channel MOS transistor 132 having a gate connected to data bus DB.

FIG. 10 is an operation waveform diagram for describing an operation of data bus amplifier 124 shown in FIG.

Referring to FIGS. 9 and 10, first, at time t0, data buses DB and / DB are both set at potential VDBEQ.
Has been equalized.

At time t1, only one side of data buses DB and / DB is driven by a data bus driver circuit (not shown) in response to data transmission.

At time t2, signal DBAEN for activating the data bus amplifier is raised to H level to activate data bus amplifier 124, and the data bus not driven to H level at time t1 is driven to L level. I do. After this amplifying operation, data is sent to the read amplifier in the case of data reading, and data is sent to the write amplifier in the case of data writing. At time t3, data transmission is completed, and the data bus is again equalized to potential VDBEQ. At time t4, equalization of the data bus is completed, and signal DBE is received to receive the next data.
Q falls to L level.

As described above, a data bus amplifier can be constituted by only N-channel MOS transistors. This N-channel MOS transistor may be an i-transistor having a low threshold value. N channel M
When the data bus amplifier is constituted only by the OS transistors, the layout area can be reduced.

[Fifth Embodiment] In a fifth embodiment, an example is shown in which a data bus amplifier is constituted only by P-channel MOS transistors.

FIG. 11 is a circuit diagram showing a configuration of a data bus amplifier used in the fifth embodiment.

Referring to FIG. 11, equalizing circuit 122
Is an N-channel MOS transistor 12 connected between a node to which potential VDBEQ is applied and data bus DB and having a gate receiving data bus equalize signal DBEQ.
6 and an N-channel MOS transistor 1 connected between a node to which potential VDBEQ is applied and data bus / DB and having a gate receiving data bus equalize signal DBEQ.
28.

Data bus amplifier 142 receives signal ZDBA
An inverter 144 that receives and inverts signal EN, and a P-channel MO connected between an output node of inverter 144 and data bus DB and having a gate connected to data bus / DB.
P channel MOS transistor 1 connected between S transistor 146 and an output node of inverter 144 and data bus / DB and having a gate connected to data bus DB
48.

FIG. 12 is an operation waveform diagram for describing an amplification operation of the data bus amplifier shown in FIG.

Referring to FIGS. 11 and 12, at time t0, data buses DB and / DB are equalized to potential VDBEQ.

At time t1, only one of data buses DB and / DB is driven to the L level by the data bus driver circuit in accordance with the output of data.

By setting signal ZDBAEN indicating activation of the data bus amplifier at time t2 to L level, data bus amplifier 142 is activated and the side not driven to L level side at time t1 in accordance with data output. Is set to the H level. This H level corresponds to the power supply potential V received by the inverter 144 in FIG.
Given by DD. After the amplification operation, data is sent to the read amplifier in the case of data reading, and data is sent to the write amplifier in the case of data writing.

At time t3, data transmission is completed, and the data bus is equalized to potential VDBEQ.
When the equalization of the data bus is completed at time t4, the equalize signal DBEQ falls to the L level, and the preparation for receiving the next data is completed.

As described above, by using the structure shown in the fifth embodiment, a data bus amplifier can be constituted only by P-channel MOS transistors. Also in this case, it is effective to reduce the layout area.

[Embodiment 6] FIG. 13 shows Embodiment 6 of the present invention.
2 is a circuit showing a configuration of a data bus amplifier used in.

Referring to FIG. 13, data bus amplifier 15
0 receives the signal ZDBAEN at the gate and outputs the potential VDBA
A P-channel MOS transistor 160 connected between a node supplied with P and a node N41;
P-channel MOS transistor 1 connected between data bus 1 and data bus DB and having a gate connected to data bus / DB
62, a P channel M connected between node N41 and data bus / DB and having a gate connected to data bus DB.
OS transistor 164.

Data bus amplifier 150 further includes an N-channel MOS transistor 166 connected between data bus DB and node N42 and a gate connected to data bus / DB, and a data bus between data bus / DB and node N42. And an N-channel MOS transistor 168 having a gate connected to data bus DB and an N-channel MOS transistor 170 connected between node N2 and the ground node to receive signal DBAEN at the gate.

FIG. 14 is an operation waveform diagram for explaining the operation of the data bus amplifier shown in FIG.

Referring to FIGS. 13 and 14, at time t0, data buses DB and / DB are equalized to potential VDBEQ.

At a time t1, a data bus D (not shown) is driven by a data bus driver
Only one of B and / DB is driven to the H level.

At time t2, signal DBAEN for activating the data bus amplifier is raised to H level, and N-channel MOS transistor 170 in the data bus amplifier is turned on. Then, amplifying operation is first performed from N channel MOS transistor side by N channel MOS transistors 166 and 168.

Here, the activation of the N-channel MOS transistor prior to the activation of the P-channel MOS transistor is based on a dynamic random access memory (DRAM).
Has been conventionally performed in the sense amplifier operation. This is because, in the N-channel MOS transistor, Vds (drain-source voltage) is lost by the threshold voltage Vth, so that the charge of the data bus can be slowly drawn to the L level. By utilizing this phenomenon, the potential of the data bus not driven to the H side is driven to the ground potential side.

Subsequently, at time t3, signal ZDBAEN, which is a complementary enable signal, is activated to L level, and P-channel MOS transistor 16 in the data bus amplifier is activated.
0 is a conduction state. Here, the data bus that has been driven to the H level side is pulled up to the potential VDBAP.
At the same time as the end of the amplification operation by the amplifier circuit, the data is transferred to the read amplifier at the time of reading and to the write amplifier at the time of writing.

At time t4, the data transmission is completed.
The bus is again equalized to the potential VDBEQ. afterwards,
When the equalization of the data bus is completed, the equalize signal DBEQ falls to the L level, and the preparation for receiving the next data is completed.

As described above, in the sixth embodiment,
When an N-channel MOS transistor and a P-channel MOS transistor are used, the sensitivity of the data bus amplifier can be increased by changing the activation timing of the N-channel MOS transistor and the P-channel MOS transistor to perform amplification. Therefore, the time for driving the data bus amplifier can be shortened, and the destruction of data due to a sudden amplification operation can be prevented.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0104]

According to the semiconductor memory device of the present invention, a complementary data bus for transmitting data between a memory cell array and an input / output circuit is provided with a data bus amplifier circuit for expanding a potential difference. Transfer can be performed at high speed.

The semiconductor memory device according to claim 2 or 3
In addition to the effects achieved by the semiconductor memory device according to the first aspect, the speed of data transfer can be increased with a small increase in layout area.

The semiconductor memory device according to claims 4 and 5 is
In addition to the effects provided by the semiconductor memory device according to claim 1, the sensitivity of the data bus amplifier circuit can be increased,
In addition, data destruction can be prevented.

According to the semiconductor memory device of the present invention, a complementary data bus for transmitting data between a memory cell array and an input / output circuit is provided with a data bus amplifier circuit for expanding a potential difference, and a data bus amplifier circuit is provided. Includes amplifier sections corresponding to a plurality of points, so that data can be exchanged at high speed even in the case of a large-scale chip.

According to the semiconductor memory device of the seventh aspect, in addition to the effects of the semiconductor memory device of the sixth aspect, a part of the plurality of amplifier units can be selectively used according to the location of data transfer. Since it is used, power consumption can be reduced.

The semiconductor memory device according to claims 8 and 9 is
In addition to the effects achieved by the semiconductor memory device according to the sixth aspect, the speed of data transfer can be increased with a small increase in layout area.

According to the semiconductor memory device of the tenth and eleventh aspects, in addition to the effects of the semiconductor memory device of the sixth aspect, the sensitivity of the data bus amplifier circuit can be increased and the destruction of data can be prevented. Can be prevented.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an overall configuration of a semiconductor memory device 1 of the present invention.

FIG. 2 is a circuit diagram showing a configuration of data transmission related to data bus amplifier 4 shown in FIG. 1 in more detail.

FIG. 3 is a circuit diagram showing the details of the contents of the data bus amplifier and explaining the operation at the time of reading data.

FIG. 4 is an operation waveform diagram for describing an operation of data bus amplifier shown in FIG.

FIG. 5 is a diagram showing a configuration related to data transmission in a semiconductor memory device according to a second embodiment;

FIG. 6 shows data bus amplifiers 74 # 0-7 in FIG.
FIG. 4 is a circuit diagram showing a configuration of 4♯N.

FIG. 7 is a circuit diagram showing a configuration of data transmission in a semiconductor memory device according to a third embodiment;

8 is a circuit diagram showing a configuration of data bus amplifier 96 # 2 in FIG.

FIG. 9 is a circuit diagram showing a configuration of a data bus amplifier and an equalizing circuit used in a fourth embodiment.

10 is an operation waveform diagram for explaining an operation of data bus amplifier 124 shown in FIG.

FIG. 11 is a circuit diagram showing a configuration of a data bus amplifier used in a fifth embodiment.

FIG. 12 is an operation waveform diagram illustrating an amplification operation of the data bus amplifier shown in FIG. 11;

FIG. 13 is a circuit diagram showing a configuration of a data bus amplifier used in the sixth embodiment.

FIG. 14 is an operation waveform diagram for explaining the operation of the data bus amplifier shown in FIG.

FIG. 15 is a circuit diagram showing a configuration for transmitting data via a conventional data bus.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor memory device, 2 timing control circuit, 4 data bus amplifier, 6 read amplifier, 8 input / output circuit, 1
0 data terminal, 12 memory cell array, 14 write amplifier, 16, 18, 22 to 28, 36 gate circuit, 32 bus driver circuit, 34, 44, 74, 9
6, 124, 142, 150 Data bus amplifier, 38
Read amplifier, 40 output circuit, 42, 122 data bus equalizing circuit, 45, 112 inverter, 4
6,48,56-60,62,66,86-90,10
6 to 110, 126 to 134, 166 to 170 N-channel MOS transistors, 50 to 54, 80 to 84, 1
00 to 104, 146, 148, 160 to 164 P-channel MOS transistor, 72, 94 data bus driver circuit, 92 selector circuit, 114 NAND circuit, 144 inverter, A0 to A3, B0 to B3, C
0 to C3, D0 to D3 Data bus driver circuit, Ba
nkA, BankB, BankC, BankD Memory bank, DB, / DB data bus, DBP data bus pair.

Claims (11)

[Claims] A memory cell array including a plurality of memory cells arranged in a matrix; an input / output circuit for exchanging data with the memory cell array from outside; and a memory between the input / output circuit and the memory cell array. A data bus pair including mutually complementary first and second data buses for performing data transmission; and a first point from the input / output circuit of the data bus pair to the memory cell array. A semiconductor device, comprising: a data bus amplifier circuit for amplifying a potential difference generated between two data buses; and a timing control circuit for activating the data bus amplifier circuit in accordance with data write and read instructions for the memory cell array. Storage device. 2. The data bus amplifier circuit further comprises: an equalizing circuit for setting both the potentials of the first and second data buses to an equalizing potential; and a first internal node corresponding to an output of the timing control circuit. A potential setting unit for setting a potential lower than an equalizing potential, a first N connected between the first internal node and the first data bus, and a gate connected to the second data bus And a second MOS transistor connected between the first internal node and the second data bus and having a gate connected to the first data bus. 2. The semiconductor memory device according to 1. 3. The data bus amplifier circuit comprises: an equalizing circuit for setting both the potentials of the first and second data buses to an equalizing potential; and a first internal node corresponding to an output of the timing control circuit. A potential setting unit for setting a potential higher than an equalizing potential, a first P connected between the first internal node and the first data bus, and a gate connected to the second data bus. And a second MOS transistor connected between the first internal node and the second data bus and having a gate connected to the first data bus. 2. The semiconductor memory device according to 1. 4. The data bus amplifier circuit includes: an equalizing circuit for setting both of the first and second data buses to an equalizing potential; and a first internal node corresponding to an output of the timing control circuit. First to set a potential lower than the equalizing potential
A potential setting unit, a first N-channel MOS transistor connected between the first internal node and the first data bus, and a gate connected to the second data bus; A second N-channel MOS transistor having a gate connected to the first data bus and a second N-channel MOS transistor connected between the internal node of the second data bus and the second data bus; A second step of setting the internal node to a potential higher than the equalizing potential;
A potential setting unit, a first P-channel MOS transistor connected between the second internal node and the first data bus, and a gate connected to the second data bus, 2. The semiconductor memory device according to claim 1, further comprising a second P-channel MOS transistor connected between an internal node and said second data bus and having a gate connected to said first data bus. 5. The semiconductor memory device according to claim 4, wherein said timing control circuit activates said second potential setting section after activating said first potential setting section. 6. A memory cell array including a plurality of memory cells arranged in a matrix, an input / output circuit for exchanging data with the memory cell array from the outside, and a memory between the input / output circuit and the memory cell array. A data bus pair including first and second data buses complementary to each other for data transmission; a timing control circuit for controlling data transmission / reception timing in accordance with data write / read instructions to / from the memory cell array; A data bus amplifier circuit for amplifying a potential difference generated between the first and second data buses in accordance with an output of the timing control circuit, wherein the data bus amplifier circuit includes the first and second data buses. An equalizing circuit for setting both of the potentials to the equalizing potential; and an equalizing circuit activated in response to an output of the timing control circuit, Respectively provided corresponding to multiple points of data buses pair includes a plurality of amplifier section for amplifying a potential difference between the first and second data buses, the semiconductor memory device. 7. The data bus includes a plurality of branch portions for selectively receiving data from the memory cell array according to an address signal, wherein the data bus corresponds to a selected one of the plurality of branch portions. 7. The semiconductor memory device according to claim 6, further comprising a selector circuit for selecting and activating a part of the plurality of amplifier units. 8. Each of the amplifier sections includes: a potential setting section that sets a first internal node to a potential lower than the equalizing potential according to an output of the timing control circuit; A first N-channel MOS transistor having a gate connected to the second data bus and a first N-channel MOS transistor connected between the first internal node and the second data bus; 7. The semiconductor memory device according to claim 6, further comprising a second N-channel MOS transistor having a gate connected to said first data bus. 9. Each of the amplifier sections includes: a potential setting section that sets a first internal node to a potential higher than the equalizing potential according to an output of the timing control circuit; A first P-channel MOS transistor having a gate connected to the second data bus and a first P-channel MOS transistor connected between the first internal node and the second data bus; 7. The semiconductor memory device according to claim 6, further comprising a second P-channel MOS transistor having a gate connected to said first data bus. 10. Each of the amplifiers sets a first internal node to a potential lower than the equalizing potential according to an output of the timing control circuit.
A potential setting unit, a first N-channel MOS transistor connected between the first internal node and the first data bus, and a gate connected to the second data bus; A second N-channel MOS transistor having a gate connected to the first data bus and a second N-channel MOS transistor connected between the internal node of the second data bus and the second data bus; A second step of setting the internal node to a potential higher than the equalizing potential;
A potential setting unit, a first P-channel MOS transistor connected between the second internal node and the first data bus, and a gate connected to the second data bus, 7. The semiconductor memory device according to claim 6, further comprising a second P-channel MOS transistor connected between an internal node and said second data bus and having a gate connected to said first data bus. 11. The timing control circuit according to claim 1, wherein:
11. The semiconductor memory device according to claim 10, wherein said second potential setting unit is activated after activating said potential setting unit.