JP2002215568A - Asynchronous data transfer method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To permit verification wherein a timing element like a synchronous circuit is disconnected by simplifying a method of using a logic composing tool, as to an asynchronous data transfer method using a data transfer reference signal as transfer reference for data and transfer data transferred in a pair with the data transfer reference signal. SOLUTION: At an asynchronous interface part between a TCLK operation part and an RCLK operation part in an LSI, 11 is a final output stage F/F for the transfer reference signal and 12 is a final output stage F/F for the transfer data D transferred in a pair with a STRB. A state is created wherein a transmission side can use determined reference timing of the transfer data as a clock edge of assert timing of the data transfer reference signal and a reception side can use the transfer data sampled with the clock edge where the assertion of the transfer reference signal is detected for the 1st time, and signals outputted from the F/Fs 11 and 12 are sampled by F/Fs 13 and 14 which operate with RCLK.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous data transfer method, and more particularly, to a data transfer reference signal serving as a data transfer reference and transfer data transferred in pairs with the data transfer reference signal. Regarding the asynchronous data transfer method to be performed.

[0002]

2. Description of the Related Art Large-scale integrated circuits (hereinafter referred to as LSIs)
Is designed using a hardware description language (hereinafter referred to as HDL) such as Verilog (registered trademark).
Generally, in HDL, description can be made at a high level of abstraction such as an operation level or at a low level of abstraction such as a gate level. The general flow of the design is as follows. L first
The operation specifications to be realized as SI are described in HDL, and the validity of the HDL description is confirmed by simulation using a separately prepared test bench. After the confirmation, a logic level tool is used to generate a gate-level circuit according to the contents of the HDL description. The generated gate level circuit is simulated at the gate level using the test bench (or with some modifications) to confirm the validity of the circuit. At this point,
Since actual layout is not performed, provisional delay time information is used. The confirmed gate level circuit is laid out to make it an actual semiconductor. Here, since the actual delay time information can be extracted, the gate level simulation is performed again using the actual delay information. Here, when the validity is confirmed, the process proceeds to the next process for manufacturing the LSI. In the above description, when the circuit to be designed is an asynchronous circuit, there are portions that cannot be performed efficiently like a synchronous circuit.

A first problem is that a logic synthesis tool cannot sufficiently handle an asynchronous circuit. The logic synthesis tool
Define a specific phase relationship for multiple clocks, and set up / hold
Generate a circuit considering the time. Normal,
Since a phase relationship cannot be defined between a plurality of clocks, a logic synthesis tool does not always generate an appropriate circuit. For this reason, it is necessary to understand the characteristics of the logic synthesis tool and control the HDL description and synthesis constraints so as to generate a circuit as designed.

A second problem is that verification of an asynchronous circuit cannot be sufficiently performed. In the case of a synchronous circuit, the quality of a timing element can be judged based on whether or not the setup / hold time is satisfied. In the case of an asynchronous circuit, however, the operation of the timing element affects the operation in a complicated manner, and the combination thereof is infinite. Since it can exist, it is difficult to perform sufficient verification. As a known technique for an asynchronous circuit, there is Japanese Patent Application Laid-Open No. H11-120212. In order to prevent the influence of metastable due to an asynchronous input signal from the outside of the LSI from affecting the inside of the LSI, synchronization is performed by a two-stage register or a warning is generated.

[0005]

Problems to be Solved by the Invention
The invention described in Japanese Patent Application Laid-Open No. 12-21012 avoids the influence of metastable due to an asynchronous input signal from the outside of the LSI by inserting two stages of F / Fs. In some cases, failures in asynchronous circuits cannot be avoided. For example, when a signal having a bit width is received, there may be a case where the entire bit is received as meaningless data due to a variation in delay time for each bit. That is, if the data changes near the sampling point on the receiving side, not all bits will be new or all bits will be old,
The entire bit may become meaningless data. However, it is difficult to detect this defect by simulation. This is until the gate level simulation using real routing delay information.
This is because the simulation is performed with the delay time of all the bits of the transfer data set to 0 or the same delay time, so that the variation between bits cannot be simulated.
Even in the gate level simulation using the actual wiring delay information, it is detected only when there is a delicate timing relationship. Therefore, it is difficult to detect this by simulation.

As described above, for an asynchronous circuit: The logic synthesis tool could not handle asynchronous circuits sufficiently, and the designer had to understand the characteristics of the logic synthesis tool and control the HDL description and synthesis constraints well. 2. In an asynchronous circuit, it is difficult to perform sufficient verification because the timing elements affect the operation in a complicated manner and the combinations can be infinite. There was a problem.

[0007]

[Means for Solving the Problems]

According to a first aspect of the present invention, there is provided an asynchronous data transfer method using a data transfer reference signal serving as a data transfer reference and transfer data transferred in a pair with the data transfer reference signal. , The reference timing of the transfer data is determined by the assertion of the data transfer reference signal.
The clock edge of the timing is used, and the receiving side creates a state where it is possible to use the transfer data sampled at the clock edge where the transfer reference signal is first detected. It simplifies and enables verification with timing elements such as synchronous circuits separated.

According to a second aspect of the present invention, in the first aspect of the present invention, the transfer reference signal is laid out so as to have a larger delay amount than the transfer data, thereby providing the environment of the first aspect.

According to a third aspect of the present invention, in the first aspect of the invention, the sampling point of the transfer data on the receiving side is configured to be selectable between the clock edge of the first aspect and one clock after the clock edge. Even if the situation of claim 2 cannot be achieved, a method for achieving the same object as the object of claim 1 is provided.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining an embodiment of the present invention, in which a TCLK (transmitting-side operating clock) operating portion in an LSI and an RCLK (receiving-side operating clock) are included.
The asynchronous interface with the operation part is shown. In FIG. 1, reference numeral 11 denotes a final output stage F / F of a transfer reference signal (STRB signal), and reference numeral 12 denotes a final output of transfer data D [31: 0] transferred in pairs with the STRB (transfer reference signal). Stage F / F. Signals output from these F / Fs 11 and 12 are supplied to F / Fs 13 and 14 operating on RCLK.
Is sampled at

FIG. 2 is a diagram showing a state of the interface shown in FIG. 1. In FIG. 2, TCLK is an operation clock on the transmission side, D [31: 0] is transfer data, and STRB is a transfer reference signal. On the transmitting side, the output of D [31: 0] is determined at the clock edge of STRB assertion. Although the timing of D [31: 0] determination may be earlier than that, STRB assertion and D [31:
0] This means that the minimum guaranteed clock number to be determined is 0.

In FIG. 2, the layout is such that the delay of the transfer data is larger than the delay of the transfer reference signal. The difference between the delay times is such that valid transfer data can always be sampled at the clock edge at which the assertion of the transfer reference signal is first sampled. Therefore, as shown in FIG. 2, on the receiving side, the transfer data sampled at the clock edge at which the assertion of STRB (transfer reference signal) is detected may be used and used. A simulation is performed by an equivalent method, and the validity of the circuit can be verified. Also in the logic synthesis tool, the special setting for the asynchronous operation is only the setting for making the delay amount of the transfer reference signal larger than the delay amount of the transfer data. In some cases, there is a method of adjusting the delay amount at the time of layout without performing any special setting for the logic synthesis tool.

FIG. 3 is a diagram for explaining another embodiment of the present invention. The F / F is different from the configuration of the embodiment shown in FIG.
15 and a selector 16 are added, so that the timing of asserting the transfer reference signal is compared with that of FIG.
The setting can be delayed by one clock. This is provided as an insurance when a delay time such that valid transfer data can always be sampled cannot be secured at the clock edge at which the assertion of the transfer reference signal is first sampled. STRB (Transfer Reference Signal) 4 is delayed by one clock to detect the assertion of FIG.
As shown in (1), valid transfer data can be always taken.

Generally, the output F / F and the input F / F of the transfer reference signal are connected one-to-one with the output F / F and the input F / F of the transfer data, and are arranged in close proximity. Therefore, the situation where the transfer data is fetched at a place delayed by one clock as shown in FIG. 4 rarely occurs, but is provided to shorten the layout period.

[0016]

According to the first aspect of the present invention, there is provided an asynchronous data transfer method performed by a data transfer reference signal serving as a data transfer reference and transfer data transferred in a pair with the data transfer reference signal. In the above, the reference timing for determining the transfer data is used as the clock edge of the assertion timing of the data transfer reference signal, and on the receiving side, the transfer data sampled at the clock edge where the assertion of the transfer reference signal is first detected. Since it is assumed that a usable state can be created, the method of using the logic synthesis tool can be simplified, and verification can be performed with timing elements such as synchronous circuits separated.

According to a second aspect of the present invention, the environment of the first aspect can be provided by laying out the transfer reference signal such that the delay amount is larger than that of the transfer data.

According to a third aspect of the present invention, in the first aspect of the invention, the sampling point of the transfer data on the receiving side is configured to be selectable between the clock edge of the first aspect and one clock after the clock edge. Even if the situation of claim 2 cannot be achieved, a method for achieving the same object as that of claim 1 can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining an embodiment of an asynchronous data transfer method according to the present invention.

FIG. 2 is a diagram showing timings of the asynchronous data transfer method shown in FIG.

FIG. 3 is a diagram for explaining another embodiment of the asynchronous data transfer method according to the present invention.

FIG. 4 is a diagram showing timings of the asynchronous data transfer method shown in FIG.

[Explanation of symbols]

11 to 15: F / F, 16: selector, TCLK: operation clock on the transmission side, RCLK: operation clock on the reception side,
STRB: transfer reference signal, D [31: 0]: transfer data.

Claims (3)

[Claims] 1. An asynchronous data transfer method comprising: a data transfer reference signal serving as a data transfer reference; and transfer data transferred in pair with the data transfer reference signal. The determined reference timing is a clock edge of an assertion timing of the data transfer reference signal, and the receiving side uses transfer data sampled at a clock edge in which the assertion of the transfer reference signal is detected first. Asynchronous data transfer method. 2. The asynchronous data transfer method according to claim 1, wherein the data transfer reference signal is laid out so as to have a larger delay amount than the transfer data. 3. The asynchronous data transfer method according to claim 1, wherein a sampling point of transfer data on the receiving side is selectable between the clock edge of claim 1 and one clock after the clock edge. .