JP2002204273A - Device and system for radio communication, and device and method for transmitting program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the transmission efficiency of a program for software radio equipment. SOLUTION: A programmable logic circuit is divided into a slice connected to the MSB side of an input-output bus and a slice connected to the LSB side, modulation is performed by a QPSK(Quadrature Phase Shift Keying) modulator (15a-3) where a bit error in which a transmission characteristics is excellent is difficult to occur with respect to data of the MSB slice, and modulation is performed by a 16QAM(Quadrature Amplitude Modulation) modulator (15a-4) where the number of multiple values is large but a transmission characteristics is inferior with respect to data of the LSB slice. The output signals of both modulators are connected on a time base by a multiplexer (15a-5), subjected to band limiting and subsequently transmitted to a transmission path (15b). On a receiving side, the two signals are subjected to band limiting, subsequently sampled, and divided by a demultiplexer (15c-3). The respective two signals are demodulated by a QPSK demodulator (15c-4) and a 16QAM demodulator (15c-5) respectively and outputted as demodulated data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio communication device, a program transmission device and a method thereof using software radio technology, and a radio communication system.

[0002]

2. Description of the Related Art Recently, software defined radio is being developed. Software defined radio is a concept of a system in which basic radio functions (bandwidth, filtering, modulation, demodulation, coding, etc.) can be changed by software. Features of software defined radio include reconfigurability (change of configuration and specifications) and downloadability (program rewriteability). A radio device configured by software defined radio technology is called a software defined radio device. More specifically, in software defined radio technology, microprocessors and DSPs (Digital Signal Pr
ocessor) chip or FPGA (Field Programmable)
Gate Array) to configure a programmable modulator / demodulator for digital wireless communication, and download software to configure the modem of the desired communication method to the modem by wire or wireless, and use the same It can be flexibly realized by hardware.

For example, if different wireless communication systems such as a PHS (Personal Handyphone System), a mobile phone, and a private LAN (Local Area Network) can be realized by a single wireless communication device by downloading software, the user is the same. If you have a wireless terminal device, you can receive services all over the world by downloading a program of the local communication system. For a terminal device manufacturer, mass production becomes possible by sharing hardware, and manufacturing costs can be reduced. In addition, since the functions of the wireless communication device can be easily updated, a communication service provider can easily add a new service, upgrade a function, change a system, correct a software error, and the like. Furthermore, by downloading software via radio, the bit rate, modulation / demodulation method, error correction coding / decoding method, etc. can be set flexibly according to the propagation environment, providing optimal transmission quality for the propagation environment and Enables the number to increase.

FIG. 1 shows an example of a software defined radio apparatus to which the present invention can be applied. The signal of the center frequency fc received from the antenna (1a) passes through the antenna switch (1b) and is input to the low noise amplifier (1j).
The signal output from the low-noise amplifier is
In k), the oscillation frequency f11 of the first local oscillator (1c) is mixed and converted into a signal of the intermediate frequency fi.

The signal converted to the intermediate frequency fi is subjected to quadrature detection by the quadrature detector (11) using the intermediate frequency f12 of the second local oscillator (1d), and is converted to analog baseband signals I and Q. Analog baseband signals I and Q
Are converted into digital baseband signals ID and QD in an A / D converter (1m). Digital baseband signals ID and QD are supplied to a demultiplexer (1p).

The demultiplexer (1p) selects a software transmission packet or information data transmission packet. When downloading software, A
The output data ID and QD of the / D converter are demodulated by a software modulation signal demodulation unit (1o). The demodulated program is downloaded to the programmable baseband digital modulator (1i) or the programmable baseband digital demodulator (1n). After downloading, the demultiplexer (1p) supplies the output data ID and QD of the A / D converter to the programmable baseband digital demodulator (1n), and the desired demodulation processing determined by the program is performed. Done.

[0007] The programmable baseband digital modulator (1i) and the programmable baseband digital demodulator (1n) are, for example, OFDM (orth orthogonal) by a program from a software modulated signal demodulator (1o).
ogonal frequency division multiplexing (orthogonal frequency division multiplexing) type modulation and demodulation function and W-CDM
A (Wideband-CDMA: wideband code division multiple access) modulation and demodulation function can be switched. This modulation / demodulation method is an example of a multi-mode radio,
The present invention provides a GSM (Global System for Mobile Commun
ication: a digital car / mobile phone system in Europe) may be implemented by a program. Further, the present invention is not limited to mobile communication, and can be applied to different systems in a wireless LAN, different systems in an ITS (Intelligent Transport System), and the like.

When transmitting software to be downloaded to a destination station, software stored in a software memory (1q) is modulated by a software modulator (1r), and the digital IQ signal I-I passed through a multiplexer (1s). D and QD are input to the D / A converter (1h). D
The / A converter (1h) converts a digital IQ signal into an analog signal. When transmitting information bits, the modulated data bits are modulated by a programmable baseband digital modulator (1i) in a desired modulation scheme. Modulation section (1i)
Is passed through the multiplexer (1s) and input to the D / A converter (1h) as digital baseband signals ID and QD. Note that the software memory (1q) and the software modulator (1r) are not limited to the base station, but may be provided in the terminal station.

The analog signal is quadrature-modulated in the quadrature modulator (1g) by the oscillation frequency f12 of the second local oscillator (1d), and is converted into a signal of the intermediate frequency fi (= f12). The signal modulated to the intermediate frequency fi is transmitted to the transmission mixer (1
In f), by the frequency f11 of the first local oscillator (1c),
The signal is converted into a signal of frequency fc (= f12 + f11).

[0010] The OFDM modulated signal converted to the frequency fc is amplified to a predetermined transmission power in a power amplifier (1e). The amplified signal is supplied to the antenna (1a) via the antenna switch (1b) and transmitted. MMAC
(Mu1timedia mobi1e accesscommunication system) and W
In mobile radio communication using a broadband spectrum such as CDMA (Wideband code division mu1tip1e access), the sampling frequency of the A / D converter (1m) and the D / A converter (1h) is several tens MSPS (Mega). samples per se
cond).

FIG. 2 shows a configuration example of a link packet for wirelessly downloading software for a software defined radio system and a configuration example of a link packet for transmitting information data. This link is a downlink from the base station to the terminal station. Packets are packets for transmitting software (2a-1, 2a-2, ..., 2a-k) and information packets for transmitting information data (2b-1, 2b-2, ..., 2b-n) Consists of

A software packet is composed of a preamble (2
c) and software (2d). The software (2d) adds a CRC (Cyc1i
c) data (2e) for redundancy check) and configuration data (2f) for reconfiguring a program or FPGA input to the microprocessor (or DSP). The information packet includes a preamble (2g) and information symbols (2h-1, 2h-2, ..., 2h-m).

A preamble, which is a known signal, is detected from the received data, and packet timing synchronization, frequency synchronization, and transmission path equalization are performed based on the detection. Error detection is performed on the received software by CRC.
If an error is detected, the packet is discarded and retransmission is requested. Only when no error is detected, the program is demodulated and an ACK signal (acknowledge signal) is transmitted to prompt transmission of the next packet. When all the programs have been demodulated, the demodulated programs are downloaded to the baseband digital signal modulation section (1i) and the demodulation section (1n), and the desired modulation / demodulation method is set. After receiving the information packet and performing packet timing synchronization, frequency synchronization and transmission path equalization on the preamble (2g), the information packet information symbols (2h-1, 2h-2, ..., 2h-m) The information data is demodulated by the demodulation method set for.

FIG. 3 shows an example of the configuration of a link (uplink) packet transmitted from a terminal station to a base station by a modulator to which software has been downloaded in a software defined radio system. Packet (3a-1,
3a-2,..., 3a-n) are composed of a preamble (3b), which is a known signal, and information data (3c). The information data (3c) is composed of information symbols (3d-1, 3d-2, ..., 3d-m). On the receiving side, based on the detection of the preamble, packet timing synchronization, frequency synchronization, transmission path equalization are performed, and then information symbols are demodulated.

FIG. 4 shows an example of packet retransmission processing in the software defined radio system. In a software defined radio system, modulation and demodulation of information data to be transmitted is performed by a modem to which software is downloaded. There is a possibility that a failure occurs in the modulation / demodulation unit due to a software error generated by the wireless transmission path.
Therefore, the error detection by the CRC is performed on the wireless transmission packet of the software, and the retransmission process is repeatedly performed until the packet becomes error free (no error).

For example, the first software packet 1 (4a) is transmitted from the software transmitting station. An error is detected by CRC for the received packet, and when the error is detected, the retransmission request signal (4b) is transmitted to the transmitting station until no error is detected. FIG. 4 shows software packet 1 transmitted after performing two retransmission requests.
Since the example is error-free in (4e), the same packet (4a, 4c, 4e) is retransmitted three times. After becoming error free, the ACK signal (4f) is transmitted to the software transmitting side.

After repeating these operations, the final software packet k (4k) is received, and demodulation of all software is completed. The decrypted software is downloaded to a programmable modulation / demodulation unit, and a desired modulation / demodulation process can be performed. After transmitting the ACK signal (41) for the final software packet k (4k), the information packet (4
m, 4n, ..., 4o) are transmitted.

Next, the processing contents of the programmable baseband digital demodulator (1n) of FIG. 1 will be described.
Generally, the processing of the demodulation unit is more complicated than the modulation unit,
Only the demodulation unit will be described. As an example, MMAC is a mobile radio communication system using a broadband spectrum.
And the configuration of the demodulation unit of WCDMA will be described.

FIG. 5 shows a configuration example of an OFDM demodulation unit for MMAC. Input digital baseband signal I
First, the packet timing synchronization unit (5a)
After obtaining the packet timing synchronization in, the carrier frequency is synchronized by the carrier frequency synchronization unit (5b), and the memory (5c)
After writing data in FFT (fast Fouriertr
ansform) (5d) to transform to the frequency domain. If the number of subcarriers is NFFT, in FFT (5d),
A fast Fourier transform of the NFFT points, ie, NFFT
The signal is demodulated into parallel reception data at point T. Thereafter, the transmission path is equalized by the equalizer (5e), the error bit is corrected by the error correction code decoder (5f), and the result is output as a demodulated bit.

FIG. 6 shows an example of the configuration of a WCDMA spread spectrum type demodulation unit. The input digital baseband signals I-D and Q-D are first synchronized in the packet timing in the packet timing synchronization section (6a) and then synchronized in the carrier frequency in the carrier frequency synchronization section (6b). After writing the data in the memory (6c), the despreading / equalization unit (6d) performs despreading and transmission path equalization using a predetermined spreading code. The output of the despreading / equalizing unit (6d) is supplied to the error correction code decoder (6e), where the error bit is corrected by the decoder (6e), and the demodulated bit is output.

In the demodulation unit as shown in FIG. 5 and FIG. 6, the processing of the FFT, despreading, equalizer, etc., is performed on the sampling data input at a rate of several tens MSPS in real time. There is a need to do. In a software defined radio system, these processes are implemented by programmable hardware. It is also conceivable to use an ultra-high-speed general-purpose microprocessor that operates with a clock of several hundred MHz as a programmable device. However, since the power consumption depends on the clock frequency, it is difficult to design a practical portable information terminal device that operates on a battery.

FPGA as a programmable device
By using the above, signal processing hardware for demodulation with relatively low power consumption and high speed can be realized. 100
Large-scale FPGAs with more than 10,000 gates are also on the market, so OFDM for MMAC with more than 1.4 million gates
The function of the LSI can be sufficiently realized by using several FPGAs. However, in order to program the FPGA to a desired function, the configuration data for programming the function of the reconfigurable logic circuit inside the FPGA, the connection between the logic circuits, and the like are required. In order to program the above-described OFDM LSI for MMAC, 8 Mbits of configuration data is required.

In the description of this specification, "software"
Alternatively, the term “program” includes configuration data that defines the function of the FPGA.

The FPGA constituting the baseband processing section will be described. FIG. 7 shows the internal configuration of the FPGA. First, configuration data is externally supplied to the FPGA chip (7a), and is written to the configuration memory (7c). The function of each circuit is programmed by this data.

A CLB (Configurab 1e 1ogic b1ock) (7g), which is a programmable logic circuit block, can be formed into a small-scale logic circuit desired by the user by using the corresponding configuration data. IOB (Input / outpu
t b1ocks) (7d) is an interface circuit for signals outside and inside the chip, and is also a kind of current amplifier. The logic voltage is set to a predetermined logic amplitude voltage by the corresponding configuration data, and has a function of converting an external logic voltage to an internal logic voltage. RC (Routing channe1) (7e) is a data bus connecting each block, and
Data transfer between B or between CLB and IOB is performed.
Programmable switch PSM (Programmab1e
switch matrix) (7f) and CB (Connection Block) (7h)
Arranged in a matrix, the connection between RCs is set according to the corresponding configuration data, and data can be exchanged between blocks.

FIG. 8 shows an example of the internal configuration of the CLB. CL
B is a 4-input, 1-output LUT (Look-up tab 1e) (8a, 8b), a 3-input, 1-output LUT (8c), and a programmable logic circuit CL (Carry 1ogic) ( 8
d, 8e), 9 multiplexers (8f, 8g, 8h, 8i, 8j, 8k, 81,8
m, 8n) and two registers (8o, 8p). CLB
Is an SRAM, and an input corresponds to an address. For a 4-input and 3-input CLB, 16-bit and 8-bit configuration data can be downloaded to configure an arbitrary logic circuit. [Table 1] shows an example of a truth table of a 4-input LUT.

[0027]

[Table 1]

The CL can realize one of several logic circuits defined in advance by the corresponding configuration data. Further, the control signal of each multiplexer is also set by the configuration data. Various configuration data
By providing the data to LB, a desired logic circuit including a register can be realized.

As described above, by supplying the configuration data from the configuration memory shown in FIG. 7 to the IOB, PSM, CB, and CLB, a logic circuit having desired specifications can be realized by the FPGA.

An adder, a multiplier, and an optional two-input arithmetic circuit designed using an FPGA block will be described below. In order to simplify the description, the contents of the LUT and CL setting data will be referred to as configuration data unless otherwise specified.

FIG. 9 shows an example of the configuration of a 9-bit adder designed using an LUT and a CL of an FPGA. This is a ripple carry type adder in which a carry signal propagates from the lower bits. Bits a8-a0 and b8 of the input data bus expressed in two's complement
-B0 is the first stage LUT (9a-1, 9a-2, 9a-3, 9a-4, 9a-5, 9
a-6, 9a-7, 9a-8, 9a-9, 9a-10). LUT (9a-
1) generates a control signal indicating that an overflow has occurred. Other LUTs calculate the sum of two bits of data having the same weight and a carry signal from the lower bits.

CL (9b-1, 9b-2, 9b-3, 9b-4, 9b-5, 9b-6)
Performs the generation of a carry signal for each corresponding bit of the input data bus and the propagation of the carry signal from lower bits to upper bits. LUT (9c-1, 9c-2, 9c-3, 9c-4, 9
In c-5, 9c-6, 9c-7, 9c-8), the encoding process corresponding to the two's complement representation for the sum output and the saturation process at the time of overflow are performed. In addition to this example, various adder algorithms have been proposed.

FIG. 10 shows a configuration example of a 3 × 2 bit multiplier designed using an LUT and a CL of an FPGA. 2
Input data a2, a1, a0 and b1, b0 expressed in complements of
Are the corresponding LUTs (10a-1, 10a-2, 10a-3), L
It is converted into an absolute value by UT (10a-5, 10a-6) and CL (10b-1, 10b-2, 10b-3). The sign of the product is determined by the LUT (1Oa-4). The bits a'2, a'1, a0 'and b'1, b'0 of the absolute value are supplied to the LUT (10c-1, 10c-2, ..., 10c-6), and the LUT (10c- 1,10c-2, ..., 10c-6) is used to calculate the partial product. The partial product is LUT (10d-1, 10d-2, 10d-
3), CL (1Oe-1,10e-2), LUT (10f-1,10f-2, ..., 10f-
5) and CL (10g-1, 10g-2, 10g-3, 10g-4) are added by an addition tree to calculate a product.

An arbitrary two-input arithmetic circuit is designed using an LUT. Table 2 shows two inputs 1 having a data word length of 12 bits.
An example of the truth table of the output operation circuit is shown as [Table 2].

[0035]

[Table 2]

FIG. 11 shows an LUT based on this truth table.
1 shows a configuration example of an arithmetic circuit designed according to the above. Since the total number of bits of input data is 24 bits, 24 inputs 1
This can be realized by preparing 12 output logic circuits. The output bits c11 (MSB), c10,..., C0 (LSB)
Calculated by the logic circuits (11 ₁₁ , 11 ₁₀ ,..., ₁₁₀ ). Each logic circuit has eight LUs for inputting 24-bit data.
T (11a-1,11a-2,11a-3,11a-4,11a-5,11a-6,11a-7,11a-
8).

The configuration data is written into each LUT of each logic circuit so as to satisfy the truth table (Table 2). The configuration shown in FIG. 11 is an example in which the number of LUTs is the largest because LUTs are directly connected in a tree shape. Depending on the contents of the truth table, it is possible to reduce the number of LUTs by simplifying the logical expression.

The timing synchronizer (5) shown in FIGS.
a, 6a), the carrier frequency synchronizing units (5b, 6b), the FFT (5d), and the despreading / equalizing unit (6d) mainly perform correlation calculations.
In the OFDM transmission path equalization (5e) process, division is performed.
That is, to configure a processing circuit on an FPGA,
Multipliers, adders, and dividers are required. Input data is input at a sampling rate of several tens of MHz, and it is necessary to perform calculations in real time. If it is assumed that the operation time of the operation circuit composed of the LUT and CL of the FPGA is several tens of nsec, it is difficult to share hardware in a time-division manner, and each operation unit requires its own operation circuit. Becomes Therefore, an enormous number of LUTs and CLs are required to configure the entire baseband modulation / demodulation processing.
For example, in order to realize only the MMAC FFT on the FPGA, about the same number of CLs as 2,300 or more LUTs are required. Large amounts of configuration data are required to program them. Furthermore, MMAC
Since the OFDM modulation / demodulation LSI has a scale of 1.4 million gates or more, assuming that this is configured by an FPGA, configuration data of 8 Mbits or more is required.

[0039]

As shown in FIG.
In the conventional wireless download method of software, CRC is performed on received software, and after error-free is confirmed, download is performed to a programmable device. If an error is detected, a retransmission request is made until the error becomes free. This method requires retransmission of an enormous amount of configuration data many times until an error-free condition is reached in a poor propagation environment, and an enormous amount of time is spent until the download is completed.

If the download time of the configuration data increases, the transmission efficiency of information data that should be transmitted as shown in the packet configuration diagram of FIG. 2 deteriorates. Also, in an adaptive transmission scheme that wirelessly downloads and implements an optimal function according to a propagation path environment that changes every moment, configuration data for implementing the function needs to be transmitted promptly. In the transmission method involving retransmission, the propagation environment changes drastically before the wireless download is completed, and an optimal function for the propagation environment after the download is completed cannot be realized on the FPGA. Therefore, in order to utilize the features of the software defined radio system, it is necessary to establish a highly efficient wireless transmission / download method of software including FPGA configuration data.

Accordingly, an object of the present invention is to provide an FPGA
It is an object of the present invention to provide a wireless communication device, a program transmission device and a method thereof, and a wireless communication system capable of improving the transmission efficiency of a program such as configuration data.

[0042]

According to a first aspect of the present invention, a part or all of hardware is configured by a programmable logic circuit, and a program for the logic circuit is received. Thus, in a wireless communication apparatus that realizes a desired wireless communication method, a logic circuit of a binary arithmetic circuit constituted by a programmable logic circuit has a power of 2 weight corresponding to each bit of its input / output. The first program is divided into at least first and second groups according to the size, and a first program for the first group of logic circuits having a large weight is modulated and transmitted by a first method with a small number of bit errors, and the weight of the first program is reduced. A wireless communication apparatus in which a program for a small second group of logic circuits is modulated and transmitted by a second method having excellent transmission efficiency. A.

According to a third aspect of the present invention, a part of or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In the device, a logic circuit of a binary arithmetic circuit constituted by a programmable logic circuit has a logic circuit corresponding to each input / output bit.
Are divided into at least first and second groups according to the magnitude of the exponentiation weight, and the first program for the logic circuit of the first group having the large weight uses an encoding method with high error correction capability. The second program transmitted to the second group of logic circuits having a small weight is a wireless communication device configured to be transmitted using a coding scheme with a high coding rate.

According to a fourth aspect of the present invention, a part or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In the device, a logic circuit of a binary arithmetic circuit constituted by a programmable logic circuit has a logic circuit corresponding to each input / output bit.
Are divided into at least a first group and a second group according to the magnitude of a power of the first group, and a first program for a first group of logic circuits having a large weight is modulated at a low symbol rate and transmitted. A wireless communication device configured to transmit a program for a logic circuit of a second group having a small symbol at a high symbol rate.

According to a fifth aspect of the present invention, a part of or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In the apparatus, a programmable logic circuit is divided into an arithmetic circuit and a non-arithmetic circuit, and a part of the first program for the arithmetic circuit is transmitted without performing a retransmission process, and a part of the first program for the arithmetic circuit and a non-arithmetic circuit are transmitted to the arithmetic circuit. The second program is a wireless communication device that performs retransmission processing to transmit data with enhanced reliability.

According to a seventh aspect of the present invention, a part or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In the device, a logic circuit of a binary arithmetic circuit constituted by a programmable logic circuit has a logic circuit corresponding to each input / output bit.
Are divided into at least first and second groups according to the magnitude of the power of the first power, and the first program for the logic circuit of the first group having the higher weight is the first program
And a second program for a second group of logic circuits having a small weight is transmitted by a transmission method in which two or more of the modulation method, the first error correction code, and the first symbol rate are combined. The signal is transmitted by a transmission method that combines two or more of a modulation method, a second error correction code, and a second symbol rate. The first modulation method has a smaller number of errors than the second modulation method. The first error correction code has higher error correction capability than the second error correction code, and the first symbol rate has a lower value than the second symbol rate. It is a wireless communication device.

According to an eighth aspect of the present invention, a part of or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In the device, a logic circuit of a binary arithmetic circuit constituted by a programmable logic circuit has a logic circuit corresponding to each input / output bit.
Are divided into at least a first group and a second group according to the magnitude of the power of, and the first and second programs are transmitted using a modulation scheme having a relatively large number of values, and the first program having a large weight is transmitted. The program of the group is assigned to a bit position where transmission is better than the average error rate of the modulation scheme, and the program of the second group having a smaller weight has transmission characteristics inferior to the average error rate of the modulation scheme. The wireless communication device is assigned to the bit position of the wireless communication device.

According to a twelfth aspect of the present invention, a part of or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a transmission method for transmitting a program to a device, a logic circuit of a binary number arithmetic circuit constituted by a programmable logic circuit is configured to at least perform a first power operation according to the magnitude of a power of 2 corresponding to each bit of input and output. And a second program divided into two groups and modulated and transmitted by a first method with a small number of bit errors for a first group of logic circuits having a large weight, and a logic of a second group having a small weight is transmitted. This is a program transmitting apparatus that modulates and transmits a program for a circuit by a second method having excellent transmission efficiency. The invention according to claim 22 is a method for transmitting a program in this way.

According to a fourteenth aspect of the present invention, a part of or all of hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a transmitting device for transmitting a program to a device, a logic circuit of a binary number arithmetic circuit constituted by a programmable logic circuit has at least a first power of 2 depending on the magnitude of a power of 2 corresponding to each input / output bit. And a first program for the first group of logic circuits, which is divided into two groups and has a large weight, is transmitted using an encoding method having a high error correction capability, and the logic of the second group having a small weight is transmitted. This is a program transmitting apparatus that transmits a second program for a circuit using an encoding method with a high encoding rate. The invention according to claim 24 is a method for transmitting a program as described above.

According to a fifteenth aspect of the present invention, a part of or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a transmitting device for transmitting a program to a device, a logic circuit of a binary number arithmetic circuit constituted by a programmable logic circuit has at least a first power of 2 depending on the magnitude of a power of 2 corresponding to each input / output bit. And a first program for a first group of logic circuits having a large weight, which is divided into two groups and modulated at a low symbol rate for transmission, and a program for a second group of logic circuits having a small weight is transmitted. Is modulated at a high symbol rate and transmitted.
The invention according to claim 24 is a method for transmitting a program as described above.

According to a sixteenth aspect of the present invention, a part of or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a transmission device for transmitting a program to an apparatus, a programmable logic circuit is divided into an operation circuit and a non-operation circuit, and a part of the first program for the operation circuit is transmitted without performing retransmission processing. And a second program for a part of the non-arithmetic circuit and a non-arithmetic circuit are retransmitted and transmitted with high reliability.
The invention according to claim 26 is a method for transmitting a program as described above.

The invention according to claim 18 is a wireless communication system in which a part or all of hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a transmitting device for transmitting a program to a device, a logic circuit of a binary number arithmetic circuit constituted by a programmable logic circuit has at least a first power of 2 depending on the magnitude of a power of 2 corresponding to each input / output bit. And a first program for the first group of logic circuits, which is divided into two groups and has a large weight, is divided into two of the first modulation scheme, the first error correction code, and the first symbol rate.
A second program for the second group of logic circuits having a small weight is transmitted by a transmission method combining the above, and two or more of the second modulation method, the second error correction code, and the second symbol rate are transmitted. The transmission is performed by the combined transmission method, and the first modulation method is assumed to have fewer errors than the second modulation method, and the first error correction code has a lower error rate than the second error correction code. It is said that the ability to correct
Is a program transmission device whose symbol rate is lower than the second symbol rate. Claim 28
The invention of the above is a method of transmitting a program in this way.

A wireless communication system according to a nineteenth aspect of the present invention is configured such that a part or all of hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a transmitting device for transmitting a program to a device, a logic circuit of a binary number arithmetic circuit constituted by a programmable logic circuit has at least a first power of 2 depending on the magnitude of a power of 2 corresponding to each input / output bit. And the second group is divided into two groups, and the first and second programs are transmitted by using a modulation scheme having a relatively large number of values, and the programs of the first group having a large weight are transmitted by the average error rate of the modulation scheme. The second group of programs having a lower weight is inferior to the average error rate of the modulation scheme. A program transmitting device to be assigned to the bit position having the transmission characteristics. The invention according to claim 29 is a method for transmitting a program in this way.

According to a thirty-second aspect of the present invention, a part of or all of hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a wireless communication system including a device and a transmitting device that transmits a program to the wireless communication device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit formed of a programmable logic circuit has input and output signals of each of the input and output. The transmission device is divided into at least first and second groups according to the magnitude of the power of 2 corresponding to the bit, and the transmission device executes the first program for the logic circuit of the first group having the larger weight with a bit error. Modulation and transmission by the small first method, and excellent transmission efficiency of programs for the second group of logic circuits having a small weight. A wireless communication system adapted to transmit modulated by the second method.

A thirty-third aspect of the present invention provides a wireless communication system in which a part or all of hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a wireless communication system including a device and a transmitting device that transmits a program to the wireless communication device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit formed of a programmable logic circuit has input and output signals of each of the input and output. The transmission device is divided into at least first and second groups according to the magnitude of the power of 2 corresponding to the bit, and the transmission device performs the error correction capability of the first program for the logic circuit of the first group having the larger weight. And a second program for the second group of logic circuits having a small weight is transmitted at a coding rate of A wireless communication system adapted to transmit using a higher coding scheme.

According to a thirty-fourth aspect of the present invention, a part of or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a wireless communication system including a device and a transmitting device that transmits a program to the wireless communication device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit formed of a programmable logic circuit has input and output signals of each of the input and output. The transmission device is divided into at least first and second two groups according to the magnitude of the power of two corresponding to the bit, and the transmitting device executes the first program for the logic circuit of the first group having the large weight by using a low-speed symbol. The program for the second group of logic circuits having a small weight is transmitted at a high symbol rate. Modulation to a radio communication system adapted to transmit.

According to a thirty-fifth aspect of the present invention, a part or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a wireless communication system comprising a device and a transmitting device for transmitting a program to the wireless communication device, the wireless communication device has a programmable logic circuit divided into an arithmetic circuit and a non-arithmetic circuit, and the transmitting device has an arithmetic circuit Some first against
This is a wireless communication system in which the program is transmitted without performing retransmission processing, and the second program for a part of the arithmetic circuit and the non-operational circuit is retransmitted and transmitted with high reliability.

According to a thirty-sixth aspect of the present invention, a part or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a wireless communication system including a device and a transmitting device that transmits a program to the wireless communication device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit formed of a programmable logic circuit has input and output signals of each of the input and output. The transmission device is divided into at least first and second groups according to the magnitude of the power of 2 corresponding to the bit, and the transmission device executes a first program for the logic circuit of the first group having the larger weight in the first group. The signal is transmitted by a transmission method in which two or more of the modulation method, the first error correction code, and the first symbol rate are combined. A second program for the second group of logic circuits is transmitted by a transmission method combining two or more of a second modulation method, a second error correction code, and a second symbol rate, and the first modulation method is used. Are assumed to have fewer errors as compared to the second modulation scheme, the first error correction code is assumed to have a higher error correction capability than the second error correction code, and the first symbol rate is Is a wireless communication system that is lower than the second symbol rate.

According to a thirty-seventh aspect of the present invention, a part of or all of the hardware is constituted by a programmable logic circuit, and a desired wireless communication system is realized by receiving a program for the logic circuit. In a wireless communication system including a device and a transmitting device that transmits a program to the wireless communication device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit formed of a programmable logic circuit has input and output signals of each of the input and output. Divided into at least first and second two groups according to the magnitude of the power of two corresponding to the bits, the transmitting apparatus uses the modulation scheme having a relatively large number of values for the first and second programs. And assigning a program of the first group having a large weight to a bit position at which transmission that is superior to the average error rate of the modulation scheme is possible, Only a wireless communication system for allocating the bit position having the transmission characteristics inferior average error rate of the modulation scheme is smaller program of the second group.

According to the present invention, the transmission method of the program for the programmable logic circuit is changed according to the degree of importance. In other words, it is divided into those that have a large effect of program errors and those that are not, and those that have a large error are transmitted so that errors do not easily occur during transmission. ,
Transmission is made with emphasis on transmission efficiency.

[0061]

Embodiments of the present invention will be described below. For ease of understanding the present invention, a programmable logic circuit, for example, an arithmetic circuit will first be described. In general, main signal processing circuits for digital wireless communication such as an FFT, a correlator, and a digital filter are constituted by an adder, a subtractor, and a multiplier based on a binary operation. In an FPGA, these arithmetic circuits are configured using a large number of LUTs. In the case of an arithmetic unit based on a binary number system, each bit of the data bus is weighted by a power of two. Each bit of the data bus is connected to the input / output of the LUT.

An error bit occurs in the configuration data transmitted wirelessly. The error bit causes an error in the operation result. The effect on the operation result differs depending on the weight assigned to the bit handled by the LUT. 4-input 1-output LU having 16-bit configuration data having the same number and positions of error bits
When T is connected to the LSB of the input / output bus of the arithmetic unit, the effect of the arithmetic error is small because the arithmetic error is small with respect to the data dynamic range.

However, if the LUT is connected to the MSB of the input / output bus of the arithmetic unit, the arithmetic error becomes relatively large with respect to the dynamic range of the data.
Arithmetic errors have a significant effect on the results. That is, the influence of the LUT configuration data error on the transmission quality of a communication device programmed with the configuration data, for example, the BER (Bit Error Rate), depends on the LUT including the configuration data error. It depends on whether processing is performed for

For example, in the case of the 9-bit adder shown in FIG. 9, each bit of the input / output data bus has LSB to M bits.
Each 2 ⁰ for ^{SB, 2 1, 2 2,} 2 3, 2 4, 2 5,
2 ^6, 2 ^7, weights -2 ⁸ is attached. Focusing on the LUT (9c-8) connected to the LSB of the sum output data bus and the LUT (9a-2) connected to the MSB, a similar error bit occurs in the configuration data of both LUTs. , LU maximum value of the error generated in the output data bus of the sum is respectively connected 2 ⁰ and -2 ⁸ next to MSB
The influence of the error bit of the configuration data of T (9a-2) is great. If it is part of the demodulator circuit,
The effect on BER is equally large.

In consideration of such points, in the present invention, the data bus of the operand of the arithmetic unit is divided into a plurality of groups. For simplicity, the LUT connected to the bits of the data bus is divided into two slices. The LUT group and the CL group on the MSB side are called an MSB slice, and the LUT group and the CL group on the LSB side are called an LSB slice. In a broad sense, slice is an LUT
And CL configuration data. For example, comparing the weight of the input / output data bits of both slices, the weight of the bit handled by the LUT belonging to the MSB slice is larger. Assuming that an error has occurred with the same probability in the configuration data of all LUTs, the LUT belonging to the MSB slice has the LS
The error of the operation result is larger than that of the LUT belonging to the B slice, and the influence of deteriorating the BER of the demodulator is large.

Therefore, a transmission method with excellent transmission characteristics in which bit errors are unlikely to be applied to the MSB slice, and a transmission method with excellent transmission efficiency even if the transmission characteristics are inferior to the LSB slice. Apply. in this way,
By properly using a transmission method for both slices, the total number of symbols can be reduced, so that transmission time can be reduced. Hereinafter, slice division in a case where the present invention is applied to some of the arithmetic circuits described above will be described.

FIG. 12 shows an example in which a 9-bit adder converts an LUT to M for an operand input and sum output data path.
An example of dividing into an SB slice and an LSB slice is shown. C
Assume that the configuration data of L is 16 bits. Assuming that the number of LUTs belonging to the MSB slice on the operand side and the number of LUTs belonging to the MSB slice are three and four, respectively, the number of LUTs belonging to the LSB slice is four and five, respectively. The number of CLs belonging to the MSB slice and the LSB slice is three each. The number of bits of the configuration data depends on the number of LUT and CL
16 which is the number of bits of the configuration data of
Multiplied by.

The configuration bits of the MSB slice are 12 × 16 = 192 bits, and the configuration bits of the LSB slice are 12 × 16 = 1.
It becomes 92 bits.

FIG. 13 shows an example of a configuration in which slice division is performed on the 3 × 2 bit multiplier shown in FIG. In FIG. 13, the LUTs and CLs assigned to the MSB slices are indicated by underlining these characters in the block. On the other hand, the LUT and CL assigned to the LSB slice are shown without underlining these characters in the block. Two LUTs (13a-LUTs) are converted from the MSB to the input buses a2, a1, a0 and b1, b0 from the MSB.
1, 13a-2, 13a-5) are allocated to the MSB slice. Further, an LUT (13a-4) for outputting the sign of the product, an LUT (13c-1, 13c-2, 13c-3) for calculating the partial product, and an LUT (13d-1, 13
d-2), CL (13e-1), LUT (13f-1, 13f-2, 13f-3) and CL (13g-1, 13g-2, 13g-3) are allocated to the MSB slice. The configuration data of the LUT and CL belonging to the MSB slice is 18 × 16 = 288 bits. For the LSB slice, the configuration data is 11 × 16 = 176 bits.

FIGS. 14 and 15 show an example of a configuration in which slicing is performed on an arbitrary two-input arithmetic circuit shown in FIG. Due to the limitation of the drawing space, one drawing is originally divided into two of FIG. 14 and FIG. FIG.
4 and FIG. 15, the LUT and CL assigned to the MSB slice are underlined for these characters in the block. On the other hand, the LUT and CL assigned to the LSB slice are shown without underlining these characters in the block. As shown in FIG. 14, a logic circuit (14 ₁₁ ) that outputs the MSB c11
, The configuration data of all the LUTs (14a-1, 14a-2,..., 14a-8) are allocated to the MSB slice.
In the LUT in the logic circuit (14 ₁₀ ) that outputs c10,
LUT (14b-1, 14b) close to the MSB bit of the input data bus
-2, 14b-4, 14b-5, 14b-7, 14b-8) are allocated to the MSB slice. As shown in FIG. 15, for the logic circuit (14 ₀ ) that outputs the LSB c0, the LUT (14c-1, 14c-4) that handles the MSB bit and the LUT (14c-7, 14c-7, The configuration data of 14c-8) is allocated to the MSB slice.

The above example is mainly an arithmetic circuit,
Circuits other than arithmetic circuits that handle clock signals, circuits that generate or receive control signals that determine functions, PMS and CB control signals that determine connections between CLBs, multiplexer control signals in CLBs, and logical operations in bit units The present invention can also be applied to configuration data for configuring an error correction code encoding or decoding circuit or the like for which high reliability is required. An embodiment in which the present invention is applied to configuration data for configuring a circuit other than an arithmetic circuit will be described later.

Further, even if the transmission time of the configuration data is equal, if the error of the configuration data is reduced, the failure rate of the downloaded hardware can be reduced and the reliability can be improved. This method will be described later as a method that can improve the transmission efficiency of configuration data.

A plurality of embodiments to which the present invention is applied to configuration data of each divided slice will be described below.

The first embodiment of the present invention applies a different modulation method to each slice. MSB
For configuration data for a slice LUT, the transmission method is excellent in transmission characteristics and bit error is unlikely to occur, for example, QPSK (quadrature phase) with a small number of values.
(se shift keying). Conversely, for the configuration data for the LUT of the LSB slice, a transmission method with excellent transmission efficiency even if the transmission characteristics are inferior, for example, a large number of multi-valued, but 16QAM (Quadr) with poor transmission characteristics
(ature Amplitude Modulation) Performs modulation. 16QAM
Although the number of error bits of the configuration data modulated in step (1) increases, it is considered that the operation error due to the bit error of the configuration data on the LSB side is relatively small. If the configuration data is transmitted in this manner, the number of transmission symbols obtained by modulating the configuration data can be reduced without significantly deteriorating the BER.

In the 9-bit adder, based on the allocation result for each slice described with reference to FIG.
An SB slice transmits two bits per symbol.
The PSK modulation is 96 symbols, and the LSB slice is 16QAM modulation transmitting 4 bits per symbol. Therefore, it is 48 symbols, which requires a total of 144 symbols. When QPSK modulation is performed on both slices, 192 symbols are required. Therefore, all QP
It is possible to reduce the number of symbols, that is, the transmission time of configuration data, by about 25% compared to the case of modulation by SK.

FIG. 16 shows a transmission system in the base band of the configuration data according to the first embodiment of the present invention. The transmission system includes a transmitter (15a) that wirelessly transmits configuration data, a transmission path (15b), and a receiver (15c) that receives configuration data. In the receiver (15c), descriptions of a symbol timing synchronization section, a carrier frequency synchronization section, a transmission path equalization section, and the like are omitted.

The memory (15a) storing the configuration data of the LUT assigned to the MSB slice
From (-1), data is supplied to the QPSK modulator (15a-3). Data is supplied to the 16QAM modulator (15a-4) from the memory (15a-2) storing the configuration data of the LUT to be allocated to the LSB slice. Q
PSK modulator (15a-3) and 16QAM modulator (15a-4)
Are combined on the time axis by the multiplexer (15a-5), band-limited by the roll-off filter (15a-6), and then transmitted to the transmission path (15b).

On the receiving side, a roll-off filter (15c-1)
After the band is limited by the sampling, sampling is performed at a symbol period by the sampler (15c-2). Sampler (1
The output of 5c-2) is supplied to a demultiplexer (15c-3), and separated into a QPSK modulation waveform and a 16QAM modulation waveform by the demultiplexer (15c-3).
The signal is demodulated by the demodulator (15c-4) and the 16QAM demodulator (15c-5). The bit demodulated by each demodulator is used as a multiplexer.
The signal is synthesized in (15c-6) and output as demodulation configuration data.

Next, a second embodiment of the present invention will be described. The second embodiment uses a different error correction code. The configuration data for the LUT belonging to the MSB slice is encoded into an error correction code having a high error correction capability. In this case, the coding rate generally decreases. The coding rate means the ratio (k / n) between the number k of bits originally representing information and the number n of bits actually transmitted or stored. If the coding rate is high, the redundancy is small, but the error correction capability is small. L
For the configuration data of the SB slice, a coding method having a relatively high coding rate but inferior to the method used for coding the configuration data of the MSB slice in error correction capability is used.

For example, in the case of a 9-bit adder, MS
For the B slice, the coding rate is 1/2,
If the LSB slice is performed by 3/4, the number of bits after encoding is 192 × 2 + 192 × (4/3) = 640 bits. When both slices are coded at a coding rate of 1/2, there are 384 × 2 = 768 bits, and a transmission time reduction of about 17% is possible.

FIG. 17 shows a transmission system in the base band of the configuration data according to the second embodiment. The transmission system includes a transmitter (16a) for wirelessly transmitting configuration data, a transmission path (16b), and a receiver (16c) for receiving configuration data. In the receiver (16c), descriptions of a symbol timing synchronization section, a carrier frequency synchronization section, a transmission path equalization section, and the like are omitted. As a modulation method, QPSK is assumed as an example.

Memory (16a-1) in which configuration data of the LUT belonging to the MSB slice is stored
From the error correction code encoder (16
a-3). Memory storing configuration data of LUT belonging to LSB slice side
Data is supplied from (16a-2) to an error correction code encoder (16a-4) having a coding rate of 3/4. Encoders (16a-3) and (1
The bits encoded by 6a-4) are
a-5). After that, the QPSK modulator (1
After being modulated by 6a-6) and band-limited by the roll-off filter (16a-7), it is transmitted to the transmission path (16b).

After the band is limited by the roll-off filter (16c-1) on the receiving side, sampling is performed at the symbol period by the sampler (16c-2). Sampler (16c-
The output of (2) is supplied to a demultiplexer (16c-3), and the demultiplexer (16c-3) separates the separated data into error correction code decoders (16c-4, 1c) having different coding rates.
6c-5). In the configuration of FIG. 17, the decoder (16c-
4, 16c-5) makes a soft decision. When decoding hard decisions, a QPSK demodulator is inserted between the sampler (16c-2) and the demultiplexer (16c-3), demodulated into bits, distributed to the decoder, and decoded. Will be The decoded bits are combined by the multiplexer (16c-6) and output as configuration data. When performing encoding and decoding at different encoding rates, hardware can be efficiently configured by performing puncturing and depuncturing processing appropriate for the encoding rate using a convolutional code as an error correction code.

Next, a third embodiment of the present invention will be described. In the third embodiment, a different symbol rate is adopted as a software transmission method for each slice. Considering transmission in an environment where radio wave propagation is degraded, that is, in a multipath (multi-propagation wave) environment, the smaller the symbol rate, the better the BER of transmission bits. Therefore, for the configuration data for the LUT belonging to the MSB slice, the symbol rate is set smaller than that of the LSB slice.

In the example of the 9-bit adder, assuming the QPSK modulation method, the number of symbols is 96 for 192 bits of the MSB slice. 1 of LSB slice
The number of symbols is 96 even for 92 bits. For example, the symbol rate of each slice is set so that the MSB slice is transmitted at a symbol rate of 1 and the LSB slice is transmitted at a symbol rate of 2. In that case, the symbol transmission time of the MSB slice is 96 × 1 = 96, and the symbol transmission time is 96 × 1 for the LSB slice.
× (1/2) = 48, and the total symbol transmission time is 144
Becomes If all bits are transmitted at a symbol rate of 1, then
Since (96 + 96) × 1 = 192, the transmission time can be reduced by about 25%.

FIG. 18 shows a transmission system in the base band of configuration data according to the third embodiment. The transmission system includes a transmitter (25a) that wirelessly transmits configuration data, a transmission path (25b), and a receiver (25c) that receives configuration data. In the receiver (25c), descriptions of a symbol timing synchronization section, a carrier frequency synchronization section, a transmission path equalization section, and the like are omitted. As a modulation method, QPSK is assumed as an example.

Memory (25a-1) in which configuration data of LUT belonging to MSB slice is stored
From the QPSK modulator (25a
-3). The modulation output of the QPSK modulator (25a-3) is supplied to the multiplexer (25a-6). The data is supplied from the memory (25a-2) in which the configuration data of the LUT belonging to the LSB slice is stored to the QPSK modulator (25a-4) having the symbol rate = 2. QPS
The modulation output of the K modulator (25a-4) is supplied to the multiplexer (25a-6). The output of the multiplexer (25a-6) is transmitted to the transmission path (25b) after the band is limited by the roll-off filter (25a-7) of symbol rate = 2.

On the receiving side, after the band is limited by the roll-off filter (25c-1) of symbol rate = 2, the configuration data relating to the MSB slice and the configuration data relating to the LSB slice are transmitted by the demultiplexer (25c-2). Are separated.
The configuration data for the MSB slice is sampled at a symbol period by a sampler (25c-3) having a symbol rate of 1. Sampler (25c-
The output of 3) is a QPSK demodulator (25c-
It is supplied to 5) and demodulated. The demodulated data is supplied to the multiplexer (25c-7).

The configuration data for the LSB slice is a sampler (25c
According to -4), sampling is performed at the symbol period. Output of sampler (25c-4) is QPSK with symbol rate = 2
The signal is supplied to the demodulator (25c-6) and demodulated. The demodulated data is supplied to the multiplexer (25c-7). The bits of both slices are combined by the multiplexer (25c-7) and output as configuration data.

In the above description, the arithmetic unit is divided into two slices, but the number of slices may be increased to three or more. For example, when the word length of the input / output data of the arithmetic unit is large, it is preferable to further divide the configuration data of the LUT by dividing the slice into three or more. [Table 3] and [Table 4] respectively show allocation of error correction coding schemes with different modulation schemes or coding rates by increasing the number of slices. Table 3 is an example of a combination of modulation schemes when the number of slices is larger than two. Table 4 shows an example of combinations of error correction coding schemes when the number of slices is larger than two.

[0091]

[Table 3]

[0092]

[Table 4]

The modulation method and the error correction method for the configuration data of each slice differ depending on the weight of the data bits handled in the slice. The modulation scheme of the configuration data of the LUT belonging to the slice including the MSB having the largest weight and the error correction encoding scheme include a QPSK modulation scheme having the best transmission characteristics and an encoding scheme having an encoding rate of 1/3, respectively. Is adopted. LS
For the configuration data of the LUT belonging to the slice including B, a 64QAM modulation method with a low transmission characteristic but high transmission efficiency and a coding method with a coding rate of 3/4 are used.

FIG. 19 shows the configuration of a 9-bit adder when the number of slices is three. Further, FIGS. 20 and 21 show an example and another example of a transmission system in the base band of the configuration data according to this method. The transmission system includes transmitters (18a, 19a) for wirelessly transmitting configuration data, transmission paths (18b, 19b), and receivers (18c, 19c) for receiving configuration data. In each receiver, descriptions of a symbol timing synchronization section, a carrier frequency synchronization section, a transmission path equalization section, and the like are omitted.

In the configuration shown in FIG. 20, the transmitter (18a)
, L corresponding to slice 1, slice 2,..., Slice k (for example, (k = 3)) in association with Table 3.
Each data is stored in the memory (18a-1, 18a-2, 18a-3) where the configuration data of the UT is stored.
SK modulator (18a-4), 8PSK modulator (18a-5), 64QA
It is supplied to the M modulator (18a-6). After the modulator output signal is combined by the multiplexer (18a-7) and the occupied band is limited by the roll-off filter (18a-8), the transmission line
(18b).

On the receiving side, after the received data is band-limited by the roll-off filter (18c-1), sampling is performed at the symbol period by the sampler (18c-2). The output of the sampler (18c-2) is supplied to the demultiplexer (18c-3). The QPSK demodulator (18c-4) and the 8PSK demodulator (18
c-5), and distributed to the 64QAM demodulator (18c-6). The bits demodulated by each demodulator are combined by a multiplexer (18c-7) and output as configuration data.

Similarly, in the other example shown in FIG. 21, the configuration data of the LUT belonging to each slice is encoded by the corresponding error correction encoding system according to the allocation method shown in Table 4. The QPSK modulation scheme is taken as an example. In the transmitter (19a), slice 1,
The memory (19a-1, 19a-) storing the configuration data of the LUT belonging to slice 2 and slice 3
2, 19a-3), the data is an error correction code encoder (19a-4) with a coding rate = 1/3, an error correction code encoder (19a-5) with a coding rate = 1/2, The coding rate is supplied to an error correction coding encoder (19a-6) of 3/4. The coded output signals are combined by a multiplexer (19a-7) to form a QPSK modulator (19a-7).
a-8). After the modulation output is restricted in the occupied band by the roll-off filter (19a-8), the transmission path (19
sent to b).

On the receiving side, after the received data is band-limited by the roll-off filter (19c-1), sampling is performed at the symbol period by the sampler (19c-2). The output of the sampler (19c-2) is supplied to the demultiplexer (19c-3). A signal separated by the demultiplexer (19c-3) corresponds to an error correction code decoder (19a-4) with a coding rate of 1/3, and an error correction code decoder with a coding rate of 1/2 ( 19
a-5), and supplied to an error correction code decoder (19a-6) with a coding rate of 3/4. When performing hard decision decoding, QPSK is applied between the sampler (19c-2) and the demultiplexer (19c-3).
A demodulator is inserted, demodulated into bits, and then distributed to a decoder for decoding. The bits decoded by each decoder are combined by a multiplexer (19c-7) and output as configuration data.

Two or more of the above-described first embodiment (that is, use of different modulation schemes), the second embodiment (use of different error correction codes), and the third embodiment (use of different symbol rates) They may be combined.

For example, as shown in Table 5 below, the error correction coding system and the modulation system of the configuration data of the LUT belonging to the slice including the MSB having the largest weight have the highest error correction capability. Conversion rate = 1
/ 3 is combined with the BPSK modulation method having the best transmission characteristic. For the configuration data of the LUT belonging to the slice including the LSB, the error correction capability is low, but the coding rate is relatively high. Transmission is performed in combination with the 64QAM modulation method.

[0101]

[Table 5]

FIG. 22 shows a configuration of a configuration data transmission system in the fourth embodiment in which the first and second embodiments are combined. The transmission system includes a transmitter (20a) for wirelessly transmitting configuration data, a transmission path (20b), and a receiver (20c) for receiving configuration data. In the receiver (20a), descriptions of a symbol timing synchronization section, a carrier frequency synchronization section, a transmission path equalization section, and the like are omitted. In the transmitter (20a), the configuration data of the LUT belonging to slice 1, slice 2, and slice 3 is different from the memory (20a-1, 20a-2, 20a-3) in correspondence with Table 3, and , 20a-4, 20a-5,..., 20a-6). The encoded configuration data of each slice is stored in a corresponding BPSK modulator (20a-7), QPSK
The modulation is performed by the modulator (20a-8) and the 64QAM modulator (20a-9). Modulator output signal is multiplexer (20a-10)
And the band is limited by the roll-off filter (20a-11), and then transmitted to the transmission path (20b).

On the receiving side, the roll-off filter (2
0c-1), sampled every symbol period by the sampler (20c-2) after the band limitation in the demultiplexer (20c-1).
According to -3), each symbol is distributed to the corresponding error correction decoder. For example, a decoder having a coding rate of 1/3 (20c-
4) Decoder with coding rate = 1/2 (20c-5), coding rate = 3/4
To the decoder (20c-6). In FIG. 22, it is assumed that the decoder makes a soft decision. When performing hard decision decoding, a BPSK demodulator, a QPSK demodulator, and a 64QAM demodulator are inserted between the demultiplexer and the respective decoders. Done. The bits decoded by each encoder are combined by a multiplexer (20c-7) and output as configuration data.

Further, a fifth embodiment of the present invention using a signal point arrangement technique will be described. With a modulation scheme having a relatively large number of levels, for example, 16 QAM, 4-bit information can be transmitted simultaneously in one symbol, but the transmission characteristic of the bit at a specific bit position in the combination of 4 bits is the average transmission of all bits. Focusing on the superiority compared with the characteristics, when modulating the sliced configuration bits, bits are assigned on signal points in consideration of the priority and bit position of the slice.

FIG. 23 shows a signal point arrangement of 16QAM and a 4-bit combination (abc
Indicates d). a, b, c, and d in (abcd) represent bits. FIG.
In the signal point arrangement of 3, the bits a and c have the same value regardless of the signal point if the quadrant is the same. That is,
The bit at this position generates a bit error only when noise is superimposed on the signal point and moves to another quadrant and is erroneously recognized. Therefore, the transmission characteristics are considered to be superior when compared with the average error rate of 16QAM. Therefore, the configuration data of the LUT belonging to the MSB slice having the higher priority is assigned to a and c, and
The configuration data of the LUT belonging to the SB slice is assigned to b and d to perform 16QAM modulation. In this case, all configuration data is 16QAM
In the case of a 9-bit adder, (384/4 = 9
6) Become a symbol.

FIG. 24 shows a transmission system of the configuration data in the base band according to the fifth embodiment. The transmission system includes a transmitter (22a) that wirelessly transmits configuration data, a transmission path (22b), and a receiver (22c) that receives configuration data.
In the receiver (22c), descriptions of a symbol timing synchronization section, a carrier frequency synchronization section, a transmission path equalization section, and the like are omitted. L belonging to the MSB slice and LSB slice sides
UT configuration data is stored in memory (22a-1,2
2a-2), the data is supplied to the bit allocation unit (22a-3), and the bits of the data of the MSB slice are placed at the bit positions a and c in FIG.
Bit positions. 16QAM modulator (22a
The signal modulated in -4) is transmitted to the transmission path (22b) after band limitation is performed by the roll-off filter (22a-5).

On the receiving side, the band is limited by the roll-off filter (22c-1), and then sampled at the symbol period by the sampler (22c-2), and the 16QAM demodulator is used.
The bits demodulated by (22c-3) are once divided into the bits at the bit positions a and c and the bits at the bit positions b and d, combined at the multiplexer (22c-5), and output as configuration data. Is done.

Next, a sixth embodiment will be described. The sixth embodiment is a transmission method in which a CRC retransmission method is combined with any one or a combination of the above-described methods. In the above-described first to fifth embodiments, the transmission method for the configuration data constituting the arithmetic circuit that processes the data having the bit weight is used. If a catastrophic failure occurs in the device due to an error in configuration data for configuring a certain circuit, the reliability of the transmission of the configuration data is improved by using retransmission processing by CRC together. It is done as follows.

The circuits to be processed include a clock frequency dividing / distributing circuit, a control circuit, and a PM for determining connection between CLBs.
Examples include a multiplexer in S and CLB, and a circuit for encoding or decoding an error correction code that requires a high reliability by performing a logical operation on a bit basis. For the configuration data of these circuits, the reliability of data transmission is improved by using both the encoding using an error correction code and the CRC. The target configuration data is referred to as CRC configuration data.

FIG. 25 shows a transmission system in the base band of configuration data according to the sixth embodiment. The transmission system includes a transmitter (23a) for wirelessly transmitting configuration data, transmission paths (23b-1, 23b-2), and a receiver (23c) for receiving configuration data. In the receiver (23c), descriptions of a symbol timing synchronization section, a carrier frequency synchronization section, a transmission path equalization section, and the like are omitted. It is assumed that QPSK modulation is used as the configuration data modulation method. Also, a preamble adding unit for generating a packet is omitted.

In the transmitter (23a), the configuration data to be transmitted includes CRC configuration data (23a-1), MSB slice (23a-2), assuming that the number of slices is two, and The configuration data (23a-3) of the LSB slice is used. The CRC configuration data (23a-1) is encoded by an encoder (23a-4) having an encoding rate of 1/3 having the highest error correction capability, and then encoded by the CRC encoder (23a-5). ) Adds a CRC. Configuration data of LUTs belonging to other MSB slices and LSB slices are encoded by encoders (23a-6, 23a-6,
23a-7). Encoder (23a-5), Encoder (23
a-6) and the output of the encoder (23a-7)
a-8), the data is combined, modulated by the QPSK modulator (23a-9), band-limited by the roll-off filter (23a-10), and transmitted to the transmission line (23b-1) Is done.

On the receiving side, band limitation is performed by a roll-off filter (23c-1), and sampling is performed at a symbol period by a sampler (23c-2). The demultiplexer (23c-3) decomposes the configuration data to which CRC has been added and the configuration data to which CRC has not been added. For the modulated signal to which the CRC is added, the bit once demodulated by the QPSK demodulator (23c-4)
Error bits are detected by RC. If no error is detected, the switch (23c-6) is closed and input to the soft-decision type error correction decoder (23c-7) having a coding rate of 1/3 to perform decoding.

If no error bit is detected in the CRC configuration data in the error detecting section (23c-5), an ACK (Acknow1edge) signal is generated to generate a modulator.
(23c-8) roll-off filter (23c-9),
The data is supplied to the roll-off filter (23a-11) of the receiving unit on the configuration data transmitting side (23a) via the transmission path (23b-2). The output of the roll-off filter (23a-11) is demodulated by the control signal demodulator (23a-12). After demodulating the ACK signal, the multiplexer (23a-8) is controlled, and the next MSB and L
The configuration data of the SB slice is transmitted. On the receiving side of the configuration data, the configuration data signals of the received MSB and LSB slices are also demultiplexed by the demultiplexer so that the soft decision type decoders (23c-10, 23c) whose coding rates are 1/2 and 3/4, respectively.
c-11) is decoded by the multiplexer (23c-12)
And output as configuration data.

When an error bit is detected in the configuration data for CRC in the error detector (23c-5), an ARQ (Automatic repeat request) signal is generated and transmitted, and then the control signal demodulator on the configuration data supply side is sent. (23a-12)
8) to retransmit the CRC configuration data.

FIG. 26 shows software packets (24a-1, 24a-2,..., 24a-k) and information packets according to the sixth embodiment.
A configuration example of (24b-1, 24b-2,..., 24b-n) is shown. Software packet 1 is a packet in which retransmission processing is considered.
It is composed of a preamble (24c) and software data (24d) encoded by an error correction code. The software data includes a CRC (24e) and CRC configuration data (24f). MSB / LSB
The configuration data of the slice is transmitted in software packets after software packet 2. These packets are composed of a preamble (24g) and software data (24h). The software data is a configuration data packet (24i) of the MSB / LSB slice encoded by the error correction code.
Consists of The information packet has the same data configuration as that of FIG.

FIG. 27 shows an example of a retransmission processing sequence of a software transmission packet according to the sixth embodiment. An error is detected by CRC for the software packet 1 (25a) transmitted from the base station that supplies the software, and if an error is detected, a retransmission request signal (25b) is transmitted to the base station. Software packet 1 accordingly
Resend (25c). This is repeated until error free is confirmed. If error free is confirmed, the ACK signal (2
5f) to the base station. After receiving the ACK signal, the base station transmits software packet 2 (25g). This is C
The error packet is continuously transmitted up to the software packet k (25h) without error detection by the RC. After demodulating all software, it is downloaded to a programmable modulator / demodulator to set the modulation / demodulation processing for the information packet. Thereafter, the information packet 1-n (25i, 25j,..., 25k) is transmitted.

The present invention is not limited to the above-described embodiment of the present invention, and various modifications and applications can be made without departing from the gist of the present invention. For example, M
As the modulation scheme for the SB slice and the LSB slice, QPSK and 16Q in the first embodiment described above are used.
It is not limited to the combination of AM, but [Table 6]
Various combinations as shown in FIG. Here, an example in which the present invention is applied to two slices is described, but various combinations of modulation methods applicable to three or more slices are also possible.

[0118]

[Table 6]

In the present invention, a device other than the FPGA may be used as the programmable logic circuit. The method of transmitting the program is not limited to the wireless transmission path, but may be a wired method.

[0120]

According to the present invention described above, the configuration data is grouped according to the magnitude of the weight given to the bit of the input / output data bus of the arithmetic circuit, and the configuration data of each group (slice) is Transmission is performed by applying a modulation scheme having different transmission characteristics and transmission efficiency, a coding scheme having different error correction capability and a coding rate, or a transmission scheme having a different symbol rate. According to the present invention, the transmission time of the configuration data can be reduced without significantly deteriorating the transmission quality of the modem programmed by the transmitted configuration data. Further, according to the present invention, the configuration bits of each slice are allocated to bit positions having different transmission characteristics and transmitted in a modulation method such as 16QAM having a relatively large number of values, so that the configuration transmitted at the same transmission time is transmitted. The transmission quality of the modem programmed by the application data can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a software defined radio communication apparatus to which the present invention can be applied.

FIG. 2 is a schematic diagram illustrating a configuration example of a packet of a link for downloading software for a software defined radio system and a configuration example of a packet of a link for transmitting information data;

FIG. 3 is a schematic diagram illustrating a configuration example of a data packet transmitted from a terminal station to a base station in a software defined radio system.

FIG. 4 is a schematic diagram illustrating a packet retransmission process.

FIG. 5 is a block diagram illustrating a configuration example of an OFDM demodulation unit for MMAC.

FIG. 6 is a block diagram illustrating a configuration example of a spread spectrum demodulation unit for WCDMA.

FIG. 7 is a block diagram illustrating a configuration example inside an FPGA.

FIG. 8 is a block diagram showing a configuration example inside a CLB.

FIG. 9 is a block diagram illustrating a configuration example of a 9-bit adder designed with an LUT and a CL of an FPGA.

FIG. 10 is a block diagram illustrating a configuration example of a 3 × 2 bit multiplier designed with an LUT and a CL of an FPGA.

FIG. 11 is a block diagram illustrating a configuration example of an arithmetic circuit designed using an LUT of an FPGA.

FIG. 12 is a block diagram showing slice division in a 9-bit adder.

FIG. 13 is a block diagram showing slice division in a 3 × 2 bit multiplier.

FIG. 14 is a block diagram showing slice division in a two-input operation circuit.

FIG. 15 is a block diagram showing slice division in a two-input arithmetic circuit.

FIG. 16 is a block diagram showing a configuration data transmission system according to the first embodiment of the present invention.

FIG. 17 is a block diagram showing a configuration data transmission system according to a second embodiment of the present invention.

FIG. 18 is a block diagram illustrating a configuration data transmission system according to a third embodiment of the present invention.

FIG. 19 is a block diagram illustrating a configuration of a 9-bit adder in which the number of slice divisions is three.

FIG. 20 is a block diagram illustrating an example of a configuration data transmission system when the number of slice divisions is three.

FIG. 21 is a block diagram showing another example of a configuration data transmission system when the number of slice divisions is three.

FIG. 22 is a block diagram illustrating a configuration data transmission system according to a fourth embodiment of the present invention.

FIG. 23 is a schematic diagram showing a signal point arrangement of 16QAM and a bit combination of 4 bits that can be transmitted per symbol.

FIG. 24 is a block diagram illustrating a configuration data transmission system according to a fifth embodiment of the present invention.

FIG. 25 is a block diagram showing a configuration data transmission system according to a sixth embodiment of the present invention.

FIG. 26 is a schematic diagram illustrating a configuration example of a software packet according to a sixth embodiment of the present invention.

FIG. 27 is a schematic diagram illustrating an example of a software packet retransmission processing sequence according to the sixth embodiment of the present invention.

[Explanation of symbols]

1p: Demultiplexer, 1o: Software modulated signal demodulator, 1q: Software memory, 1r: Software modulator, 15a: Transmitter, 15b: Transmission path, 15c ... Receiver, 15a-3 ... QPSK modulator, 1
5a-4 ・ ・ ・ 16QAM modulator

Continuation of the front page (72) Inventor Hiroshi Harada 3--4 Hikarinooka, Yokosuka City, Kanagawa Prefecture Within the Ministry of Posts and Telecommunications Research Institute Yokosuka Radio Communication Research Center (72) Inventor Masayuki Fujise 3-4, Hikarinooka, Yokosuka City, Kanagawa Prefecture F term in the Yokosuka Wireless Communication Research Center (Reference) 5K004 AA05 AA08 FA05 FD05 JA03 JD05 5K014 AA01 BA06 BA10 FA11 HA06 5K060 BB07 CC04 FF06 HH02 HH06 HH33 5K067 AA01 EE04 GG01 GG11 HH26

Claims (37)

[Claims] 1. A wireless communication apparatus in which a part or all of hardware is constituted by a programmable logic circuit and a program for the logic circuit is received to realize a desired wireless communication system. The logic circuit of the binary arithmetic circuit composed of various logic circuits is divided into at least first and second groups according to the magnitude of the power of 2 corresponding to each input / output bit, and the weight is large. A first program for a first group of logic circuits is modulated and transmitted by a first method with a small number of bit errors, and a program for a second group of logic circuits with a small weight has a high transmission efficiency. A wireless communication device that is modulated and transmitted. 2. The wireless communication apparatus according to claim 1, wherein the first modulation scheme is QPSK modulation, and the second modulation scheme is 16QAM. 3. A wireless communication apparatus in which a part or all of hardware is constituted by a programmable logic circuit and a program for the logic circuit is received to realize a desired wireless communication system. The logic circuit of the binary arithmetic circuit composed of various logic circuits is divided into at least first and second groups according to the magnitude of the power of 2 corresponding to each input / output bit, and the weight is large. The first program for the first group of logic circuits is transmitted using a coding scheme with high error correction capability, and the second program for the second group of logic circuits with low weight has a high coding rate. A wireless communication device adapted to be transmitted using an encoding method. 4. A wireless communication device in which a part or all of hardware is constituted by a programmable logic circuit, and a program for the logic circuit is received to realize a desired wireless communication system. The logic circuit of the binary arithmetic circuit composed of various logic circuits is divided into at least first and second groups according to the magnitude of the power of 2 corresponding to each input / output bit, and the weight is large. The first program for the first group of logic circuits is modulated and transmitted at a low symbol rate, and the program for the second group of low weight logic circuits is modulated and transmitted at a high symbol rate. Wireless communication device. 5. A wireless communication device in which a part or all of hardware is constituted by a programmable logic circuit and a desired wireless communication scheme is realized by receiving a program for the logic circuit. Logic circuit is divided into an operation circuit and a non-operation circuit, and a part of the first program for the operation circuit is transmitted without performing retransmission processing, and a second program for the part of the operation circuit and the second Is a wireless communication device in which the program is retransmitted and transmitted with enhanced reliability. 6. The circuit according to claim 5, wherein a part of the arithmetic circuit and a second
Is a wireless communication device that requires higher reliability than the first program. 7. A wireless communication apparatus in which a part or all of hardware is constituted by a programmable logic circuit and a desired wireless communication scheme is realized by receiving a program for the logic circuit. The logic circuit of the binary arithmetic circuit composed of various logic circuits is divided into at least first and second groups according to the magnitude of the power of 2 corresponding to each input / output bit, and the weight is large. The first program for the first group of logic circuits is transmitted in a transmission scheme that combines two or more of the first modulation scheme, the first error correction code, and the first symbol rate. The second program for the logic circuits of the second group includes a second modulation scheme, a second error correction code, and a second symbol rate. The first modulation scheme has a smaller number of errors than the second modulation scheme, and the first error correction code is the second error correction code. A wireless communication device having an error correction capability higher than a correction code, and wherein the first symbol rate is lower than the second symbol rate. 8. A wireless communication apparatus in which a part or all of hardware is constituted by a programmable logic circuit and a program for the logic circuit is received to realize a desired wireless communication system. The logic circuit of the binary arithmetic circuit composed of various logic circuits is divided into at least first and second groups according to the magnitude of the power of 2 corresponding to each input / output bit, And the second program is transmitted using a modulation scheme having a relatively large number of values, and the program of the first group having a large weight is assigned to a bit position at which transmission that is superior to the average error rate of the modulation scheme is possible. The programs of the second group, which are assigned and have small weights, are assigned to bit positions having transmission characteristics inferior to the average error rate of the modulation scheme. Wireless communication device to be assigned. 9. The wireless communication apparatus according to claim 8, wherein the modulation scheme is 16 QAM or 64 QAM. 10. The programmable logic circuit according to claim 1, wherein the programmable logic circuit is an FPGA (Field Programmable Circuit).
ammable Gate Array). 11. The wireless communication apparatus according to claim 1, wherein when the arithmetic circuits are grouped, the grouping is further performed in consideration of intermediate data in the arithmetic circuits. 12. A program for a wireless communication device that is configured to realize a desired wireless communication system by receiving a program for a logic circuit, wherein a part or all of hardware is configured by a programmable logic circuit. In the transmitting apparatus, the logic circuit of the binary arithmetic circuit constituted by a programmable logic circuit has at least the first and second binary signals depending on the magnitude of the power of 2 corresponding to each input / output bit. A first program for the first group of logic circuits having a large weight is divided into two groups, and modulated and transmitted by a first method with a small bit error, and a program for the second group of logic circuits with a small weight is transmitted. A program transmitting apparatus configured to modulate and transmit the modulated signal by the second method having excellent efficiency. 13. The program transmission device according to claim 12, wherein the first modulation scheme is QPSK modulation, and the second modulation scheme is 16QAM. 14. A program for a wireless communication apparatus which is configured with a part or all of hardware by a programmable logic circuit and which realizes a desired wireless communication system by receiving a program for the logic circuit. In the transmitting apparatus, the logic circuit of the binary arithmetic circuit constituted by a programmable logic circuit has at least the first and second binary signals depending on the magnitude of the power of 2 corresponding to each input / output bit. The first program for the first group of logic circuits having a large weight is transmitted using an encoding method having a high error correction capability, and the second program for the second group of logic circuits having a small weight is transmitted. A program transmission device for transmitting a program using an encoding method having a high encoding rate. 15. A program for a wireless communication apparatus that is configured with a part or all of hardware by a programmable logic circuit and that realizes a desired wireless communication system by receiving a program for the logic circuit. In the transmitting apparatus, the logic circuit of the binary arithmetic circuit constituted by a programmable logic circuit has at least the first and second binary signals depending on the magnitude of the power of 2 corresponding to each input / output bit. A first program for a first group of logic circuits, which is divided into two groups and has a large weight, is modulated at a low symbol rate and transmitted;
A program transmitting apparatus for modulating a program for a second group of logic circuits having a small weight at a high symbol rate and transmitting the modulated signal. 16. A program for a wireless communication device that is configured by a part or all of hardware with a programmable logic circuit and that realizes a desired wireless communication system by receiving a program for the logic circuit. A programmable logic circuit is divided into an arithmetic circuit and a non-arithmetic circuit, and a part of the first program for the arithmetic circuit is transmitted without performing retransmission processing; And a program transmitting apparatus which retransmits the second program for the non-operational circuit and transmits the program with high reliability. 17. The method according to claim 15, wherein a part of the arithmetic circuit and a second
Is a program transmission device that requires higher reliability than the first program. 18. A program for a wireless communication device that is configured with a part or all of hardware by a programmable logic circuit and that realizes a desired wireless communication system by receiving a program for the logic circuit. In the transmitting apparatus, the logic circuit of the binary arithmetic circuit constituted by a programmable logic circuit has at least the first and second binary signals depending on the magnitude of the power of 2 corresponding to each input / output bit. A transmission method in which a first program for a first group of logic circuits divided into two groups and having a large weight is combined with two or more of a first modulation scheme, a first error correction code, and a first symbol rate; And a second program for a second group of logic circuits having a small weight is transmitted in a second modulation scheme and a second error correction code. And a transmission scheme combining two or more of the second symbol rates, wherein the first modulation scheme has less errors than the second modulation scheme, and the first error rate The program transmission device, wherein the correction code has a higher error correction capability than the second error correction code, and the first symbol rate is lower than the second symbol rate. . 19. A program for a wireless communication device that is configured with a part or all of hardware as a programmable logic circuit and that realizes a desired wireless communication system by receiving a program for the logic circuit. In the transmitting apparatus, the logic circuit of the binary arithmetic circuit constituted by a programmable logic circuit has at least the first and second binary signals depending on the magnitude of the power of 2 corresponding to each input / output bit. The first and second programs are divided into two groups, and the first and second programs are transmitted using a modulation scheme having a relatively large number of values, and the programs of the first group having a large weight are superior to the average error rate of the modulation scheme. The program of the second group having a small weight is assigned to a bit position where the transmission is possible, and the transmission of the program having a weight lower than the average error rate of the modulation scheme is performed. A program transmission device that assigns to bit positions having transmission characteristics. 20. The program transmission device according to claim 19, wherein the modulation method is 16 QAM or 64 QAM. 21. Claims 12, 14, 15, 16, 18
(19) In the program transmission device according to (19), when the arithmetic circuits are grouped, the grouping is further performed in consideration of intermediate data in the arithmetic circuits. 22. A program for a wireless communication device which is configured to realize a desired wireless communication system by receiving a program for a logic circuit, wherein a part or all of hardware is configured by a programmable logic circuit. In a transmission method for transmitting a binary number, a logic circuit of a binary number arithmetic circuit composed of a programmable logic circuit has at least first and second binary numbers depending on the magnitude of a power of 2 corresponding to each bit of the input and output. A first program for the first group of logic circuits having a large weight is divided into two groups, and modulated and transmitted by a first method with a small bit error, and a program for the second group of logic circuits with a small weight is transmitted. A program transmission method in which a modulated signal is transmitted by a second method having excellent efficiency. 23. The program transmission method according to claim 22, wherein the first modulation scheme is QPSK modulation, and the second modulation scheme is 16QAM. 24. A program for a wireless communication device that is configured with a part or all of hardware by a programmable logic circuit and that realizes a desired wireless communication system by receiving a program for the logic circuit. In a transmission method for transmitting a binary number, a logic circuit of a binary number arithmetic circuit composed of a programmable logic circuit has at least first and second binary numbers depending on the magnitude of a power of 2 corresponding to each bit of the input and output. The first program for the first group of logic circuits having a large weight is transmitted using an encoding method having a high error correction capability, and the second program for the second group of logic circuits having a small weight is transmitted. A program transmission method for transmitting a program using an encoding method having a high encoding rate. 25. A program for a wireless communication device that is configured with a part or all of hardware by a programmable logic circuit and that realizes a desired wireless communication system by receiving a program for the logic circuit. In a transmission method for transmitting a binary number, a logic circuit of a binary number arithmetic circuit composed of a programmable logic circuit has at least first and second binary numbers depending on the magnitude of a power of 2 corresponding to each bit of the input and output. A first program for a first group of logic circuits, which is divided into two groups and has a large weight, is modulated at a low symbol rate and transmitted;
A program transmission method wherein a program for a logic circuit of a second group having a small weight is modulated at a high symbol rate and transmitted. 26. A program for a wireless communication apparatus that is configured to implement a desired wireless communication system by receiving a program for a logic circuit, wherein a part or all of hardware is configured by a programmable logic circuit. A programmable logic circuit is divided into an arithmetic circuit and a non-arithmetic circuit, and a part of the first program for the arithmetic circuit is transmitted without performing retransmission processing; And a program transmission method in which the second program for the non-arithmetic circuit is retransmitted and transmitted with improved reliability. 27. The circuit according to claim 15, wherein a part of the arithmetic circuit and a second
Is a program transmission method that requires higher reliability than the first program. 28. A program for a wireless communication device that is configured with a part or all of hardware by a programmable logic circuit and that realizes a desired wireless communication system by receiving a program for the logic circuit. In a transmission method for transmitting a binary number, a logic circuit of a binary number arithmetic circuit composed of a programmable logic circuit has at least first and second binary numbers depending on the magnitude of a power of 2 corresponding to each bit of the input and output. A transmission method in which a first program for a first group of logic circuits divided into two groups and having a large weight is combined with two or more of a first modulation scheme, a first error correction code, and a first symbol rate; And a second program for a second group of logic circuits having a small weight is transmitted in a second modulation scheme and a second error correction code. And a transmission scheme combining two or more of the second symbol rates, wherein the first modulation scheme has less errors than the second modulation scheme, and the first error rate The program transmission method, wherein the correction code has a higher error correction capability than the second error correction code, and the first symbol rate is lower than the second symbol rate. . 29. A program for a wireless communication apparatus that is configured with a part or all of hardware by a programmable logic circuit and that realizes a desired wireless communication system by receiving a program for the logic circuit. In a transmission method for transmitting a binary number, a logic circuit of a binary number arithmetic circuit composed of a programmable logic circuit has at least first and second binary numbers depending on the magnitude of a power of 2 corresponding to each bit of the input and output. The first and second programs are divided into two groups, and the first and second programs are transmitted using a modulation scheme having a relatively large number of values, and the programs of the first group having a large weight are superior to the average error rate of the modulation scheme. The program of the second group having a small weight is assigned to a bit position where the transmission is possible, and the transmission of the program having a weight lower than the average error rate of the modulation scheme is performed. A program transmission method for allocating to a bit position having transmission characteristics. 30. The program transmission method according to claim 29, wherein the modulation scheme is 16 QAM or 64 QAM. 31. The method of claim 22, 24, 25, 26, 28.
Or the program transmission method according to 30, wherein when the arithmetic circuits are grouped, the grouping is further performed in consideration of intermediate data in the arithmetic circuits. 32. A wireless communication device in which a part or all of hardware is constituted by a programmable logic circuit, and a wireless communication device which realizes a desired wireless communication system by receiving a program for the logic circuit, and In a wireless communication system including a transmission device that transmits a program to a device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit configured by a programmable logic circuit corresponds to each input / output bit. The transmission device is divided into at least first and second groups according to the magnitude of the power of two, and the transmitting device executes a first program for the logic circuit of the first group having a large weight in the first group having a small bit error.
A wireless communication system which modulates and transmits a program for a second group of logic circuits having a small weight with a second method having excellent transmission efficiency and transmits the modulated signal. 33. A wireless communication device in which a part or all of hardware is constituted by a programmable logic circuit, and a wireless communication device which realizes a desired wireless communication system by receiving a program for the logic circuit, and In a wireless communication system including a transmission device that transmits a program to a device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit configured by a programmable logic circuit corresponds to each input / output bit. The transmission device is divided into at least two groups, a first group and a second group, according to the magnitude of a power of two. A second program for a second group of logic circuits having a small weight is transmitted using a coding scheme, Wireless communication system adapted to transmit using the scheme. 34. A wireless communication device in which a part or all of hardware is configured by a programmable logic circuit, and a wireless communication device configured to realize a desired wireless communication system by receiving a program for the logic circuit, and In a wireless communication system including a transmission device that transmits a program to a device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit configured by a programmable logic circuit corresponds to each input / output bit. The transmitter is divided into at least first and second groups according to the magnitude of a power of two, and the transmitting apparatus modulates a first program for a first group of logic circuits having a large weight at a low symbol rate. And modulate the program for the second group of logic circuits having a small weight at a high symbol rate. Wireless communication system adapted to transmit. 35. A wireless communication device in which a part or all of hardware is configured by a programmable logic circuit, and a wireless communication apparatus configured to realize a desired wireless communication system by receiving a program for the logic circuit, and In a wireless communication system including a transmitting device that transmits a program to a device, the wireless communication device includes a programmable logic circuit divided into an arithmetic circuit and a non-arithmetic circuit; Wireless communication in which the first program of the section is transmitted without performing retransmission processing, and the second program for a part of the arithmetic circuit and the non-operation circuit is subjected to retransmission processing and transmitted with improved reliability system. 36. A wireless communication device in which a part or all of hardware is constituted by a programmable logic circuit, and a wireless communication apparatus which realizes a desired wireless communication system by receiving a program for the logic circuit is provided. In a wireless communication system including a transmission device that transmits a program to a device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit configured by a programmable logic circuit corresponds to each input / output bit. The transmission device is divided into at least first and second two groups according to the magnitude of the power of two, and the transmitting device executes a first program for a logic circuit of the first group having a large weight in a first modulation scheme; A transmission method combining two or more of the first error correction code and the first symbol rate is used, and a second signal having a small weight is transmitted. A second program for the logic circuits of the group is transmitted by a transmission scheme combining two or more of a second modulation scheme, a second error correction code, and a second symbol rate, and the first modulation scheme includes: The first error correction code has a higher error correction capability than the second error correction code, and the first error correction code has a higher error correction capability than the second error correction code. A wireless communication system wherein the symbol rate is lower than the second symbol rate. 37. A wireless communication device in which a part or all of hardware is configured by a programmable logic circuit, and a wireless communication device that realizes a desired wireless communication system by receiving a program for the logic circuit is provided. In a wireless communication system including a transmission device that transmits a program to a device, the wireless communication device is configured such that a logic circuit of a binary number arithmetic circuit configured by a programmable logic circuit corresponds to each input / output bit. The transmitter is divided into at least first and second groups according to the magnitude of a power of two, and the transmitting apparatus transmits the first and second programs using a modulation scheme having a relatively large number of values. And assigning the program of the first group having a large weight to a bit position at which transmission that is superior to the average error rate of the modulation scheme is possible, A wireless communication system that assigns programs of the second group having a small weight to bit positions having transmission characteristics inferior to the average error rate of a modulation scheme.