JP2002204171A - Apparatus and method for decoding multiplexed contiguous variable code length per clock cycle - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decode a plurality of code lengths more than one per clock cycle with the number of code length decoders kept in small and without using large barrel shifters for a code length decoding means in a circuit. SOLUTION: In a single clock cycle, the code lengths of contiguous multiplexed variable length decoding code words embedded in a bit stream are decoded. In this method, each code length decoding means is provided with a mask for masking all the bits related to all the former code words and a pseudo length decoder for performing a pseudo length decoding process before finding the real length of one word. In each code length decoding means, only a single code length decoder is used to reduce a chip area, thereby reducing production cost.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an embodiment of a variable length decoder (also known as a Huffman decoder or an entropy decoder) for decoding compressed digital signals. In the following, "MPEG standard" for moving images
(H.262 ISO / IEC 13818-2: 1995 (E), "Information Tec
hnology-Generic Coding of Moving Pictures and As
sociated Audio Information: Video ") knowledge is assumed.

[0002]

BACKGROUND OF THE INVENTION Currently, a common method used to decode the code length of adjacent variable length encoded data values in a data stream within a single clock cycle is to decode the length within the same clock cycle. A method using multiple barrel shifters used for every power word,
Using multiple second length decoders used for each of all possible start bit positions of the second encoded data value corresponding to all possible code lengths of the encoded data value of Including.

[0003] Bakmutsky's International Patent WO97 /
No. 24809 discloses a variable length decoder (VLD) that includes an apparatus and method for determining the length of adjacent variable length coded data values in a data stream within a single clock cycle by using multiple barrel shifters. Includes teachings and is incorporated herein by reference. In certain embodiments of the invention, the apparatus includes a second, third and fourth three barrel shifters in addition to the first barrel shifter. One barrel shifter is used for each of the four parallel codeword processing paths.

[0004] Sita and Brosz, EP 079
No. 8931 includes teachings on variable length decoders using multiple second length decoders, which are incorporated herein by reference. Here, each of the second length decoders is for each of all possible start bit positions of the second encoded data value corresponding to all possible code lengths of the first encoded data value. Used for The apparatus (see FIG. 1) includes a first length decoding means coupled to receive a subset of the plurality of encoded data values. The first length decoding means performs a first decoding process for determining the length of the first data value among the encoded data values in the subset. The apparatus further includes a second length decoding means coupled to receive the subset of the plurality of encoded data values. The second length decoding means performs a second decoding process for determining the length of the second data value among the encoded data values in the subset. Further, the apparatus includes a merged length decoder corresponding to the length of the first and second encoded data values for outputting a merged length of the first and second data values.

[0005]

The method used by Bakmutsky requires a large number of barrel shifters, and the amount of barrel shifters is the length of adjacent code lengths that are intended to be decoded in a single clock cycle. Is linearly proportional to the number of Each barrel shifter is preferably 1 equal to the maximum codeword length number (eg, 32 bits).
Receive a set of parallel output bit lines. The chip area required for the barrel shifter can be large.

[0006] The Sita and Brosz variable length decoders described above individually determine the length of a second one of the encoded data values corresponding to each of the sixteen possible lengths of the first encoded data value. Is a method using a multiplexed second code length decoder. Variable length decoders become increasingly difficult to implement as the number of codewords to be decoded in the same clock cycle increases. Thus, the number of codewords that can be decoded in a clock cycle using a reasonably low cost and small chip area has conventionally been limited to two. For example, if the number of codewords to be decoded is three per clock cycle, the third code length decoding means may determine that the number of codewords to be decoded is 16 for each possible length of the second encoded data value.
May have to be included. Since the second length decoding means must include 16 decoders for each of the possible lengths of the first encoded data value for startup, it performs the third length decoding process. in the third length decoding unit, it is required in total 16 ^two decoders. The estimated number of Nth code length decoders required for the Nth length decoding means to decode up to N codes per clock cycle is 16 ^{N -1} . Cumulatively, first length decoding means,
The second length decoding means and the N-th length decoding means including the N-th length decoding means
The estimated number of overall decoders needed for the variable length decoder, including decoding means up to length decoding means, It is. Further, in addition to the increasing difficult technical complexity associated with implementing such a variable length decoder circuit for decoding up to N codes per clock cycle,
The increased cost resulting from the larger memory required for the look-up table (LUT) makes such a method uneconomical.

It is an object of the present invention to keep the number of code length decoders small and to use one barrel per clock cycle without using a large barrel shifter for the code length decoding means in the circuit.
Another approach is to decode more code lengths.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, an apparatus for generating and transmitting a code length signal indicating the length of a word of a multiplex code included in a data stream in a single clock cycle is described. It comprises code length decoding means, m-th code length decoding means, and next code length decoding means. In the present description, all code length decoding means included in the preceding code length decoding means and the next code length decoding means employ the same architecture and method as the m-th code length decoding means. Therefore, the m-th code length decoding means exemplifies the (m-1) th code length decoding means included in the preceding code length decoding means or the (m + 1) th code length decoding means included in the next code length decoding means. . Therefore, description of the structure and function of the (m-1) th code length decoding means and the (m + 1) th code length decoding means will not be repeated below. The m-th code length decoding unit performs a code length decoding process on the m-th encoded data value included in the input data stream, and transmits an m-th code length signal indicating the code length of the m-th encoded data value.

In the present invention, the m-th code length decoding means is used to perform a code length decoding process on the m-th encoded data value included in the input data stream.
The m-th code length decoding unit transmits an m-th code length signal indicating the code length of the m-th encoded data value. In the m-th code length decoding means, the mask generator, based on a signal indicating the sum of all previously decoded code length values not including the m-th decoded code length value but up to the m-th decoded code length value Generate and transmit a set of mask bits. These code length values are decoded within the same clock cycle. The first bit extracting means is used to determine the bit value of the least significant first bit of the m-th encoded data value. The masking means is used to generate and transmit the pre-length signal. The pre-length signal is, among all bits included in the m-th encoded data value, the least significant bit of the first encoded data value having a bit value opposite to the least significant bit of the m-th encoded data value. For the fixed bit position of the first bit, the first bit
Indicates the bit position of the bit. The pseudo length decoder is used to generate and transmit a pseudo length signal. The pseudo length signal is
Indicates the number of adjacent bits in the m-th encoded data value that have the same leading bit value. The identifier extracting means is used to generate and transmit a fixed number of identifier bits from the m-th encoded data value. The identifier bit has a bit position higher than the least significant first bit position of the m-th encoded data value, and the other reference signal given according to the pseudo length and the decoding protocol is used for the m-th encoded data value. Has the role of determining the actual unique code length of the m-th encoded data value if it is not sufficient to determine the actual unique code length of the m-th encoded data value. The code length decoder is used to generate and transmit a code length signal indicating the code length of the m-th encoded data value. The code length is determined by the m-th encoded data value based on the pseudo length decoder, the identifier fetching means and the signal received from the preceding bit fetching means and other reference signals provided according to a decoding protocol. Indicates the actual code length for

In the masking means, the stream inverting means generates a set of adjacent inverted bits from the input data stream. This inverted bit 1
The set includes inverted bits of some or all bits included in the m-th encoded data value.
The stream selecting means, based on the signal received from the leading bit extracting means, includes a set of non-inverted bits in the input data stream and the input signal received from the stream inverting means. One of the set of inverted bits in the data stream is selected for transmission. A set of mask gates receives the output from the stream selection means. This mask gate masks adjacent bits included in all encoded data values in the range from the first encoded data value to the m-th encoded data value (but not including the m-th encoded data value itself). , Allows the other remaining higher significant consecutive bits to be transmitted unmasked. The masked and unmasked bits are the number of lower significant identical leading bits of the same number as the number of masked bits and successive lower identical leading bits of the m-th encoded data value. A stream stamp signal composed of a pair of adjacent sets is generated. The stream stamp signal further includes, at higher significant bit positions, the remaining unmasked adjacent bits received from the stream selector. Based on the output of the mask gate, the pre-length signal will have the pseudo-length of the m-th encoded data value within the same clock cycle in which the first encoded data value was decoded in length. Represents the sum of all previously decoded code length values.

According to the present invention, there is provided a method for determining a code length of an m-th encoded data value included in an input data stream in a single clock cycle, wherein a current code length is being decoded from a first encoded data value. Of the encoded data values, up to (but not including) the m-th encoded data value, decoded within a single clock cycle, Generating and transmitting a set of bits based on a signal indicating the sum of the calculated code length values; determining a bit value of the least significant first bit of the m-th decoded value; Of all the bits included in the data value, the first bit of the least significant bit of the first encoded data value having the opposite bit value to the least significant bit of the mth encoded data value A bit of Generating and transmitting a stream stamp signal indicating a bit position of a certain first bit; and generating a signal indicating the number of adjacent leading bits in the m-th encoded data value having the same leading bit value. Transmitting, and having a significant bit position higher than the least significant first bit position of the m-th encoded data value,
The actual length of the m-th encoded data value if the pseudo-length and other reference signals provided according to the decoding protocol are not sufficient to determine the actual unique code length of the m-th encoded data value. Extracting a fixed number of bits from the m-th encoded data value, which is responsible for determining the unique code length of the m-th encoded data value, and based on the pseudo-length signal and other reference signals provided according to a decoding protocol. , Generating and transmitting a code length signal indicating the actual code length of the m-th encoded data value.

[0012] In the above method, the step of determining the pre-length signal preferably comprises, from the input data stream, a set of inverted adjacent bits including bits included in the m-th encoded data value. Generating a set of non-inverted bits from the input data stream based on the least significant bit of the m-th encoded data value; Selecting one of the set of inverted bits and transmitting the inverted bit, and selecting from the first encoded data value to the m-th encoded data value (not including the m-th encoded data value itself). Masking said adjacent bits associated with one or more encoded data values in a range; and from said first encoded data value to said m th encoded data value (including the m th encoded data value itself). No) a set of adjacent leading bits of the same number of identical bit values as the number of all bits associated with one or more encoded data values in the range, and the same identical lower order of the mth encoded data value. Forming and transmitting a stream stamp signal consisting of significant leading bits; and all previously decoded lengths of said first encoded data value decoded in a single clock cycle decoded. Generating a pre-length signal representing the sum of the code length value and the pseudo length of the m-th encoded data value by indicating the number of adjacent identical leading bits found in the stream stamp signal; Transmitting.

The m-th code length decoding means is used for performing an m-th code length decoding process on an m-th encoded data value in an input data stream. This m-th
The code length decoding means includes a mask generator for generating a set of mask bits. The mask bit is the (m−
1) Generated based on the previous code length signal received from the code length decoding means. The previous code length signal is composed of all data values from the first encoded data value to the m-th encoded data value (excluding the m-th encoded data value itself) whose code length is being decoded. 5 shows the sum of all code length decoded values decoded within the same clock cycle. This encoded data value is hereinafter referred to as the "previous code."
That. The mask generator sends these mask bits to a set of mask gates located in the mask device. A set of mask gates masks a set of adjacent bits corresponding to the previous code from the input data stream and produces at the output of the mask gate the masked bits. The leading bit extracting unit receives the masked bits from the mask generating unit, and transmits the bit value of the least significant leading bit of the m-th encoded data value as the extracted leading bit. The extracted leading bits are used to select a set of inverted input data streams or a set of non-inverted input data streams,
Used by the stream selector in the mask device. After this selection process, a set of adjacent identical leading bits of the m-th encoded data value is defined as a set of adjacent identical bits having the same bit value as the masked bit.
Appears at the output of the stream selector. In the following, a set of adjacent identical leading bits of the m-th encoded data value that appear in the output of the stream selector will be referred to as presented head bits. The previous code sent by the stream selector, the presented leading bits, and all bits belonging to the other significant bits sent by the stream selector are sent to the set of mask gates. Form the input. This set of mask gates masks all bits belonging to the set of adjacent previous codes sent by the stream selector, but does not mask the other significant bits received from the stream selector.
The set of adjacent masked bits and the set of higher significant bits sent unmasked by the mask gate form a stream stamp signal and are received by the precoder. The precoder receives the stream stamp signal from the mask gate, generates and transmits a prelength signal. The pre-length signal is adjacent masked from the least significant significant bit of the first encoded data value to the last bit of a set of identical identical leading bits of the m-th encoded data value. Indicates the number of identical bits. Thus, the preceding length represents the sum of the preceding code length and the pseudo length of the m-th encoded data value. This pseudo length is the m-th
This is the number of identical adjacent leading bits in the encoded data value. The pseudo length decoder receives the pseudo length signal and the previous code length signal. The pre-length decoder receives the pre-length signal and the pre-code length signal. The pre-length decoder processes the two signals and outputs a pseudo-length signal of the m-th encoded data value. On the other hand, the identifier extracting unit receives the pre-length signal and extracts an identifier bit corresponding to the m-th encoded data value from the input data stream. The identifier bit and the fetched leading bit are the actual code length of the m-th encoded data value in many situations where the pseudo-length signal alone is not sufficient to represent the actual code length of the m-th encoded data value. Used to determine The pseudo length signal, the identifier bit, the fetched leading bit, and the specific decoding protocol (for example, Table B-14 of the MPEG standard)
Alternatively, based on another normative signal given by table_id indicating one of B-15, the code length decoder generates and transmits a length signal indicating the actual code length of the m-th encoded data length. I do. As an example of the operation of the code length decoder, Table 1 shows a table of compressed code lengths of Table B-14 and Table B-15 that can be used by the code length decoder of the present invention.

[0014]

[Table 1] Note: "x" stands for "don't care" bit. table_id
"0" in Table B-14 indicates that Table B-14 is used. tabl
"1" of e_id indicates that Table B-15 is used.

According to the present invention, there is another method for decoding a plurality of code lengths greater than one per clock cycle without using a large barrel shifter for the code length decoding means in the circuit while keeping the number of code length decoders small. Introduce a method. By using such a method, Table B-14 and Table B-15 required by the MPEG standard are combined by removing the redundancy of the code length information found in the two tables. Also, the number of entries in the combined table is reduced. Thus, the overall chip area and cost can be reduced.

[0016]

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, the same reference symbols indicate the same or equivalent ones. FIG. 2 shows an apparatus 100 including a first code length decoding unit 106, an m-th code length decoding unit 108, and a next code length decoding unit 110. The first code length decoding means 106 sends the full length signal (total_length_ (m-1)) 198_
(m-1) is output. Total length signal (total_length_ (m-
1)) 198_ (m-1) is the number of encoded data values up to the m-th encoded data value (not including the m-th encoded data value itself) before all within a single clock cycle. It shows the previous code length value representing the sum of the decoded length values. The m-th code length decoding means 108 outputs stream_data 10
M-th in the input data stream named
It is used to perform a code length decoding process on the encoded data value. The m-th code length decoding unit 108 transmits a length_m signal 190_m indicating the code length of the m-th encoded data value. The m-th code length decoding means 108 calculates total_leng
th_ (m-1) signal 198_ (m-1), stream data 1
02 and table_id 104, total_length
_m signal 198 _m, and the next code length decoding means 110
Send to

FIG. 3 shows one embodiment of the present invention. FIG. 3 shows details of the m-th code length decoding means 208. In the m-th code length decoding means 208, the mask generator 220 outputs a total_length_ (m-1) signal 298_ (m-1)
And transmits a set of mask bits 225. The leading bit extracting section 240 includes a mask bit 225 and a stream_data 20
2 and transmits an extraction head bit 245. Extraction leading bit 245
Indicates the bit value of the least significant first bit of the m-th encoded data. The mask device 290 uses these stream_data 20
2, receiving the extracted leading bit 245 and the mask bit 225, generates a pre-length signal 292, and generates a pseudo-length decoder 230
To the identifier extracting unit 250. The pseudo-length decoder 230 outputs a total_length_ (m-1) signal 298_ (m-1)
And generates a pseudo-length signal 235 and transmits it to the code length decoder 260. Further, the identifier extracting unit 250
Ream_data 202 is received, a fixed number of identifier bits 255 are extracted from the m-th encoded data value embedded in stream_data 202, and identifier bits 255 are output to code length decoder 260. The code length decoder 260 outputs a pseudo-length signal 235, an identifier bit 255, and an extraction head bit 245.
And table_id 204, and a code length signal code_m
(290_m) is generated and transmitted. Code length signal code
_m (290_m) indicates the actual code length from the m-th encoded data value. The adder 295 outputs the length_m signal 290
_M and a total_length_ (m-1) signal 298_ (m-1), and outputs a total_length_m signal 298_m.

The operation of the embodiment shown in FIG. 3 will be described in detail below. The m-th code length decoding unit 208 performs an m-th code length operation on the m-th encoded data value embedded in the input data stream stream_data 202. M-th
The mask generator 220 in the code length decoding means 208 receives the total_length received from the preceding code length decoding means 106.
A set of mask bits is generated based on the _ (m-1) signal 298_ (m-1). The mask generator 220 sends the mask bits 225 to the mask device 290. The first bit extracting unit 240 receives the mask bit 225 from the mask generator 220, extracts the bit value of the least significant first bit of the m-th encoded data value from the stream_data 202, and transmits it as the extracted first bit 245. The extracted leading bit 245 is output to the mask device 290. The mask device 290 also receives the stream_data 202. The mask device 290 generates and transmits the pre-length signal 292. The pre-length signal 292 comprises adjacent identical masked bits from the least significant first bit of the first encoded data value to the most significant bit of a set of adjacent identical identical bits of the mth encoded data value. Indicates the number of The pseudo length 235 indicating the number of the same adjacent leading bits found in the m-th coded data value is the leading length signal 292 and the total_length_ (m-1) signal 2
98_ (m-1). Pseudo length decoder 23
0 indicates that the preceding length signal 292 is received from the mask device 290 and the total_length_ (m-1) signal 2 is received from the preceding code length decoding means.
98_ (m-1). The pseudo-length decoder 230
These signals are processed and a pseudo length signal indicating the pseudo length of the m-th encoded data value is output. The identifier extracting unit 250 is used to extract a fixed number of identifier bits 255 embedded in the stream_data 202 from the m-th encoded data value. Identifier bit 255 and fetch start bit 245
Are used to determine the value of the actual length of the m-th encoded data value in many situations where the pseudo-length signal 235 alone is not sufficient to represent the actual code length of the m-th encoded data value. used. The pseudo-length signal 235 sent by the pseudo-length decoder 230, the identifier bit 255, the extracted leading bit 245, and the table_id given by the decoding protocol
Based on the signal 204, the code length decoder 260
The th_m signal 290_m is generated and transmitted. This length_m
Signal 290_m indicates the actual length of the m-th encoded data value. The adder 295 calculates the length_m signal and the total_length_
(m-1) The value of the signal 298_ (m-1) is added, and total_leng
The th_m signal 298_m is generated.

The m-th code length decoding means 208 calculates the total_le
Although the ngth_m signal 298_m is output to the next code length decoding means 110, it should be understood that the next code length decoding means 110 need not be present.
As will be appreciated by those skilled in the art, a circuit configuration similar to that of the m-th code length decoding means described herein may be used within the preceding code length decoding means and / or the next code length decoding means to depart from the spirit and scope of the invention Can be used without.

An advantage of this embodiment is that the entire code length value required for a shift in the next set of codes whose length is to be decoded is obtained in a single clock cycle.

Referring to FIG. 4 showing another embodiment of the present invention, details of the structure of a mask device 390 are shown. Stream inverter 375 processes a set of selected stream_data 336 selected from stream_data 302 and outputs a set of inverted adjacent bits 378a. The stream selector 380 calculates the non-inverted set of adjacent bits 378b of the stream_data 302 and the inverted set of adjacent bits 37
8a and select one set of adjacent bits,
Output a set of stream_data 382 to be presented. A set of mask gates receives the presented set of stream_data 382 from the stream selector 380 and the mask bits 325 from the mask generator 320 and provides a precoder 388 with one of the stream stamp signals 386. Send the adjacent stream. The precoder 388 generates and outputs a prelength signal 392. The operation of the embodiment shown in FIG. 4 will be described in detail below. Stream inverter 375
Forms an inverted set of adjacent bits from a set of selected stream_data 336 selected from the stream data 302. Based on the fetched leading bits 345 received from the leading bit fetching unit 340, the stream selector 380 determines the non-inverted set of adjacent bits 37
8b and one of the set of adjacent bits 378a of the inversion are selected, and stream_data3 is set to the set of mask gates 384.
82, and sends the presented set of stream_data 382. The presented set of stream_data 382 includes some or all bits included in the m-th encoded data value. Based on the mask bits 325 received from the mask generator 320, the set of mask gates 384
Masks adjacent bits associated with all encoded data values from the first encoded data value to the m-th encoded data value (excluding the m-th encoded data value itself). But,
A set of mask gates 384 causes the other significant significant bits sent to its output to be sent as a set of adjacent unmasked bits. The adjacent masked and unmasked bits are connected to mask gate 38
4 form the stream stamp signal 386.
The stream stamp signal 386 consists of adjacent lower significant significant bits equal to the number of masked bits and several adjacent identical lower significant bits of the m-th encoded data value. The stream stamp signal 386 is
In addition, it includes the remaining unmasked adjacent bits received from the stream selector 380 at the position of the remaining upper significant bits. This stream stamp signal 38
6, the pre-encoder 388 is used to generate and transmit the pre-length signal 392. This predecessor signal 392
Represents the sum of all previously decoded code lengths decoded in the same clock cycle in which the length of the first encoded data value is decoded, and the pseudo length of the mth encoded data value.

It should be noted that the embodiment shown in FIG. 4 is not limited in the number of bits assigned to all input and output bits, and is not described here. The invention is described using a DCT coefficient length decoder as an example. Although the invention has been described by way of example with an embodiment using a video data bitstream encoded in MPEG, it can be embodied in other types of variable length decoders.
Although the present invention has been described by way of example embodiments,
Should not be limited to it. Rather, the appended claims should be construed to include other modifications and embodiments of the invention made by those skilled in the art without departing from the spirit of the invention.

[0023]

The present invention can achieve higher data throughput than a single code length decoding means. Such high data throughput is essential for high throughput applications such as HDTV.

The clock speed used by the present invention is:
Increased throughput can be reduced, allowing slower but lower cost memory to be used.

The present invention is directed to a single variable length decoder for decoding multiple DCT coefficients in a single clock cycle.
A length decoding solution is provided. In high throughput applications, multiple parallel tunable decoders are used for increasing data throughput. The present invention can constitute an essential part of such a single tunable decoder required to reduce the amount of memory at the rate buffer interface. In addition, if multiple DCs are
If a single variable length decoder to decode the T coefficients is used instead, no overhead is required in switching between multiple tunable decoders.

The length decoding means of the present invention can be used in place of other length decoding means used in some of the currently available variable code length decoding methods. The present invention can achieve several effects. In the present invention, the use of a single code length decoder for each code length decoding means, in its implementation, each possible start of a previous code word whose length is to be decoded within the same clock cycle. The chip area and cost are reduced as compared with the method using a large number of multiplex code length decoders according to positions.

Further, since a large barrel shifter is not used in the present invention, it contributes to making the code length decoder smaller. In addition, the look-up table used for each next length decoding means stores the code length information for all the entries found in Tables B-14 and B-15, thereby reducing redundancy. Can be smaller.
Also, since the number of entries in each lookup table used is reduced, the chip area is made smaller and manufacturing costs are reduced.

[Brief description of the drawings]

FIG. 1 illustrates a length used in a decoder that uses multiple multiple code length decoders for use at each possible starting bit position of a first codeword whose length is decoded within the same clock cycle. Block diagram for explaining a decoder

FIG. 2 is a block diagram for explaining a multiplex adjacent code length decoding apparatus according to the present invention;

FIG. 3 is a block diagram of an embodiment of the present invention, showing details of the structure of an m-th code length decoding unit that is an example of a typical code length decoding unit introduced in the present invention;

FIG. 4 is a block diagram for explaining a mask device used in an m-th code length decoding unit.

[Explanation of symbols]

Reference Signs List 100 multiplex code length decoding device 102 stream data stream_data 104 table_id 106 preceding code length decoding means 108 m-th code length decoding means 110 next code length decoding means 190_m length_m signal 198_ (m-1) total_length_ (m-1) signal 198_m total_length_m signal 202 stream data stream_data 204 table_id 208 m-th code length decoding means 220 mask generator 225 mask bit 230 pseudo-length decoder 235 pseudo-length signal 240 leading bit extraction unit 245 shifted-leading bit 250 identifier extraction unit 255 identifier bit 260 code length decoding Unit 290 mask device 290_m length_m 292 pre-length signal 295 adder 298_ (m-1) total_length_ (m-1) 298_m total_length_m 302 stream data stream_data 320 mask generator 325 mask bit 3 36 Selected set of stream data 340 Leading bit extractor 345 shifted-leading-bit 375 Stream inverter 378a Set of adjacent inverted bits from stream data 302 378b Adjacent non-inverted bits from stream data 302 Set 380 stream selector 382 presented set of stream data 384 mask gate 386 stream stamp signal 388 precoder 390 mask device 392 prelength signal

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Claims (5)

[Claims] 1. An apparatus for generating and transmitting a code length signal indicating a length of a multiplex codeword included in a data stream in a single clock cycle, wherein the (m-1) th encoding included in an input data stream is provided. A preceding code including an (m-1) th code length decoder for performing a code length decoding process on the data value and transmitting an (m-1) th code length signal indicating the code length of the (m-1) th encoded data value Long decoding means, and m-th code length decoding means for performing a code length decoding process on the m-th encoded data value included in the input data stream and transmitting an m-th code length signal indicating the code length of the m-th encoded data value; The code length decoding process is performed on the next encoded data value immediately after the m-th encoded data value included in the input data stream, and the (m + 1) -th code value indicating the code length of the (m + 1) -th encoded data value The transmitting the over de length signal (m + 1) device comprising a next code length decoding means including code length decoder. 2. The apparatus according to claim 1, wherein said m-th code length decoding means is configured to decode said m-th code length currently being decoded from a first coded data value. The sum of all previously decoded code length values, decoded within a single clock cycle, of encoded data values, up to (but not including) the m-th encoded data value itself, A mask generator for generating and transmitting a set of mask bits based on the indicated signal; a first bit extracting means for extracting and transmitting the bit value of the least significant first bit of the m-th encoded data value; Of all the bits contained in the encoded data value,
For the fixed bit position of the least significant first bit of the first encoded data value having a bit value opposite to the least significant bit of the m-th encoded data value, the bit position of the first bit which is the first bit is indicated. Mask means for generating and transmitting a pre-length signal; a pseudo-length decoder for generating and transmitting a pseudo-length signal indicating the number of adjacent bits having the same leading bit value in the m-th encoded data value; An identifier extracting means for generating and transmitting a fixed number of bits from the m-th encoded data value, wherein the fixed number of bits are higher than the least significant first bit position of the m-th encoded data value , And the pseudo length and other reference signals provided according to the decoding protocol are not sufficient to determine the actual unique code length of the m-th encoded data value, m encoded data Identifier fetching means having a role in determining the actual unique code length of the pseudo-length decoder, identifier fetching means, and other criteria provided according to the decoding protocol and the signals received from the identifier fetching means. A code length decoder for generating and transmitting a code length signal indicating an actual code length of the m-th encoded data value based on the signal. 3. The apparatus according to claim 2, wherein said masking means comprises: inverting from the input data stream some or all bits contained in the m-th encoded data value. Stream inverting means for generating a set of adjacent inverted bits including the extracted bits, and a set of non-inverted bits in the input data stream based on the signal received from the leading bit extracting means. Stream selecting means for selecting and transmitting one of an inverted bit and a set of inverted bits in the input data stream received from the stream inverting means; and the input data from the stream selecting means. A set of mask gates that receive one of a set of non-inverted bits in the stream and a set of inverted bits in the input data stream. Adjacent bits included in all encoded data values in a range from the first encoded data value to the m-th encoded data value (not including the m-th encoded data value itself). And a set of mask gates for generating a stream stamp signal by masking and transmitting the other remaining higher significant bits unmasked; said first encoded data A forward length representing the sum of all previously decoded code length values decoded in a single clock cycle in which the value length is decoded, and the pseudo length of the m-th encoded data value. An apparatus for generating and transmitting a signal by indicating the number of adjacent identical leading bits found in said stream stamp signal. 4. A method for determining a code length of an m-th encoded data value included in an input data stream within a single clock cycle, wherein the current code length is being decoded from a first encoded data value. Of the encoded data values, up to (but not including) the m-th encoded data value, decoded within a single clock cycle, Generating and transmitting a set of bits based on a signal indicating the sum of the calculated code length values; determining the bit value of the least significant first bit of the m-th decoded value; Of all the bits in the data value,
For the fixed bit position of the least significant first bit of the first encoded data value having a bit value opposite to the least significant bit of the m-th encoded data value, the bit position of the first bit that is the first bit is indicated Generating and transmitting a stream stamp signal; generating and transmitting a signal indicating the number of adjacent leading bits in the m-th encoded data value having the same leading bit value; m has a significant bit position higher than the least significant first bit position of the encoded data value, and another reference signal provided according to the pseudo length and the decoding protocol is the m-th encoded data value.
If the actual unique code length of the encoded data value is not sufficient to determine the actual unique code length of the m-th encoded data value, the fixed number of bits that serve to determine the actual unique code length of the m-th encoded data value are Extracting from the m-th encoded data value; and a code length signal indicating an actual code length of the m-th encoded data value based on the pseudo-length signal and other reference signals provided according to a decoding protocol. Generating and transmitting the. 5. The method of claim 4, wherein said step of determining a pre-length signal comprises: a set of bits from said input data stream comprising bits contained in said m-th encoded data value. Generating an inverted adjacent bit; and a set of non-inverted bits in the input data stream based on the bit value of the least significant bit of the m-th encoded data value; Selecting and transmitting one of the set of inverted bits in the input data stream; and selecting from the first encoded data value to the m-th encoded data value (the m-th encoded data value itself). Masking said adjacent bits associated with one or more encoded data values in a range (not including), from said first encoded data value to said m-th encoded data value (m-th encoded data value) Self A first bit set of the adjacent one or more identical bit values equal in number to the number of all the bits associated with the encoded data values that do not) ranges include, the m
Forming and transmitting a stream stamp signal consisting of adjacent identical lower significant bits of the encoded data value; and within a single clock cycle in which the length of said first encoded data value is decoded. The preceding length signal representing the sum of all the previously decoded code length values decoded at and the pseudo length of the m-th encoded data value, with the adjacent length found in the stream stamp signal Generating and transmitting by indicating the number of identical leading bits.