JP2002203907A - Method and device for circuit operation verification - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform high-accuracy circuit operation verification even on a fined LSI by performing the verification through circuit simulation taking the deviation of a characteristic length after correcting dimensions in a chip into consideration. SOLUTION: An estimated finished dimension, for example, a gate length obtained from data corrected through OPC is reflected (back annotation) in a circuit diagram (schematic). Thereafter, the circuit operation verification taking a partial dimensional deviation in the chip into consideration is performed by performing the circuit simulation on the circuit diagram. Consequently, the circuit operation verification can be performed with high accuracy even on the fined LSI.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an OPC (Optical Proximity Effect Correlation) for verifying the operation of an LSI design circuit.
The present invention relates to a circuit operation verification method and a circuit operation verification device capable of performing verification in consideration of dimensional deviation due to the optical proximity effect using a technique.

[0002]

2. Description of the Related Art In recent years, the miniaturization of LSIs has been evolving rapidly, needless to say here, but there is an OPC technology as one of the technologies supporting the miniaturization technology. This technique is a technique for minimizing an error between layout data generated by the optical proximity effect and a finished dimension by correcting the data.

On the other hand, a circuit simulation for a circuit diagram (Schematic) designed by a circuit designer is conventionally performed by a circuit operation verification method as shown in FIG. FIG.
, A Schematic is generated by a circuit designer (step 701). This includes connection information of each element, element size information, electric characteristic information, and the like. However,
In this state, it is a circuit diagram and cannot be input to the circuit simulator. So Netlister
A netlist (Net1
ist) (step 702), and a net list is obtained (step 703). Circuit simulator (Circui
t Simu1ator) inputs this netlist and simulates it. The output file (Ou
tput Vector) 1 is output (step 704). The circuit designer sets the output file 1 to the expected value file (Ref.Vect
or) By comparing with (2), it can be determined whether the circuit function operates normally.

[0004]

In the conventional circuit operation verification method as described above, it is still necessary to calculate the oxide film thickness and the gate length in the netlist by increasing or decreasing by 3σ and verify the timing by circuit simulation. ing. But,
This is a method of performing simulation including process variations. However, there is a problem that a change in the entire chip is uniform and a partial bias in the chip cannot be verified.

[0005] Here, even if the above-described OPC technology is used, the LS which has been manufactured using a state-of-the-art process and has been miniaturized has advanced.
In the case of I, unevenness in finished dimensions occurs due to the density of patterns in the chip. For example, when this bias occurs in the poly (Poly) gate length, the signal integrity within the chip (Signal
Integrity) is deteriorated, and at the worst, the function is bad.

However, even with the conventional circuit operation verification method,
Although a dimensional change of about 10% has been performed uniformly, circuit verification has not been performed in consideration of a partial deviation of the dimensional change in a chip, so that the verification accuracy is reduced for an LSI that has been miniaturized. There was a problem.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide an operation verification by circuit simulation in which a partial dimensional deviation after dimensional correction in a chip by OPC is considered. And to provide a circuit operation verification method and a circuit operation verification device capable of performing highly accurate circuit operation verification even for an LSI that has been miniaturized.

[0008]

In order to achieve the above object, a first feature of the present invention is to compare an output value obtained by performing a circuit simulation for a designed circuit diagram with an expected value and to compare the output value with an expected value. A circuit operation verification method for verifying the operation of (a), generating layout data from the circuit diagram;
/ OPC processing to obtain modified layout data; comparing the layout data with the modified layout data to extract data at different points between the two; And reflecting it on a circuit diagram.

A second feature of the present invention is a circuit operation verification method for verifying the operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value. A step of creating a netlist from; a step of obtaining the output value as a result by inputting the netlist and performing circuit simulation; and a step of comparing the output value as the circuit simulation result with the expected value. Generating the layout data from the circuit diagram when the output value and the expected value match; performing MDP / OPC processing on the layout data to obtain corrected layout data; Simulation is performed to determine the gate length of the transistor after MDP / OPC processing. That step a, obtaining a net list after the resulting gate length is reflected in the netlist MDP / OPC process, the MDP / OP
Obtaining an output value after the MDP / OPC processing by inputting the netlist after the C processing and performing a circuit simulation; and comparing the obtained output value after the MDP / OPC processing with the expected value. Is provided.

A third feature of the present invention resides in that the method includes a step of performing lithography simulation on the modified layout data to obtain GDS data, and a step of extracting a gate length and its coordinates from the GDS data.

A fourth feature of the present invention is a circuit operation verification method for verifying the operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value. A step of creating a netlist from; a step of obtaining the output value as a result by inputting the netlist and performing circuit simulation; and a step of comparing the output value as the circuit simulation result with the expected value. Generating the layout data from the circuit diagram when the output value matches the expected value value; performing MDP / OPC processing on the layout data to obtain corrected layout data; and inputting the corrected layout data. Applying a lithography simulation to the corrected layout data. S extracting data for device simulation from the data obtained by applying the simulation, by performing the device simulation by entering the data for the device simulation
Obtaining a PICE model file, and combining the SPICE model file with the netlist to obtain an MD
Obtaining a netlist after the P / OPC processing, obtaining an output value after the MDP / OPC processing by inputting the netlist after the MDP / OPC processing and performing circuit simulation, / O
Comparing the output value after the PC processing with the expected value.

A fifth feature of the present invention is that the verification of the circuit operation is performed only on a limited range of circuits on a chip.

A sixth feature of the present invention is a circuit operation verification apparatus for verifying the operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value. And a function for creating layout data from the
A function of performing modified DP / OPC processing to obtain modified layout data, a function of comparing the layout data and the modified layout data to extract data at a different point between the two, and a function of comparing the extracted data at the different points. And a function to be reflected in the circuit diagram.

A seventh feature of the present invention is a circuit operation verifying apparatus for verifying the operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value. A function of creating a netlist, a function of obtaining the output value as a result by inputting the netlist and performing a circuit simulation, and a function of comparing the output value as the circuit simulation result with the expected value, When the output value and the expected value match, a function of creating layout data from the circuit diagram, a function of performing MDP / OPC processing on the layout data to obtain corrected layout data, and a lithography simulation of the corrected layout data MDP
A function of obtaining the gate length of the transistor after the / OPC processing, a function of reflecting the obtained gate length in the netlist to obtain a netlist after the MDP / OPC processing, and a function of obtaining the netlist after the MDP / OPC processing And MDP / OP by performing circuit simulation
A function for obtaining an output value after the C processing, and a function for obtaining the obtained MDP /
A function of comparing the output value after the OPC process with the expected value is provided.

An eighth feature of the present invention resides in that the modified layout data is provided with a function of performing a lithography simulation to obtain GDS data, and a function of extracting a gate length and its coordinates from the GDS data.

According to a ninth feature of the present invention, there is provided a circuit operation verification apparatus for verifying the operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value. A function of creating a netlist from the above, a function of obtaining the output value as a result of performing the circuit simulation by inputting the netlist, and a function of comparing the output value as the circuit simulation result with the expected value. A function of creating layout data from the circuit diagram when the output value and the expected value match, and MDP / OPC
A function of performing processing to obtain corrected layout data, a function of inputting the corrected layout data and performing lithography simulation, and a function of obtaining device simulation data from data obtained by performing lithography simulation on the corrected layout data. A function of obtaining a SPICE model file by performing device simulation by inputting data for the device simulation, and a function of obtaining a netlist after MDP / OPC processing by combining the SPICE model file with the netlist, By inputting the netlist after the MDP / OPC processing and performing a circuit simulation,
A function for obtaining an output value after the / OPC processing;
A function of comparing the output value after the DP / OPC processing with the expected value is provided.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart showing a flow according to a first embodiment of the circuit operation verification method and device of the present invention. The operation verification method of the present example includes a block A and a block B, and the block A is the same as the conventional method.

Next, the operation of this embodiment will be described.
A Schematic is generated by a circuit designer (Step 101). This includes connection information of each element, element size information, electric characteristic information, and the like. However, in this state, it is a circuit diagram and cannot be input to the circuit simulator. Therefore, a netlist (Net1ist) which is connection information of elements etc.
(Step 102), and a netlist is obtained (step 103). Circuit simulator (Circuit Si
mu1ator) performs a circuit simulation using this netlist as an input, and outputs an output file (Output Vector) 1 as an output result (step 104).

The circuit designer compares the output file 1 with the expected value file (Ref. Vector) 2 to judge whether the circuit function operates normally as designed. If it is not determined that the operation is normal, return to the Schematic and make a correction, and repeat the above-described operation verification again.

When it is determined that the circuit function operates normally, the Schematic that is normally verified in the block A can be obtained.
Thereafter, a layout pattern corresponding to this is created (step 105). In generations with loose design rules, patterns could be transferred to silicon wafers according to this layout, but in recent ultra-miniaturization processes, MDP (Mask Data Processing) / OPC processing must be performed (step 106), it is very difficult to realize the target dimensions such as the poly gate length of the MOSFET intended by the circuit designer.

The layout data after the MDP / OPC processing is converted into a file in the GDS format as modified layout data (step 107), and a litho simulation (Litho Simu1ation) is performed using the GDS data as an input (step 108). A file of the gate length after the MDP / OPC processing reflecting the dimensional deviation is created (step 109). Gate 1ength Back A
The program returns to the netlist of block A by the notate by LVS program (step 110) and is reflected in the netlist file after MDP / OPC processing (step 11).
1) The circuit simulation is executed again (step 112). Output file 3 obtained by this
Since this reflects the correction bias in the chip, this is compared with the expected value file 2 to perform circuit verification.

Here, the poly gate shown by the broken line in FIG. 2 is the layout pattern before the lithography simulation is performed, and the shape of the poly gate shown by the solid line is the pattern after the lithography simulation is performed.

FIG. 3 is a flowchart showing the details of the processing indicated by the solid line in the block B of FIG. 1, and details the key portion of the present embodiment. The process from the lithography simulation processing in step 108 to the point where the poly gate length is back annotated in step 111 is shown.

First, a lithography simulation (step 1)
GDS data of the shape calculated in step 08) is obtained (step 113). This GDS data is data including a deviation in the poly gate length in the chip due to the pattern density in the chip. These two types of data are acquired by a program that extracts the poly gate length and the coordinates in the chip by using this data as an input. Therefore, the file created in step 109 includes the poly gate length and the coordinates in the chip. The information is linked with the LVS information, and a net list having an estimated finished polygate length is generated by the Back Annotate program in step 110 (step 111).

According to the present embodiment, a circuit simulation is performed by back-notating an estimated finished dimension (eg, gate length) obtained from data corrected by OPC, thereby reducing partial dimensional deviation in a chip. It is possible to perform circuit operation verification in consideration of the above, and it is possible to perform highly accurate circuit operation verification even for an LSI that has been miniaturized.

FIG. 4 is a flowchart showing a flow according to a second embodiment of the circuit operation verification method and apparatus of the present invention. The basic flow of this example is the same as that of the first embodiment. When all the MOSFETs have straight gates, the processing from step 401 to step 412 is performed, and is the same as that of the first embodiment. When a vent gate is used for the MOSFET, the processing from step 401 to step 408 is the same as described above, but the process proceeds from step 415 to step 411 or 412 via step 417. It is different.

FIG. 5 shows an example of a bent gate. After the lithography simulation, the gate may become thick as indicated by a in the figure, which is different from the original layout data.

Next, features of the operation of the present embodiment will be described. After inputting the modified layout in step 408 and performing lithography, data for device simulation of the bend gate is extracted from the simulation result (step 415), and device simulation is performed using this data (step 4).
16). The result of this device simulation is
After saving as an E model file (step 41
7), the SPICE model file is stored in step 403
(Step 4)
11) A circuit simulation is executed again using this netlist (step 412). As a result, the obtained output file 3 reflects the correction bias of the bent gate in the chip. The output file 3 is compared with the expected value file 2 to perform circuit verification.

According to the present embodiment, it is possible to perform a circuit operation verification in consideration of a partial deviation of a vent gate in a chip, and to perform a highly accurate circuit operation verification even for an LSI that has been miniaturized. Can be. The straight gate also has the same effect as the first embodiment.

FIG. 6 is a flowchart showing a flow according to a third embodiment of the circuit operation verification method and apparatus of the present invention. Although the first and second embodiments describe the method of verifying the poly gate length of the MOSFET specifically, in this example, the accuracy is not limited to the width of the metal wiring in addition to the gate length of the MOSFET. A method for performing a circuit operation verification with high reliability is described.

Next, the operation of this embodiment will be described.
First, a schematic is generated by a circuit designer (step 601). A layout is created from this Schematic by a layout designer (step 60).
2). At this point, schematic and layout circuit attributes
(Gate length, gate width, RC of metal, etc .; however, R of metal
When C is considered, this Schematic has Bac
k Annotated RC) has a one-to-one correspondence. Next, MDP / OP
C processing is performed (step 603), and a corrected layout is created (step 604).

At this point, the circuit attributes of the layout in step 602 and the modified layout in step 604 are not equal. Thereafter, the layout created in step 603 and the modified layout created in step 604 are compared to extract different points (step 605) and obtain data of different points (step 606). The data of this different point is reflected in the schematic of step 601 (B
ack Annotation) and Schematic take into account the bias in the chip due to the pattern density. After that, a netlist is created from this Schematic and circuit simulation is performed.

According to the present embodiment, not only the gate length and gate width of the MOSFET but also the width (RC) of the metal are estimated by performing Back Anotation on the estimated finished dimensions obtained from the data corrected by OPC. By performing circuit simulation, it is possible to perform circuit operation verification in consideration of partial dimensional deviations in the chip such as the gate length and metal width, and to perform highly accurate circuit operation verification even for LSIs that have been miniaturized. it can.

Here, in the first, second, and third embodiments, the application range of the lithography is not mentioned. Of course, if it is possible to simulate the entire chip, it is ideal without any burden on the designer, but since the range of verification is wide, a high-speed computer is needed to produce results within an appropriate time, and the cost is high. Will be expensive. Therefore, in order to perform verification at an appropriate time and at an appropriate cost, it is necessary to limit the range in which the lithography simulation is performed. For example, it is also important that a litho simulation is performed on only a cell including a critical path in a logic LSI as a processing target to suppress the processing time to a realistic range.

The present invention is not limited to the above-described embodiment, and may be embodied in various other forms with specific configurations, functions, functions, and effects without departing from the gist thereof. .

[0036]

As described in detail above, according to the present invention, a circuit simulation is performed in consideration of a difference between a circuit design value and a circuit / physical characteristic caused by a layout due to an optical proximity effect in semiconductor manufacturing. Timing mismatch can be discovered before product prototype.

Further, a timing mismatch caused by performing a circuit simulation in consideration of a dimensional deviation in a chip due to an optical proximity effect of a poly gate can be found before a prototype of a product.

Further, it is possible to realize an improvement in element characteristics accuracy by device simulation based on the BendGate shape caused by the optical proximity effect, and find a timing mismatch caused by performing circuit simulation before product trial production.

Further, it is possible to solve the time constraint of lithography simulation during the verification method (to secure a realistic processing time).

[Brief description of the drawings]

FIG. 1 is a flowchart showing a flow according to a first embodiment of a circuit operation verification method and apparatus of the present invention.

FIG. 2 is a diagram showing an example of a shape change before and after a lithography simulation of a poly gate.

FIG. 3 is a flowchart showing details of a process indicated by a broken line of a block B in FIG. 1, and is a diagram illustrating a key portion of the present embodiment in detail.

FIG. 4 is a flowchart showing a flow according to a second embodiment of the circuit operation verification method and apparatus of the present invention.

FIG. 5 is a diagram showing an example of a shape change before and after a lithography simulation of a vent gate.

FIG. 6 is a flowchart showing a flow according to a third embodiment of the circuit operation verification method and apparatus of the present invention.

FIG. 7 is a flowchart illustrating a conventional circuit operation verification method.

[Explanation of symbols]

 1 Output file 2 Expected value file 3 Output file after MDP / OPC

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 21/822 H01L 27/04 TF term (Reference) 2H095 BB01 BB02 BB36 5B046 AA08 BA04 DA05 JA04 5F038 CA17 CA20 DT01 EZ20 5F046 AA25 AA28 DA11 5F064 CC10 DD10 EE09 HH09 HH10 HH20

Claims (9)

[Claims] 1. A circuit operation verification method for verifying the operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value, wherein layout data is created from the circuit diagram. Subjecting the created layout data to MDP / OPC processing to obtain modified layout data; comparing the layout data with the modified layout data to extract data of different points between the two; Reflecting the extracted data of the different points on the circuit diagram. 2. A circuit operation verification method for verifying an operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value, wherein a netlist is created from the circuit diagram. Obtaining the output value as a result by inputting the netlist and performing a circuit simulation; comparing the output value as the circuit simulation result with the expected value; and outputting the output value and the expected value. If the values match, a step of creating layout data from the circuit diagram; a step of performing MDP / OPC processing on the layout data to obtain modified layout data; Obtaining the gate length of the processed transistor; Reflecting the obtained gate length in the netlist to obtain a netlist after the MDP / OPC processing; and inputting the netlist after the MDP / OPC processing and performing a circuit simulation to perform a circuit simulation, A circuit operation verifying method, comprising: obtaining an output value of the above; and comparing the obtained output value after the MDP / OPC processing with the expected value. 3. The circuit according to claim 2, further comprising: performing a lithographic simulation on the modified layout data to obtain GDS data; and extracting a gate length and its coordinates from the GDS data. Operation verification method. 4. A circuit operation verification method for verifying operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value, wherein a netlist is created from the circuit diagram. Inputting the netlist and performing a circuit simulation to obtain an output value as a result thereof; comparing the output value as the circuit simulation result with the expected value; and the output value and the expected value. If the values match, a step of creating layout data from the circuit diagram; a step of performing MDP / OPC processing on the layout data to obtain modified layout data; a step of inputting the modified layout data and performing lithography simulation Lithography simulation on the modified layout data Extracting device simulation data from the data obtained by performing the device simulation, obtaining the SPICE model file by performing the device simulation by inputting the device simulation data, and storing the SPICE model file in the netlist. Combining to obtain a netlist after MDP / OPC processing; inputting the netlist after MDP / OPC processing and performing circuit simulation to obtain an output value after MDP / OPC processing; And a step of comparing the output value after the MDP / OPC processing with the expected value. 5. The circuit operation verification method according to claim 1, wherein the verification of the circuit operation is performed only for a limited range of circuits on the chip. 6. A circuit operation verification device for verifying the operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value, wherein a function of generating layout data from the circuit diagram A function of performing MDP / OPC processing on the created layout data to obtain modified layout data; a function of comparing the layout data with the modified layout data to extract data at a different point between the two; A function of reflecting the extracted data of different points on the circuit diagram. 7. A circuit operation verification device for verifying the operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value, wherein a function of creating a netlist from the circuit diagram A function of obtaining the output value as a result of the circuit simulation by inputting the netlist; a function of comparing the output value of the circuit simulation result with the expected value; and the output value and the expected value If they match, a function of creating layout data from the circuit diagram; a function of performing MDP / OPC processing on the layout data to obtain corrected layout data; and a MDP / OPC processing of performing lithographic simulation on the corrected layout data A function of obtaining a gate length of a transistor to be obtained later; A function of obtaining a netlist after the MDP / OPC processing by reflecting the result on the list, a function of obtaining an output value after the MDP / OPC processing by inputting the netlist after the MDP / OPC processing and performing a circuit simulation, A function of comparing the obtained output value after the MDP / OPC processing with the expected value. 8. The circuit according to claim 7, further comprising: a function of obtaining a GDS data by performing a lithographic simulation on the modified layout data; and a function of extracting a gate length and its coordinates from the GDS data. Operation verification device. 9. A circuit operation verification apparatus for verifying the operation of the circuit by comparing an output value obtained by performing a circuit simulation on a designed circuit diagram with an expected value, wherein a function of creating a netlist from the circuit diagram A function of obtaining the output value as a result of the circuit simulation by inputting the netlist; a function of comparing the output value of the circuit simulation result with the expected value; and the output value and the expected value When the values match, a function of creating layout data from the circuit diagram, a function of performing MDP / OPC processing on the layout data to obtain corrected layout data, and a function of inputting the corrected layout data and performing lithography simulation From the data obtained by performing the lithography simulation on the modified layout data A function of obtaining data for device simulation, a function of obtaining a SPICE model file by performing device simulation by inputting the data for device simulation, and an MDP / OPC process by combining the SPICE model file with the netlist A function for obtaining a netlist after the MDP / OPC processing; a function for obtaining an output value after the MDP / OPC processing by inputting the netlist after the MDP / OPC processing and performing a circuit simulation; And a function of comparing the output value of the above with the expected value.