JP2002198754A - Variable gain amplifier, imaging unit, imaging system and amplification method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier having a highly accurate gain characteristic without increasing the power consumption through the configuration of the variable gain amplifier whose gain characteristic can be correctable. SOLUTION: The variable gain amplifier receives digital data to control is gain and is provided with a measurement means that measures a gain when the most significant bit of the data is changed and a correction means that corrects the gain of the amplifier according to the measured gain.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a variable gain amplifier, and more particularly to an analog signal processing circuit combining a variable gain amplifier and an AD converter.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional analog signal processing circuit combining a variable gain amplifier and an AD converter. In the figure, an input analog signal is applied with a preset gain by a variable gain amplifier PGA (programmable gain amp), and is converted into an analog signal matching the input range of the AD converter ADC. Further, the analog signal is converted into a digital signal by an AD converter, and the digital signal is output. Generally, the gain setting data of the variable gain amplifier is set by a serial interface and a register.

FIG. 4 is a circuit diagram showing a switched capacitor type circuit suitable for use in such a variable gain amplifier. The circuit shown in the figure is composed of a capacitor group with a predetermined weight applied to the input section, a feedback capacitor, and a plurality of transfer switches, and is a circuit of differential input and differential output. .. Represent the capacitance values of the respective capacitors. This example shows a case where the gain setting data has a 4-bit resolution. The relationship between the gain setting data d0-d3 and the gain of the circuit is as follows.

Setting data gain 0000 1 0001 2 0010 3 0011 4:: 1100 13 1101 14 1110 15 1111 16

When the PGA circuit is ideal, the relationship between the gain setting data and the gain generally has a linear characteristic as shown in FIG.

When gain setting with high resolution is required, it is useful to adopt a configuration in which a circuit is separated for each bit and added at a subsequent stage as shown in FIG. The reason is that as the resolution becomes higher, the size of the capacitor weighted with binary weights becomes larger.For example, when 8-bit resolution is realized with a one-stage configuration as in FIG. 4, it is assumed that the least significant bit is 1C. Then, the most significant bit becomes as large as 128C, which is very disadvantageous in terms of circuit operation speed and circuit size. In the figure, only the positive side of the differential amplifier is shown, and the circuit on the negative side and switches corresponding to φ1 and φ2 in FIG. 4 are omitted. This example shows a case where the gain setting data has an 8-bit resolution. In this case, the relationship between the gain setting data and the gain is as follows.

[0007] Setting data gain 00000000 1 00000001 1.0625 00000010 1.125 00000011 1.1875:: 11111100 16.5 11111101 16.5625 11111110 16.625 11111111 16.6875

[0008]

The above-mentioned prior art has the following problems. The circuit has a finite parasitic capacitance and a variation in capacitance value corresponding to the processing accuracy. When the magnitude of the parasitic capacitance and the variation cannot be ignored with respect to the capacitance values of the input capacitor and the feedback capacitor which determine the gain, the gain value of the actual circuit has an error with respect to the desired gain value. . When high-precision gain setting is required, it is necessary to increase the capacitor size in order to reduce the influence of parasitic capacitance and variation. This means an increase in the load to be driven, and it is required that the slew rate of the amplifier be high. In particular, when high-speed operation is required, power consumption increases. If the capacitor size is reduced to avoid this, there is a problem in the linearity, especially when the data of the most significant bit changes.
In many cases, the gain characteristic has poor linearity as shown in FIG. However, with a resolution of about 4 bits, an extreme linearity error is unlikely to occur as shown in the figure. However, when the resolution becomes higher than about 8 bits, this problem becomes apparent. The feedback capacitance of the circuit block with the largest gain in the circuit of Fig. 11 is 1C, which is the smallest in the circuit, and at the same time, the gain is set large. Affect. Result, FIG. 9
Or, a linearity error as shown in FIG. 10 is likely to occur.

It is an object of the present invention to realize a high-speed and high-precision variable gain amplifier without increasing power consumption.

[0010]

According to one aspect of the present invention, there is provided a variable gain amplifier whose gain can be controlled by digital data, wherein a measuring means for measuring a gain value when a most significant bit changes; And a correcting means for correcting the gain value based on the measured gain value.

According to another aspect of the present invention, a variable gain amplifier whose gain can be controlled by digital data,
Correction means for correcting the gain value of the variable gain amplifier based on the gain value of the variable gain amplifier in the first digital data and the gain value of the variable gain amplifier in the second digital data. Variable gain amplifier is provided.

According to still another aspect of the present invention, there is provided a method of amplifying a variable gain amplifier capable of controlling a gain by digital data, the method comprising: measuring a gain value when a most significant bit changes; And a correction step of correcting the gain value based on the measured gain value.

According to still another aspect of the present invention, there is provided a method of amplifying a variable gain amplifier, wherein the gain is controllable by digital data, wherein a gain value of the variable gain amplifier in first digital data and a second digital A method of amplifying a variable gain amplifier, comprising: a correction step of correcting a gain value of the variable gain amplifier based on a gain value of the variable gain amplifier in data.

According to the present invention, the gain characteristic of the variable gain amplifier can be corrected, so that a variable gain amplifier having high-precision gain characteristics can be realized without increasing power consumption.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below along with examples with reference to the drawings. FIG. 1 is a block diagram showing an embodiment according to the present invention. In the figure, as gain correction means, means for latching and comparing gain setting data generation, generation of an analog signal for gain correction, and AD conversion results in each gain setting, and a switch for a gain correction capacitor according to the comparison result. . FIG. 2 shows ga in FIG.
FIG. 3 is a circuit block diagram illustrating an in cal. logic unit. FIG. 3 is a circuit diagram showing an example of the configuration of the cal.sig.gen. Section in FIG. FIG. 6 is a circuit diagram showing a variable gain amplifier to which a capacitor for gain correction is added.

First, gain cal e is externally applied as a control signal.
Input the nable signal and start the gain correction operation. This signal connects the two switches in Figure 1 to the bottom,
2 and 3 also operate at the same time. First, from the TG in FIG. 2, the gain setting data generating means sets only the most significant bit to low, that is, (0111). Further, the first analog signal level generated from the analog signal generation means (FIG. 3) is input to the variable gain amplifier. The analog output at this time is converted into digital data by the AD converter, and this data is stored in the first latch means latch1 in synchronization with the signal of the output lat1 from the TG in FIG. Then Figure 2
, The gain setting data generating means sets only the most significant bit to high, that is, (1000) gain setting. Further, the second analog signal level generated from the analog signal generation means (FIG. 3) is input to the variable gain amplifier. The analog output at this time is similarly converted into digital data by an AD converter, and this data is output from the TG shown in FIG.
Is stored in the second latch means latch2 in synchronization with the signal of the second latch. Then, the digital data stored in the first and second latch means are compared in magnitude by a digital comparator d_comp.

Here, the signal is generated from the analog signal generating means.
When the characteristics of the two analog signals are ideal, that is, when the characteristics of the variable gain amplifier are ideal, that is, when the characteristics are as shown in FIG. 8, the digital data stored in the first and second latch means match. The resistance value of the resistance element in FIG. 3 is set in advance. Therefore, if there is no problem in the gain characteristics of the variable gain amplifier, the digital comparator outputs eq. At this time, no gain correction capacitor is used.

On the other hand, when the gain characteristic becomes as shown in FIG. 9, the digital data stored in the first latch means is larger than the digital data stored in the second latch means, and the digital comparator Output gt. With this signal, when the most significant bit of the gain setting data is set to high, at the same time, the gain correcting capacitor is activated to increase the gain and operate to improve the gain linearity characteristic.

Further, when the gain characteristic becomes as shown in FIG. 10, the digital data stored in the first latch means becomes smaller than the digital data stored in the second latch means, and the digital comparator becomes lt. Is output. With this signal, when the most significant bit of the gain setting data is set to low, the gain correction capacitor is activated simultaneously and the gain is forcibly increased to improve the gain linearity characteristic.

Such processing can be realized by, for example, the circuit shown in FIG. The circuit of FIG. 7 has two latching means, INV
Gate, EX-NOR gate, and AND gate. In FIG. 7, during the calibration operation, cal.e
The switch is connected to the lower side by the signal of n.
Is output low, and the gain correcting capacitor does not operate in FIG. Next, when the calibration operation is completed, the two latch units are set to e by the latch signal in FIG.
The signals of q and gt are accumulated, and the switch is connected to the upper side.
First, when eq = high and lt = low, the d_add signal is always fixed to low, and the correction circuit does not operate. Then eq = lo
If w, lt = low, d_add = low, d3 = hi when d3 = low
When gh, d_add = high, and when the most significant bit d3 is high, the correction circuit operates. Further, when eq = low and lt = high, d_add = high when d3 = low, and the correction circuit operates when the most significant bit d3 is low.

In the above embodiment, the capacitance value of the gain correction capacitor is the same size as the least significant bit capacitor of the variable gain amplifier. If the resolution of the AD converter is high, the gain correction can be made even more accurate. That is, as shown in FIG. 13, the capacitance for gain correction is constituted by half the capacitance value of the capacitor for the least significant bit of the variable gain amplifier. In this embodiment, the gain characteristic can be corrected with an accuracy of 1/2 LSB of the gain setting data of the variable gain amplifier. At this time, two-bit signals d_add0 and d_add1 are generated from the output result of the AD converter.

FIG. 10 is a diagram in which gain can be set with higher resolution.
Such a conventional example is the embodiment of FIG. Also in this embodiment, the correction circuit of the switched capacitor controlled by d_add is controlled in the same manner as in the above embodiment.

FIG. 14 is a block diagram showing an embodiment in which a variable gain amplifier having a gain correction function according to an embodiment of the present invention is applied to an image pickup apparatus. The image signal photoelectrically converted by the area sensor is input to a variable gain amplifier,
The signal is converted to an analog signal that matches the input range of the conversion circuit. Although omitted in the figure, it is common practice to provide a correlated double sampling (CDS) circuit before the variable gain amplifier in order to remove noise from the sensor output. This analog signal is input to an analog-to-digital converter and converted into a digital signal. Then, the image signal converted into the digital signal is output to the outside. In this embodiment, since a gain correction function is added to the variable gain amplifier, analog signal processing with higher resolution and higher accuracy is possible. As a result, gain setting according to the subject can be realized with high accuracy.

An image pickup system using the image pickup apparatus described with reference to FIG. 14 will be described with reference to FIG.

In FIG. 15, reference numeral 1 denotes a barrier which functions both as protection of the lens and as a main switch, 2 as a lens for forming an optical image of a subject on the solid-state image pickup device 4, and 3 as an aperture for varying the amount of light passing through the lens 2. Reference numeral 4 denotes a solid-state imaging device (imaging device) for capturing a subject formed by the lens 2 as an image signal; An image signal processing circuit including a gain correction circuit unit for correction; 6, an A / D converter for performing analog-digital conversion of an image signal output from the solid-state image sensor 4; 7, an A / D converter
The signal processing unit 8 performs various corrections on the image data output from the converter 6 and compresses the data. The signal processing unit 8 includes a solid-state imaging device 4, an imaging signal processing circuit 5, an A / D converter 6, and a signal processing unit 7. A timing generator 9 for outputting various timing signals, a general control / arithmetic unit 9 for controlling various calculations and the entire still video camera, a memory unit 10 for temporarily storing image data, and a recording or recording unit 11 for recording on a recording medium. An interface unit for performing reading, 12 is a detachable recording medium such as a semiconductor memory for recording or reading image data, and 13 is an interface unit for communicating with an external computer or the like.

Next, the operation of the still video camera at the time of shooting in the above configuration will be described.

When the barrier 1 is opened, the main power supply is turned on, then the control system power supply is turned on.
The power of the imaging system circuit such as the / D converter 6 is turned on.

Then, in order to control the amount of exposure, the overall control / arithmetic unit 9 opens the aperture 3 and the signal output from the solid-state image sensor 4 is converted by the A / D converter 6 and then processed by the signal processing unit. Input to the unit 7.

Based on the data, the exposure calculation is totally controlled.
The calculation is performed by the arithmetic unit 9. The brightness is determined based on the result of the photometry, and the overall control / arithmetic unit 9 controls the aperture according to the result.

Next, based on the signal output from the solid-state imaging device 4, high-frequency components are extracted, and the distance to the subject is calculated by the overall control / calculation unit 9. Thereafter, the lens is driven to determine whether or not the lens is in focus. When it is determined that the lens is not focused, the lens is driven again to perform distance measurement.

Then, after the focusing is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 4 is A / D converted by the A / D converter 6, passes through the signal processing unit 7, and is written in the memory unit by the overall control / arithmetic unit 9.

Thereafter, the data stored in the memory unit 10 is transferred to the recording medium control I / O under the control of the overall control / arithmetic unit 9.
The data is recorded on a removable recording medium 12 such as a semiconductor memory through the F section.

Further, the image may be processed by inputting it directly to a computer or the like through the external I / F unit 13.

As is clear from the above description, according to the present embodiment, the gain characteristic of the variable gain amplifier can be corrected, so that the gain having a high-precision gain characteristic can be obtained without increasing power consumption. A variable amplifier can be realized.

It should be noted that each of the above embodiments is merely an example of a concrete embodiment for carrying out the present invention, and the technical scope of the present invention should not be interpreted in a limited manner. It is. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features.

[0036]

As described above, according to the present invention, it is possible to correct the gain characteristic of a variable gain amplifier, so that a variable gain amplifier having a high-precision gain characteristic can be obtained without increasing power consumption. Is feasible.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a variable gain amplifier according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram illustrating a logic circuit unit of the gain correction circuit according to the embodiment.

FIG. 3 is a circuit diagram showing an example of a correction analog signal generation circuit of the gain correction circuit according to the embodiment.

FIG. 4 is a circuit diagram showing a conventional switched capacitor circuit suitable for realizing a variable gain amplifier.

FIG. 5 is a block diagram showing a circuit in which a conventional variable gain amplifier and an AD converter are combined.

FIG. 6 is a circuit diagram showing a switched capacitor circuit capable of correcting a gain according to the embodiment.

FIG. 7 is a circuit diagram showing a part of a gain correction logic circuit of the variable gain amplifier according to the embodiment.

FIG. 8 is a diagram illustrating gain characteristics of an ideal gain variable amplifier.

FIG. 9 is a diagram illustrating gain characteristics of a variable gain amplifier having a gain error.

FIG. 10 is a diagram illustrating gain characteristics of a variable gain amplifier having a gain error.

FIG. 11 is a circuit diagram showing a conventional high-resolution variable gain amplifier.

FIG. 12 is a diagram illustrating a high-resolution variable gain amplifier capable of gain correction according to the present embodiment.

FIG. 13 is a diagram illustrating a variable gain amplifier capable of performing gain correction with high accuracy according to the present embodiment.

FIG. 14 is a diagram illustrating an imaging device to which the variable gain amplifier according to the present embodiment is applied.

FIG. 15 is a diagram illustrating an imaging system to which the variable gain amplifier according to the present embodiment is applied.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Barrier 2 Lens 3 Aperture 4 Solid-state image sensor 5 Image signal processing circuit 6 A / D converter 7 Signal processor 8 Timing generator 9 Overall control / arithmetic unit 10 Memory unit 11 Recording medium control interface unit 12 Recording medium 13 External interface Department

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (reference) // H04N 101: 00 H04N 101: 00 F term (reference) 5C022 AA13 AB20 AC69 5C024 BX01 CX00 CX41 HX18 HX23 5J022 AA01 BA06 BA08 CA07 CC02 CF02 5J100 AA02 AA04 AA21 AA26 BA07 BB11 BB16 BB17 BC07 CA12 CA14 CA22 CA23 CA26 CA28 CA29 DA06 EA02 FA00

Claims (8)

[Claims] 1. A variable gain amplifier whose gain can be controlled by digital data, a measuring means for measuring a gain value when a most significant bit changes, and a correction for correcting a gain value based on the measured gain value. And a variable gain amplifier. 2. The measuring means includes means for outputting a predetermined level to an input section of an amplifier; data for setting only the most significant bit as 1 and other bits as 0 as gain setting data; And a logic circuit for processing the analog-to-digital converted digital data. Item 4. The variable gain amplifier according to Item 1. 3. The variable gain amplifier according to claim 1, wherein said variable gain amplifier is a switched capacitor type circuit, and said correction means is a switched capacitor added for gain correction. 4. A variable gain amplifier whose gain can be controlled by digital data, based on a gain value of the variable gain amplifier in first digital data and a gain value of the variable gain amplifier in second digital data. Correction means for correcting the gain value of the variable gain amplifier. 5. An area sensor unit in which a plurality of pixels performing photoelectric conversion are arranged in rows and columns, a variable gain amplifier for converting an image signal output from the area sensor unit into a predetermined amplitude, and a variable gain unit. An image pickup apparatus in which analog / digital conversion means for converting an analog signal output from an amplifier into a digital signal is integrated, wherein the variable gain amplifier uses the variable gain amplifier according to any one of claims 1 to 4. An imaging device characterized by the above-mentioned. 6. An imaging device for capturing an imaged subject as an image signal, a lens for forming an optical image of the object on the imaging device, an aperture for varying the amount of light passing through the lens, An imaging system comprising: an image signal processing circuit that processes an image signal output from an imaging device; and an A / D converter that performs analog-to-digital conversion of the image signal processed by the image signal processing circuit. An imaging system using the imaging device according to claim 5 as the imaging device. 7. A method for amplifying a variable gain amplifier capable of controlling a gain by digital data, comprising: a measuring step of measuring a gain value when a most significant bit changes; and a gain value based on the measured gain value. A method of amplifying a variable gain amplifier. 8. A method for amplifying a variable gain amplifier, wherein a gain can be controlled by digital data, wherein a gain value of the variable gain amplifier in first digital data and a gain value of the variable gain amplifier in second digital data A step of correcting the gain value of the variable gain amplifier based on the above method.