JP2002198501A - Semiconductor storage device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which the parasitic capacitances between word lines and a substrate are reduced. SOLUTION: This semiconductor storage device has the substrate, a trench formed at a prescribed position on the substrate, a capacitor positioned in the lowermost part of the trench, and a transistor having a gate extended in the vertical direction along the side walls of the trench above the capacitor in the trench. The storage device is provided with a first word line which is positioned above the trench and connected to the gate of the transistor, and a second word line which is extended in parallel with the first word line. The transistor has a first diffusion layer which is extended in the horizontal direction from a spot above the gate of the transistor provided in the trench along the substrate on the outside of the trench, and a second diffusion layer connected to the capacitor provided in the lowermost part of the trench from the lower part of the gate. As the feature of this semiconductor storage device, the storage device is provided with an insulating film which separates the second word line from a first diffusion area and has a prescribed thickness under the second word line. The first diffusion layer of the transistor is connected to the bit line of the storage device through the bottom side of the second word line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a random access memory using a vertical transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, the miniaturization and integration of DRAMs have advanced, and the area per unit cell has been reduced.
At present, device development with a design based on the 0.18 μm rule is in progress. However, in a one-transistor, one-capacitor (1T1C) structure such as a DRAM, the area is reduced by devising the channel length L of the transistor. I have. However, shortening the channel length of the transistor has a limit due to a large influence of a short channel effect and the like.

[0006] Therefore, instead of a conventional lateral (horizontal) transistor, a vertical transistor has been proposed in which a transfer transistor is buried vertically in a trench to secure a channel length and improve the degree of integration.

FIG. 15A shows a cross-sectional structure of a lateral trench DRAM in which a conventional lateral transistor and a trench capacitor are combined. FIG. 15 (b)
Shows a vertical trench DRAM cross-sectional structure created by applying a manufacturing process of a lateral trench DRAM.

In the lateral type cell shown in FIG. 15A, a polysilicon electrode 102 in a trench, a diffusion electrode 109 extending from a lower portion thereof, and a dielectric film (non-conductive) inserted between these two electrodes. ) Constitute a trench capacitor. On the other hand, a gate oxide film 110 connected to the word line 103 and a diffusion layer 101 extending horizontally on both sides of the gate oxide film 110 constitute a lateral transistor.
Word line 103 connected to gate oxide film 110 is referred to as a selected word line of the cell. On the other hand, the word line 103 'located above the trench is not connected to the cell shown in FIG. 15A, but is connected to another cell which is alternately arranged with this cell in an adjacent column. Word line 10
3 'is called an unselected word line.

A vertical trench DRAM shown in FIG.
The cell is formed by using the conventional lateral trench DRAM manufacturing process shown in FIG. FIG. 16 shows such a vertical trench D
FIG. ^{2 is} a plan layout diagram of 8F ² generally used in a RAM. Here, F means the minimum line width of the design rule of photolithography, and the layout of 8F ² means that the occupation area of the unit cell is designed to be 4F × 2F.

In FIG. 15B, a gate oxide film 110 extending vertically along the side wall inside the trench, a diffusion strap 112, and
The diffusion region 101 extending horizontally from the upper end of the trench and connected to the bit line contact 106 forms a vertical transistor. GC (gate conductor) polysilicon 102 in contact with gate oxide film 110 in the trench
Are connected to the word line 103. On the other hand, the word line 103 'located outside the trench is not connected to this cell and is a non-selected word line. As shown in FIG. 16, the unselected word 103 'is a selected word line of another cell located at a 1/2 pitch shift along an adjacent bit line.

[0008] By forming the transistor in a trench to be a vertical type, the positional relationship between a selected word line and a non-selected word line of a conventional lateral DRAM cell in a unit cell is reversed.

In the conventional process, an insulating film (oxide film in a trench) 111 for separating a capacitor and a transistor is used.
Is formed, a GC polysilicon 102 is buried, and subsequently, the polysilicon 102 below the non-selected word line 103 ′ and the polysilicon 1 below the selected word line 103 ′ are formed.
02 are simultaneously deposited. Further, a word line material is deposited thereon, and the word line and the polysilicon are simultaneously patterned, thereby forming the vertical trench DR shown in FIG.
AM can be easily created.

[0010]

However, in a trench DRAM formed by a conventional process, the non-selected word line 103 'and the polysilicon layer 102 thereunder are not formed.
Just by separating the thin insulating film, it is in the vicinity of the drain (diffusion layer) 101 which crosses the substrate horizontally and is connected to the bit line contact. Diffusion layer 101 is doped, for example, into n-type, which affects non-selected word line 103 ′ and polysilicon layer 102 thereunder, and has a high possibility of causing parasitic capacitance. Such a parasitic capacitance is not preferable because it causes a malfunction particularly when the transistor has a high frequency.

Therefore, a first object of the present invention is to provide a vertical trench DRAM in which the parasitic capacitance between a word line and a substrate is reduced and the degree of integration is improved.

A second object of the present invention is to provide a method of manufacturing such a vertical trench DRAM.

A third object of the present invention is to improve the degree of integration by eliminating unselected word lines, specifically to realize a 4F ² cell arrangement (where F is the minimum size of photolithography). With the goal.

[0014]

In order to achieve the first object, a vertical trench DRAM according to the present invention has a structure in which a transistor is vertically arranged inside a trench and a non-selected word line of a cell of interest. By inserting an insulating film having a thickness between the substrate and the diffusion conductive region on the substrate surface, the influence of the substrate on unselected word lines is reduced.

Specifically, the semiconductor memory device of the present invention
A transistor having a substrate, a trench formed at a predetermined location in the substrate, a capacitor located at a lower portion of the trench, a gate extending vertically along a trench sidewall above the capacitor inside the trench, and A first word line positioned and connected to the gate of the transistor; and a second word line extending parallel to the first word line. The transistor includes a first diffusion layer extending horizontally from above the vertical gate in the trench and along the substrate outside the trench, and a second diffusion layer connected from below the gate to a capacitor below the trench. Having. As a feature of this semiconductor memory device, an insulating film having a predetermined thickness is provided below the second word line and vertically separates the second word line and the first diffusion region of the transistor.

The semiconductor memory device further includes a bit line located above the first and second word lines, and the first diffusion layer of the transistor passes below the second word line,
Connected to bit line. In this case, since the insulating film having a sufficient thickness is inserted between the second word line and the first diffusion layer, the influence of the substrate (first diffusion layer) on the second word line is reduced. .

In order to achieve the second object of the present invention, there is provided a method of manufacturing the above-mentioned semiconductor memory device. In this method, first, a trench is formed at a predetermined position on a substrate. A capacitor is formed in the lower part of the trench, and a gate oxide film 10 is formed on the inner wall of the trench above the capacitor with the capacitor and the thin oxide film being separated. Further, a buried strap material (for example, polysilicon) is deposited on the inside of the trench above the capacitor and on the substrate. The polysilicon layer is processed such that the deposited buried strap material (polysilicon) protrudes from the opening (ie, upper end) of the trench onto the substrate in a columnar manner.

Next, a diffusion region of the first conductivity type is formed on the surface of the substrate outside the trench, for example, by ion implantation. For example, when the substrate is p-type, an n-type dopant may be implanted, or when the substrate is n-type, a p-type well may be formed first, and then an n-type diffusion region may be formed.

Next, an insulating film covering the diffusion region and having the same height as the surface of the buried strap projecting in a columnar shape is formed. The insulating film is, for example, SiN (silicon nitride film)
It is. After the surface of the insulating film is flattened, word lines are formed on the insulating film at positions corresponding to the lower diffusion layers and on the upper surfaces of the columnar buried straps.

According to such a manufacturing method, the selected word line is directly connected to the gate conductor, and the unselected word line is separated from the diffusion layer on the substrate surface by the insulating layer. This makes it possible to manufacture a vertical transistor semiconductor memory device in which the parasitic capacitance between the unselected word line and the substrate is reduced and the degree of integration is improved.

In order to achieve the third object of the present invention, a semiconductor memory device having a layout in which non-selected word lines are eliminated in each cell is provided.

As a first example of such a semiconductor memory device, a bit line contact is shared between two adjacent cells, and the cross-sectional structure of the cell is adjusted so that the cell arrangement is symmetrical with respect to the bit line. I do.

Specifically, the semiconductor memory device includes a substrate,
First and second cells formed at predetermined positions on a substrate, word lines extending in a first direction above the first and second cells, and above the first and second cells; so,
A bit line extending along a second direction;
And a bit line contact shared by the other cells. Each cell includes a trench, a capacitor located at the bottom of the trench, and a transistor located vertically along the trench sidewall at the top of the capacitor within the trench, the transistor comprising a vertical gate along the trench sidewall,
A drain extending above the gate to the outside of the trench; and a source connected to the capacitor from below the gate.
The gate of the transistor is connected to a word line, and the drain of the transistor is shared by the first and second cells and connected to a bit line contact. 1st and 2nd
Are arranged such that the cross-sectional structure is line-symmetric with respect to the bit line contact via an insulating isolation region (STI) therebetween.

By omitting unselected word lines and sharing bit line contacts between two adjacent cells,
A layout with an occupied area per cell of 4F ² is realized.

As another example of a highly integrated semiconductor device, all cells are arranged so that their cross-sectional structures face the same direction. This is because, when the minimum cell area is set in the above-described symmetric arrangement, two adjacent cells are
An object of the present invention is to provide a layout configuration capable of avoiding a possibility that a source (diffusion region) connecting a transistor and a capacitor of each cell contacts each other. That is, the semiconductor memory device
A substrate, and a plurality of cells formed at predetermined positions on the substrate;
A word line located above the plurality of cells and extending in a first direction; a bit line located above the plurality of cells and extending in a second direction; and a bit line contact corresponding to each of the plurality of cells. Is provided. Each cell includes a trench, a capacitor located at the bottom of the trench, and a transistor located vertically along the trench sidewall at the top of the capacitor within the trench, the transistor comprising a vertical gate along the trench sidewall, It has a drain extending from the upper end of the gate to the outside of the trench, and a source connected to the capacitor from below the gate. The gate of each transistor is connected to a word line, and the drain is connected to a corresponding bit line contact. These cells are arranged such that their sectional configurations all face the same direction.

The first direction (word line) and the second direction (bit line) are orthogonal to each other. In this case, the 4F ² cell arrangement can be relatively easily realized in the rectangular coordinate system, and interference between adjacent cells in the diffusion region connecting the transistor and the capacitor can be prevented, thereby improving the reliability of the semiconductor memory device. can do.

The first direction (word line) and the second direction (bit line) may intersect in an oblique direction that is not orthogonal. By utilizing an oblique direction, it is possible to take the distance between adjacent cells in the cell layout of the same 4F ^2, it is possible to provide a margin between cells.

As another example of a highly integrated semiconductor memory device, a layout is adopted in which active areas of adjacent cells, that is, diffusion regions from the gates of the transistors to the bit line contacts are alternately directed in opposite directions. In this case, the active region preferably extends obliquely at a predetermined angle (for example, 45 °) with respect to the word line. When the layout is such that the bit lines extend obliquely at a predetermined angle with respect to the word lines, the active region of each transistor extends obliquely at a predetermined angle with respect to the bit lines. Thus, even with the same 4F ² cell layout, 1 / co
It is possible to provide a margin for sθ.

As still another configuration example, the layout is such that the active regions of each cell are all arranged in the same direction, and the diffusion region extends at a predetermined angle with respect to the bit line. In this case, the word lines and the bit lines are preferably orthogonal. According to this layout, the active regions are all oriented in the same direction, so that the cells S to separate the cells are separated.
There is an advantage that embedding of a TI (Shallow Trench Isolation) is easy, and that word lines and bit lines can be formed relatively easily in a rectangular coordinate system.

Other features and advantages of the present invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

[0031]

FIG. 1 is a cross-sectional view of a vertical trench DRAM device according to a first embodiment of the present invention. This DRAM device has the following overall configuration:
The configuration of the conventional vertical trench DRAM device is used. However, as a feature of the first embodiment, the lower layer of the non-selected word line 3 ′ is made of, for example, S
By using an insulating layer such as iO2 or SiN, the influence from the diffusion layer of the substrate is reduced.

Specifically, the vertical DRAM includes a capacitor located at the lower part of the trench, a transistor located vertically inside the trench along the trench sidewall above the capacitor, and a gate of the transistor located above the trench. First word line 3 (selected word line) connected to 10
And a second word line (non-selected word line) 3 'extending in parallel with the first word line. The transistor has a gate 10 along the trench sidewall, a first diffusion layer 1 extending horizontally along the substrate 4 outside the trench from above the gate, and a second diffusion layer 1 connected to the capacitor from below the gate.
Diffusion layer 12. On the other hand, the capacitor is composed of a diffusion electrode layer 9 extending from the lower part of the trench, a polysilicon electrode layer 2 buried in the lower part of the trench, and a dielectric film inserted therebetween.

The vertical trench DRAM according to the first embodiment
Is characterized in that the second word line (unselected word line) 3 '
And an insulating layer 13 having a thickness that separates the second word line 3 ′ from the first diffusion layer 1 of the transistor.
The thickness of the insulating layer 13 varies depending on the design rule, but no matter what rule, for example, the n-type first diffusion layer 1 extending to the substrate surface is thick enough not to affect the word line 3 ′. That's it. The first diffusion layer 1 is connected to the bit line contact 6 under the unselected word line 3 ′, and is connected to the bit line 5.

As described above, the lower portion of the non-selected word line 3 'is formed of the insulating layer 13 having a thickness, thereby reducing the influence of the substrate on the non-selected word line 3' connected to the gate of the adjacent cell. be able to. As a result, malfunction of the transistor is also reduced.

FIGS. 2 to 5 show the vertical trench DR shown in FIG.
1 shows a manufacturing process of an AM.

First, as shown in FIG. 2A, a trench 18 is formed in the substrate 4, and a buried diffusion layer 9 is formed by solid phase diffusion. Specifically, a solid-phase diffusion source such as ASSG (arsenic silicate glass) is deposited and diffused by heat treatment.
After the ASSG is peeled off, a dielectric film (not shown) such as an NO film is formed, and polysilicon is embedded.

Next, as shown in FIG. 2B, the collar oxide film 7 is buried by digging down the polysilicon in the trench. The color oxide film on the upper surface of the polysilicon is removed by RIE.

Next, as shown in FIG. 2C, the inside of the trench is further filled with polysilicon 2 again, and the portion of the oxide film not filled with polysilicon is wet-etched using, for example, buffered hydrofluoric acid. To remove.

Next, as shown in FIG. 2D, a silicon nitride film (SiN) is formed on the exposed inner wall of the trench to protect the inner wall of the trench from oxidation or the like.

Next, as shown in FIG. 3A, a buried strap (B
S) Polysilicon 2 is deposited. This polysilicon is
It becomes a diffusion source.

Next, as shown in FIG. 3B, the BS polysilicon 2 is dug to a predetermined depth. The digging is performed by, for example, combining CMP and RIE.

Next, as shown in FIG. 3C, an oxide film 11 is formed on the surface of the polysilicon 2 in the trench.
This oxide film 11 plays a role of separating the capacitor at the bottom of the trench from the transistor at the top. At this time, the diffusion layer 12 is formed in the substrate by thermal diffusion.

Next, as shown in FIG. 3D, the silicon nitride film remaining on the inner wall of the trench above the capacitor is peeled off.
A gate oxide film 10 is formed on the inner wall of the trench. Thereafter, polysilicon 2 for a gate conductor (GC) is deposited inside the trench, and the surface is flattened by CMP or the like. Next, as shown in FIG. 4A, the active region (AA)
Is formed by photolithography and RIE.

Next, as shown in FIG. 4B, a shallow trench for the element isolation region (STI) 8 is formed by RIE, and an oxide is buried. When planarizing the surface of the STI 8 by CMP, the SiN film functions as a stopper.

Next, as shown in FIG.
Is dropped by wet etching to remove SiN.

Next, as shown in FIG. 4D, after forming a gate oxide film, a diffusion region 1 is formed by ion implantation. This gate oxide film is a sacrificial oxide film for ion implantation. In the example of FIG. 4, an n-type channel is formed by forming a p-type well in the substrate and making the diffusion regions 1 and 12 n ⁺ -type. However, the conductivity type may be reversed.

Next, as shown in FIG. 5A, for example, SiN (TEOS) is deposited on the substrate to form an insulating layer separating the word line and the diffusion region. The SiN surface is planarized by CMP using the polysilicon left in a pillar shape above the trench as a stopper.

Next, as shown in FIG. 5B, the material of the word line 3 (for example, WSi: tungsten silicide)
Are deposited, and a SiN film is deposited thereon.

Next, as shown in FIG. 5C, the SiN film and WSi are processed into a pattern of the word line 3 by photolithography and RIE.

Finally, as shown in FIG. 5D, the side wall of the word line 3 is oxidized, and Si is used as a spacer by CVD.
An N film is entirely formed, and the surface of the insulating film 13 is etched by RIE. When the portion between the word lines 3 in the insulating film 13 above the diffusion region 1 is removed from the state of FIG. 5D, the trench DR having the sectional shape shown in FIG.
The AM cell is completed.

According to such a manufacturing method, in each cell, a non-selected word line and a diffusion region running on the substrate surface can be sufficiently separated, and a semiconductor memory device with reduced undesirable parasitic capacitance can be manufactured. it can.

<Second Embodiment> FIG. 6 is a sectional view of a semiconductor memory device according to a second embodiment of the present invention.
Is a planar layout of the semiconductor memory device shown in FIG. In the second embodiment, a bit line contact is shared between two adjacent cells, and the cross-sectional structure of these cells is symmetrical with respect to the bit line contact. General 8F ²
From the cell arrangement (see FIG. 16) to 4F ² .

That is, the semiconductor memory device of the second embodiment includes a substrate 4, first and second cells formed at predetermined positions on the substrate, and a word line 3 extending in a first direction above each cell. And a bit line 5 extending in a second direction above each cell, and a bit line contact 6 shared by the first and second cells. Each cell includes a capacitor located at the bottom of the trench and a transistor located vertically inside the trench along the trench sidewall above the capacitor. The capacitor is polysilicon 2 in the lower part of the trench.
And the lower diffusion layer 9 are upper and lower electrodes, respectively, and have a dielectric layer (not shown) inserted between these electrodes. The transistor has a gate 10 extending vertically along the trench side wall, a drain 10 extending from the upper end of the gate 10 to the outside of the trench, and a source 12 connected to the capacitor from below the gate. Transistor gate 10
Is connected to the word line 3 and the drain 10 is shared between the two cells, and is connected to the shared bit line contact 6 as it is.

As shown in FIG. 6, adjacent two cells have a line symmetrical cross section with respect to the bit line contact 6. Further, by omitting the unselected word lines in each cell, the degree of cell integration can be improved. That is, as shown in the layout of FIG. 7, while the 4F ² of 2F × 2F occupied area of each cell, allowing highly integrated layout 2F ensure the width of the active region (AA).

<Third Embodiment> FIG. 8 shows a sectional shape of a semiconductor memory device according to a third embodiment, and FIGS.
The plane layout is shown. 9 shows a 4F ² cell layout, and FIG. 10 shows a 5F ² layout with a margin.

In the third embodiment, bit line contacts are arranged for each cell in a one-to-one correspondence.
In the sectional structure, they face in the same direction. In the second embodiment, a bit line contact is shared between adjacent cells,
It had a cross-sectional structure of left and right objects. In the structure of the second embodiment, since the buried diffusion layers (sources) 12 face each other, interference may occur between the facing cells, which may affect device operation.

Therefore, as shown in FIG. 8, each cell is made to face the same direction in the cross-sectional shape, so that interference between the cells is prevented. Specifically, the semiconductor memory device of the third embodiment includes a substrate 4, a plurality of cells formed at predetermined positions on the substrate, and a word line 3 located above each cell and extending in a first direction. , A bit line 5 located above each cell and extending in the second direction, and a bit line contact 6 corresponding to each cell. Each cell includes a capacitor located at the bottom of the trench and a transistor located vertically inside the trench along the trench sidewall above the capacitor. The drain 1 of each transistor extends in the same direction and is connected to a corresponding bit line contact 6, and the source 12 is connected to the capacitor in the same direction.

That is, the cells are all arranged in the same direction in the sectional shape.

[0059] Also by this way cells disposed toward the same direction, it is possible cell layout of 4F ² as shown in FIG. Figure 10 remain in the same layout as Figure 9, it is obtained by slightly increased to a 5F ² cell layout cell size. This is because the width of the active region (AA) has a margin and the sectional size of the bit line contact 6 is increased. This is the cell layout of 4F ² in FIG.
This is to prevent the possibility that the substrate (p-well) will float when the buried diffusion layer (source) 12 reaches the STI (element isolation region) 8 by thermal diffusion. The cell layout of 5F ² is 4F ^{2 in} terms of integration.
Although slightly inferior to the layout, the degree of integration is improved in each step as compared with the conventional layout, and a highly reliable semiconductor memory device in which floating is prevented can be provided.

<Fourth Embodiment> FIGS. 11 and 12 show a plan layout and a sectional shape of a semiconductor memory device according to a fourth embodiment of the present invention. FIG. 11 shows 4F
FIG. 12A shows a ^2- cell layout, and FIG. 12A shows a 5-F ^2- cell layout.

In the layout of FIG. 11, the active region of the transistor of each cell is arranged obliquely at an angle of 45 ° with respect to the word line, and the active region (A
The direction in which A) extends is alternately set to the opposite direction. This is because, in the 4F ² cell layout of FIG. 9 in the third embodiment, the length of the active region becomes the minimum line width F, the margin for alignment and the bit line contact, the buried diffusion layer (source)
Considering the floating of the substrate by the method of FIG.
The way, a layout that better to slightly spread in the 5F ² cell layout intervals of the word line is in view of the point that preferred from the viewpoint of operation. That is, the intention is to increase the length of the active region by obliquely keeping the cell layout at 4F ² , thereby improving the reliability of the operation of the transistor.

The semiconductor memory device according to the fourth embodiment includes a substrate, a plurality of cells arranged at predetermined positions on the substrate, a word line 33 extending in a first direction above the cells, and a second line above the cells. , And a bit line contact 26 corresponding to each cell. Each cell includes a capacitor located at the bottom of the trench and a transistor located vertically inside the trench along the trench sidewall above the capacitor.

The active area (AA) of the transistor extending from the trench to the bit line contact 26 is shown in FIG.
In the 4F ² layout, since an angle of 45 ° to the word lines, when the F of the minimum line width of the word line width and the word line spacing, the length of the F / cos45 ° (1.4F) It can give room.

[0064] FIG. 12 (a) shows an example in which an extension of the arrangement of Figure 11 to 5F ² layout. In this layout, in order to secure a sufficient active region, the word line width is increased to 1.5F while the word line interval is maintained at F, and the active region is 61.3 ° (adjacent to the word line). The cells are arranged at an angle of 38.7 °. Thus, the length of the active region can be given a margin up to 1.9F.

FIG. 12B is a sectional view taken along the line CC ′ in FIG.
It is sectional drawing. Word line 33 and diffusion region (drain) 21 extend obliquely to corresponding bit line contact 26. 1T1C in which a capacitor and a vertical transistor are arranged in a trench as in the first to third embodiments.
Is realized in a fine layout.

<Fifth Embodiment> FIGS. 13 and 14 show a plan layout and a sectional shape of a semiconductor memory device according to a fifth embodiment of the present invention. FIG. 13 shows 4F
FIG. 14A shows a ^2- cell layout, and FIG. 14A shows a 5-F ^2- cell layout.

In the layout shown in FIG. 13, the active regions of the transistors of each cell are arranged obliquely at an angle of 45 ° with respect to the word line, and the active regions (AA) extend in the same direction in all the cells. In this layout, a sufficient interval between the active regions of each cell can be ensured, so that the STI (element isolation region) 48 can be relatively easily buried. Further, since the bit lines are orthogonal to the word lines, it is relatively easy to form the semiconductor memory device itself in an orthogonal coordinate system.

Specifically, the semiconductor memory device of the fifth embodiment includes a substrate, a plurality of cells arranged at predetermined positions on the substrate, a word line 43 extending above the cells in a first direction,
It has a bit line 45 extending in a second direction above the cell, and a bit line contact 46 corresponding to each cell. Each cell includes a capacitor located at the bottom of the trench and a transistor located vertically inside the trench along the trench sidewall above the capacitor.

The active regions (AA) of the transistors extending from the trench to the bit line contact 26 are all oriented in the same direction and extend obliquely at a predetermined angle to the bit line. Both the bit line and the word line have the minimum line width F, and are orthogonal to each other.

In the 4F ² layout of FIG. 13, the active region AA forms an angle of 45 ° with the bit line, so that the length of the active region can be given a margin up to 1.4F.

[0071] FIG. 14 (a) shows an example in which an extension of the arrangement of Figure 11 to 5F ² layout. In the layout of FIG. 14A, in order to secure a more sufficient active region, the word line width is increased to 1.5F while the word line interval is maintained at F, and the active regions of all cells are changed to bit lines. 3 for
It is arranged diagonally at an angle of 8.7 °. Thus, the length of the active region can be given a margin up to 1.9F.

In the fifth embodiment, the 4F ² layout of the rectangular coordinate system is maintained, and the active regions are arranged obliquely with respect to the bit lines, so that the active regions are sufficiently secured. At the same time, by arranging the active regions of each cell in the same direction, the step of embedding the element isolation region can be facilitated.

[0073]

As described above, according to the present invention, the structure of the conventional vertical trench DRAM is utilized as it is,
A semiconductor memory device in which the influence of the substrate on the unselected word lines is eliminated and the parasitic capacitance is reduced is provided.

A method for efficiently manufacturing such a semiconductor memory device is provided.

Further, a non-selected word line is omitted from the conventional vertical trench DRAM, and a highly integrated semiconductor memory device with a fine layout is provided.

[Brief description of the drawings]

FIG. 1 is a vertical trench DR according to a first embodiment of the present invention.
It is sectional drawing of an AM cell.

FIG. 2 is a view showing a manufacturing process of the vertical trench DRAM cell shown in FIG. 1;

FIG. 3 is a diagram showing a manufacturing process of the vertical trench DRAM cell shown in FIG. 1 and a diagram showing a process following FIG. 2;

FIG. 4 is a view showing a manufacturing process of the vertical trench DRAM cell shown in FIG. 1 and showing a step following FIG. 3;

FIG. 5 is a view showing a manufacturing step of the vertical trench DRAM cell shown in FIG. 1, and a view showing a step following FIG. 4;

FIG. 6 is a cross-sectional view of a symmetrically arranged vertical trench DRAM cell according to a second embodiment of the present invention.

FIG. 7 is a plan layout diagram of the vertical trench TMR element shown in FIG. 6;

FIG. 8 is a sectional view of a vertical trench DRAM cell arranged in the same direction according to a third embodiment of the present invention.

FIG. 9 is a 4F ² plane layout diagram of the vertical trench DRAM shown in FIG. 8;

FIG. 10 is a 5F ² plane layout diagram of the vertical trench DRAM shown in FIG. 8;

FIG. 11 is a 4F ² plane layout diagram of a slant-wiring vertical trench DRAM cell according to a fourth embodiment of the present invention.

12 is an oblique wiring vertical trench DRAM shown in FIG. 11;
5F ^{2 is a} plan layout view and a CC ′ cross-sectional view thereof.

FIG. 13 shows 4F ^{2 of} a vertical trench DRAM in which active regions are arranged obliquely by orthogonal wiring according to a fifth embodiment of the present invention.
It is a plane layout view.

FIG. 14 shows 5F ^{2 of the} vertical trench DRAM shown in FIG. 13;
It is a plane layout diagram and its DD 'sectional drawing.

FIG. 15 is a cross-sectional view of a conventional lateral trench DRAM and a conventional vertical trench DRAM in which the conventional lateral DRAM is arranged as it is vertically.

FIG. 16 is a diagram showing a general planar layout of a conventional vertical trench DRAM.

[Explanation of symbols]

 1, 21, 41 First diffusion region (drain) 2 Polysilicon 3, 33, 43 Word line 4 Substrate 5, 25, 45 Bit line 6, 26, 46 Bit line contact 7, 27, 47 Trench collar sidewall oxide film 8, 28, 48 STI 9, 29, 49 Diffusion plate 10, Gate oxide film 11, 31, 51 Oxide film in trench 12, 32, 52 Second diffusion region (source) 13 Insulation film

Claims (11)

[Claims] 1. A substrate, a trench formed at a predetermined position in the substrate, a capacitor located at a lower portion of the trench, and extending vertically inside the trench along a trench sidewall above the capacitor. A transistor having a gate, a first word line located above the trench and connected to a gate of the transistor, and a second word line extending in parallel with the first word line; Has a first diffusion layer extending in a horizontal direction along the substrate outside the trench from above the gate, and a second diffusion layer connected to the capacitor from below the gate; An insulating film having a predetermined thickness, which is located below the word line and vertically separates the second word line and the first diffusion region of the transistor, is further provided. Semiconductor storage device. 2. The semiconductor device according to claim 1, further comprising a bit line located above the first and second word lines, wherein a first diffusion layer of the transistor passes below the second word line and passes through the bit line. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to the semiconductor memory device. 3. A substrate, first and second cells formed at predetermined positions on the substrate, and word lines extending in a first direction above the first and second cells. A bit line extending along a second direction above the first and second cells; and a bit line contact shared by the first and second cells, wherein each of the cells includes a trench. A capacitor located in a lower part of the trench; a gate extending vertically along a trench sidewall above the capacitor inside the trench; a drain extending outside the trench above the gate; and a capacitor extending from below the gate. A transistor having a source connected to the transistor, a gate of the transistor connected to the word line, and a drain of the transistor connected to the first and second cells. And the first and second cells are arranged so that their cross-sectional configurations are line-symmetric with respect to the bit line contacts. . 4. A substrate, a plurality of cells formed at predetermined positions on the substrate, a word line located above the plurality of cells and extending in a first direction, and above the plurality of cells. A bit line extending in a second direction, a bit line contact corresponding to each of the plurality of cells, and an insulating isolation region separating an active region of each of the cells.
Each of the cells, a trench, a capacitor located at the lower portion of the trench, a gate extending vertically along a trench sidewall above the capacitor inside the trench, and a drain extending outside the trench above the gate. A transistor having a source connected to the capacitor from below the gate, wherein a gate of each transistor is connected to the word line; a drain of each transistor is connected to a corresponding bit line contact; A semiconductor memory device, wherein the cells are arranged so that all of the cross-sectional structures face the same direction with the insulating isolation region interposed therebetween. 5. The semiconductor memory device according to claim 4, wherein said first direction and said second direction are directions orthogonal to each other. 6. The semiconductor memory device according to claim 4, wherein said first direction and said second direction intersect in an oblique direction that is not orthogonal. 7. A substrate, a plurality of cells disposed at predetermined positions on the substrate, a word line extending in a first direction above the cells, and extending in a second direction above the cells. A bit line; and a bit line contact corresponding to each of the cells, wherein each of the cells includes a trench, a capacitor located at a lower portion of the trench, and a trench inside the trench and along a trench sidewall above the capacitor. A transistor having a vertically extending gate, a first diffusion region extending outside the trench above the gate and connecting to the bit line contact, and a second diffusion region connecting to the capacitor from below the gate; Wherein the active region of the transistor extending from the trench to the bit line contact extends alternately in opposite directions in adjacent cells. The semiconductor memory device according to claim. 8. The semiconductor memory device according to claim 7, wherein said active region extends obliquely at a predetermined angle with respect to said word line. 9. The semiconductor memory device according to claim 7, wherein said second direction is an oblique angle that is not orthogonal to said first direction. 10. A substrate, a plurality of cells arranged at predetermined positions on the substrate, a word line extending in a first direction above the cells, and extending in a second direction above the cells. A bit line; and a bit line contact corresponding to each of the cells, wherein each of the cells includes a trench, a capacitor located at a lower portion of the trench, and a trench inside the trench and along a trench sidewall above the capacitor. A transistor having a vertically extending gate, a first diffusion region extending outside the trench from above the gate and connecting to the bit line contact, and a second diffusion region connecting to the capacitor from below the gate and Wherein the active region of the transistor extending from the trench to the bit line contact extends in the same direction in all cells, and The semiconductor memory device characterized by obliquely extending at an angle to the bit lines. 11. A step of forming a trench at a predetermined position on a substrate, a step of forming a capacitor at a lower portion of the trench, a step of forming a gate oxide film 10 on an inner wall of the trench above the capacitor, Forming a material for the buried strap inside the upper trench and on the substrate; processing the material for the buried strap such that the buried strap protrudes from the upper end of the trench onto the substrate in a columnar manner; Forming a diffusion region of a first conductivity type on a surface of the substrate outside the trench; forming an insulating film covering the diffusion region and corresponding to a height of a surface of the buried strap protruding in a columnar shape; Word lines are formed on the insulating film above the diffusion layer and on the upper surface of the columnar buried strap. Method of manufacturing a semiconductor memory device including the step.