JP2002197887A - Nonvolatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compensate data held in a memory cell without rewriting data constantly, in a ferroelectric memory device using ferroelectric substance for a capacitor of a memory cell. SOLUTION: For example, data of a PF cell 21 having an electrical characteristic being almost same as that of a memory cell MC is read by a data compensating system control circuit 13 in data compensation operation. And it is compared with a reference potential adjusted so that data of the PF cell 21 is made defective earlier than that of the memory cell MC by a PF cell data decision circuit 14. Consequently, when deterioration of data of the PF cell 21 is decided, deterioration of data of the memory cell MC is predicted, and data is rewritten in the memory cell MC by a dara rewriting control circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile memory, and more particularly to a ferroelectric memory device using a ferroelectric for a capacitor of a memory cell.

[0002]

2. Description of the Related Art In recent years, a ferroelectric memory device which is nonvolatile and can be randomly accessed is 1 × 10 ⁸
Development is being pursued with high functionality, such as compensating for the number of data rewrites more than once.

However, during the trial manufacture and study, the data retention characteristic of the write data may deteriorate significantly with the lapse of the data retention time, mainly due to imprint or depolarization. I'm getting it. Such phenomena are expected to be improved by future prototypes and studies, but it is expected that it will become more and more difficult to maintain data retention characteristics as the device configuration becomes finer. .

A ferroelectric memory device using a ferroelectric for a capacitor has a relatively short history as a device.
There is a high possibility that unknown problems are latent in the data retention characteristics. On the other hand, when a device is put on the market, a capability that can be said to be an over-spec for maintaining data retention characteristics as a nonvolatile memory is expected.

[0005] However, as far as the reports at the academic society level or the prototype / development stage are concerned, there is no novel method for suppressing the deterioration of the retained data (write data), especially for depolarization. For that reason, ferroelectric memory devices require a great deal of time from development to commercialization,
There is a trade-off between early commercialization and poor reliability,
It is not easy to commercialize. Even if it can be commercialized at an early stage, the current situation is that the data retention characteristics have not been sufficiently compensated since the market launch.

[0006] On the other hand, a refresh operation in a DRAM is known as one of the methods for suppressing deterioration of held data. However, the normal refresh operation is performed regularly (regularly) irrespective of the degree of deterioration of the held data, and thus, there is a concern about fatigue of the memory cell. Therefore, it is not a very preferable method for a ferroelectric memory device having a short history.

[0007]

As described above, in the prior art, although there is a great expectation for higher functionality in terms of compensation for the number of times of data rewriting and data retention characteristics, a novel method for suppressing deterioration of retained data. There was a problem that was not found.

Therefore, the present invention can suppress deterioration of retained data while preventing fatigue of a storage element due to rewriting of data, and can prevent loss of retained data due to a change over time in data retention characteristics. It is an object of the present invention to provide a nonvolatile memory.

[0009]

In order to achieve the above object, in a nonvolatile memory according to the present invention, a storage element having a ferroelectric capacitor for holding data, and a storage element having the ferroelectric capacitor. A monitor element for monitoring the deterioration of the held data, and by rewriting the data when the deterioration of the data is monitored by the monitor element, the data is held in the storage element. The data is compensated for.

Further, in the nonvolatile memory according to the present invention, a first storage element having a ferroelectric capacitor for holding the first data and a ferroelectric memory for holding the second data are provided. A second storage element having a dielectric capacitor, and the first data stored in the first storage element, based on the second data stored in the second storage element. A determination circuit for predicting deterioration; and a control circuit for instructing a data writing circuit to rewrite the first data held in the first storage element in accordance with a result of the determination circuit. It is characterized by having done.

According to the nonvolatile memory of the present invention, it is possible to predict the deterioration of the held data. This makes it possible to rewrite data only when the deterioration of the held data is predicted.

[0012]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 schematically shows a circuit configuration of a ferroelectric memory device according to a first embodiment of the present invention.

That is, in the ferroelectric memory device, for example, the memory cell region 11, PF (Pass / Fai
l) cell area 12, data compensation system control circuit 13,
It is configured to include a PF cell data determination circuit 14, a data write control circuit 15, a memory control processor 16, and the like.

In the memory cell region 11, a plurality of (here, two) memory cells (first storage elements) MC are provided at intersections of the bit lines BL and the word lines WL, respectively, and are arranged in a matrix. It is configured to be.
Each memory cell MC holds one transistor T for a transfer gate and "1" and "0" of data (first data) in correspondence with binary charges of high potential / low potential. And one ferroelectric capacitor C (so-called 1T1C cell).

In the memory cell area 11, a sense amplifier (S / A) 1 for amplifying data read from each memory cell MC via the bit line BL is provided.
1a is provided.

For example, the PF cell region 12 is provided adjacent to the memory cell region 11 and in the column direction, and is connected to each bit line (data line) BL and word line (row direction selection line) WL. At the intersections, PF cells (second storage elements) 21 as deterioration detection cells are arranged.

Each PF cell 21 is for monitoring the deterioration of data held in the memory cells MC in the row direction, which is commonly connected to the bit line BL. For example, one PF cell 21 for a transfer gate is used. Transistor T
And one ferroelectric capacitor (monitor element) C for holding "1" and "0" of data (second data) in correspondence with binary charges of high potential / low potential. (A so-called 1T1C cell).

In this case, each PF cell 21 is formed at the same time by the same process using the same standard (for example, dimensions and area) and the same material as that of the memory cell MC, and thus is substantially equivalent to the memory cell MC. (The area of the capacitor, the charge retention ability, and the like).

The data compensation system control circuit 13 includes:
The data held in the PF cell 21 is used to predict the deterioration of the data held in the memory cell MC, and at the time of a data compensation operation for compensating the deterioration, based on an instruction from the memory control processor 16. For controlling the main components, for example, the data held in the PF cell 21 is read out to the sense amplifier 11a via a bit line BL connected to the PF cell 21 or the PF cell data determination circuit 14 Is output to the data write control circuit 15 in accordance with the result of the determination.

The data compensation system control circuit 1
3 outputs a signal indicating the completion of the data compensating operation to the memory control processor 16.

The PF cell data determination circuit 14 compares the data supplied through the sense amplifier 11a and held in the PF cell 21 with reference potentials (reference potentials) PFvRef-H and PFvRef-L. ,
From the magnitude relation, the deterioration of the data held in the memory cell MC is indirectly predicted.

The reference potential PFvRef-H,
As the PFvRef-L, the level at which the data holding capacity of the PF cell 21 is evaluated to be lower than that of the memory cell MC, that is, the deterioration of the data held at the memory cell MC indicates the loss of data ( Fail)
Before the data reaches the level at which the data held in the PF cell 21 is already determined to be defective (for example, a reference potential (reference potential) compared when reading the data held in the memory cell MC). potential)
(The level difference from vRef is 0.1 V or more).

That is, assuming that the reference potential vRef to be compared when reading the data held in the memory cell MC is 1.5 V, the data to be compared is “1 (binary high-potential charge)”. The reference potential PFvRef-H is set to about 1.6V, and the reference potential PFvRef-L when the data to be compared is "0 (binary low potential charge)" is set to about 1.4V.

The reference potential PFvRef-
H and PFvRef-L may be either a method of taking in from outside the ferroelectric memory device or a method of generating inside the device.

The data write control circuit 15 normally writes data to the memory cell MC. During the data compensation operation, the data write control circuit 15 operates in accordance with the result of the decision made by the PF cell data decision circuit 14. Data is rewritten to the memory cell MC and the PF cell 21 in accordance with an instruction output from the control circuit 13.

The data write control circuit 15
Is configured to notify the data compensation system control circuit 13 when the data rewriting is completed.

The memory control processor 16 controls the overall operation of the ferroelectric memory device.
In the data compensation operation, a signal for permitting the data compensation operation is output to the data compensation system control circuit 13 or a signal indicating the end of the data compensation operation is received from the data compensation system control circuit 13. It has become.

The memory control processor 16 waits after outputting the signal for permitting the data compensation operation (Wa).
It returns to the standby state by receiving a signal indicating the end of the data compensation operation.

Next, a description will be given of a flow of a process related to a data compensation operation in the above configuration.

As shown in FIG. 2, it is assumed that the power supply of the ferroelectric memory device is turned on. Then, first, a signal (for example, a rise detection signal of the internal potential of the device) for permitting the data compensation operation is output from the memory control processor 16 to the data compensation system control circuit 13 and immediately held in the PF cell 21. Using the stored data, a deterioration of data held in the memory cell MC is predicted, and a data compensation operation for compensating the deterioration is performed.

That is, the data compensation system control circuit 1
By the control of 3, the word line WL in the PF cell region 12 is released at an arbitrary time, and the data held in the PF cell 21 is read out to the bit line BL. The read data is amplified by the sense amplifier 11a and sent to the PF cell data determination circuit 14. The data sent to the PF cell data determination circuit 14 is compared with the reference potentials PFvRef-H and PFvRef-L, and the result is compared with the data compensation system control circuit 13.
Sent to

Here, if the data is determined to be Fail, the data compensation system control circuit 13 outputs a rewrite instruction to the data write control circuit 15. As a result, the data write control circuit 15 rewrites data to the PF cell 21 (in this case, writes a reset value) and rewrites data to the memory cell MC.

In the writing of the reset value, in order to predict the deterioration of the "1" data, the "1" data is predicted in the PF cell 21 having the "1" data as the expected value. In order to perform P
“0” data is written in the F cell 21.

In rewriting data to the memory cells MC, all memory cells MC sharing the word line WL are rewritten by accessing an arbitrary memory cell MC in the direction of the bit line BL.

Thereafter, the data compensation system control circuit 13
As a result, a signal indicating that normal operation can be performed upon completion of the data compensation operation is output to memory control processor 16.

On the other hand, when the data held in the PF cell 21 is determined to be Pass in the PF cell data determination circuit 14, the signal indicating that the normal operation is possible is sent from the data compensation system control circuit 13 to the memory control. Output to the processor 16.

On the other hand, the memory control processor 1
6 receives a signal indicating that normal operation is possible from the data compensation system control circuit 13 and returns from the standby state to a state where normal operation is possible.

Then, after executing the normal operation as the ferroelectric memory device, the power is turned off.

As described above, the reference potential P of the PF cell 21 having almost the same electrical characteristics as that of the memory cell MC.
FvRef-H and PFvRef-L are transferred to the memory cell MC
The data in the PF cell 21 is adjusted so that it becomes defective earlier than the data in the PF cell 21, and the margin for passing the data in the PF cell 21 is reduced. , The data in the memory cell MC can be compensated before the data in the memory cell MC is destroyed or lost.

Normally, in the case of a ferroelectric memory device, the data read operation is a data destructive read method, and after the data read, the data is always rewritten or the data read operation includes a rewrite operation. ing.

Therefore, taking advantage of this fact, the data is read out in substantially the same operation as the normal data readout.
By writing the data amplified by the sense amplifier directly to the memory cells, the data rewriting operation can be easily realized.

For example, in the case of the folded bit line method, when a rewrite operation is performed on all the memory cells of one column connected to an arbitrary bit line in the bit line direction, an arbitrary bit line can be rewritten. Data is rewritten to the memory cell having the word line and all the memory cells sharing the word line with the memory cell.

In the above description, the case where the data compensating operation is performed when the power of the ferroelectric memory device is turned on has been described. However, the present invention is not limited to this. For example, as shown in FIG. Alternatively, the data compensation operation may be performed after the normal operation of the memory device is completed.

That is, it is assumed that the power of the ferroelectric memory device is turned on. Then, first, the normal operation of the memory device is performed. When the normal operation is completed, a signal for permitting the data compensation operation is output from the memory control processor 16 to the data compensation system control circuit 13.

Thus, as described above, after the data compensating operation is performed in the same manner, the power is turned off.

As described above, even when the data compensating operation is performed after the normal operation of the ferroelectric memory device is completed, the same effect as when the data compensating operation is performed before the normal operation is performed. Is obtained.

In any case, the access to the PF cell may be performed at an arbitrary time according to the capacity of the memory cell.

In the first embodiment, the PF
The case where the cell 21 is formed with substantially the same electrical characteristics as the memory cell MC has been described. However, the present invention is not limited to this. For example, the PF cell 21 may be formed with a different electrical characteristic from the memory cell MC. By doing so, it can be similarly implemented.

(Second Embodiment) In the configuration shown in FIG. 1, for example, each PF cell 21 is
Using the same material as C and according to different standards, its electrical characteristics (capacitor area, charge retention ability, etc.)
Is formed to be several percent smaller than that of the memory cell MC.

In this case, regardless of the reference potential, P
The data of the F cell 21 can be set so as to be more likely to become defective earlier than the data of the memory cell MC. That is, by using the same reference potential as that of the memory cell MC, It is possible to determine the deterioration of the data (the held data amount is small).

For example, a reference potential v to be compared when reading data held in memory cell MC is read.
Assuming that Ref is 1.5 V, the reference potential PFvRef-H for "1" data and the reference potential PFvRef-L for "0" data are each set to about 1.5 V.

As described above, when the electric characteristics of the PF cell are smaller than those of the memory cell, generally,
Since the F cell causes data deterioration earlier than the memory cell, by setting the same reference potential, the data compensation operation can be realized in substantially the same manner as in the first embodiment. .

However, when the data holding characteristic is not affected by the area of the capacitor or the magnitude of the charge holding ability, for example, when the data holding characteristic is large even if the area or the charge holding ability of the capacitor is small, Adjust the reference potential appropriately to make PF
The same can be realized by setting so that the cell data is more likely to be defective.

Third Embodiment In the configuration shown in FIG. 1, for example, each PF cell 21 is
Using the same material as C and according to different standards, its electrical characteristics (capacitor area, charge retention ability, etc.)
Is formed to be several percent larger than that of the memory cell MC.

In this case, the PF cell 21 is set by setting the reference potential so that the data in the PF cell 21 is more likely to become defective earlier than the memory cell MC.
Can be determined whether the data has deteriorated.

For example, the reference potential v to be compared when reading data held in the memory cell MC is read.
Assuming that Ref is 1.5 V, the reference potential PFvRef-H in the case of “1” data is about 1.8 V,
Reference potential PFvRef- in the case of "0" data
L is set to about 1.2 V, respectively.

As described above, when the electric characteristic of the PF cell is larger than that of the memory cell, the reference potential is largely changed and set, so that it is almost the same as that of the first embodiment. Thus, a data compensation operation can be realized.

In particular, by making use of the fact that the data in the PF cell is less likely to be defective than the data in the memory cell, the setting of the reference potential can be largely varied (set with a wider reference potential width). Therefore, it is effective when it is difficult to finely adjust the reference potential with high accuracy, and the circuit design becomes easier.

Here, the PF cell can be arranged by providing a dedicated area, instead of being arranged close to the memory cell area. If the size of the PF cell is different from that of the memory cell, it is more likely that a dedicated area is provided and arranged, resulting in a process problem (for example, a shape abnormality due to a continuous identical pattern and a special pattern). Can be reduced.

On the other hand, when the size of the PF cell is the same as that of the memory cell (the same standard), it is more convenient to arrange the PF cell close to the memory cell area so that the PF cell can be efficiently arranged. .

In particular, when the PF cells are arranged close to the memory cell area, for example, as shown in FIG. 1, when the PF cells are arranged in the word line direction (column direction), the PF cells are arranged in the bit line direction. It is also possible to arrange a plurality of PF cells.

(Fourth Embodiment) FIG. 4 shows a PF of a ferroelectric memory device according to a fourth embodiment of the present invention.
13 shows another example of a cell arrangement. Here,
The case where a plurality of PF cells are arranged in the bit line direction when the PF cells are arranged in the word line direction will be described.

In this case, an arbitrary number of word lines WL of PF cells are provided, and PF cells 21 are arranged at intersections of each word line WL and each bit line BL. And P of each column
The F cell 21 is rotated on a word line WL basis, for example, according to the number of accesses.

For example, the cell column 21a is selected for the even-numbered "0" data access, the cell column 21b is selected for the even-numbered "1" data access, and the odd-numbered "0" data access is performed. Then, the cell column 21c is selected, and in the odd-numbered access of "1" data, the cell column 21d is selected, and the above-described data compensation operation is performed.

Thus, when the word line WL of the PF cell 21 is set to 1, every time the data compensation operation is performed, the data of all the PF cells 21 connected to the word line WL are read / rewritten. Thus, it is possible to prevent the data retention time in the same PF cell 21 from being shortened.

As a result, the data retention time in the same PF cell 21 can be prevented from greatly deviating from the data retention time in the memory cell MC. It can be implemented using data of the PF cell in a state closer to the data of the PF cell.

When the PF cells are arranged close to the memory cell area, for example, the PF cells can be arranged in the bit line (row direction).

(Fifth Embodiment) FIG. 5 shows an example in which a PF cell is arranged in a row direction of a memory cell in a ferroelectric memory device according to a fifth embodiment of the present invention. Things.

In this case, PF cell region 12 is provided, for example, adjacent to memory cell region 11 and provided in the row direction, and PF cells 21 are arranged at intersections of bit lines BL and word lines WL, respectively. It is configured as follows.

In the PF cell region 12, a sense amplifier 12a for amplifying data from each PF cell 21 read via the bit line BL is provided.

As described above, when the PF cell region 12 is arranged in the row direction of the memory cell region 11, substantially the same as in the first to third embodiments described above,
It is possible to perform a data compensation operation.

(Sixth Embodiment) FIG. 6 shows another example in which the PF cells are arranged in the row direction of the memory cells in the ferroelectric memory device according to the sixth embodiment of the present invention. It is shown.

In the data compensation operation, any word line WL
Increases, the data is rewritten to all the memory cells MC in the word line WL direction. Therefore, the word line W of the memory cell MC is
L and the word line WL of the PF cell 21 are shared, and the PF cell 21 is arranged in the row direction.
1 every time all memory cells MC are accessed.
Is rewritten, and as a result, the fatigue of the memory cell MC is accelerated.

In order to avoid this, if the PF cells are arranged in the row direction of the memory cells, for example, the PF cells 21 and the memory cells M sharing the same word line WL may be used.
C and a gate (φT) in the middle of the word line WL.
Is provided. When reading data from the PF cell 21, the gate is closed, and when accessing the memory cell MC, the gate is opened.
Similarly, the data is rewritten.

By doing so, the data retention time of the PF cell 21 and the memory cell MC can be kept the same, and the deterioration of the data of the memory cell MC can be predicted more accurately.

In this case, every time the data compensation operation is performed, all the PF cells 21 connected to the word line WL
Is read / rewritten, for example, as shown in FIG. 6, one or more arbitrary number of cell columns 21a, 21b, 21c, 21d in the row direction.
And a number of PF cell select gates SG corresponding to the number of PF cells 21 in each column.

Then, the PF cell select gate S
G is controlled by the PF cell selector CS, respectively.
Each time the data compensation operation is performed, each cell column 21a, 2
1b, 21c and 21d are rotated.

For example, the cell column 21a is selected in the even-numbered "0" data access, the cell column 21b is selected in the even-numbered "1" data access, and the odd "0" data access is performed. Then, the cell column 21c is selected, and in the odd-numbered access of "1" data, the cell column 21d is selected, and the above-described data compensation operation is performed.

In this case, it is possible to predict the deterioration of the data of the memory cell MC by using the data of the PF cell which is closer to the data of the memory cell MC.

FIG. 7 shows a configuration example of the PF cell selector CS.

The PF cell selector CS has, for example, two PF cell access counter capacitors PFC made of ferroelectric capacitors.

For example, when the data compensation operation is performed according to the flowchart shown in FIG.
The F cell selector CS receives the PF cell / address drive select signal “L” from the data compensation system control circuit 13 at an arbitrary time after the power of the ferroelectric memory device is turned on. Read the potential (fast signal) of the access counter capacitor PFC by 2T2C operation.

After the read potential is amplified by the sense amplifier S / A, the amplified potential is
Apply to F cell / select gate SG.

As a result, either the cell row for the even-numbered access or the cell row for the odd-numbered access is selected, and the above-mentioned PF cell 21 of the selected cell row is used. A data compensation operation is performed.

Upon completion of a series of data compensating operations, PF cell address drive select signal (data rewrite signal) “H” from data compensating system control circuit 13 is received.
S is PF cell access counter capacitor PF
A potential obtained by inverting the first signal is written in C.

As described above, by rewriting the potential of the PF cell access counter capacitor PFC for each data compensation operation, a cell column different from the cell column selected this time is selected at the next data compensation operation. Will be.

The PF cell selector CS is not limited to a configuration using two PF cell access counter capacitors PFC. For example, the PF cell selector CS depends on the charge holding ability of the capacitor of the memory cell MC.
It can be easily changed.

It is not necessary to form the PF cell access counter capacitor PFC using a ferroelectric capacitor. In particular, when the PF cell access counter capacitor PFC is formed using a ferroelectric capacitor, it cannot withstand rewriting for each data compensation operation. To the extent possible, it is necessary to devise ways to increase the data retention capability and data degradation resistance, etc., compared to the capacitor of the memory cell.

(Seventh Embodiment) FIG. 8 shows a configuration example of a ferroelectric memory device according to a seventh embodiment of the present invention. Here, a so-called word line type PF cell system in which the deterioration of data in a memory cell is predicted from the history of increasing the potential of the word line at the time of accessing the memory cell will be described.

In the case of this method, the PF cells 21 are connected to the word lines WL used for the transfer gates (selection transistors) of the memory cells MC, respectively.
The configuration is such that the L potential is written to the PF cell 21.

Further, a gate φT is provided between the word line WL and the PF cell 21, and the gate φT is closed when reading data from the PF cell 21 during the data compensation operation. .

Further, a PF cell / bit line connection gate PF-G is provided between the word line WL and the PF cell / data bit line PF-BL.

Ref-BL is a bit line for a reference potential. When a ferroelectric capacitor is used for the PF cell 21, the following reference potential is used.

For example, when the electrical characteristics of PF cell 21 are smaller than that of memory cell MC, a potential equal to or higher than a reference potential compared when reading data held in memory cell MC is read. But PF
It is used as a reference potential when comparing data in the cell 21.

When the electrical characteristics of the PF cell 21 are equal to those of the memory cell MC, the reference potentials compared when reading data held in the memory cell MC are "1" and "0". An arbitrary potential at which both data are likely to be defective is used as a reference potential when comparing data of the PF cell 21.

When the electric characteristics of the PF cell 21 are larger than those of the memory cell MC, the reference potentials when the electric characteristics of the PF cell 21 are equal to those of the memory cell MC are "1" and "1". An arbitrary potential in which both 0 ″ data are likely to be defective is used as a reference potential when comparing data in the PF cell 21.

Here, when the transfer gate of memory cell MC is set to a high potential of, for example, 4.2 V,
In a ferroelectric memory device capable of writing data to a capacitor of a memory cell MC, when data is written to an arbitrary memory cell MC, the data is transferred to a PF cell 21 sharing a word line WL with the arbitrary memory cell MC. "1" data is written.

That is, the word line WL of the memory cell MC is
If the data of the PF cell 21 attached to "1" is "1", it means that the data has been accessed recently and the data is "0" or "Fail".
In the case of, there is no evidence of access, that is,
This means that the data of the memory cell MC may have been degraded after a long time since the data was not written or after the data was written.

Therefore, the data of the memory cell MC is compensated by rewriting the data in the memory cell MC other than the data "1" in the PF cell 21 which may have deteriorated data. It is possible to do.

Since the data read operation of the PF cell 21 using the ferroelectric capacitor is a data destruction read method, if only one PF cell 21 is connected to one word line WL, the data of the PF cell 21 is read. At this time, the data is rewritten even if the PF cells 21 of all the word lines WL are Pass.

For example, PF cell 2 previously accessed
When 1 is Pass, rewriting of data to the PF cell 21 is performed, so that it becomes impossible to predict data of the memory cell MC that was not accessed last time.

In order to avoid this, 2 word lines WL
One or more PF cells 21 are connected, and switching is performed each time the PF cells 21 are accessed by a PF cell access counter.

As described above, two or more PF cells 21 are
By switching by the PF cell access counter, the data of the PF cell 21 not accessed last time can be read out while the PF cell 21 accessed last time remains unchanged.
Deterioration can be predicted using the data of the PF cell 21 in a state closer to the data of C.

A number of PF cells 21 are connected to one word line WL, and an access counter is used, for example, every time the power of a memory device is turned on / off.
If the configuration is such that the state of selection / non-selection of the word line WL is stored, it is possible to more accurately predict the deterioration of the data of the memory cell MC.

However, if the number of PF cells 21 is increased, P
Since the ratio of the F cell 21 to the memory device increases and causes an adverse effect such as an increase in chip area, it is necessary to determine the capability of the memory device and arrange an appropriate number of PF cells 21.

FIG. 9 shows an example in which a plurality of PF cells and a PF cell access counter are provided in a ferroelectric memory device.

For example, two PF cells 21 and one P
An F cell access counter PF-AC is provided, and each of the PF cells 21 is configured to store data of the PF cell 21 accessed last time and immediately before.

In this case, for example, as shown in FIG.
If there are two capacitors PFC for the PF cell access counter, a ferroelectric capacitor is used as the capacitor PFC for the PF cell access counter, and by combining a sense amplifier and an inverter circuit,
It can be easily realized. That is, each time the power of the memory device is turned on / off, the H / L data of the capacitor PFC for the PF cell access counter is switched to control the PF cell select gate SG.

In the present embodiment, the word line WL of the memory cell MC and the PF cell 21 are connected to each other via the gate φT, so that the capacity of the word line WL increases and the memory capacity increases. An adverse effect such as a decrease in the operation speed of the device may occur.

In this case, writing of data to the memory cell MC is performed by accessing the word line WL, and data degradation starts from the end of the data writing. ,
It is important to store the state of deterioration of the data over time.

Therefore, in order to suppress an increase in the capacity of the word line WL, the word lines WL and P
Instead of connecting to the F cell 21, a method in which data is written to the memory cell MC and a state of deterioration due to aging of data may be stored in the PF cell.

In particular, in the case of the above-described word line type PF cell system, after turning on the power of the ferroelectric memory device, it is detected which memory cell (word line) is accessed, and the word line which is not accessed is detected. May be selected to rewrite data.

As described above, the deterioration of the data held in the memory cell can be predicted.

That is, by judging the deterioration of the data held in the PF cell, the deterioration of the data held in the memory cell can be monitored in a pseudo (indirect) manner. This makes it possible to rewrite data only when the deterioration of the data held in the memory cell is predicted. Therefore, it is not necessary to constantly rewrite data, and it is possible to surely compensate the data held in the memory cell while minimizing the influence of the fatigue on the memory cell.

In particular, when the PF cells are formed at the same time by the same material, the same standard (the same shape and the same size), and the same process as the memory cells, a problem occurs when the PF cells are made different. Defect in the manufacturing process, which can be avoided.

In addition, since the data of the PF cell deteriorates under the same conditions as the data of the memory cell, it is possible to faithfully monitor the change over time in the data holding characteristic of the memory cell.

In the case where the PF cell is formed using the same material as the memory cell, the capacitance and the charge holding capacity of the capacitor of the PF cell are increased, and the data holding characteristics of the PF cell are improved more than the memory cell. In such a case, the stable characteristics of the ferroelectric material can be obtained,
The width of the reference potential can be set roughly, and the circuit design becomes easier.

Conversely, if the data holding characteristic of the PF cell is made lower than that of the memory cell, it is not necessary to adjust the setting of the reference potential so that the PF cell is likely to be defective. Is made possible by a single reference potential.

When the PF cells are arranged in the column direction of the memory cells, the word lines of the memory cells are not selected at the time of reading the data of the PF cells, so that the memory cells are protected from fatigue due to rewriting of data. it can.

If the PF cells are arranged in the row direction of the memory cells, the word lines of the memory cells are
By sharing with the word line of the PF cell via the gate, without affecting the memory cell, such as fatigue,
The data of the PF cell can be read.

When a memory cell is accessed, a high potential is applied to the pair of select transistors. By utilizing this, the lapse of time from the previous access is detected, and the data in the memory cell is similarly detected. Can be predicted.

In each of the embodiments described above, the case where the capacitor of the PF cell is formed of a ferroelectric material is described. However, the present invention is not limited to this. Is also possible. When the capacitor of the PF cell is formed using a material other than the ferroelectric, depending on the material, the deterioration of the data in the memory cell is predicted with higher sensitivity than when the same material is used as the capacitor of the memory cell. It becomes possible.

Although the transfer gate transistor is provided in the PF cell in order to reduce the load on the bit line, the transfer gate transistor can be omitted.

Further, assuming that the deterioration characteristics of the “1” and “0” data are almost the same, the PF for the “1” and “0” data is
Each cell is prepared. If the data holding characteristics of "1" and "0" data are biased due to the characteristics of the ferroelectric memory device, only one of the PF cells for data is prepared. It doesn't work.

Of course, various modifications can be made without departing from the spirit of the present invention.

[0127]

As described above in detail, according to the present invention, deterioration of retained data can be suppressed while preventing fatigue of a storage element due to rewriting of data, and retained data due to a temporal change in data retention characteristics can be suppressed. A non-volatile memory capable of preventing the loss of data can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a circuit configuration example of a ferroelectric memory device according to a first embodiment of the present invention.

FIG. 2 is a flowchart for explaining a flow of processing relating to a data compensation operation in the ferroelectric memory device shown in FIG. 1;

FIG. 3 is a flowchart shown to explain another flow of the data compensation operation in the ferroelectric memory device shown in FIG. 1;

FIG. 4 is a schematic configuration diagram showing another arrangement example of PF cells in a ferroelectric memory device according to a fourth embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of a ferroelectric memory device according to a fifth embodiment of the present invention, in which PF cells are arranged in the row direction of memory cells as an example.

FIG. 6 is a schematic configuration diagram of a ferroelectric memory device according to a sixth embodiment of the present invention, showing another example in which PF cells are arranged in the row direction of memory cells.

7 is a schematic diagram showing a configuration example of a PF cell selector used in the ferroelectric memory device shown in FIG.

FIG. 8 is a schematic configuration diagram showing an example in which a ferroelectric memory device according to a seventh embodiment of the present invention is a word line type PF cell type.

FIG. 9 is a schematic configuration diagram of a ferroelectric memory device, showing an example of a case in which access can be stored a plurality of times;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... Memory cell area 11a ... Sense amplifier 12 ... PF cell area 12a ... Sense amplifier 13 ... Data compensation system control circuit 14 ... PF cell data determination circuit 15 ... Data write control circuit 16 ... Memory control processor 21 ... PF cell 21a, 21b .., 21c, 21d cell row WL word line BL bit line T transfer transistor C ferroelectric capacitor MC memory cell φT gate SG PF cell select gate CS PF cell selector PFC PF cell access counter capacitor PF-BL PF cell data bit line PF-G PF cell bit line connection gate Ref-BL reference bit line PF-AC PF cell access counter

Claims (25)

[Claims] A storage element having a ferroelectric capacitor for holding data; and a monitor element for monitoring deterioration of the data held in the storage element. And rewriting the data when the deterioration of the data is monitored, thereby compensating for the data held in the storage element. 2. A determination circuit for predicting deterioration of the data based on an output of the monitor element, and a control for instructing a data writing circuit to rewrite the data according to a result of the determination circuit. The nonvolatile memory according to claim 1, further comprising a circuit. 3. The nonvolatile memory according to claim 1, wherein said monitor element is formed of a ferroelectric capacitor. 4. The nonvolatile memory according to claim 1, wherein the monitor element is configured using a storage element different from the storage element. 5. A first storage element having a ferroelectric capacitor for holding first data, and a second storage element having a ferroelectric capacitor for holding second data. A determination circuit for predicting deterioration of the first data stored in the first storage element based on the second data stored in the second storage element; A non-volatile memory, comprising: a control circuit that instructs a data write circuit to rewrite the first data held in the first storage element in accordance with the result of (1). 6. The determination circuit compares the second data held in the second storage element with a reference potential,
6. The nonvolatile memory according to claim 2, wherein deterioration of the first data held in the first storage element is predicted from the magnitude relation. 7. The device according to claim 6, wherein the second storage element is designed so as to obtain the same data retention characteristics according to the same standard as the first storage element. Non-volatile memory. 8. The first storage device according to claim 1, wherein the first and second data held in the first and second storage elements are binary high-potential charges when the first and second data are binary high-potential charges. Higher than a reference potential to be compared when reading out the first data held in the element, and when the first and second data are binary low-potential charges, higher than the reference potential. The nonvolatile memory according to claim 7, wherein the value is set low. 9. The second storage element is designed so as to obtain a data retention characteristic larger than that of the first storage element according to a standard different from that of the first storage element. The nonvolatile memory according to claim 6. 10. The first storage device according to claim 1, wherein the first and second data held in the first and second storage elements are binary high-potential charges. Lower than a reference potential to be compared when reading out the first data held in the element, and when the first and second data are binary low-potential charges, lower than the reference potential. The nonvolatile memory according to claim 9, wherein the value is set high. 11. The second storage element is designed so that a data retention characteristic smaller than that of the first storage element is obtained according to a different standard from that of the first storage element. The nonvolatile memory according to claim 6. 12. The first storage device according to claim 1, wherein the first and second data held in the first and second storage elements are binary high-potential charges. The potential equal to or lower than the reference potential to be compared when reading the first data held by the element;
12. The nonvolatile memory according to claim 11, wherein when the data is binary low-potential charge, the data is set to be equal to or higher than the reference potential. 13. The storage device according to claim 1, wherein the second storage element is provided adjacent to the first storage element, and a data line is shared with the first storage element. 6. The nonvolatile memory according to 5. 14. The nonvolatile memory according to claim 13, wherein a plurality of said second storage elements are provided in a row direction and are sequentially selected in units of a row direction selection line. 15. The semiconductor device according to claim 13, wherein a plurality of the first storage elements are arranged in a matrix, and the second storage elements are provided in a column direction, respectively.
5. The nonvolatile memory according to 4. 16. The semiconductor device according to claim 1, wherein the second storage element is provided adjacent to the first storage element, and a row direction selection line is shared with the first storage element. The nonvolatile memory according to claim 5. 17. The nonvolatile memory according to claim 16, wherein said second storage element is connected to said row direction selection line via a gate. 18. The non-volatile memory according to claim 16, wherein a plurality of said second storage elements are provided in a column direction, and are selected in order for each data line. 19. The device according to claim 16, wherein a plurality of said first storage elements are arranged in a matrix, and said second storage elements are provided in a row direction, respectively. Non-volatile memory. 20. The nonvolatile memory according to claim 2, wherein the control circuit controls so that a series of operations is performed before a normal operation is performed. 21. The nonvolatile memory according to claim 2, wherein the control circuit controls so that a series of operations is performed after a normal operation is performed. 22. The nonvolatile memory according to claim 6, wherein said second data held in said second storage element is a potential of a row direction selection line. 23. When the second storage element is designed so as to obtain the same data retention characteristics according to the same standard as the first storage element, the reference potential is equal to the first and second storage elements. When the first and second data stored in the second storage element are binary high-potential charges, the first data stored in the first storage element is read out. 3. When the first and second data are binary low-potential charges, the reference potential is set to be lower than the reference potential.
3. The nonvolatile memory according to 2. 24. When the second storage element is designed so as to obtain a large data retention characteristic according to a standard different from that of the first storage element, the reference potential is:
The first and second storage elements held by the first and second storage elements
When the second data is a binary high-potential charge, the second data is lower than a reference potential to be compared when reading the first data held in the first storage element.
23. The nonvolatile memory according to claim 22, wherein when the second data is a binary low-potential charge, the second data is set higher than the reference potential. 25. When the second storage element is designed so as to obtain a small data retention characteristic according to a standard different from that of the first storage element, the reference potential is
The first and second storage elements held by the first and second storage elements
If the second data is a binary high-potential charge, it is equal to or lower than the reference potential compared when reading the first data held in the first storage element. 23. The nonvolatile memory according to claim 22, wherein when the first and second data are binary low-potential charges, they are set to be equal to or higher than the reference potential. .