JP2002197139A - Voltage drop analyzing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the accuracy in analyzing the voltage drop of a semicon ductor integrated circuit. SOLUTION: The consumed current of one megacell 60 is divided into plural constant-current sources 64, and these plural constant-current sources 64 are equally allocated to a power source wiring 62 in the megacell to modelize the megacell 60. The modelized megacell 60 is applied as the megacell in the semiconductor integrated circuit, and then the voltage drop of the semiconductor integrated circuit is analyzed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a voltage drop analysis system, and more particularly to a voltage drop analysis system for performing a voltage drop analysis that more accurately reflects current consumption inside a cell.

[0002]

2. Description of the Related Art In recent years, miniaturization and speeding up of semiconductor integrated circuits have been progressing due to advances in semiconductor manufacturing technology. For this reason, the problem of a drop in the power supply voltage inside the semiconductor integrated circuit is becoming apparent with respect to the power supply wiring of the power supply system of the semiconductor integrated circuit. For this reason, a computer is used to analyze the state of the voltage drop in one semiconductor integrated circuit.

[0003] In such a semiconductor integrated circuit, a plurality of elements such as transistors and capacitors for realizing various functions and wirings for electrically connecting the plurality of elements are provided. Further, in order to increase the efficiency of the design work, a method of preparing elements and wirings for realizing a set of functions as cells in advance and arranging them in a semiconductor integrated circuit is also used. Among such cells, a particularly large-scale and high-performance cell is called a megacell. When a cell (megacell) is arranged in a semiconductor integrated circuit, the internal configuration of the cell (megacell) also affects the voltage drop.

[0004]

However, in this computer analysis, the cell (megacell) portion in the semiconductor integrated circuit does not have a specific internal configuration, and therefore, the semiconductor integrated circuit including the cell (megacell) is omitted. There is a problem that the analysis of the voltage drop in the circuit cannot be performed with the required accuracy.

For example, Japanese Unexamined Patent Application Publication No. 5-47928 discloses a voltage drop analysis method in the case where hierarchical nodes of a parent cell and a child cell exist in a semiconductor integrated circuit. However, no consideration is given to the internal configuration of the cell (megacell) and the distribution of the places where the power is consumed. Therefore, when the cell (megacell) is included, There is a problem that voltage drop analysis cannot be performed properly.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a semiconductor integrated circuit voltage drop analysis system capable of more appropriately analyzing a voltage drop in a semiconductor integrated circuit including cells. The purpose is to provide.

[0007]

In order to solve the above-mentioned problems, a voltage drop analysis system according to the present invention models a cell arranged in a semiconductor integrated circuit in consideration of the distribution of current consumption inside the cell. A first modeling unit, and an analyzing unit that performs a voltage drop analysis based on a circuit network modeled by the first modeling unit.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] In a first embodiment of the present invention, the current consumption in a megacell is divided into a plurality of constant current sources, and the plurality of constant current sources are connected to a power supply wiring in the megacell. , It is possible to analyze the voltage drop of the semiconductor integrated circuit more appropriately reflecting the distribution of the current consumption in the megacell. A more detailed explanation will be given below.

FIG. 1 shows a voltage drop analysis system 1 according to the present embodiment for analyzing a voltage drop in a semiconductor integrated circuit.
FIG. 2 is a block diagram showing a hardware configuration at 0.

As shown in FIG. 1, a voltage drop analysis system 10 according to this embodiment includes a computer
And the display device 3 connected to the computer body 20
0. Computer body 20
Is a CPU (Central Processing Unit) 40 and RA
M (Random Access Memory) 42 and ROM (Read Onl
yMemory) 44, which are mutually connected via an internal bus. The hard disk 48 is connected to the internal bus via an interface circuit 46 connected to the internal bus. The internal bus via and a cable interface circuit 50 connected to the internal bus, is connected to the interface circuit 32 of the display device 30.

Next, a voltage drop analysis process according to this embodiment will be described with reference to FIG. FIG. 2 is a flowchart illustrating a voltage drop analysis process performed by the voltage drop analysis system 10. In the present embodiment, this voltage drop analysis process is stored in the hard disk 48 as a voltage drop analysis program, and is realized by the CPU 40 reading and executing the program.

As shown in FIG. 2, first, the voltage drop analysis system 10 extracts a resistance network of a power supply system in a semiconductor integrated circuit (step S10). That is, the design data of the semiconductor integrated circuit designed by the user is stored in the hard disk 48.
Is stored in Based on the design data, the voltage drop analysis system 10 extracts a power supply wiring of the power supply system from the wirings in the semiconductor integrated circuit.

Next, the voltage drop analysis system 10 extracts current consumption for the extracted power supply system resistance network (step S11). That is, it determines how much current is consumed by elements such as transistors and capacitors connected to the power supply wiring.

Next, the voltage drop analysis system 10 replaces the megacell arranged in the semiconductor integrated circuit with a megacell model (step S12). The type of megacell model to be replaced will be described later.

Next, the voltage drop analysis system 10 analyzes the voltage drop in the semiconductor integrated circuit (step S).
13). Since a specific method of this analysis is known, a detailed description thereof will be omitted here.

Next, referring to FIG. 3, the megacell model adding process in step S12 will be described in detail. FIG 3 is a flowchart illustrating a mega cell model adding process according to the present embodiment in detail. In the present embodiment, the megacell model addition processing is also realized by the CPU 40 reading and executing the megacell model addition program stored in the hard disk 48.

As shown in FIG. 3, first, the voltage drop analysis system 10 selects one mega cell in the semiconductor integrated circuit (step S20). Specifically, one megacell is selected from the semiconductor integrated circuits based on the design data of the semiconductor integrated circuits stored in the hard disk 48.

Next, the voltage drop analysis system 10 calculates the current consumption of the entire selected megacell (step S2).
1). The current consumption of the entire megacell is registered in a library in advance for each type of megacell. However, step S21
In, the current consumption of the entire megacell may be obtained by each time analysis.

Next, the voltage drop analysis system 10 extracts a power supply wiring from the wiring laid inside the megacell (step S22). FIG. 4 is a diagram illustrating a megacell 60 as an example. The megacell 60 shown in FIG.
In step S22, the power supply wires 62 laid in a lattice are extracted in step S22.

Next, as shown in FIG. 3, the voltage drop analysis system 10 equally divides the current consumption of the entire megacell obtained in step S21 into a plurality of pieces, and allocates the divided current to the power supply wiring as a constant current source (step S21). S23). In the case of the mega cell 60 shown in FIG.
Assigned equally to 2. For example, if the current consumption of the entire megacell 60 is 20 mA, twenty constant current sources of 1 mA are equally allocated to the power supply wiring 62.

Next, as shown in FIG. 3, the voltage drop analysis system 10 adds the mega cell model generated in step S23 to the semiconductor integrated circuit as a mega cell (step S24). Subsequently, it is determined whether or not all the megacells in the semiconductor integrated circuit have been modeled (step S25). If all the megacells have not been modeled (step S25: No), the above steps from step S20 are repeated. On the other hand, when the finished model all mega cells (step S25: Yes), the CPU ends the mega cell model adding process.

As described above, according to the voltage drop analysis system 10 according to the present embodiment, for example, as shown in FIG.
At the time of voltage drop analysis, the current consumption of the entire megacell 60 is
Since the plurality of constant current sources are used to equally allocate the power supply wiring 62, the current consumed inside the megacell 60 can be represented in a form closer to an actual product. Therefore, a more accurate voltage drop analysis can be performed.

[Second Embodiment] A second embodiment of the present invention is a modification of the above-described first embodiment, and reduces the current consumption of the entire megacell based on the area ratio of the power supply pins provided in the megacell. The power supply is divided and the divided current consumption is allocated to each power supply pin as a constant current source.
This will be described in more detail below.

The voltage drop analysis system 10 of the present embodiment differs from the above-described first embodiment in the processing of adding a megacell model.

FIG. 5 is a flowchart for explaining the megacell model adding process according to the present embodiment in detail. Also in the present embodiment, the megacell model addition process is realized by the CPU 40 reading and executing the megacell model addition program stored in the hard disk 48.

As shown in FIG. 5, first, the voltage drop analysis system 10 selects one mega cell in the semiconductor integrated circuit (step S30). Specifically, one megacell is selected from the semiconductor integrated circuits based on the design data of the semiconductor integrated circuits stored in the hard disk 48.

Next, the voltage drop analysis system 10 calculates the current consumption of the entire selected megacell (step S3).
1). The current consumption of the entire megacell is registered in a library in advance for each type of megacell. However, step S31
Thus, the current consumption of the entire megacell may be determined by analysis each time.

Next, the voltage drop analysis system 10 extracts power supply pins provided inside the megacell and calculates the area of each power supply pin (step S32). FIG. 6 is a diagram illustrating a megacell 70 as an example. In the case of the megacell 70 shown in FIG. 6, in step S32, seven power supply pins 72 provided in the megacell are extracted. further,
In this step S32, the area of each of the seven power supply pins 72 is calculated. The power supply pin 72 is a portion for connecting a power supply wiring from the outside to the inside of the megacell 70. As the area of the power supply pin 72 increases, the degree of freedom in designing a portion for connecting the power supply wiring from the outside increases. .

Next, as shown in FIG. 5, the voltage drop analysis system 10 divides the current consumption of the entire megacell determined in step S31 so as to be proportional to the power supply pin area calculated in step S32. Assigned to each power supply pin as a constant current source (step S33). In the case of the mega cell 70 shown in FIG. 6, seven constant current sources 74 are allocated with current capacities proportional to the area of each power supply pin 72.

Next, as shown in FIG. 5, the voltage drop analysis system 10 adds the mega cell model generated in step S33 to the semiconductor integrated circuit (step S3).
4). Subsequently, it is determined whether or not model all megacell in the semiconductor integrated circuit (step S35).
If not finished model all mega cells (step S35: No), the repeated from step S30 described above. On the other hand, when all the megacells have been modeled (step S35: Yes), the megacell model addition processing ends.

As described above, according to the voltage drop analysis system 10 according to the present embodiment, for example, as shown in FIG.
The current consumption of the entire megacell 70 is divided according to the area ratio of the power supply pins 72, and the constant current source 7
4, the current consumed inside the megacell 70 can be represented in a form closer to an actual product. Therefore, a more accurate voltage drop analysis can be performed.

The present embodiment can be applied to a mega cell 80 having a power supply ring 82 as shown in FIG. In this case, in step S32, the power supply ring 82 is divided into
And calculate the area of each. And step S
At 33, the current consumption of the entire megacell 80 may be divided according to the area ratio of the power supply pins 84, and the constant current source 86 having the divided current capacity may be assigned to each power supply pin.

[Third Embodiment] A third embodiment of the present invention is a modification of the above-described second embodiment, and a current consumed by each power supply pin in a megacell is obtained by using a simulator. the is obtained by the assignment of the corresponding power pins as a constant current source. This will be described in more detail below.

The voltage drop analysis system 10 of this embodiment is different from the first and second embodiments in the megacell model addition processing.

FIG. 8 is a flowchart for explaining in detail the megacell model adding process according to the present embodiment. Also in the present embodiment, the megacell model addition process is realized by the CPU 40 reading and executing the megacell model addition program stored in the hard disk 48.

As shown in FIG. 8, first, a voltage drop analysis system 10, selects one megacell in the semiconductor integrated circuit (step S40). Specifically, one megacell is selected from the semiconductor integrated circuits based on the design data of the semiconductor integrated circuits stored in the hard disk 48.

Next, the voltage drop analysis system 10 reads the current consumption of each power supply pin in the megacell from the library (step S41). That is, in the present embodiment, the current consumed by each power supply pin is calculated in advance using a simulator, and the calculation result is registered in a library for each type of megacell. Therefore, in the megacell model addition processing according to the present embodiment, the current consumption of each power supply pin in the corresponding megacell registered in the library is read. In the present embodiment, this library is also stored in the hard disk 48.

The simulator is SPIC.
E and PowerMill are known, but not limited to these. A program for realizing the simulator is stored in the hard disk 48, and is realized by the CPU 40 reading and executing the program. Further, in the present embodiment, the current consumption of each power supply pin is registered in the library in advance, but may be calculated by the simulator each time in step S41.

FIG. 9 is a diagram showing a mega cell 90 as an example. In the case of the mega cell 90 shown in FIG. 9, in step S41, the seven power supply pins 9 provided in the mega cell
2 are read from the library.

Next, as shown in FIG. 8, the voltage drop analysis system 10 allocates a constant current source having a current capacity corresponding to the current consumption of each power supply pin determined in step S41 to the corresponding power supply pin (step S41). S42). In the megacell 90 of FIG. 9, constant current sources 94 having a current capacity corresponding to the current consumption calculated by the simulator are assigned to the corresponding power supply pins 92.

Next, as shown in FIG. 8, the voltage drop analysis system 10 adds the megacell model generated in step S42 to the semiconductor integrated circuit as a megacell (step S43). Subsequently, it is determined whether or not all the megacells in the semiconductor integrated circuit have been modeled (step S44). If all the megacells have not been modeled (step S44: No), the above steps S40 to S40 are repeated. On the other hand, when all the megacells have been modeled (step S44: Yes), the megacell model addition processing ends.

As described above, according to the voltage drop analysis system 10 according to the present embodiment, the current consumed inside the megacell 90 is reduced in a format closer to the actual product as compared with the above-described second embodiment. This makes it possible to perform more accurate voltage drop analysis.

The present embodiment can be applied to a megacell 100 having a power supply ring 102 as shown in FIG. In this case, the power supply ring 102 is divided into an appropriate size to form a plurality of power supply pins 104, and the current consumed by each power supply pin 104 is calculated in advance using a simulator and registered in a library. Then, in step S41, the current consumption of each power supply pin 104 is read from the library, and in step S42,
A constant current source 106 having a current capacity corresponding to the current consumption of the power supply pins 104 may be assigned to each power supply pin.

[Fourth Embodiment] In a fourth embodiment of the present invention, a circuit network comprising a resistance network modeling a power supply wiring of a megacell and a constant current source modeling a current consumption is generated. A reduced version of the circuit network is registered as a library, and the registered version is used for voltage drop analysis. This will be described in more detail below.

FIG. 11 is a diagram showing a circuit network in which the power supply wiring of the megacell 110 is modeled using a resistor, and the current consumption is modeled using a constant current source. In FIG. 11, nodes at the four corners constitute an external node 112 connected to the outside of the megacell 110, and other nodes constitute an internal node 114 not connected to the outside.

When a nodal equation is generated from the circuit network of the megacell 110 in FIG. 11, the equation becomes as shown in equation (1).

[0047]

(Equation 1) Here, Y11 to Ymn are admittances of each node, V1 to Vn are voltages of each node, and I1 to Imn
m is a current flowing into each node. In Expression (1), when the external node 112 and the internal node 114 are separated and arranged, Expression (2) is obtained.

[0048]

(Equation 2) Here, A, B, C, and D each represent an admittance matrix, Ve represents a matrix of external node voltages, Vi represents a matrix of internal node voltages, and Ie represents Represents a matrix of currents at external nodes,
i represents a matrix of the current of the internal node. By transforming the equation (2), the equation (3) is obtained.

[0049]

(Equation 3) In this equation (3), it has become nodal equation erasing the internal node from the equation (1). By using the equation (3), a reduced circuit network 120 including only the external nodes 112 as shown in FIG. 12 is obtained. That is, when the mega cell 110 in FIG. 11 is reduced, the circuit network 12 shown in FIG.
0 is obtained.

The values of the resistors R120 to R125 of the network 120 are determined by A-BD ^-1 C in the equation (3), and the constant current sources I120 to R125 of the network 120 are determined by -BD ^-1 Ii in the equation (3). The current capacity of I123 is determined.

In the present embodiment, the reduced circuit network 120 is registered in a library. Alternatively, when A-BD ^-1 C and -BD ^-1 Ii in the equation (3) are registered in a library and a node equation of the entire semiconductor integrated circuit is established, a Y matrix element and an I vector element of a megacell portion are set. As such, it may be used. Further, since the reduced network differs for each type of megacell, a network is generated for each type and registered in a library.

It should be noted that equation (2) may be modified to form equation (4).

[0053]

(Equation 4) Equation (4) is a relational expression between the voltage Vi of the internal node 114 and the voltage Ve of the external node 112.
This equation (4) may be registered in a library. Accordingly, when the voltage Ve of the external node of the megacell is obtained by the voltage drop analysis of the entire semiconductor integrated circuit, the voltage Vi of the internal node of the megacell can be obtained by using the equation (4).

Next, the megacell model adding process according to the present embodiment will be described with reference to FIG. This FIG.
It is a flowchart explaining in detail the megacell model addition process concerning this embodiment. In this embodiment, the mega cell model adding process, a mega cell model adds program stored in the hard disk 48, CPU
This is realized by reading and executing by 40.

As shown in FIG. 13, first, the voltage drop analysis system 10 selects one mega cell in the semiconductor integrated circuit (step S50). Specifically, one megacell is selected from the semiconductor integrated circuits based on the design data of the semiconductor integrated circuits stored in the hard disk 48.

Next, the voltage drop analysis system 10 reads a circuit network corresponding to the selected megacell from the library (step S51). That is, in the present embodiment, since the circuit network obtained by the above equation (3) is registered in the library in advance, it is read. In the present embodiment, this library is also stored in the hard disk 48. However, instead of registering the network reduced by the equation (3) in the library in advance, in step S51, a network reduced based on the equation (3) may be generated each time.

Next, the voltage drop analysis system 10 adds the circuit network read in step S51 to the semiconductor integrated circuit as a megacell model (step S52). Subsequently, the voltage drop analysis system 10 determines whether all the megacells in the semiconductor integrated circuit have been modeled (Step S53). If all the megacells have not been modeled (step S53: No), the above steps from step S50 are repeated. On the other hand, when all the megacells have been modeled (step S54: Ye
In s), the megacell model addition processing ends.

As described above, according to the voltage drop analysis system 10 according to the present embodiment, for example, as shown in FIG. 12, a reduced network of the megacell 120 is obtained in advance and registered in the library. Keep it. Then, at the time of the voltage drop analysis, a circuit network corresponding to the mega cell registered in the library is allocated to the mega cell in the semiconductor integrated circuit, and the analysis is performed, so that the actual circuit can be further analyzed. can make a voltage drop analysis in close format,
Analysis accuracy can be improved.

[0059] Fifth Embodiment of the Fifth Embodiment The present invention models the current consumption and power wiring megacell generates resistor network, the network having contracted the resistor network, registered as a library The data registered in this library is used for the voltage drop analysis. This will be described in more detail below.

[0060] The average current consumption of the CMOS logic gate is represented by the formula (5).

[0061]

(Equation 5) Here, I is the average current consumption of the CMOS logic gate, f is the drive frequency, and _VDD is the power supply voltage.
As can be seen from equation (5), if the driving frequency f is constant, the average current consumption is proportional to the power supply voltage. Therefore, in the DC analysis, as shown in FIG. 14, instead of modeling the current consumption with a constant current source, the current consumption is modeled in consideration of the power supply voltage dependency by modeling it with a resistor. Can be. That is, in the power supply voltage V _DD , the portion of the consumption current I can be modeled by a resistance of R = V _DD / I instead of being modeled by a constant current source of I.

FIG. 15 is a diagram showing a resistance network 130 in which a power supply wiring and a current consumption of a certain megacell are modeled using resistance. In FIG. 15, four nodes among the nodes at the corners constitute an external node 132 connected to the outside of the megacell, and the other nodes constitute an internal node 134 not connected to the outside. . Also,
In the example of FIG. 15, a resistor R130 provided on a wiring extending in the vertical direction in the figure is a resistance modeling a consumption flow source, and a resistor R13 provided on a wiring extending in the horizontal direction in the figure.
Reference numeral 1 denotes a resistor that models a power supply wiring.

Formulating a nodal equation from the resistance network 130 in FIG.

[0064]

(Equation 6) Here, Y11 to Ymn are admittances of each node, V1 to Vn are voltages of each node, and I1 to Imn
m is a current flowing into each node. In Expression (1), when the external node 132 and the internal node 134 are separated and arranged, Expression (7) is obtained.

[0065]

(Equation 7) Here, A, B, C, and D each represent an admittance matrix, Ve represents a matrix of voltages of external nodes, Vi represents a matrix of voltages of internal nodes, and Ie represents a matrix of voltages of internal nodes. The matrix of the current of the external node is shown. Also, since no current source exists at the internal node, the corresponding current matrix is zero. By transforming the equation (7), the equation (8) is obtained.

[0066]

(Equation 8) Equation (8) is a nodal equation in which internal nodes are eliminated from equation (6). Using this equation (8), as illustrated in FIG 16, the contracted network 140 consisting of only the external node 132 in the absence of internal nodes is obtained as a node. The values of the resistors R140 to R145 of the network 140 are determined by A-BD ^-1 C in equation (8).

In the present embodiment, the reduced circuit network 140 is registered in a library. Alternatively, when A-BD ^-1 C in equation (8) is registered in a library and a node equation of the entire semiconductor integrated circuit is established,
It may be used as a Y matrix element of a megacell part. Further, since the reduced network differs for each type of megacell, a network is generated for each type and registered in a library.

Equation (7) may be modified to form equation (9).

[0069]

(Equation 9) Equation (9) is a relational expression between the voltage Vi of the internal node 144 and the voltage Ve of the external node 142.
This equation (9) may be registered in a library. Thus, when the voltage Ve of the external node of the megacell is determined from the voltage drop analysis of the entire semiconductor integrated circuit, the voltage Vi of the internal node of the megacell can be determined by using equation (9).

Since the megacell model adding process according to the present embodiment is the same as that of the above-described fourth embodiment, a detailed description thereof will be omitted.

As described above, according to the voltage drop analysis system 10 of the present embodiment, for example, as shown in FIG. 16, a reduced circuit network 140 of the megacell 130 is obtained in advance and registered in the library. Keep it. Then, at the time of the voltage drop analysis, the mega cell in the semiconductor integrated circuit
Analysis is performed after allocating a circuit network corresponding to the megacell registered in the library, so voltage drop analysis can be performed in a format closer to the actual circuit, improving analysis accuracy be able to.

The present invention is not limited to the above embodiment, but can be variously modified. For example, in the above-described embodiment, a mega cell has been described as an example, but the present invention can be similarly applied to a normal cell having a smaller circuit scale than the mega cell.

Further, with respect to each processing described in the above embodiment, a program for executing each processing is stored in a floppy (registered trademark) disk, CD-ROM (Co-ROM).
It can be recorded on a recording medium such as a mpact disc-read only memory (ROM), a ROM, or a memory card and distributed in the form of a recording medium. In this case, the above-described voltage drop analysis system 10 can be realized by causing the computer main body 20 to read and execute a recording medium on which the program is recorded.

The computer main body 20 may include another program such as an operating system or another application program. In this case, by utilizing another program included in the computer main body 20, an instruction for calling a program for realizing the same processing as the above-described embodiment from among the programs included in the computer main body 20 is recorded on the recording medium. You may do so.

[0075] Further, such a program is not in the form of a recording medium, it can be distributed as carrier waves through a network. The program transmitted on the network in the form of a carrier wave is taken into the computer main body 20, and the above-described embodiment can be realized by executing the program.

Further, when a program is recorded on a recording medium or transmitted as a carrier wave over a network, the program may be encrypted or compressed.
In this case, the computer main body 20 that has read the program from the recording medium or the carrier wave needs to execute the program after decoding and decompressing the program.

[0077]

As described above, according to the present invention,
The first modeling means models a cell arranged in the semiconductor integrated circuit in consideration of the distribution of current consumption inside the cell, and performs a voltage drop analysis based on the modeled network. Therefore, a more accurate voltage drop analysis can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a hardware configuration of a voltage drop analysis system according to an embodiment of the present invention.

FIG. 2 is a view showing a flowchart illustrating a voltage drop analysis process according to an embodiment of the present invention.

FIG. 3 is a flowchart illustrating a megacell model adding process according to the first embodiment of the present invention.

FIG. 4 is a diagram showing a megacell for explaining a constant current source allocation method according to the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating a megacell model adding process according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a megacell for explaining a constant current source allocation method according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a megacell explaining a modification of the second embodiment of the present invention.

FIG. 8 is a flowchart illustrating a megacell model adding process according to a third embodiment of the present invention.

FIG. 9 is a diagram showing a megacell for explaining a constant current source allocation method according to a third embodiment of the present invention.

FIG. 10 is a diagram showing a megacell explaining a modification of the third embodiment of the present invention.

FIG. 11 is a diagram showing a megacell for explaining a technique for reducing a megacell in a fourth embodiment of the present invention.

FIG. 12 is a diagram showing a circuit network in which the megacell of FIG. 11 is reduced in the fourth embodiment of the present invention.

FIG. 13 is a flowchart illustrating a megacell model adding process according to a fourth embodiment of the present invention.

FIG. 14 is a diagram illustrating that a constant current source can be replaced with a resistor in the fifth embodiment of the present invention.

FIG. 15 is a view showing a megacell for explaining a technique for reducing a megacell in a fifth embodiment of the present invention.

FIG. 16 is a diagram showing a circuit network in which the megacell of FIG. 11 is reduced in the fifth embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 voltage drop analysis system 20 computer main body 30 display device 32 interface circuit 40 CPU 42 RAM 44 ROM 46 interface circuit 48 hard disk 50 interface circuit

Claims (7)

[Claims] 1. A cell arranged in a semiconductor integrated circuit is modeled in consideration of a distribution of current consumption inside the cell.
A voltage drop analysis system comprising: first modeling means; and analysis means for performing a voltage drop analysis based on a circuit network modeled by the first modeling means. 2. The power supply system according to claim 1, further comprising a second modeling unit configured to model a power supply wiring laid in the semiconductor integrated circuit and an element connected to the power supply wiring as a resistance network. The voltage drop analysis system according to claim 1. 3. The method according to claim 1, wherein the first modeling means equally divides a current consumed by the cell to a power supply line laid in the cell and allocates the divided current as a constant current source. The voltage drop analysis system according to claim 1. 4. The first modeling means divides a current consumed by the cell on the basis of an area ratio of a power supply pin provided in the cell, and divides the current consumed by the division. voltage drop analysis system according to claim 1 as a constant current source, assigned to the power supply pin, I am characterized in having a current capacity. Wherein said first modeling means analyzes the consumption current consumed by the power source pins provided in the cell, based on the analysis result, allocates a constant current source to the power supply pin, it The voltage drop analysis system according to claim 1, wherein: 6. The first modeling means generates a network having a resistance network which models a power supply wiring in the cell and a constant current source which models a current consumption in the cell. The voltage drop analysis system according to claim 1, wherein a reduced network obtained by reducing a network is added as the cell in the semiconductor integrated circuit. 7. The first modeling means generates a network in which power supply wiring and current consumption in the cell are modeled by using resistors, and generates a reduced network obtained by reducing this network. 2. The voltage drop analysis system according to claim 1, wherein the voltage drop analysis system is added as the cell in the semiconductor integrated circuit.