JP2002189711A - Coefficient varying circuit and digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optionally set in detail the coefficient variation time needed to vary a coefficient used for signal processing from an initial value to a target value. SOLUTION: In a coefficient varying circuit 200, a subtracter 202, a register 203, and a shifter 205 calculate an update quantity Cc from the difference between the target value Cend and initial value Cstart of the coefficient to be varied. An accumulator composed of an adder 208 and a register 209 accumulates output data of a mute control part 207 and outputs the accumulation result as a current value Cnew of the coefficient. The mute control part 207 controls which of the update quantity Cc and '0' is sent to the accumulator according to a time-series pattern previously defined corresponding to the variation needed time of the coefficient each time a clock of fixed frequency is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coefficient changing circuit for gradually changing a coefficient used for signal processing from an initial value to a target value, and a digital signal processing device including the coefficient changing circuit.

[0002]

2. Description of the Related Art In the field of digital signal processing, coefficients used for signal processing are sometimes changed with time. As one example, there is coefficient control in a so-called cross-fade circuit. This cross-fade circuit is a circuit for synthesizing and outputting, for example, two types of tone signals. The output signal is naturally shifted from one tone signal to the other tone signal by changing the synthesis ratio over time. It is to let. Further, as another example, in a digital signal processing device (hereinafter, referred to as DSP) for performing signal processing such as filter processing and reverberation processing on a digital signal, a part or all of coefficients used for signal processing are temporally changed. There is control to make it. More specifically, in this type of DSP, a new digital signal sample is fetched every sampling period, and the past n samples Xm to Xm-n + 1 taken so far and predetermined coefficients C1 to Cn are acquired. Is used to perform the convolution operation shown in Expression 1 below, and the operation result Y
Output m.

(Equation 1) In this case, control is generally performed to temporally change a part or all of the coefficients C1 to Cn to temporally change a filtering process, a reverberation imparting process, and the like for a digital signal.

In such a case, if the coefficient for signal processing is changed from the current value to another value immediately, the output signal as a result of the signal processing changes rapidly, causing annoying noise. Sometimes. In order to prevent such inconvenience, a technique for gradually changing a signal processing coefficient from an initial value to a target value by interpolation processing has been proposed in, for example, Japanese Patent Application Laid-Open No. 7-122997.

[0004] This interpolation processing is performed by using an initial value Cstar of the coefficient.
When t and the target value Cend are given, the difference C between the two is given.
end-Cstart = Cd =
By calculating (Cend-Cstart) / L and sequentially accumulating the update amount Cd for each sampling cycle,
The coefficient is set to the initial value Cstar by using the L sampling period.
The target value is sequentially changed from t to the target value Cend. Here, L is, for example, “2”, “4”, “8”, “1”
For example, a number corresponding to a power of 2 is used.

[0005]

When various effects are applied to a tone signal by an effector, for example, when a coefficient used for signal processing for giving the effect is changed from an initial value to a target value. May need to be finely adjusted. However, under the above-described conventional technology, the required time can only be selected from several types of predetermined times, and it is difficult to fine-tune the required time, which gives various effects. Had been the above restrictions.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a coefficient changing circuit and a digital signal capable of finely adjusting the time required for changing a signal processing coefficient from an initial value to a target value. It is an object to provide a processing device.

[0007]

According to a first aspect of the present invention, there is provided an update amount for calculating an update amount of a coefficient from a difference between a target value and an initial value of a coefficient to be changed. Calculating means, an accumulator for initializing the initial value according to a coefficient change instruction, accumulating the update amount, and outputting the accumulation result as a current value of the coefficient, and a clock of a constant frequency being provided. And accumulating control means for controlling whether to accumulate the update amount by the accumulator according to a time-series pattern defined in advance corresponding to the target change time of the coefficient. Features.

According to a second aspect of the present invention, there is provided a convolution operation unit for storing sample data inputted every sampling period and convolving a predetermined number of coefficients with respect to a predetermined number of sample data inputted in the past; And a coefficient changing circuit for changing a desired coefficient over a desired time, wherein the coefficient changing circuit calculates an update amount of the coefficient from a difference between a target value and an initial value of the coefficient to be changed. An update amount calculating means, an accumulator for initializing the initial value according to a coefficient change instruction, accumulating the update amount, and outputting the accumulation result as a current value of the coefficient, and a clock of a constant frequency. Accumulation control means for controlling whether or not to accumulate the update amount by the accumulator according to a time series pattern defined in advance corresponding to the target change time of the coefficient each time the coefficient is changed. You It is characterized in that.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. Note that the present embodiment is merely an example of the embodiment of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

FIG. 1 shows a DS according to an embodiment of the present invention.
FIG. 3 is a block diagram showing a configuration of P. As shown in FIG.
The DSP includes a convolution operation unit 100, a coefficient changing circuit 200, and a control unit 300 that generates various control signals for controlling these. Here, the convolution operation unit 100 is a unit that executes signal processing for convolving a predetermined filter coefficient with respect to the sample data of the musical sound signal to be processed for each sampling cycle. The convolution operation unit 100 includes a data shift register 10, a coefficient shift register 20, and an operation unit 30. The data shift register 10 is supplied with a sampling clock φs and an operation clock φc having a higher frequency than the sampling clock φs from the control unit 300. In the data shift register 10, every time the sampling clock φs is supplied, the writing of the sample data of the tone signal to be processed and the shifting of the already written sample data are performed. Data shift register 1
0 has a storage area enough to store the past n pieces of sample data input in this way as Xm to Xm-n + 1 (Xm is the newest sample data). Then, in each sampling period, the sample data strings Xm to Xm-n + 1 stored in the data shift register 10 are
The data is sequentially read out by the operation clock φc and supplied to one input terminal of the operation unit 30.

The coefficient shift register 20 is a register for storing n operation coefficients C1 to Cn convolved with the past n sample data Xm to Xm-n + 1 stored in the data shift register 10. These operation coefficients C1 to Cn
Is the operation clock φ in each sampling period.
c, and are sequentially supplied to the other input terminal of the arithmetic unit 30. Further, the coefficient shift register 20 is configured such that an arbitrary operation coefficient can be written from the coefficient changing circuit 200 side under the control of the control unit 300. That is, the selection signal SEL for selecting a desired operation coefficient (for example, the operation coefficient C2) among the operation coefficients C1 to Cn stored in the coefficient shift register 20 and the write signal WR are transmitted from the control unit 300 to the coefficient shift register 20. When given, the new coefficient Cnew output from the coefficient changing circuit 200 at this time is used as the operation coefficient C2 in the coefficient shift register 2
Written to 0.

The arithmetic unit 30 is constituted by a multiplier and an accumulator (neither is shown). In each sampling cycle, the arithmetic unit 30 multiplies the sample data read from the data shift register 10 by the arithmetic coefficient read from the coefficient shift register 20 by the multiplier every time the arithmetic clock φc is generated. The result of the multiplication is accumulated in the existing data in the accumulator. The arithmetic unit 30 repeats the multiplication and addition n times in synchronization with the operation clock φc, thereby executing the operation of convolving the operation coefficients C1 to Cn with the sample data Xm to Xm-n + 1 of the tone signal, and the convolution operation result Ym is output. The above is the details of the configuration of the convolution operation unit 100.

Next, the coefficient changing circuit 200 will be described. The coefficient changing circuit 200 sets a desired operation coefficient (for example, operation coefficient C2) among the operation coefficients stored in the coefficient shift register 20 of the convolution operation unit 100 to an initial value Csta.
This is a means for performing an interpolation process for gradually changing from rt to a target value Cend. As shown in FIG. 1, the coefficient changing circuit 200 includes a switching circuit 201, a subtractor 202, a register 203, an adder 204, a shifter 205, a counter 206, a mute control unit 207, and an adder 208. And a register 209.

The switching circuit 201 is supplied with selection information SEL for designating a coefficient to be changed in a sampling cycle in which the interpolation processing is started and in each sampling cycle until the interpolation processing is completed. In the sampling period for starting the interpolation processing, this selection information SEL
Is given, the switching circuit 201 selects a coefficient specified by the selection signal SEL from among the coefficients of the coefficient shift register 20, and supplies the selected coefficient as an initial value Cstart to the subtractor 202 and the register 209. In each subsequent sampling period, the selection information SE
When L is given, the switching circuit 201 sets the current value Cne of the coefficient stored in the register 209 at that time.
w is supplied to the storage area specified by the selection signal SEL. The current value Cnew is written to the corresponding storage area in the coefficient shift register 20 by the selection signal SEL and the write signal WR as described above.

Subtractor 202 receives an initial value Cst output from switching circuit 201 when selection signal SEL is applied.
is set to the target value Cend output from the control unit 300.
, And outputs the total correction amount Cd. This total correction amount C
d is written into the register 203 by the preset signal P output from the control unit 300 at the start of the interpolation processing.

The adder 204 adds the parameters M and Ba given from the control unit 300, and outputs a downshift number M + Ba. This downshift number M + Ba is
The data is supplied to the shifter 205. The shifter 205 shifts down the total correction amount Cd output from the register 203 by M + Ba bits, and outputs an update amount Cc per one time. The update amount Cc is given by the following equation (2).

(Equation 2)

Here, N is the number of coefficient updates,
M and Ba are shift down number parameters. Normal M
Is fixed by hardware, and Ba is determined by coefficient change required time information from the host computer.
May be determined based on information from the host computer.

The counter 206 is an octal counter in this example, and counts the sampling clock φs.
The count value i is output. The counter 206 is reset every time the preset signal P is generated.

The mute control unit 207 includes an update amount Cc output from the shifter 205 and a counter 206.
And a pattern selection signal Bb of a later-described through / mute selection pattern output from the control unit 300
Is supplied. This mute control unit 207
It has a gate circuit (not shown). This gate circuit is a circuit that selects and executes either a through operation in which the update amount Cc supplied from the shifter 205 is directly output to the adder 208 or a mute operation in which “0” is output instead of the update amount Cc. is there.

Here, switching control of through / mute of the gate circuit is performed in synchronization with switching of the count value i of the counter 206. Mute control unit 2
Reference numeral 07 stores a table including a plurality of through / mute selection patterns for performing switching control of through / mute according to the count value i.

FIG. 2 illustrates the contents of this table. Each through / mute selection pattern is a time-series pattern including a plurality of through / mute selection bits that specify whether the gate circuit performs a through operation or a mute operation. In the present embodiment, an octal counter is used as the counter 206. Therefore, each through / mute selection pattern is composed of eight through / mute selection bits corresponding to each count value from “0” to “7”.

The mute control unit 207 selects a through / mute selection pattern specified by the pattern selection signal Bb from a plurality of through / mute selection patterns. Then, according to the count value i of the counter 206, each through / mute selection bit constituting the through / mute selection pattern is sequentially read, and the through / mute control of the gate circuit is performed according to the through / mute selection bit.

As illustrated in FIG. 2, a plurality of through / mute selection patterns in the table have different frequencies for instructing through. Pattern selection signal Bb =
When the through / mute selection pattern corresponding to “0” is selected, through is instructed for all count values while the count value i makes one round from “0” to “7”. Further, when the through / mute selection pattern corresponding to the pattern selection signal Bb = “1” is selected, the mute is instructed only once while the count value i makes one round from “0” to “7”, and the remaining is selected. Through is instructed seven times.
Therefore, in this case, the frequency at which a through instruction is issued within a unit time is 7/7 when the through / mute selection pattern corresponding to the pattern selection signal Bb = "0" is selected.
8 Then, the pattern selection signal Bb = “2”,
When the through / mute selection pattern corresponding to “3” is selected, the frequency at which a through instruction is performed within a unit time is determined by the selection of the through / mute selection pattern corresponding to the pattern selection signal Bb = “0”. 6/8 and 5/8 in the case where it is performed. Which of the through / mute selection patterns is selected is determined by the control unit 300.

The adder 208 adds the current value Cnew of the coefficient stored in the register 209 and the output data of the mute control unit 207. Register 209
Captures the output data of the adder 208 every time the write signal WR is generated, and holds it as a new current value Cnew. Each time the write signal WR is generated, the adder 208 and the register 209 control the mute control unit 2
An accumulator that accumulates the output data of 07 and outputs the accumulation result as the current value Cnew of the coefficient. The write signal WR is such that the current value Cnew of the coefficient is equal to the target value Cend from the second sampling period after the interpolation process is started.
Is generated by the control unit 300 in each sampling cycle until the interpolation processing is completed. The above is the details of the configuration of the coefficient changing circuit 200. Since the lower bits of the update amount Cc in the shifter 205 are rounded down,
Even when the current value Cnew does not reach the target value Cend slightly, the control unit 300 sets the target value Cend after the interpolation.
May be loaded into the register 209.

The control section 300 is a circuit for controlling each section described above. The control unit 300 divides the frequency of the reference signal so that the sampling clock φs and the arithmetic clock φ
Output c. Further, the control unit 300 includes a parameter M,
It stores a table of a correspondence relationship between a combination of Ba and the pattern selection signal Bb and a time required to change a coefficient from an initial value to a target value when the combination is adopted (hereinafter referred to as a coefficient change time). . Table 1 below exemplifies a part of a portion corresponding to M = “5” in this table.

[Table 1]

The control unit 300 designates a command for instructing a coefficient change from a host computer (not shown) above the DSP, information for specifying a coefficient to be changed, a coefficient target value Cend, and a required time for coefficient change. When the information is received, the parameters M and Ba and the pattern selection signal Bb that can obtain the designated coefficient change required time are obtained from the table of Table 1 above, and these parameters M and Ba are obtained.
And a pattern selection signal Bb to the coefficient changing circuit 200. Then, the write signal WR, the selection signal SEL, and the preset signal P are output to control the timing of the interpolation processing. The above is the details of the configuration of the DSP according to the present embodiment.

FIG. 3 is a time chart showing the operation of the DSP according to this embodiment. Hereinafter, the operation of the present embodiment will be described with reference to this time chart. As shown in FIG. 3, in this DSP, a sampling clock φs is generated in each sampling cycle, and a new sample is stored in the data shift register 10 in synchronization with the sampling clock φs. Then, in each sampling period, the coefficients C1 to Cn are read from the coefficient shift register 20, and a convolution operation using these is performed.

In this embodiment, when an instruction to change the coefficient and necessary control information are given from the host computer to the control unit 300, the convolution operation by the convolution operation unit 100 under the control of the control unit 300. In parallel, the interpolation process for gradually changing the coefficient from the initial value to the target value is performed.

As described above, the control unit 300 receives a command for changing the coefficient from the host computer, information for specifying the coefficient to be changed, and the target value C of the coefficient.
When receiving the information specifying the end and the required time for changing the coefficient, the parameters M and Ba and the pattern selection signal Bb for obtaining the specified required time for changing the coefficient are obtained from the table of Table 1 above, and these parameters M and Ba are obtained. And a pattern selection signal Bb to the coefficient changing circuit 200.

In the following, it is assumed that the parameter M = “3”, the parameter Ba = “0”, and the pattern selection signal Bb = “1” are given from the control unit 300 to the coefficient changing circuit 200. When the supply of these parameters is completed, the control unit 300 starts control for the interpolation processing.

More specifically, the control unit 300 outputs a selection signal SEL for selecting the coefficient C1 to be subjected to the interpolation processing. The selection signal SEL for selecting the coefficient C1 is
It is maintained until the interpolation processing ends, that is, until the current value Cnew of the coefficient C1 reaches the target value Cend.

The control unit 300 outputs a preset signal P and a coefficient target value Cend in synchronization with the first sampling clock φs after the start of the interpolation processing.

As a result, in the coefficient changing circuit 200, the counter 206 is reset by the preset signal P, and its count value becomes "0". Further, the coefficient C1 stored in the coefficient shift register 20 is selected as an initial value Cstart of the coefficient by the switching circuit 201, and the subtractor 202
, And is written to the register 209 by the preset signal P. Further, the difference Cd between the coefficient target value Cend and the initial value Cstart is calculated by the subtractor 202.
Cend-Cstart is calculated, the difference Cd is written into the register 203 by the preset signal P, and thereafter, the difference Cd is held as the total correction amount Cd until the interpolation processing ends.

Therefore, during the interpolation processing, the total correction amount Cd
And the update amount Cc determined by the above-described parameters M and Ba (see Equation 2 above) is supplied to the mute control unit 207.

In the mute control unit 207, a through / mute selection pattern corresponding to the pattern selection signal Bb = "1" is selected (see FIG. 2), and from the same pattern, a count value i (initially "0") is selected. Through /
The mute selection bit is read, and the gate circuit of the mute control unit 207 is switched through / mute according to this. In the example shown in FIG. 2, in the through / mute selection pattern corresponding to the pattern selection signal Bb = “1”, the through / mute selection pattern corresponding to the count value i = “0”
The mute selection bit indicates a mute operation. Therefore, the gate circuit of the mute control unit 207
While the count value i is “0”, “0” is added to the adder 208.
Output to The above is the operation in the first sampling cycle after the start of the interpolation processing.

The control unit 300 outputs a write signal WR in synchronization with the sampling clock φs in each subsequent sampling cycle. In each sampling cycle, the sum of the output data of the mute control unit 207 at that time and the coefficient Cnew stored in the register 209 is written to the register 209 by the write signal WR, and is newly written to the register 209. The coefficient Cnew is supplied to the coefficient register 20 via the switching circuit 201, and is written into the coefficient register 20 as the coefficient C1 by the selection signal SEL and the write signal WR.

In each sampling period, the count value i of the counter 206 is determined by the sampling clock φs.
Is incremented. Then, the pattern selection signal B
A through / mute selection bit corresponding to the new count value i is read from the through / mute selection pattern (see FIG. 2) corresponding to b = “1”, and the gate circuit of the mute control unit 207 is accordingly read. Is switched between through and mute. The above operation is performed in each sampling cycle until the interpolation processing ends.

Here, when the pattern selection signal Bb is “1”, the mute control unit 207 outputs “0” only when the count value i is “0”, and the count value i is “1” to “1”. When it is “7”, the update amount Cc is output. Therefore, while the count value i switches from “0” to “7” eight times, the accumulation process of increasing the current coefficient value Cnew by the update amount Cc is performed seven times.

Therefore, the time required for the coefficient C2 to change from the initial value Cstart to the target value Cend is: Becomes

The same applies to other conditions.
0 selects the appropriate parameters M and Ba and the pattern selection signal Bb from Table 1 based on the required coefficient change time instructed by the host computer to change the coefficient from the initial value Cstart to the target value Cend. The required time required for changing the coefficient can be finely adjusted.

In the above embodiment, the coefficient register 2
Although the case where one coefficient of 0 is interpolated has been described,
It is also possible to interpolate a plurality of coefficients simultaneously. In this case, the number of registers 20 is equal to the number of coefficients for performing the interpolation processing.
3 and the register 209 can be prepared.

[0042]

As described above, according to the present invention, when the coefficients used for signal processing are gradually changed from the initial value to the target value, the time required for the change can be set finely and arbitrarily.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a table of a through / mute selection pattern stored in a mute control unit in the embodiment.

FIG. 3 is a time chart for explaining the operation of the embodiment.

[Explanation of symbols]

 100 convolution unit 200 coefficient changing circuit 201 switching circuit 202 subtractor 203 register 204 adder 205 shifter 206 counter 207.・ Mute control unit 208 ・ ・ ・ Adder 209 ・ ・ ・ Register 300 ・ ・ ・ Control unit

Continued on the front page (72) Inventor Kazuo Nakamura 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Prefecture Inside Yamaha Corporation (72) Inventor Takaaki Makino 10-1 Nakazawa-cho, Hamamatsu-shi, Shizuoka Prefecture F-term in Yamaha Corporation (Reference) ) 5B056 HH00 5D108 AA01 AB19 AD02 5D378 GG25 JB00

Claims (2)

[Claims] 1. An update amount calculating means for calculating an update amount of the coefficient from a difference between a target value and an initial value of a coefficient to be changed, the initial value is initially set by a coefficient change instruction, and the update amount is set. And an accumulator that outputs the accumulation result as the current value of the coefficient. Each time a clock of a constant frequency is given, the accumulator according to a time-series pattern defined in advance corresponding to the target change time of the coefficient. And an accumulation control means for controlling whether or not to accumulate the update amount by the accumulator. 2. A convolution operation unit for storing sample data input in each sampling cycle and convolving a predetermined number of coefficients with a predetermined number of sample data input in the past; A coefficient changing circuit for changing over a desired time, wherein the coefficient changing circuit calculates an update amount of the coefficient from a difference between a target value and an initial value of the coefficient to be changed; The initial value is initialized by a coefficient change instruction, the update amount is accumulated, and an accumulator that outputs the accumulation result as a current value of the coefficient. Accumulation control means for controlling whether or not to accumulate the update amount by the accumulator according to a time series pattern defined in advance corresponding to the target change time of the coefficient. Digital signal processing apparatus.