JP2002187333A - Pattern data generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pattern data generator which can prepare various types of test pattern data as required by a user through a simple arrangement. SOLUTION: The pattern data generator generating a test pattern based on register data forming a pattern comprises means for setting the register data forming a pattern being generated, and means for generating pattern data based on the register data set by the setting means.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for generating pattern data for image evaluation used in digital copiers and printers.

[0002]

2. Description of the Related Art Conventionally, data of basic patterns (horizontal line pattern, vertical line pattern, lattice pattern, etc.) for image evaluation process output of a main scanning counter and a sub scanning counter based on fixed register data. It was created by a pattern data generation device that performs

[0003]

In the conventional pattern data generating apparatus, when a test pattern to be used is changed, it is necessary to prepare a circuit having a new combination of register data, which is inconvenient. To switch between a plurality of patterns and make them available, as shown in FIG.
A device that simply collects the devices 501 to 504 that individually generate the respective patterns and selects and outputs these outputs by the selector 505 is conceivable. However, when such a configuration is employed, the size of the entire apparatus becomes large. There is also a problem that there are many processing units that are not used after the patterns to be used are set, so that there is much waste.

An object of the present invention is to provide an apparatus for generating test pattern data which can prepare various test pattern data according to a user's request with a simple configuration.

[0005]

A first pattern data generation device according to the present invention is a device for generating pattern data based on register data for pattern generation, and is used for generating a pattern to be generated. It is characterized by comprising register data setting means and pattern data generating means for generating pattern data based on the register data set by the setting means.

A second pattern data generating device according to the present invention is the first generating device described above, wherein the setting means includes: a storage unit for storing register data of a plurality of types of patterns; A selecting unit that reads out register data of the selected pattern from the storage unit, wherein the pattern data generating unit generates pattern data based on the register data read by the selecting unit of the setting unit. Features.

A third pattern data generating apparatus according to the present invention is any one of the above pattern data generating apparatuses,
The pattern data generating means generates pattern data in which horizontal lines having a specified width are arranged at intervals specified based on the register data, based on the register data for pattern creation set by the setting means. It is characterized by including horizontal line data generation means.

According to a fourth aspect of the present invention, there is provided an apparatus for generating pattern data, comprising:
The pattern data generating means generates pattern data in which vertical lines having a specified width are arranged at intervals specified based on the register data, based on the register data for pattern creation selected by the setting means. And a vertical line data generating means.

A fifth pattern data generating apparatus according to the present invention is the fourth pattern data generating apparatus, wherein the pattern data generating means includes the horizontal line pattern data generated by the horizontal line data generating means. And a lattice pattern data generating means for outputting the logical sum of the vertical line pattern data generated by the vertical line data generating means as lattice pattern data.

A sixth pattern data generating apparatus according to the present invention is the fourth or fifth image evaluating pattern data generating apparatus, wherein the horizontal line data generating means generates the pattern data as the pattern data generating means. And a dot pattern data generating means for outputting a logical product of the horizontal line pattern data and the vertical line pattern data generated by the vertical line data generating means as dot pattern data.

A seventh pattern data generating apparatus according to the present invention is any one of the fourth to sixth pattern data generating apparatuses, wherein the horizontal line data generating means generates the pattern data as the pattern data generating means. Checker pattern data generating means for outputting exclusive OR of the horizontal line pattern data and the vertical line pattern data generated by the vertical line data generating means as checker-like pattern data.

[0012]

FIG. 1 is a block diagram showing a configuration of a copying machine 100. The reading unit 200 reads image data of a document to be copied, and outputs the read image data. The image forming unit 300 performs an image forming process on copy paper based on the image data read by the reading unit 200. The pattern data generation device 400 is started by operating an operation unit (not shown), generates pattern data for image evaluation selected by the operation unit, and outputs the generated data to the image forming unit 300.

Hereinafter, the configuration and function of the pattern data generation device 400 according to the present invention will be described in detail. Note that the reading unit 200 and the image forming unit 300 are the same as those included in a known copying machine, and therefore, further detailed description will be omitted.

FIG. 2 is a block diagram showing the configuration of the pattern data generation device 400. The pattern data generation device 400 includes a central processing unit (hereinafter, referred to as a CPU) 4.
01, a ROM 402 storing a register data database necessary for generating various test pattern data and a register data setting program, a memory 403 used as a work area when executing the program, types of test patterns to be created and Operation unit 4 including a plurality of keys 404a to 404k for selecting register setting values
04, a bit selection unit 410, an edge detection unit 420, a data selection unit 430, and an operation selection unit 440.

The operation unit 404 is shown in a simplified form in the figure, but in all, a selection key 404a for a horizontal line pattern at two pixel intervals, and a selection key 404 for a horizontal line pattern at four pixel intervals.
b, a selection key 404c of a vertical line pattern at one line interval,
Selection key 404d for a vertical line pattern with 4 line intervals, selection key 404e for a grid pattern composed of 4 pixels × 4 lines, and selection key 404f for a lattice pattern composed of 8 pixels × 4 lines, 4 pixels And a grid line pattern selection key 404g composed of four lines, a grid line pattern selection key 404h composed of eight pixels and eight lines, and a checker pattern selection key having four pixels × 4 lines as one block 404i, a selection key 404j of a pattern obtained by inverting the checker pattern, and a selection key 404k of a checker pattern having 8 pixels × 8 lines as one block.

The operation unit 404 has, in addition to the above configuration, for example,
A total of five test pattern types: a liquid crystal display for checking and setting the settings, a horizontal line pattern selection key, a vertical line pattern selection key, a grid pattern selection key, a grid line pattern selection key, and a checker pattern selection key A selection key and a numeric keypad for performing detailed settings of the selected test pattern may be used. in this case,
After selecting the type of the test pattern to be used, the user follows the selection screen displayed on the liquid crystal display unit, and uses the details of the test pattern, that is, how many pixels or how many lines, how many pixels or how many lines are used. Set whether to do so.

The contents of the register data setting process performed by the program stored in the ROM 402 will be described below with reference to the flowchart shown in FIG. The configurations and functions of the bit selection unit 410, the comparison unit 420, the shift selection unit 430, and the operation selection unit 440 will be described after the description of the register data setting process.

First, it waits until one of various test pattern selection keys 404a to 404k provided on the operation unit 404 is pressed to select a pattern to be generated (step S1). When the key 404a provided on the operation unit 404 is pressed to select a horizontal line pattern with two pixel intervals (step S2), a register for creating horizontal line data with two pixel intervals shown in Table 1 below. The data is selected,
A bit selection unit 410, an edge detection unit 420, a data selection unit 430, and an operation selection unit 44, which will be described in detail below.
The register data selected via the bus B is output to 0 (step S3). When the key 404b provided on the operation unit 404 is pressed to select a horizontal line pattern with four pixel intervals (step S2), the horizontal line data with four pixel intervals shown in Table 1 below is generated. Is selected, and the bus B is sent to each of the units 410 to 440.
(Step S4).

[Table 1]

When a key 404c provided on the operation unit 404 is pressed to select a vertical line pattern with one line interval (step S5), a vertical line pattern with one line interval shown in Table 2 below is created. The register data is selected and output to each of the units 410 to 440 via the bus B (step S6). Also, when the key 404d is pressed to select a vertical line pattern with a 4-line interval (step S
5) The register data for creating a vertical line pattern with a 4-line interval shown in Table 2 below is selected, and
To 440 via the bus B (step S
7).

[Table 2]

When the key 404e provided on the operation unit 404 is pressed to select a grid pattern composed of 4 pixels × 4 lines (step S8), the 4 pixels × 4 lines shown in Table 3 below are selected. The register data for creating the lattice pattern is selected and output to each of the units 410 to 440 via the bus B (step S9). When the key 404f is pressed to select a grid pattern composed of 8 pixels × 4 lines (step S8), register data for creating a grid pattern of 8 pixels × 4 lines shown in Table 3 below. Is selected, and a bus B is provided to each of the units 410 to 440.
(Step S10).

[Table 3]

When a key 404g provided on the operation unit 404 is pressed to select a grid line pattern with a 4-pixel interval (step S11), a grid line pattern with a 4-pixel interval shown in Table 4 below is created. Register data is selected,
The data is output to each of the units 410 to 440 via the bus B (step S12). When the key 404h is pressed to select a grid line pattern with an 8-pixel interval (step S11), register data for creating a grid line pattern with an 8-pixel interval shown in Table 4 below is selected. The data is output to each of the units 410 to 440 via the bus B (step S13).

[Table 4]

If the key 404i provided on the operation unit 404 is pressed to select a checker pattern having blocks of 4 pixels × 4 lines (step S14), a 4 pixel × 4 line checker shown in Table 5 below is selected. The register data for pattern creation is selected, and
0 is output via the bus B (step S15). When the key 404j is pressed and a pattern obtained by inverting the checker pattern set by the key 404i is selected (step S14), 4 pixels of "Table 5" shown below.
Register data for creating a 4-line inversion checker pattern is selected and output to each of the units 410 to 440 via the bus B (step S15). If the key 404k is pressed to select a checker pattern having 8 pixels × 8 lines as one block (step S14), a checker pattern for forming 8 pixels × 4 lines as one block shown in Table 5 below is used. Register data is selected,
The data is output to each of the units 410 to 440 via the bus B (step S17).

[Table 5]

Next, the configurations and functions of the bit selector 410, the edge detector 420, the data selector 430, and the operation selector 440, which generate pattern data in accordance with the register data set by the register setting process, will be described. I do.

FIG. 4 is a block diagram showing a configuration of the bit selection unit 410. The bit selection unit 410 selects an address of a pixel or a line to be used as a pattern. The selector 411 receives the count value MCOUNT [7: 0] of the 8-bit pixel counter in the main scanning direction and msel_reg [2: 0] as register data. When the value of msel_reg [2: 0] is nhex (where n is 0, 1, 2,...), the selecting unit 411 sets the interval of 2 ⁿ pixels, that is, the lower n bits of MCOUNT [7: 0]. (However, the least significant bit is 0) is "1"
Outputs mc0 = 1 at the time of. An inversion element (noted as NOT in the figure) 413 outputs an inversion value of mc0. Selector 4
12 is the value of register data not_reg [0], that is,
If the data value of the lower 0 bits of not_reg is 0, mc0 is set to mc
When not_reg [0] is 1, the inverted signal of mc0 is output as mc.

For example, when a horizontal line pattern with a two-pixel interval is selected, as shown in Table 1 above, msel_reg
[2: 0] is set to 1 hex, and not_reg [0] is set to 0. As a result, the selector 411 outputs mc of “1” at intervals of two pixels.

The selector 414 receives the count value FCOUNT [7: 0] of the 8-bit line counter in the sub-scanning direction and fsel_reg [2: 0] as register data. The value of fsel_reg [2: 0] is nhex (where n is 0, 1,
2,...), The selector 414 outputs 2 ⁿ
Mc0 = 1 at pixel intervals, ie, when the lower n bits of FCOUNT [7: 0] (where the least significant bit is 0) are “1”.
Is output. Inverting element (not shown in the figure) 416
Outputs the inverted value of fc0. The selector 415 outputs fc0 as fc when the value of the not_reg [0] register data, that is, the data value of the lower 0 bits of not_reg is 0, and outputs the inverted signal of fc0 when not_reg [1] is 1. Output as fc.

For example, when a vertical line pattern with a 4-line interval is selected, as shown in Table 2 above, fsel_r
eg [2: 0] is set to 2 hex and not_reg [1] is set to 0. As a result, fc of “1” is output from the selector 414 at an interval of 4 lines.

FIG. 5 is a block diagram showing the configuration of the edge detection section 420. The edge detection unit 420 detects, as an edge, a portion where the values of mc and fc output from the bit selection unit 410 change from “0” to “1”. The data of the detected edge is used when drawing a grid line pattern.

The shift circuit 421 includes a bit selection unit 41
The reference clock signal WCLK in the horizontal direction is input together with mc output from 0. The shift circuit 421 is connected to the WCLK
And outputs data delayed by one pixel from mc as mc1. When mc = 1 and mc1 = 0, the edge detection circuit 422 determines that it is the rising edge of the edge, and determines that mc_edg
e = 1 is output. In other cases, mc_edge = 0 is output.

The shift circuit 423 includes a bit selection unit 41
The reference clock signal LSYNC in the vertical direction is input together with fc output from 0. The shift circuit 423 has the LSY
Data obtained by delaying fc by one pixel based on NC is output as fc1. The edge detection circuit 424 determines that fc = 1 and fc1 =
If it is 0, it is determined that the edge is a rising point, and fc
Outputs _edge = 1. Otherwise, fc_edge = 0 is output.

FIG. 6 is a block diagram showing the configuration of the comparison / selection section 430. The comparison and selection unit 430 selects a line type constituting the pattern. More specifically, the bit selection unit 4
A pattern (for example, a grid pattern) composed of two pixels and lines having a width and an interval of two lines generated in step 10 and a pattern (for example, a lattice line) in which the width of the lines constituting the pattern is replaced with one pixel and one line Pattern).

The selector 431 includes a bit selection unit 410
And mc_edge output from the edge detection unit 420, and medge_sel_reg, which is register data, is input. The selector 431 sets m
If the value of edge_sel_reg is “0”, mc is output as mcdata. If the value of medge_sel_reg is “1”, mc_edge is set to mc.
Output as data. The selector 432 receives the fc output from the bit selector 410 and the fc_edge output from the edge detector 420, and
ge_sel_reg is input. The selector 432 selects the fedge_se
When the value of l_reg is “0”, fc is output as fcdata and f
When the value of edge_sel_reg is “1”, fc_edge is output as fcdata.

FIG. 7 is a block diagram showing the structure of the operation selecting section 440. The operation selection unit 440 selects an operation result of the operation unit specified by the selected pattern from among the plurality of operation circuits 441, 442, 443, 444, 445, and 446, and selects the operation result of the selected operation circuit. The logical sum (OR) is output as pattern data. The synchronization circuit 448 outputs the pattern data output from the OR circuit 447 in synchronization with WCLK.

The four AND circuits 441, 442, 44
4,446, one of the signal input terminals is mcdata,
fcdata, the logical product (AND) of mcdata and fcdata by the AND circuit 443, and the logical sum (OR) of mcdata and fcdata by the OR circuit 445 are input. AND circuits 441 and 44
The remaining signal input terminals of 2,444,446 have lower 0-bit data, lower 1-bit data, lower 2-bit data, lower 2 bits of cal_sel_reg [3: 0], which is 4-bit register data. The data of the third bit is sequentially input. The output of the AND circuit to which the bit data set to “1” of cal_sel_reg [3: 0] is input is applied to the OR circuit 447.

Specifically, cal_sel_reg [3: 0] = 0001
In the case of, only the mcdata from the AND circuit 441 is the OR circuit 4
47. In this case, the test pattern is a pattern pattern with only horizontal lines. Here, as shown in Table 1 above, msel_reg [2: 0] = 1hex, not_reg [1: 0] = 0h
When ex, medge_sel = 0hex is set, a horizontal line pattern with a 2-pixel interval as shown in FIG.
When [2: 0] = 2 hex, not_reg [1: 0] = 0 hex, and medge_sel = 0 hex, the pattern has a 4-pixel interval as shown in FIG.

When cal_sel_reg [3: 0] = 0010, only fcdata is output from the AND circuit 442 to the OR circuit 447.
Will be output to In this case, the test pattern is a pattern pattern consisting of only vertical lines. Here, Table 2 above
Fsel_reg [2: 0] = 0hexnot_reg [1: 0] = 0hex,
When fedge_sel = 0hex is set, a vertical line pattern with one line interval as shown in FIG. 10 is obtained, and fsel_reg [2:
When 0] = 2hex, not_reg [1: 0] = 0hex, and fedge_sel = 0hex, a vertical line pattern with a 4-line interval as shown in FIG. 11 is obtained.

When cal_sel_reg [3: 0] = 0011, when mcdata is output from the AND circuit 441,
Fcdata is output from the AND circuit 442. in this case,
The test pattern becomes a lattice pattern. Here, as shown in Table 3, msel_reg [2: 0] = 2hex, fsel_reg [2: 0] = 2hex, no
When t_reg [1: 0] = 0hex, medge_sel = 0hex, and fedge_sel = 0hex, a grid pattern of 4 pixels × 4 lines as shown in FIG. 12 is obtained, and msel_reg [2: 0] = 4hex, fsel_re
g [2: 0] = 2hex, not_reg [1: 0] = 0hex, medge_sel = 0hex, fedge
When _sel = 0 hex is set, a grid pattern of 8 pixels × 4 lines as shown in FIG. 13 is obtained.

Also, in the case where cal_sel_reg [3: 0] = 0011, a grid line pattern can be formed by setting medge_sel = 1hex and fedge_sel = 1hex. Specifically, as shown in Table 4, msel_reg [2: 0] = 1hex, fsel_reg
If [2: 0] = 1hex, not_reg [1: 0] = 0hex,
A grid line pattern with four pixels and four lines as shown in FIG. 14 is obtained, and msel_reg [2: 0] = 2hex, fsel_reg [2: 0] = 2he
When x, not_reg [1: 0] = 0hex is set, a grid line pattern having eight pixels and eight lines is formed as shown in FIG.

When cal_sel_reg [3: 0] = 0100, the AND circuit 444 outputs an AND operation result of mcdata and fcdata. In this case, as the test pattern, a dot-like pattern formed of an area where the horizontal line and the vertical line intersect is formed. Although the operation unit 404 is not provided with a key for selecting the dot pattern, it goes without saying that
A key for selecting this may be provided.

When cal_sel_reg [3: 0] = 1000, the AND circuit 446 outputs an XOR operation result of mcdata and fcdata. In this case, the test pattern becomes a checker pattern. Here, as shown in Table 5, ms
el_reg [2: 0] = 2hex, fsel_reg [2: 0] = 2hex, not_reg [1: 0] = 0
When hex, medge_sel = 0 hex and fedge_sel = 0 hex are set, a checker pattern having 4 pixels × 4 lines as one block is formed as shown in FIG. msel_reg
[2: 0] = 2hex, fsel_reg [2: 0] = 2hex, not_reg [1: 0] = 1hex, me
If dge_sel = 0hex, fedge_sel = 0hex,
As shown in FIG. 17, a checker pattern obtained by inverting the checker pattern of FIG. 16 is formed. Also, msel_r
eg [2: 0] = 3hex, fsel_reg [2: 0] = 3hex, not_reg [1: 0] = 0hex,
When medge_sel = 0hex and fedge_sel = 0hex are set, a checker pattern having 8 pixels × 8 lines as one block is formed as shown in FIG.

As described above, the pattern data generating apparatus 400 according to the embodiment utilizes the output of the bit selection unit 410 for generating the horizontal line and the horizontal line pattern data to use the grid pattern, the grid line pattern, and the dot. Generates a shape pattern and a checker pattern. This makes it possible to simplify the configuration as compared with a case where devices for individually and independently generating data of each pattern are collected and their outputs are selectively output using a selector. Another advantage is that the number of unused processing units when a pattern is set can be reduced.

In the pattern data generation device 400 according to the embodiment, a total of 11 types of patterns shown in Tables 1 to 5 are prepared. As will be easily understood from the above description, the value of each register By changing the number, a very large number of patterns can be formed. For example, the operation unit 4
It is conceivable that a liquid crystal panel is provided as 04 so that the value of each register can be set more freely in an interactive manner. For example, the selection screen of “thicken / increase” the width and interval of the horizontal line is displayed. If “thick / increase” is selected, the value of msel_reg [2: 0] is selected. Increase. Also, display the selection screen of "Normal" 普通 "Edge line" for the vertical line type, and when "Edge line" is selected,
Set fedge_sel = 1hex. By adopting such a configuration, it is possible to more finely set the pattern, the width of the line to be used, the interval between the lines, and the like.

[0043]

According to the first pattern data generating apparatus of the present invention, register data for generating pattern data can be selected and set from a plurality of patterns, and data of various patterns can be set with a simple configuration. Can be generated.

The second pattern data generating device of the present invention can set register data for generating pattern data only by selecting a pattern to be used from a plurality of types of patterns stored in advance. Thus, data of various patterns can be generated with a simple configuration.

A third pattern data generating apparatus according to the present invention is any of the above generating apparatuses, and can easily generate horizontal line pattern data in which horizontal lines of various widths are arranged at selected intervals. it can.

The fourth pattern data generating apparatus of the present invention is any one of the above-described generating apparatuses, and simply generates vertical line pattern data in which vertical lines of various widths are arranged at selected intervals. be able to.

The fifth pattern data generating apparatus of the present invention is any one of the above-described generating apparatuses, and can easily generate grid pattern data in which lines of various widths are arranged at selected intervals. .

According to a sixth aspect of the present invention, there is provided a pattern data generating apparatus according to any one of the above-described apparatuses, which can easily generate dot pattern data composed of vertical lines and horizontal lines having various widths. Can be.

A seventh pattern data generating apparatus according to the present invention is any one of the above generating apparatuses, and can easily refine checker pattern data composed of vertical lines and horizontal lines of various widths. .

[Brief description of the drawings]

FIG. 1 shows a pattern data generation device 4 according to an embodiment.
FIG. 1 is an overall configuration diagram of a copying machine provided with 00.

FIG. 2 is a block diagram showing a configuration of a test pattern generator.

FIG. 3 is a flowchart of a register data setting process.

FIG. 4 is a configuration diagram of a bit selection unit.

FIG. 5 is a configuration diagram of an edge detection unit.

FIG. 6 is a configuration diagram of a data selection unit.

FIG. 7 is a configuration diagram of an operation selection unit.

FIG. 8 is a diagram showing a horizontal line pattern at two pixel intervals.

FIG. 9 is a diagram showing a horizontal line pattern at an interval of 4 pixels.

FIG. 10 is a diagram showing a vertical line pattern with one line interval.

FIG. 11 is a diagram showing a vertical line pattern with four line intervals.

FIG. 12 is a diagram showing a grid pattern of 4 pixels × 4 lines.

FIG. 13 is a diagram showing a grid pattern of 8 pixels × 4 lines.

FIG. 14 is a diagram showing a grid line pattern of 4 pixels × 4 lines.

FIG. 15 is a diagram showing a grid line pattern of 8 pixels × 4 lines.

FIG. 16 is a diagram showing a checker pattern of 4 pixels × 4 lines.

FIG. 17 is a diagram showing a pattern obtained by inverting the checker pattern shown in FIG. 16;

FIG. 18 is a diagram showing a checker pattern of 8 pixels × 8 lines.

FIG. 19 is a block diagram illustrating a configuration of a device that generates a plurality of pattern data by collecting conventional devices.

[Explanation of symbols]

100 copier, 200 reading unit, 300 image forming unit, 4
00 pattern data generation device, 401 CPU, 40
2 ROM, 403 memory, 404 operation unit, 410
Bit selector, 420 edge detector, 430 data selector, 440 operation selector

Claims (7)

[Claims] An apparatus for generating pattern data based on register data for creating a pattern, comprising: means for setting register data for creating a pattern to be generated; and register data set by the setting means. And a pattern data generating means for generating pattern data. 2. The pattern data generating apparatus according to claim 1, wherein the setting unit selects a pattern to be generated, a storage unit that stores register data of a plurality of types of patterns, and selects the selected pattern. The pattern data generating means generates pattern data based on the register data read by the selecting section of the setting means. Generator. 3. The pattern data generating apparatus according to claim 1, wherein said pattern data generating means is specified based on register data for pattern creation set by said setting means. Pattern data generating means for generating pattern data in which horizontal lines having different widths are arranged at intervals specified based on the register data. 4. The pattern data generating device according to claim 1, wherein said pattern data generating means is based on register data for pattern creation selected by said setting means. And a vertical line data generating means for generating pattern data in which vertical lines having a specified width are arranged at intervals specified based on the register data. 5. The pattern data generating apparatus according to claim 4, wherein the pattern data generating means includes horizontal line pattern data generated by the horizontal line data generating means and vertical line data generating means. A pattern data generating apparatus, comprising: a grid pattern data generating unit that outputs a logical sum of the vertical line pattern data obtained as grid pattern data. 6. The pattern data generating apparatus according to claim 4, wherein the pattern data generating means includes a horizontal line pattern data generated by the horizontal line data generating means and a vertical line data. A pattern data generating apparatus, comprising: dot pattern data generating means for outputting the logical product of the vertical line pattern data generated by the generating means as dot pattern data. 7. The pattern data generating apparatus according to claim 4, wherein said pattern data generating means includes horizontal line pattern data generated by said horizontal line data generating means; An apparatus for generating pattern data, comprising: checker pattern data generating means for outputting exclusive OR of vertical line pattern data generated by vertical line data generating means as checker-like pattern data.