JP2002185426A - Transmitter integrating a plurality of decoding systems - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a digital transmitter/receiver of an OFDM signal, or the like, in which a more stable transmission is realized by dealing with the phase shift of an FFT gate caused by inevitable variation in the receiving level of the main wave and a reflected wave. SOLUTION: In a digital transmitter for transmitting/receiving a transmission stream comprising a plurality of symbols having a valid data interval and a guard interval generated by multi-carrier modulating input digital information, a plurality of systems of fast Fourier transforming section and decoding section are provided when the digital information is multi-carrier demodulated by detecting the switching point of symbol interval from the received transmission stream. Each system is operated in the extraction phase of different valid data interval and any one of decoded output data obtained from respective systems is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an orthogonal frequency division multiplex (OFDM).
ex) It relates to a digital transmission device using a modulation method or the like.

[0002]

2. Description of the Related Art In recent years, digital broadcasting has been studied in Europe, the United States, and Japan, and the adoption of an OFDM modulation system as a modulation system is considered to be promising. This O
The FDM modulation method is a type of multi-carrier modulation method and is a combination of a large number of digitally modulated waves. At this time, QPSK (Q
An uadrature Phase Shift Keying (four-phase phase shift keying) method or the like is used, and an OFDM signal that is a synthetic wave can be obtained. Here, when this OFDM signal is expressed by a mathematical formula,
It looks like this: First, assuming that the QPSK signal of each carrier is α _k (t), this can be expressed by equation (1). α _k (t) = _ak (t) · cos (2πkft) + b _k (t) · sin (2πkft) (1) where k indicates a carrier number, a _k (t), b _k (t)
Is the data of the k-th carrier and takes a value of [-1] or [1]. Next, assuming that the number of carriers is N, the OFDM signal is a combination of N carriers, and if this is β _k (t), this can be expressed by the following equation (2). β _k (t) = Σα _k (t) (where k = 1 to N) (2) By the way, in the OFDM modulation method, a guard interval is added to a signal in order to reduce the influence of multipath. It is common to add. This OFDM signal is composed of the above signal unit, and the signal unit symbol includes, for example, 1024 valid samples and guard interval data 48
Symbol 894 of 1072 samples to which samples are added
Each set is composed of a repetition of a stream unit called a frame consisting of 900 symbols in which six sets of synchronization symbols are added.

FIG. 8 is a block diagram showing a basic configuration of a modulation / demodulation unit in an OFDM transmission apparatus according to the prior art.
erseFast Fourier Transform) section 3
A, a transmission side processing unit 101 including a guard addition unit 3B, a synchronization symbol insertion unit 5, a clock oscillator 6, and a quadrature modulation processing unit 8, and a transmitter Tx having a transmission antenna (not shown)
Receiving antenna and ACG unit 9A, quadrature demodulation processing unit 9B, synchronization detection & correlation unit 4A, FST correction unit 4
B, a receiving side processing unit 203 ′ including an FFT (Fast Fourier Transform) unit 3 C, a decoding unit 2 R, a transmission line decoding unit 1 R, and a voltage controlled clock oscillator 10.
And a receiver Rx having
x and the receiver Rx are connected by, for example, a wireless transmission line L using radio waves. Hereinafter, the modulation / demodulation processing of the OFDM signal will be described with reference to FIG. Transmission side processing unit 101
Din continuously input to the transmission line coding unit 1T of FIG.
Is processed for each frame of, for example, 900 symbols, and within this frame period, every 894 information symbols excluding 6 synchronization symbol periods, for a total of 800 sample periods 1 to 400 and 625 to 1024 Is output as the rate-converted data Dii in the intermittent state. Further, the transmission path encoding unit 1T transmits the frame control pulse FS on the transmission side every 900 symbols which is a frame period.
T is generated and supplied to other blocks as a frame pulse signal indicating the start of a synchronization symbol period. Encoding unit 2
T encodes the input data Dii and outputs data Rf and If mapped to two axes, I-axis and Q-axis. I
The FFT unit 3A regards these data Rf and If as frequency components and converts them into a time axis signal R (real component) and I (imaginary component) consisting of 1024 samples. Guard addition part 3B
In the waveforms in the start period of the time-axis signals R and I consisting of 1024 samples, for example, the waveform of the first 48 samples is added after 1024 samples, and information symbols Rg and Ig consisting of a time-axis waveform of 1072 samples in total are added. Output. These 48 samples serve as a buffer band when a reflected wave is mixed.

The synchronizing symbol insertion unit 5 inserts a synchronizing waveform signal consisting of, for example, six symbols stored in a memory or the like in advance into each of the information symbols Rg and Ig for every 894 samples, thereby forming a frame structure. Data R
Create sg and Isg. Here, as the synchronization symbol signal, for example, a null (NU) for roughly finding the existence of the synchronization symbol group without a signal during one symbol period
(LL) symbol, a special symbol having a signal component in only one carrier in one symbol period (hereinafter referred to as CW symbol), a waveform that changes from the lower limit frequency to the upper limit frequency of the transmission band in one symbol period. , A sweep symbol (SWEEP) symbol for accurately determining a symbol switching point, a reference symbol (hereinafter, referred to as a reference symbol) indicating a phase reference required for differential detection and demodulation, and the like. When there are six sets of synchronization symbols, two additional spare symbols are added to the above. These data Rsg and Isg are supplied to the quadrature modulation processing unit 8, where D / G
An A-converter 81, a quadrature modulator 82, and a local oscillator 83 generate an OFDM modulated wave signal RF with a carrier of a frequency Fc, amplify it at a high frequency, and transmit it to a transmission line L via a transmission antenna (not shown). Will be. As a transmission band, a UHF band or a microwave band is used. Here, an example of a synchronization symbol and a data symbol of the output OFDM signal is shown in FIG. The clock CK (frequency 1) required for processing in the transmitter Tx
6 MHz) is supplied from the clock oscillator 6 to each block as the transmission side clock CKd.

[0005] The OFDM modulated wave signal RF transmitted as described above is transmitted to a receiver R via a receiving antenna (not shown).
The signal is input to the quadrature demodulation processing unit 9B via the AGC unit 9A, which is a high frequency unit of x, and is multiplied by the quadrature demodulator 91 by the local signal of the frequency Fc ′ supplied from the voltage controlled oscillator 93 to generate the baseband signal. , Are digitized by the A / D converter 92, and the data R'sg and I '
Converted to sg. These data R'sg and I'sg are FF
T (Fast Fourier Transform) section 3C
And generates a gate signal for determining a data period of 1024 samples to be used as an FFT based on the pulse FSTrc, and by excluding 48 samples that are a buffer band, the time-axis waveform signal R'sg, I 'sg is converted into frequency component signals R'f and I'f. Then, these frequency component signals R'f and I'f are identified and decoded by the decoding unit 2R, become data D'o, and output as a continuous signal Dout by the transmission line decoding unit 1R. You. On the other hand, the data R'sg and I'sg are also input to the synchronization detection and correlation unit 4A, where a synchronization symbol group is detected, and a pulse FSTr serving as a frame pulse is extracted. This pulse FSTr becomes a frame control pulse of the receiving side Rx, and is supplied to each block of the receiver Rx. Also,
The synchronization detecting and correlating unit 4A includes a clock CKrc generated from the voltage controlled clock oscillator 10, data R'sg, and I '.
Compare the synchronous components of sg, and calculate the correlation output Sc according to the comparison result.
Is output to the FST correction unit 4B. Then, the control voltage VC is generated by the FST correction unit 4B, thereby controlling the voltage-controlled clock oscillator 10 and the clock CK having the correct cycle.
An rc is generated and supplied to each block on the receiving side.

Next, the configuration operation of the receiver Rx will be described. In the receiver Rx, the transmitted signal of the frame configuration is input to the AGC unit 9A, where the control signal Sa for correcting the received signal level to an appropriate level is generated and the level is changed. The OFDM signal of the frame configuration that has been set to the appropriate level in the AGC unit 9A is output to the quadrature demodulation processing unit 9B
Is input to The processing here is opposite to the transmitter Tx,
The quadrature demodulator 91 extracts an output demodulated by a carrier signal of a frequency Fc ′ output from the voltage controlled oscillator 93 as a real part signal, and extracts an output obtained by shifting the phase of the carrier signal by 90 ° as an imaginary part signal. It is. Then, the demodulated analog signals of the real part and the imaginary part are converted into digital signals by the A / D converter 92. The synchronization detecting and correlating unit 4A searches for a frame delimiter from the received signals R'sg and I'sg, and
It outputs STrc and outputs a correlation output Sc. Then, the FFT unit 3C delimits the symbol based on the pulse FSTrc, performs OFDM demodulation by performing the Fourier transform as described above, and outputs data R′f and I′f. The decoding unit 2R uses, for example, a ROM table method,
Data R'f and I'f are identified, and data D'o is calculated. The transmission path decoding unit 1R performs deinterleaving processing, energy despreading processing, error correction processing, and the like, and obtains continuous digital data Dout and BER indicating the error correction processing status.
(Bit error rate) The signal Sb indicating the state and the receiving side clock signal CK _RX are output.

[0007] In the receiver, a delayed signal (hereinafter, referred to as a reflected wave) generated by reflection of a transmission signal itself (hereinafter, referred to as a main wave) from a mountain, a building, or the like in addition to a transmitted signal itself (hereinafter, referred to as a main wave) is synthesized. In addition, a transmission signal having multipath fading is received. Here, a case where there is a reflected wave whose arrival time is slower than that of the main wave and the magnitude thereof changes every moment will be described with reference to FIG. Case 1 is a case where the reception level of the main wave and the reflected wave is 10: 0, and is synchronized with the main wave. Therefore, the FSTrc pulse representing the symbol delimiter output from the synchronization detection & correlation unit 4A is the symbol of the reception signal. Is set to a time position that indicates the correct break in. FFT unit 3
C performs an FFT process on the FSTrc pulse according to a gate signal delayed by a time tg corresponding to a guard interval. In this case, since there is only a component of the current symbol due to the main wave, there is no interference between symbols, accurate decoding is possible in the decoding unit 2R, and the error rate is low. Case 2 is a case where the reception levels of the main wave and the reflected wave are 1: 9. In this case, in order to synchronize with the reflected wave, FSTrc representing the symbol delimiter output from the synchronization detection & correlation unit 4A is used.
The pulse is set at the symbol break of the reflected wave. F
The FT unit 3C creates a gate signal and performs FFT processing according to the FSTrc pulse. In this case, since the next symbol component due to the main wave is slightly mixed immediately before the end of the gate signal, interference between symbols slightly occurs, and the decoding unit 2R
There is a slight error effect on the decoding of. In case 3, the reception levels of the main wave and the reflected wave are 9:
It shows a case where it returns to 1. In this case, the FSTrc pulse is calculated based on the state in which the reception level of the main wave and the reflected wave at which the previous synchronization symbol appeared is 1: 9,
The phase of the FSTrc pulse remains shifted for a period of several hundred symbols, which is inserted only every 900 symbols (about 60 msec) until the next synchronization symbol appears.
That is, the FSTrc pulse is set at the symbol break of the delayed reflected wave, and the FFT unit 3C performs the FFT processing so as to include the next symbol component which is the main wave, resulting in large interference between symbols and decoding. Many errors occur in the decoding result of the conversion unit 2R. The state of this case 3 is also called a pre-ghost, and the effect of the card interval peculiar to OFDM cannot be obtained, so that it is the state in which the error is the largest. Such a state is inevitable and stable transmission is difficult.

[0008]

In the conventional configuration described above, if the states of the main wave and the reflected wave change every moment, the state as in the above case 3 frequently occurs and the transmission state becomes unstable. . In this state, the phase of the FSTrc pulse is corrected at the next timing when the synchronization symbol inserted only at a maximum of about 60 msec appears.
This continues until the phase of the gate signal is normalized. Note that the synchronization symbol insertion cycle is standardized and cannot be changed without permission. Therefore, a situation where the phase of the gate signal becomes inappropriate is inevitable. The present invention eliminates these drawbacks and realizes more stable transmission in a digital transmission receiving apparatus for OFDM signals and the like by coping with an FFT gate phase shift caused by a change in the reception level of a main wave and a reflected wave which is difficult to avoid. The purpose is to:

[0009]

In order to achieve the above object, the present invention provides a transmission stream composed of a plurality of symbols each consisting of a valid data period and a guard interval created by multi-carrier modulation of input digital information. In the digital transmission apparatus for transmitting and receiving, when detecting the switching point of the symbol period from the received transmission stream and performing multi-carrier demodulation of digital information, a plurality of fast Fourier transform processing units and decoding processing units are provided, The system is configured to operate with the extraction phases of different valid data periods and to select any one of the decoded output data obtained from the respective systems. Also, the criterion for selecting any one of the decoded output data obtained from each of the above-described systems is determined based on the degree of error in the decoding process. Further, a plurality of transmission path decoding units are provided, and a criterion for selecting any one of the decoding output data obtained from the transmission path decoding units of the respective systems is determined based on each of the transmission path decoding units. Is determined depending on the number of errors during the error correction processing. In addition, a criterion for selecting any one of the decoded output data obtained from each of the above-described systems is based on the degree of error in decoding processing and the number of errors in error correction processing in the transmission path decoding unit. Is determined from some two situations. That is, a plurality of FFT processing & DEM units including an FFT processing unit and a DEM processing unit for decoding are provided, and each system is operated at a different FFT gate phase.
The decoded data is obtained from each system. And DEM
By referring to the error output at the time of decoding simultaneously output from the processing unit, the decoded data of the system with the least level is regarded as a system with little inter-symbol interference, selected, and subjected to transmission path decoding including error correction. , To realize more stable transmission. As a result, even if the FSTrc pulse has an inappropriate phase, a plurality of FFT
By performing FFT decoding with the gate, one or more of the systems have a gate phase close to normal, and a data output with a small decoding error can be obtained.

[0010]

FIG. 1 is a block diagram showing an entire configuration of an embodiment of the present invention, which will be described below in detail.
Here, those having the same reference numerals as those shown in FIG. 8 indicate equivalents. The outputs R'sg and I'sg of the quadrature demodulation processing unit 9B of the reception-side processing unit 203 are connected to the synchronization detection & correlation unit 4A and the A-system F
The signals are input to the FT processing & DEM unit 204-A and the B-system FFT processing & decoding (DEM) unit 204-B. The FSTrc signal from the synchronization detection and correlation unit 4A is input to the FST correction unit 4B, the phase correction units 4C-A and 4C-B, and the transmission path decoding unit 1R. A-system decoded data D'oA and decoding error eo-A from B-system FFT processing & DEM unit 204-A and B-system FFT processing & DEM unit 204-B, and B-system decoding data D'oB and decoding error eo. -B is input to the selection unit 205. The output of the selection unit 205 is input to the transmission path decoding unit 1R. Next, the operation of each unit will be described. The phase correction unit 4C-A outputs the FSTrc phase
STrc-A is output. The phase correction unit 4C-B uses the FS
FSTrc-B with a delayed Trc phase is output. The DEM unit 2Rx converts DQPSK (D
A decoding process of an ifferentialQuadrature Phase Shift Keying (differential four phase shift keying) signal is performed. In the demodulation of DQPSK, the difference from the previous mapping point is the transmission data, and the phase is changed by 90 ° from the previous mapping point. However, in actual transmission, a situation deviating from the 90 ° unit occurs due to various factors. How much the phase difference from the previous symbol deviates from 90 ° is D
This is an amount indicating the accuracy of demodulation of QPSK. If the carrier level is equal to or higher than the appropriate level, DQPSK demodulation with higher accuracy can be performed. Therefore, these 90 °
The deviation from the unit and the carrier level are output as demodulation error eo. It should be noted that the modulation side has another modulation scheme, for example, 8
In the case of PSK or the like, demodulation of that method is naturally performed, and eo is output with a deviation accuracy of 45 °. Selector 2
In step 05, the demodulation errors eo-A and eo-B from the two systems are compared, and the eo system having a smaller value is selected and output.

By the above operation, the two-system FFT processing & DEM units 204-A and 204-B are supplied to the transmission path decoding unit 1R.
, The output D′ o of the system with high DQPSK demodulation accuracy is selected and input one by one. Here, referring to FIG. 2, case 1 in which the reception levels of the main wave and the reflected wave described above (FIG. 10) are 10: 0, and the FSTrc pulse is in a normal state in which the main wave is set to a symbol delimiter
When the reception levels of the main wave and the reflected wave return to 9: 1 from the state once synchronized with the reflected wave, the FSTrc pulse is
Case 3 is shown, which is an incorrect state set at the symbol break of a delayed reflected wave, and each operation will be described. In case 1, the A system has a normal FFT gate phase set to the FSTrc pulse, and the B system has an FFT gate phase set earlier than the normal phase. That is, in Case 1 in which the FSTrc pulse is in a normal state, the decoding error becomes very low in the A system because the correct FFT processing does not include the preceding and following symbol components, but the B system uses the previous symbol component. Since the FFT processing is performed in a form including the decoding error, the decoding error increases. On the other hand, in case 3, since the FSTrc pulse is set at the symbol break of the reflected wave and lags behind the normal phase, in the A system, the FFT processing including the subsequent symbol component is performed, and the decoding error becomes extremely high. The B system performs FFT processing without including the preceding and succeeding symbol components, so that the decoding error is reduced. So, in case 1,
The output of the A system with a small decoding error is selected, and in case 3, the output of the B system with a small decoding error is selected.

Next, an example of a specific block configuration of the selection unit 205 is shown in FIG. 3 and will be described in detail below. The output D'oA from the A system is connected to the input A of the selector 205-1. Similarly, the demodulation error eo-A from the A system is connected to the input A of the magnitude comparator 205-2. The output D'oB from the B system is connected to the input B of the selector 205-1. Similarly, the demodulation error eo-B from the B system is supplied to the magnitude comparator 205
Connected to input B of -2. The output of the selector 205-1 is D'o
Output as -S. Output S of size comparator 205-2
Is connected to the control terminal of the selector 205-1. less than,
The operation of each unit will be described. The large / small comparator 205-2 is
When input A> input B, a level H is output to the output terminal S, and when input A <input B, a level L is output. The selector 205-1 selects and outputs the input A when the control terminal is at the level H, and selectively outputs the input B when the control terminal is at the level L. The selection unit 205 compares the decoding errors eo of the A system and the B system as a whole, and outputs a decoding error of a small system.

FIG. 4 shows a DEM unit 2R for detecting a phase error.
An example of a specific block configuration of x will be shown and described below. The input signals R'f and I'f are connected to the input terminals of the phase demodulator 2Rx-1 and the phase calculator 2Rx-2. The output of the phase demodulator 2Rx-1 is output as D'o. The output of the phase calculator 2Rx-2 is connected to the phase difference calculator 2Rx-3 and the delay unit 2Rx-4. The output of the delay unit 2Rx-4 is connected to the other input terminal of the phase difference calculator 2Rx-3. The operation of each unit will be described below. The phase demodulator 2Rx-1 performs DQPSK demodulation based on R'f and I'f to reproduce data. The phase calculator 2Rx-2 is
Calculating the phase angle of the mapping point from the R'f and I'f signals,
Output. The phase difference calculator 2Rx-3 calculates a phase error with a unit of 90 °. Specifically, the mapping point of the previous symbol is 40 °, and the mapping point of the current symbol is 135 °.
In the case of °, since the angle difference is 95 °, a decoding error eo having a value indicating 5 ° which is a difference from the 90 ° unit is output.
When the mapping point of the previous symbol is 40 ° and the mapping point of the current symbol is 30 °, the difference between the angles is −
Since it is 10 °, a decoding error eo having a value indicating 10 °, which is a difference from the 90 ° unit, is output. Here, the DEM unit 2Rxx for phase error & amplitude detection shown in FIG. 5 may be used instead of the DEM unit 2Rx for phase error detection. This configuration will be described below. The input R'f and I'f are
It is connected to the input terminals of the phase demodulator 2Rx-1, the phase calculator 2Rx-2, and the amplitude calculator 2Rx-5. Phase demodulator 2R
The output of x-1 is output as D'o. Phase calculator 2
The output PH of Rx-2 is calculated by the phase difference calculator 2Rx-3 and the delay 2
Connected to Rx-4. The output of the delay unit 2Rx-4 is connected to the other input terminal of the phase difference calculator 2Rx-3.
The output AM of the amplitude calculator 2Rx-5 is equal to the amplitude adder 2Rx
-6 and the delay unit 2Rx-4. Phase difference calculator 2R
The output ep of x-3 and the output ea of the amplitude adder 2Rx-6 are connected to a combining (MIX) unit 2Rx-7.

The operation of each section will be described below. The phase demodulator 2Rx-1 uses DQPSK based on R'f and I'f.
Demodulate and reproduce the data. Phase difference calculator 2Rx-3
Is the phase angle difference e of the mapping point from the R'f and I'f signals.
Calculate and output p. The amplitude calculator 2Rx-5 calculates the amplitude of the mapping point. The amplitude adder 2Rx-6 obtains an addition result ea of the amplitudes of the previous and current symbols of the delay decoding. This is because when the amplitude is insufficient, the reliability of the phase decoding is low. These are multiplied by an appropriate coefficient by the MIX unit 2Rx-7, and then added, to obtain an error output eo. The FFT unit 3C in FIG. 1 uses the phase correction unit 4C to output the time axis waveforms R'sg and I'sg with guard intervals.
The FFT processing is performed to extract the output of the frequency component signals R'f and I'f to the DEM unit 2Rx. In this case, it has been described that only the time phase changes and the output timing does not change.

FIG. 6 is a block diagram showing the overall configuration of the second embodiment of the present invention, which will be described in detail below.
Here, the same reference numerals as those shown in FIGS. 1 and 8 denote the same components, and a description thereof will be omitted. This is to select the system having the lowest value among the error situations Sb from the two transmission line decoding units 1R-A and 1R-B. The decoding unit of each system may be the decoding unit 2R having no error output function. A
The output D'oA of the system is connected to the transmission line decoding unit 1R-A, and the output D'oB of the system B is connected to the transmission line decoding unit 1R-B. The error status Sb-A and the error status Sb-B of the B system are selected by the selector 2
05 is input. The selector 205 selects the smaller one of the error situations Sb of the transmission path decoding of the A system and the B system and outputs digital information.

FIG. 7 is a block diagram showing the overall configuration of a third embodiment of the present invention, which will be described in detail below.
Here, the same reference numerals as those shown in FIGS. 1 and 8 denote the same components, and a description thereof will be omitted. This is to add the error status Sb from the two transmission path decoding units 1R-A and 1R-B and the decoding state error eo, and select the system having the lowest value in each system. The output D'oA of the A-system DEM unit 2Rx is connected to the transmission line decoding unit 1R-A, and the output D'oB of the B-system DEM unit 2Rx is connected to the transmission line decoding unit 1R-B. The decoding error eo-A of the A system is calculated by the transmission path decoding unit 1R
After being added by the MIX 206-A and the error status Sb-A of -A, the result is input to the selector 205. The B-system decoding error eo-B is added to the error status Sb-B of the transmission path decoding unit 1R-B by the MIX 206-B, and then input to the selector 205. The selector 205 selects the smaller one of the decoding errors of the A system and the B system and the error condition of the transmission path decoding, and outputs digital information. Note that MIX 206 is:
Instead of adding 1, one may be added after weighting each. Although the above description has been made with reference to the example of DQPSK decoding in two systems, a decoding method such as 8PSK or 16DAPSK may be used. Although the above description has been made with reference to an example including two systems, a total of three or more systems including a system without phase correction are provided, and the phase of the FSTrc pulse is advanced.
As the three or more types of delay, a system in which the decoding error eo has the smallest value may be selected.

[0017]

As described above, according to the present invention,
Even when the gate position of the FFT is temporarily inappropriate, the FFT and DEM are performed at the gate position set to advance or delay.
By performing the processing, data output with a small decoding error can be obtained from at least one of the systems, that is, only signals of the system with the least error are selected, so that the reception performance is greatly improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a schematic diagram showing a basic operation at a plurality of gate positions according to the present invention.

FIG. 3 is a block diagram illustrating a configuration of a selection unit 205 according to the present invention.

FIG. 4 is a block diagram showing a configuration of a decoding unit 2Rx of the present invention.

FIG. 5 is a block diagram showing another configuration of the decoding unit 2Rxx of the present invention.

FIG. 6 is a block diagram showing the overall configuration of a second embodiment of the present invention.

FIG. 7 is a block diagram showing the overall configuration of a third embodiment of the present invention.

FIG. 8 is a block diagram showing the entire configuration of the related art.

FIG. 9 is a diagram showing a frame configuration of an OFDM signal.

FIG. 10 is a schematic diagram showing a conventional gate position inappropriate operation.

[Explanation of symbols]

1R: transmission path decoding unit, 2Rx, 2Rxx: decoding unit, 3
C: FFT section, 4A: Synchronization detection & correlation section, 4B: FST
Correction unit, 4C-A, 4CB: phase correction unit, 10: voltage control clock oscillation unit, 9A: AGC unit, 9B: quadrature demodulation processing unit, 203: reception side processing unit, 204-A: A system FF
T processing & DEM part, 204-B: B system FFT processing & DE
M unit, 205: selection unit, 206: MIX unit.

Claims (4)

[Claims] 1. A digital transmission apparatus for transmitting and receiving a transmission stream composed of a plurality of symbols each composed of a valid data period and a guard interval created by multi-carrier modulation of input digital information. When digital information is multi-carrier demodulated by detecting a switching point of a period, a plurality of fast Fourier transform processing units and decoding processing units are provided, and each system is operated at a different effective data period extraction phase. And a means for selecting any one of the decoded output data obtained from the plurality of decoded output data. 2. The method according to claim 1, wherein a criterion for selecting any one of the decoded output data obtained from each of the systems is determined based on an error in decoding processing. Decoding system integrated transmission device. 3. The transmission device according to claim 1, wherein
A plurality of transmission path decoding units are provided, and a criterion for selecting any one of the decoding output data obtained from the transmission path decoding units of the respective systems is determined by the error correction of each of the transmission path decoding units. An integrated transmission system for a plurality of decoding systems, which is determined based on the number of errors during processing. 4. The transmission apparatus according to claim 3, wherein a criterion for selecting any one of the decoded output data obtained from each of the systems is determined based on an error in decoding processing and the transmission path decoding. A multi-decoding system integrated transmission apparatus characterized in that the number of errors during error correction processing of a decoding unit is determined from two types of situations.