JP2002185303A - Logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a general-purpose logic circuit which can correspond to both of a 3 V system output destination circuit and a 5 V system output destination circuit. SOLUTION: A logic circuit is structured by a 74HCT type CMOS gate element 10 of Hi level input voltage VIH=2 V(min) and Lo level input voltage VIL=0.8 V(max) in correspondence to a TTL level input (0 to 5 V). The 74HCT type CMOS gate element 10 is operated to switch in both of 3 V system input (2.7 V to 3.3 V) and 5 V system input (4.5 V to 5.5 V), and a 5 V system voltage or a 3 V system voltage is output corresponding to a power source voltage to be supplied from an output destination circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit, and more particularly to a logic circuit adapted to support both a 3V output circuit and a 5V output circuit.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional 3V system input / 5V system output logic circuit, in which an open collector and open drain type input composed of a transistor 2 and a pull-up resistor 3 is provided before a 5V CMOS gate element 1. A level conversion circuit is inserted.

The electrical characteristics of a conventional 5V CMOS level input gate element are Hi level input voltage V _IH = 3.5V (min),
Since the Lo level input voltage V _{IL is} 1.5 (max), the output (0 to 3 V) of the 3 V logic circuit is increased to 0 to 3.5 V or more by the input level conversion circuit as shown in the figure to 5 V. System CMO
It is necessary to supply to the S gate element.

The power supply Vcc for the CMOS gate element and the input level conversion circuit is supplied from a 5 V output destination circuit (4.5 V to 5.5 V).
By pulling up the output of the V logic circuit by the input level conversion circuit and inputting it to the CMOS gate element 1, C
The 5V system inversion signal is output to the output destination circuit through the MOS gate element 1.

[0005]

Conventionally, a 3V input / output CMOS logic circuit and a 5V input / output CMOS logic circuit having an IC configuration are widely used, but when a 3V input / 5V output logic circuit is formed. Requires an input level conversion circuit to be added to the 5V input / output logic circuit.
There is no one that can support both the system output destination circuit and the 5V system output destination circuit.

Therefore, there arises a technical problem to be solved in order to provide a general-purpose logic circuit which can cope with both the 3V-system output destination circuit and the 5V-system output destination circuit. The purpose is to solve.

[0007]

SUMMARY OF THE INVENTION The present invention proposes to achieve the above object, and corresponds to a TTL level input, a Hi level input voltage V _IH = 2 V (min) and a Lo level input voltage. 74HCT voltage V _IL = 0.8V (max) type or 74VHCT
It is an object of the present invention to provide a logic circuit characterized in that both types of 5V output circuit and 3V output circuit are supported by a type CMOS gate element.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. As shown in the figure, the logic circuit of the present invention is a single 74HCT type or 74VHCT type CMOS.
It is composed of a gate element 10. CMOS gate element 10
Configuration is n-channel, similar to a conventional general-purpose CMOS gate device.
A complementary circuit of MOS-FET and p-channel MOS-FET, the electrical characteristics is compatible with TTL level input (0 to 5V), Hi-level input voltage _{V IH = 2V (min),} Lo -level input voltage V _IL = 0.8V (max) and 5V input (4.5V to 5.5V)
V) and 3V input (2.7V to 3.3V) perform switching operation.

When the Hi level input voltage V _IH = 2V (min), n
Channel MOS-FET is turned on, p-channel MOS-FET is turned off, the output destination circuit is connected to GND through n-channel MOS-FET, the potential of the output destination circuit falls to Lo level output voltage V _OL.

When the Lo level input voltage V _IL = 0.8 V (max), the n-channel MOS-FET is turned off, the p-channel MOS-FET is turned on, and the power supply Vcc supplied from the output destination circuit is switched to the p-channel MOS-FET. current flows to the output terminal through the FET, the voltage of the output terminal becomes Hi level output voltage Vo _H.

The output voltage of the CMOS gate element 10 depends on the power supply voltage Vcc supplied from the connected output destination circuit, and is 5 V
If the system power supply voltage 5V system Hi-level output voltage Vo _H ≒ 4.5V to 5.5V through n-channel MOS-FET when the gate-on is outputted, n-channel MOS when the gate-on when a 3V system power supply voltage
-3V system Hi level output voltage Vo _H ≒ 2.7V to 3.3V is output through FET.

Thus, one logic circuit can support both the 3V output destination circuit and the 5V output destination circuit, and since no input level conversion circuit is used, the pull-up resistance and the parasitic capacitance of the input level conversion circuit are reduced. There is no problem of waveform distortion and signal delay due to the above.

It should be noted that the present invention is not limited to the above-described embodiment, and various modifications are possible within the technical scope of the present invention, and it goes without saying that the present invention extends to those modified embodiments. is there.

[0014]

As described above, the logic circuit of the present invention is constituted by a 74HCT type CMOS gate element having a Hi level input voltage V _IH = 2 V (min) and a Lo level input voltage V _IL = 0.8 V (max). Therefore, one logic circuit can handle both 3V output destination circuit and 5V output destination circuit, and since no input level conversion circuit is used, waveform distortion and signal delay inherent in the input level conversion circuit There is no problem such as the above.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a 74HCT type CMOS logic circuit of the present invention.

FIG. 2 is a circuit diagram of a conventional 3V input / 5V output CMOS logic circuit.

[Explanation of Signs] 10 74HCT type CMOS gate element

Claims (1)

[Claims] 1. High level input voltage V _IH = 2V (min) and low level input voltage V _IL = 0.8V corresponding to TTL level input
A logic circuit characterized by using both (max) 74HCT type or 74VHCT type CMOS gate elements for both 5V output destination circuits and 3V output destination circuits.