JP2002185294A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a cost by unifying a set value of an overcurrent irrespective of a state of a load and narrowing an input range width of a comparator without necessity of considering an influence of a change in a power source voltage. SOLUTION: A detection of the overcurrent flowing to a switching element MV1 connected to the load is executed with the power source voltage VDD as a reference. Thus, setting of a detected value of the overcurrent is facilitated irrespective of whether or not the load is short circuited before or after the start of the operation. When a voltage Vcp1 is compared with a voltage Vcp1 by a comparator CMP, a change amount of the voltage VDD is cancelled to eliminate dependency on the voltage VDD. Since the voltages Vcp1, Vcp2 to be input to the comparator CMP are near the voltage VDD irrespective of the state of the load, setting of the input voltage range of the comparator CMP is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit and, more particularly, to a circuit having a protection function for detecting an overcurrent.

[0002]

2. Description of the Related Art The configuration of a conventional semiconductor integrated circuit is shown in FIG. This circuit has a switching element above the load (high side). The drain of the N-channel power MOSFET MV1 is connected to the power supply voltage VDD terminal, the gate is connected to the gate terminal VG for inputting the gate signal VG, and the source is connected to the output terminal OUT. A load (not shown) is connected between the output terminal OUT and the ground terminal. The following configuration is provided to detect when the current flowing through the load exceeds a predetermined value and becomes an overcurrent.

In order to detect a current flowing to a load via the MOSFET MV1, a power supply voltage VDD terminal and an output terminal O
A resistor R1 between the UT and the N-channel MOSFET M
The drain and source of D1 are connected in series. The connection point between the resistor R1 and the drain of the MOSFET MD1 is
It is connected to one end of the comparator CMP and is input as the voltage Vcp1.

An N-channel MOSFET MD2 is connected between a power supply voltage VDD terminal and a ground terminal for setting a reference value.
, A resistor R2, and a current source IREF through which substantially the same current flows. Resistor R2 and current source IREF
Is connected to the other end of the comparator CMP and the voltage V
Entered as cp2.

The comparator CMP determines that the operation is normal while the voltage Vcp1> Vcp2, and when the relationship is inverted to Vcp1 <Vcp2, determines that an abnormality has occurred and outputs an abnormality detection signal.

Here, the on resistance of the MOSFET MV1 is Rmv1, the on resistance of the MOSFET MD1 is Rmd1,
The on-resistance of OSFET MD2 is Rmd2, unit ratio:
N times MOSFET MV1 / MOSFET MD1,
The gate-source voltage of MOSFET MD1 is Vgsmd
1. The gate-source voltage of MOSFET MD2 is Vgsm
d2.

In normal operation, a high-level gate signal VG is input to the gate of the MOSFET MV1 to turn on, and a current is supplied to a load connected between the output terminal OUT and the ground terminal to operate. The MOSFETs MD1 and MD2 also turn on.

[0008] The voltage Vcp1 at the connection point between the resistor R1 and the MOSFET MD1 is determined by the following equation: Vcp1 = VDD- (R1 × Is1 / N) (1) where Is1 is the drain current of the MOSFET MV1.

On the other hand, the voltage Vcp2 at the connection point between the resistor R2 and the current source IREF is reduced by the constant current IREF flowing through the resistor R2, and is expressed by the following equation (2).

Vcp2 = VDD− (IREF × R2) (2) Here, R1 >> Rmd1, R2 >> Rmd2.

The on-resistance of MV1 is Rmv1, MD1
The on resistance of MD2 is Rmd1, the on resistance of MD2 is Rmd2, MV
The unit ratio of 1 to MD1 is N times, and the gate-source voltages of MD1 and MD2 are Vgsmd1 and Vgsmd2.

During normal operation, the relationship Vcp1> Vcp2 holds, as described above.

There are two types of abnormalities to be detected. The first abnormality is caused by the gate signal V rising to a sufficiently high level at the gate of the MOSFET MV1.
This is a case where, from the state where G is input and the normal operation is performed, a short circuit occurs in the load, an abnormality occurs, and Vcp1 <Vcp2.

The second abnormality is that a short circuit has already occurred in the load before the start of the operation.
This is the case where Vcp1 <Vcp2 in the middle of gradually rising from the ground voltage to the high level at the gate of V2, and an abnormality is detected. Hereinafter, each of them will be described.

In the case of (1): When a short circuit occurs in the load from the state where the normal operation is performed (the voltage between the power supply voltage VDD terminal and the output terminal OUT is small) The gate signal VG rises to a sufficiently high level MO
The SFET MV1 is sufficiently turned on with a low on-resistance, and a current is supplied to the load to be driven. This case corresponds to a case where a short circuit occurs in the load and the load becomes abnormal.

Since the MOSFET MV1 is sufficiently turned on, the MOSFETs MD1 and MD2 are similarly turned on with low resistance. The detection current at this time, ie, M
Assuming that the drain current of the OSFET MV1 is Is1,
The voltage Vcp1 is represented by the above equation (1).

The voltage Vcp2 is represented by the above equation (2).

In this state, if Vcp1 <Vcp2, an abnormality detection signal is output from the comparator.

Case (2): When an abnormality is detected while the gate signal rises to a high level from a state where a short circuit exists in the load (the power supply voltage VDD terminal and the output terminal OUT).
The gate signal VG gradually rises to a high level from a state in which the load is short-circuited, and the MOSFET MV1 is turned on with a high on-resistance before reaching a sufficiently high level. Similarly, MOSFET MD1 and MD2
Also turns on with high resistance. In this case, the MOSFET MD
The on-resistances of 1 and 2 cannot be ignored. The voltage Vcp1 in this case is expressed as follows: Vcp1 = (VDD−VOUT) × (Rmd1 / (Rmd1 + R1)) (3)

The voltage Vcp2 is obtained by the following equation: Vcp2 = VG−Vgsmd2− (IREF × R2) (4)

In this state, if Vcp1 <Vcp2, abnormality is detected.

Although the two abnormality detections have the same circuit configuration, the set values of the overcurrent at the time of detection are different. This is because, as shown in the equations (1) to (4), the elements required for the setting are different, and the variation temperature characteristics are independent.

In the abnormality detection in the case (1), both the voltages Vcp1 and Vcp2 are equal to the power supply voltage Vcp.
Determined based on DD. However, in the abnormality detection in the case (2), the voltage Vcp1 is determined based on the power supply voltage VDD, but the voltage Vcp2 is determined based on the voltage of the gate signal VG. As described above, since the reference value is different, it is difficult to set an overcurrent value to be detected.

Furthermore, when the power supply voltage VDD fluctuates, in the case of the above (1) in which both the voltages Vcp1 and Vcp2 are based on the power supply voltage VDD, the fluctuations are canceled out, so that there is no particular problem without consideration.

However, in the case of the above (2), only the voltage Vcp1 is based on the power supply voltage VDD, and the voltage Vcp2 is
Equation (4) does not include the power supply voltage VDD based on the voltage of G. Therefore, the power supply fluctuation VDD is not canceled, and the fluctuation causes a variation in the value of the overcurrent to be detected.

Further, in the case of the above (1), the power supply voltage V
The voltage near DD is compared by the comparator CMP, and in the case of the above (2), the voltage near the ground voltage is compared. In such a case, if the input voltage range of the comparator CMP is narrow, an overcurrent may not be detected at a desired set value in any of the cases (1) and (2). Therefore, a wide input voltage range is required for the comparator CMP, which results in a complicated circuit configuration and an increase in cost.

[0027]

As described above, conventionally, there are two types of abnormalities to be detected. However, it is difficult to make the set values of overcurrents the same, and the influence of power supply fluctuations. However, the comparator is required to have a wide input voltage range, resulting in an increase in cost.

The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor integrated circuit capable of unifying the set values of overcurrent, canceling the influence of power supply fluctuation, and preventing an increase in cost. .

[0029]

A semiconductor integrated circuit according to the present invention is connected between a power supply terminal and an output terminal, receives a control signal, and turns on or off, and the first switching element. A first voltage generation unit that generates a first voltage corresponding to a current flowing when the switching element is turned on from a first voltage generation terminal, and is connected between the power supply terminal and a second voltage generation terminal; A second switching element that is turned on or off by receiving the control signal, a current source connected between the second voltage generating terminal and a ground terminal, and a current source connected between the power terminal and the first terminal. And a fourth switching element connected between the power supply terminal and the second voltage generating terminal, wherein the third switching element is turned on and A power terminal and the first terminal; When a current flows between the power supply terminal and the second voltage generation terminal, the current mirror circuit is connected between the first terminal and the output terminal, and the control signal is input to the current mirror circuit. A fifth switching element that is turned on or off, and compares the first voltage generated at the first voltage generation terminal with a second voltage generated at the second voltage generation terminal. And a comparator that outputs a signal corresponding to the result.

The present invention also relates to a first switching element which is connected between a power supply terminal and an output terminal and is turned on or off by inputting a control signal, and comprising a first switching element connected to the power supply terminal and a first voltage generation terminal. A first resistor connected between the first voltage generating terminal and an output terminal, a second switching element that receives the control signal and turns on or off, A third switching element connected between the first terminal and a fourth switching element connected between the power supply terminal and the second terminal; and a voltage of the first terminal. When the third and fourth switching elements are turned on or off in response to and the third switching element is turned on and a current flows between the power supply terminal and the first terminal, the power supply terminal Karen with current flowing between it and the second terminal A mirror circuit, a second resistor having one end connected to the first terminal, and a second resistor connected between the other end of the second resistor and an output terminal. The control signal is input to turn on or off. A fifth switching element and the second switching element;
A third resistor connected between the second voltage generating terminal and the second voltage generating terminal; a current source connected between the second voltage generating terminal and the output terminal; A sixth switching element connected between the first voltage generation terminal and the first voltage generation terminal, the sixth voltage switching element being connected between the first voltage generation terminal and the second voltage generation terminal; A comparator that compares the second voltage generated at the terminal and outputs a signal corresponding to the comparison result.

Alternatively, a semiconductor integrated circuit according to the present invention is connected between a power supply terminal and an output terminal, receives a control signal, and turns on or off; and a power supply terminal and a first voltage generator. A first resistor connected between the first voltage generating terminal and the output terminal, and a second switching element that is connected between the first voltage generating terminal and the output terminal and that receives the control signal and turns on or off; A second resistor connected between the power supply terminal and the first terminal, and a second resistor connected between the power supply terminal and the second terminal and turned on or off according to the voltage of the first terminal. 3 switching elements and the first switching element.
A third resistor having one end connected to a terminal of the second resistor, a fourth switching element connected between the other end of the second resistor and an output terminal, the control signal being input to turn on or off, A fourth resistor connected between the second terminal and a second voltage generation terminal, a current source connected between the second voltage generation terminal and an output terminal; A fifth switching element connected between the second terminal and receiving the control signal and turning on or off;
And a comparator that compares the first voltage generated at the voltage generation terminal of the second voltage generation terminal with the second voltage generated at the second voltage generation terminal, and outputs a signal according to the comparison result. And

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

(A) First Embodiment FIG. 1 shows a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

This embodiment corresponds to a circuit in which a MOSFET MD3, a resistor R3, and PNP bipolar transistors P1 and P2 are further added to the circuit shown in FIG.

The emitters of the bipolar transistors P1 and P2 are connected to the power supply voltage VDD terminal, and the bases are both connected to the collector of the bipolar transistor P1. The transistors P1 and P2 form a current mirror circuit.

One end of the resistor R3 is connected to the collector of the transistor P1, and the drain of the MOSFET MD3 is connected to the other end. The gate of the MOSFET MD3 is connected to the gate terminal VG, and the source is connected to the output terminal OUT. One end of a resistor R2 is connected to the collector of the transistor P2. The other same circuit elements are given the same numbers and their explanation is omitted.

The bipolar transistors P1, P2
The collector-emitter voltage of Vce (P
1), Vce (P2), and collector currents of Ic (P2)
1), Ic (P2), the voltage between the power supply voltage VDD terminal and the output terminal OUT is Vdsmv1.

In this embodiment, detection of an abnormality in the above two cases (1) and (2) will be described.

In the case of (1): When a short circuit occurs in the load from the normal operation state (the voltage between the power supply voltage VDD terminal and the output terminal OUT is small) The gate signal VG rises to a sufficiently high level MO
The SFET MV1 is sufficiently turned on with a low conduction resistance, and a current is supplied to the load to be driven. In this state, a short circuit occurs in the load, and an abnormality is detected.

Since the MOSFET MV1 is sufficiently turned on, the MOSFETs MD1 and MD2 are similarly turned on with low resistance. Since the MOSFET MD2 is sufficiently on, the bipolar transistor P
2 is short-circuited between the emitter and collector, and Vdsmv1 <Vce
(P1), and neither of the transistors P2 and P1 operates (Vdsmv1 = Is1 × Rmv1).

The detection current at this time, that is, the MOSFET M
Assuming that the drain current of V1 is Is1, the voltage Vcp1 is
Similar to the circuit shown in FIG. 5, it is expressed by the above equation (1). The voltage Vcp2 is represented by the above equation (2).

In this state, if Vcp1 <Vcp2, the comparator outputs an abnormality detection signal.

Case (2): When an abnormality is detected while the gate signal rises to a high level from a state where a short circuit exists in the load (the power supply voltage VDD terminal and the output terminal OUT)
The voltage of the gate signal VG gradually increases toward the high level. The threshold value at which the transistor P1 turns on is set lower than the threshold value at which the MOSFET MD2 turns on. Therefore, while the voltage of the gate signal VG is increasing, the transistor P1 is turned on at an earlier timing than when the MOSFET MD2 is turned on.

When the transistor P1 is turned on, the power supply voltage VDD
When a current flows from the terminal to the resistor R3, the transistor P2 is also turned on by the current mirror effect, and a current flows from the power supply voltage VDD terminal to the resistor R2.

Here, by setting the drain currents of the transistors P1 and P2 so that Ic (P1) <Ic (P2) and setting Vce (P2) in the saturation region, the MOSFET The source voltage of MD2 becomes higher than the gate voltage. Thereby, the MOSFET MD
2 does not operate and maintains the off state.

The detection current (the drain current of MV1) is Is
Assuming that 2, the voltage Vcp1 is expressed by the following expression: Vcp1 = VDD− (R1 × Is2 / N) (5) On the other hand, the voltage Vcp2 is as follows: Vcp2 = VDD−Vce (P2) −IREF × R2 (6)

However, it is assumed that Vce (P2) ＲIREF × R2.

In this state, if Vcp1 <Vcp2, abnormality is detected.

As is apparent from the above equations (5) and (6), in both cases, the voltage Vcp1 and the voltage Vcp2 can be compared by the comparator CMP based on the power supply voltage VDD. Therefore, it is easy to set the overcurrent detection value in any of the above cases (1) and (2).

Further, even when the power supply voltage VDD fluctuates, in both cases (1) and (2), the voltages Vcp1 and Vcp2 are both based on the power supply voltage VDD. For this reason, the fluctuation of the power supply voltage VDD is offset, and it is not necessary to consider the influence of the fluctuation.

In any of the above cases (1) and (2), the voltages Vcp1 and Vcp2 near the power supply voltage VDD.
Will be detected. Therefore, it is not necessary to widen the input voltage range required for the comparator CMP, and it is possible to prevent an increase in cost.

(B) Second Embodiment In the first embodiment, the bipolar transistor P
1 and P2 constitute a current mirror circuit.
However, not limited to bipolar transistors, P-type MOS
A current mirror circuit may be configured using FETs.
The configuration in this case is shown in FIG. 2 as a second embodiment of the present invention.

The sources of the MOSFETs MP1 and MP2 are connected to the power supply voltage VDD terminal, respectively, and the gates are both connected to the drain of the MOSFET MP1.
The drain of ETMP1 is connected to one end of a resistor R3,
The drain of the OSFET MP2 is connected to one end of the resistor R2.

In this case, the same operation and effect as those of the first embodiment can be obtained. That is, the voltage Vcp1 and the voltage Vcp2 can be compared with the power supply voltage VDD irrespective of the state of the load, so that the detection value of the overcurrent can be easily set in any case. Further, the fluctuation of the power supply voltage VDD is offset between the voltage Vcp1 and the voltage Vcp2, and there is no need to consider the influence of the fluctuation. Further, the voltage V
Since both cp1 and Vcp2 are near the power supply voltage VDD, it is not necessary to widen the input voltage range required for the comparator CMP, thereby preventing an increase in cost.

(C) Third Embodiment In the first and second embodiments, a current mirror circuit is formed by using two transistors P1 and P2 or MP1 and MP2. However, it is not always necessary to form a current mirror circuit, and one transistor may be replaced with a resistor.

This embodiment is different from the second embodiment shown in FIG.
In the embodiment, the MOSFET MP1 is connected to the resistor R
4 and replace the gate of MOSFET MP2 with a resistor R
4 and R3. The same elements as those in the other second embodiment are denoted by the same reference numerals, and description thereof is omitted.

In the present embodiment, the same effects as in the second embodiment can be obtained. That is, when the load is the above (2), while the voltage of the gate signal VG is gradually increasing, the transistor MP2 to which the voltage at the connection point between the resistors R3 and R4 is input turns on first, and the transistor MD2 Maintain the off state. This allows
In any of the above cases (1) and (2), it is easy to set the detection value of the overcurrent, it is not necessary to consider the fluctuation of the power supply voltage VDD, and the input voltage range required for the comparator CMP can be reduced. There is no need to increase the size and the cost is reduced.

(D) Fourth Embodiment In this embodiment, as shown in FIG. 4, an IGBT (Embodiment 4) is used as a voltage-controlled element instead of the power MOSFET MV1 in the first embodiment. Insulated Gate
Bipolar Transistor) It is equivalent to one using IG.

In the present embodiment, the first to third
The same operation and effect as those of the embodiment can be obtained.

[0060]

As described above, according to the semiconductor integrated circuit of the present invention, the detection of the overcurrent flowing in the first switching element connected to the load is performed with reference to the power supply voltage, thereby irrespective of the state of the load. It is easy to set the detection value of the overcurrent, and when the first and second voltages are compared by the comparator, the fluctuation of the power supply voltage is cancelled, and the load does not depend on the power supply fluctuation. Regardless, since the first and second voltages input to the comparator are near the power supply voltage, it is easy to set the input voltage range of the comparator.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 P1, P2 PNP type bipolar transistor MD1, MD2, MD3 MOSFET R1, R2, R3, R4 Resistance MV1 Power MOSFET IREF Current source MP1, MP2 P channel type MOSFET VDD Power supply voltage terminal VG Gate voltage terminal OUT output terminal

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03K 17/687 H03K 17/687 A (72) Inventor Yoshiyuki Sano 25 Ekimae Honcho, Kawasaki-ku, Kawasaki-shi, Kanagawa Address 1 F-term in Toshiba Microelectronics Corporation (reference) 5G004 AA04 AB02 BA03 BA04 CA04 DC03 DC04 5G053 AA01 AA02 BA01 BA04 DA01 EA09 EC03 5G065 BA04 EA01 HA07 JA02 KA05 LA01 MA09 MA10 NA02 5J055 AX36 AX38 AX39 EX07 AX47 EY17 EY21 EZ03 EZ04 EZ10 FX04 FX08 FX38 GX01

Claims (3)

[Claims] A first switching element that is connected between a power supply terminal and an output terminal and that is turned on or off by receiving a control signal; and a first switching element corresponding to a current flowing when the first switching element is turned on. A first voltage generation unit that generates a voltage of 1 from a first voltage generation terminal; a first voltage generation unit connected between the power supply terminal and a second voltage generation terminal;
A second switching element that is turned on or off by receiving the control signal; a current source connected between the second voltage generating terminal and a ground terminal; and a power source terminal and a first terminal. And a fourth switching element connected between the power supply terminal and the second voltage generating terminal, wherein the third switching element is turned on and the third switching element is turned on. A current mirror circuit in which a current flows between the power supply terminal and the second voltage generation terminal when a current flows between the power supply terminal and the first terminal; A fifth switching element, which is connected between the control signal and the control signal to turn on or off, the first voltage generated at the first voltage generation terminal, and the fifth voltage generated at the second voltage generation terminal. Ratio with the second voltage And a comparator for outputting a signal corresponding to the comparison result. 2. A first switching element connected between a power supply terminal and an output terminal, the control signal being inputted to turn on or off, and a first switching element connected between the power supply terminal and a first voltage generation terminal. A first resistor connected between the first voltage generation terminal and the output terminal;
A second switching element that receives the control signal and turns on or off, a third switching element that is connected between the power supply terminal and the first terminal, and a power supply terminal and a second terminal. A fourth switching element connected between the first switching element and the first switching element.
When the third and fourth switching elements are turned on or off according to the voltage of the terminal, and the third switching element is turned on and a current flows between the power supply terminal and the first terminal, A current mirror circuit in which a current flows between the power supply terminal and the second terminal; a second resistor having one end connected to the first terminal; and a second resistor connected to the other end of the second resistor and an output terminal. A fifth switching element connected between the second terminal and the second voltage generating terminal, the fifth switching element being turned on or off by receiving the control signal, the third switching element being connected between the second terminal and the second voltage generating terminal, A second current source connected between the voltage generating terminal and the output terminal of the second power supply terminal and a second switching terminal connected between the power supply terminal and the second terminal, the control signal being input to turn on or off. And an element generated at the first voltage generation terminal. Serial and first voltage, the second comparing the second voltage generated in the voltage generating terminal, the semiconductor integrated circuit, characterized in that it comprises a comparator for outputting a signal corresponding to the comparison result. 3. A first switching element connected between a power supply terminal and an output terminal and turned on or off by receiving a control signal, and connected between the power supply terminal and a first voltage generation terminal. A first resistor connected between the first voltage generation terminal and the output terminal;
A second switching element that is turned on or off by receiving the control signal; a second resistor connected between the power supply terminal and the first terminal; and between the power supply terminal and the second terminal. Connected to the first
A third switching element that is turned on or off in accordance with a voltage of a terminal of the third terminal, a third resistor having one end connected to the first terminal, and a third resistor connected between the other end of the second resistor and an output terminal. A fourth switching element that is connected to turn on or off by receiving the control signal, a fourth resistor connected between the second terminal and a second voltage generation terminal, A current source connected between a voltage generation terminal and an output terminal; a fifth switching element connected between the power supply terminal and the second terminal, which receives the control signal and turns on or off. A comparator that compares the first voltage generated at the first voltage generation terminal with a second voltage generated at the second voltage generation terminal, and outputs a signal according to the comparison result; A semiconductor integrated circuit comprising: