JP2002182928A - Instruction emulation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance instruction simulation speed by shortening time in pipeline mechanism and increasing use rate of a super sealer in instruction simulation. SOLUTION: In the instruction simulation, a process to copy an arithmetic processing of the next instruction after an arithmetic processing of the present instruction for simulation, a process to obtain a critical path (long instruction arithmetic processing) for which long time is required by comparing time to allocate a processing variable to the arithmetic processing of the present instruction and to execute resources by occupying them for execution of an arithmetic operation with time to allocate a processing variable different from the arithmetic operation of the present instruction and to execute the resources by occupying them for execution of the arithmetic operation and a process to allocate a step of a short instruction arithmetic processing in free time and to perform a parallel arithmetic processing when the resource in which use is doubled by the other short instruction arithmetic processing in the free time of execution cycle to be included in a step in a long instruction arithmetic processing are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to computer software, and more particularly to a processing method for realizing the operation of a computer having a certain instruction set (Computer B) on a computer having another command set. .

[0002]

2. Description of the Related Art Conventionally, a computer (computer) determines instruction specifications such as machine instruction codes and functions for each model, and common specifications that do not depend on individual instructions. Arithmetic processing unit). By the way, the processor is becoming LSI, and the processor is composed of one chip or several chips.
While being able to execute instructions with a high-speed clock, LS
I-development costs enormous costs, and development costs cannot be recovered unless a large number of products are shipped. Furthermore, the performance of microprocessors used as industry standards has been further improved,
The performance gap with dedicated processors that have their own instruction set is growing. Although there is a major trend toward the transition to industry-standard processors, the operating system on which it is installed is not always versatile, and there are concerns about the compatibility with user applications. In addition, there is a need for respect for user applications, user data, and operating environments, which are assets of the user, and for the continuation of conventional computers based on the same and the need for lower prices. As a solution to these problems, techniques such as "instruction simulation", "instruction emulation", and "instruction conversion", which simulate conventional computers using an industry-standard processor, have recently become popular. Have been.

There are two flows in the technology for simulating the instruction operation of a computer. One is by software,
Another is by hardware. The first software is a computer simulation method for simulating a computer having a certain instruction set (Computer B) by using a program on a computer having a different instruction set (Computer A). It has been used for a long time, and has been used for analyzing computer characteristics, debugging programs, and developing software for microprocessors in a host computer environment.

The second hardware is mainly used for a central processing unit of a computer having a plurality of instruction sets. In other words, using the hardware optimized for the instruction set A, it is called "emulation" in a method that prepares only a small part of the hardware such as an instruction decoder and microprogram for another instruction set B. I have. The advent of horizontal microprogrammable microprocessors has also been used to implement minicomputer processors. This emulation method is ten to several tens times faster than the simulation execution by software, and generally achieves a fraction of the performance of a dedicated circuit.

[0005] However, as a method of increasing the processing speed by the advance of LSI technology, a pipeline circuit or RISC (R)
reduced Instruction Set Co
mputer) architecture. As a result, it is not possible to change the microprogram by anyone other than the LSI maker, and if an external circuit is added, the delay between circuits will increase, the number of clocks will increase, and the overhead due to pipeline disturbance will increase. As a result, effective emulation utilizing the performance of the processor was no longer possible. On the other hand, instruction simulation by software (hereinafter referred to as instruction simulation)
However, there is a disadvantage that the processing content of the instruction simulation cannot utilize the high-speed performance of the hardware of the processor, which hinders the speeding up of the instruction simulation. Hereinafter, the problem will be described.

FIG. 14 shows a flow of a general instruction simulation. FIG. 15 is a flowchart showing a simple program example for simulating one instruction. There are instructions that perform complex operations in the function of the instructions, but when analyzing the actual operation of the core business program, the frequency of loading from memory to registers, storing from registers to memory, and branch processing is extremely high. I know. It has been empirically found that, among these instruction processes, common processes that do not depend on individual instructions, such as instruction decoding and memory operand address calculation, occupy a large number of instructions.

The decoding of an instruction requires a branch process depending on data called an instruction code composed of a specific field of an instruction word. In a high-performance processor, prefetch control of an instruction sequence at a branch destination is performed. However, a plurality of consecutive branches has a large overhead due to a pipeline disorder.
Further, since the same instruction sequence for decoding is used many times, the speed-up effect by branch history retention is reduced. Furthermore, in the method of determining a branch destination using an instruction code value as an offset,
There is a problem that the pipeline is stopped or restarted and a large number of clocks are consumed.

In the decoding of the instruction, the process of determining which register to use is performed by bit shifting of the instruction code or A
It is necessary to perform an ND operation and then access a data array corresponding to the register value arranged on the memory, and it is necessary to sequentially perform shift, AND, and memory access operations. This sequential operation causes register interference in pipeline processing of a high-performance processor. Furthermore, the advantage of the superscaler, which is a technique for simultaneously executing a plurality of instructions, is hardly used.

On the other hand, although the processing flow is not shown,
There is also a method in which the instruction field indicating the register number and the instruction code are collectively decoded, and the number of branch destination addresses is increased to determine a memory address corresponding to the register number as a fixed value in advance without dynamically obtaining the same. Such a method has an advantage that the disturbance of the pipeline is reduced in principle. However, there is a problem that the memory area where the instructions are arranged is enlarged and the cache miss overhead is significantly increased. For example, as shown in FIG. 16 where the instruction field is 8 bits and there are three sets of register fields each having 4 bits, if the decoding bit width is 8 bits,
If it is 12 bits, it is suitable for the secondary cache memory, but if it is larger than 12 bits, the overhead of cache miss is large. Therefore, whether the pipeline overhead or the branch overhead is selected, or the cache miss overhead is selected, the high speed of the processor cannot be utilized.

An example of hardware operation when an instruction simulation of a computer (Otsu) of a different instruction set is executed by using a processor (A) having a superscalar mechanism will be described with reference to FIGS. Fig. 17 shows the instruction format and function of the "load instruction" (hereinafter, referred to as "L instruction") in pseudo code, and Fig. 18 shows the processing flow of the instruction simulation performed by Party A and how to use the registers of Party A. Is shown. Alphabetic symbols A to Y in the figure correspond to each instruction (unit processing) of the former. We assume that we have the following hardware: a) Instruction fetch unit, instruction decode unit,
The execution unit performs a pipeline operation. The execution unit has two operation execution units and one memory execution unit. b) The operation units execute the inter-register operation independently and in parallel in one cycle. c) There is one memory execution unit, which consists of a three-stage pipeline of address calculation, address translation and tag memory access for cache, and data access. d) The instruction cache and data cache are independent. e) When register interference occurs, wait between the execution units and transmit the result by bypass. f) The instruction decode unit can dispatch up to two instructions at the same time. Dispatch does not overtake the previous instruction, but guarantees consistency by H / W so that the sequential execution order of the program is maintained even if the execution order is reversed. g) The branch processing is performed by the execution unit, and the tag memory of the instruction cache is pulled to the execution stage. h) The instruction register holds up to four instructions until it is delivered to the instruction decode unit. The fetch holds instructions for four instructions, and when it becomes empty, reads the necessary part from the instruction cache memory. FIG. 21 illustrates a mnemonic code, a notation, and a meaning of a part of the instruction set of the instep A.

FIG. 19 shows a machine instruction sequence of the first party when the first party executes the instruction simulation of the second party's L instruction. Instructions A to E in the figure are common processing among the instructions of the second party, and F, which is an instruction-specific processing, does not need to be arranged continuously to E. In the figure, the command description of Party A regarding the other command processing of Party B is omitted. FIG. 20 shows B's two consecutive L instructions,
The state of the pipeline stage when executed by the instep using the instruction sequence shown in FIG. 19 is shown using the number of execution clock cycles in the vertical direction. The alphabetic symbols in FIGS. 19 and 20 are identification symbols provided for explanation and correspond to the command of the former. Similarly, the numbers are clock cycle numbers. The identifier in parentheses indicates that the result of the pipeline stage operation of the instruction is not effectively used in the cycle. In this example, it takes 27 cycles to simulate one L instruction of Otsu.
As described above, only the 25 instructions (see the drawing) are executed for 27 cycles, and the H / W specification is such that the instep processor can execute a maximum of 2 instructions in one cycle, and its theoretical value is 5
Only 46% of the four instructions are used.

[0012]

As described above, the conventional instruction simulation is an instruction simulation for simulating and executing an instruction using a processor having a pipeline structure having another instruction set and a superscaler mechanism. However, unlike ordinary application programs, there is a problem that it is difficult to utilize the high speed of the processor due to the general characteristics of instruction simulation. In particular, when a general-purpose computer is used as a simulation target, instructions that can be easily used by the superscalar function are used very rarely. There is a problem that a large number of cycles are required for extracting information and calculating addresses, and the number of cycles is increased, resulting in a longer execution time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and in the instruction simulation processing, the time in the pipeline mechanism is reduced, the use rate of the superscaler is increased, and the instruction simulation speed is improved.

[0014]

An instruction emulation method according to the present invention uses a simulation program combining a pipeline instruction and a machine instruction set of a processor having a multiple instruction simultaneous execution mechanism (super scaler mechanism). In a method of simulating a program created for a set of machine instructions, a process of copying the operation of the next instruction after the operation of the current instruction for simulation, and allocating a processing variable to the operation of the current instruction and executing the operation The time required to occupy resources for execution and the processing time allocated to the next instruction operation and different from the current instruction operation, and the time required to occupy resources for execution of the operation are compared. The step of obtaining a critical path (long instruction operation processing) requiring time, and the execution cycle idle time included in the step during the long instruction operation processing, If the short instruction operation processing square uses resources that do not overlap the use, comprising: a step of parallel computation by assigning step short instruction processing in the free time, the.

Further, in a step subsequent to the current instruction operation processing, a step of reading the next instruction word and comparing it with the instruction of the next instruction operation processing which has already been performed in parallel, and when the compared instructions do not match, There is provided a step of discarding the next instruction operation currently being performed in parallel and performing the next instruction operation process again.

Further, the critical path is obtained by cutting out the unit processes constituting the instruction operation process for each unit process,
In the cut-out unit processing, the order between the unit processings is determined based on the operation execution condition, and the unit operation processing in the critical path is performed during the execution cycle idle time included in the instruction execution step of the unit processing group that gives the determined critical path. When a resource other than the group uses a resource whose use is not duplicated, a step of allocating a step of the other unit arithmetic processing to the idle time and performing a parallel arithmetic operation is provided.

Further, when there is a branch step in the instruction operation processing, this branch step is provided after both the current instruction operation processing and the next instruction operation processing.

Further, when the resource is a pipeline operation mechanism, steps are allocated on the assumption that different register portions of the pipeline are not used repeatedly.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a typical processing flow of a program for executing an instruction simulation according to an embodiment of the present invention. As shown in the figure, the instruction simulation method according to the present embodiment simulates the machine instruction processing of the computer B by a program of a processor A having a pipeline and a super scaler mechanism. In this simulation processing, each instruction is constituted by processing classified into any of the following processing. The process of setting necessary variables and constants in a memory or a register. 1) Perform common processes without depending on the instruction code. 2) Cut out the instruction code and perform the processing. 3) The following processes 4) to 6) prepared for each instruction are performed. That is, 4) the instruction processing corresponding to the address indicated by the program counter in each instruction specific processing is performed. 5) The instruction counter fetches and processes the instruction corresponding to the address indicated next or predicted by the program counter in the program concept in the instruction specific processing. 6) The instruction word refetched after the store operation to the main memory is compared with the instruction word fetched speculatively in advance. 7) Copy the next instruction to the instruction. 8) Loop processing for moving to the next instruction processing after processing corresponding to each instruction code. 9) After the comparison, replace the previously fetched instruction word with the fetched instruction word.

The functional operation of instruction simulation execution will be described with reference to FIG. In 2 shown by processes 2a to 2f in the figure, an instruction word is fetched (2a), an instruction code field is cut out (2b), and 256 types of branch table fetches (2
c), cutting out a field indicating the register number of the instruction (2d), and speculatively fetching in advance the contents of the memory corresponding to the register used or possibly used as address calculation or data in the instruction (2e) By branching to a routine specific to each instruction (2f), common processing including instruction decoding and partial execution processing is performed.

Each process 3) includes a system of process 4) and two systems of processes 5) to 7). 4) and 4e to 41 indicate processing of an instruction indicated by the program counter, and 5) and 5a to 5m indicate instruction processing indicated by the next program counter instead of the current program counter. Regarding 5), it is irrelevant when the value of the register or the memory variable, which is the actual state of the program counter, is updated, and the program counter, which is a concept on the program, corresponds to the following address. When the current program counter is an instruction that does not involve branching, it is an address obtained by adding the word length of the current instruction to the program counter that is the current instruction address. For instructions with branches,
This is the specified or calculated address, or the address to which the word length of the current instruction is added. If the instruction involves a branch,
The instruction may be an instruction indicated by the next program counter that completely matches the actual operation of the actual program, or may be an address that has been speculatively determined without waiting for the execution result of the previous instruction to be determined. The processing 4) and the processing 5) conceptually show that the two processings flow in parallel from top to bottom as shown by the broken arrows, but on the program of Party A as shown by the solid arrows in the figure. It is arranged and executed in the order of the solid arrows in the concept of the program of the instep. On the instep hardware, dispatch of the super scaler mechanism to the execution unit is 4), 5).
Flow in parallel, and the clock operation is executed as indicated by the dashed arrow. As shown by 5m and 5a in FIG.
4) and 5) need not necessarily be performed alternately.

The processing of 5) includes all or most of the processing of 2). 5a in the figure becomes 2a and 5b
Is 2b, and 5f is equivalent to 2f.
By including the process 2 in 5, that is, while the current instruction is being executed in 4), the portion of 2) of the next instruction is actually performed in parallel, so that the processor 2 It can be considered that the number of clocks can be substantially reduced. The fastest simulation processing is realized by the loop 8a.

In a conventional computer called a von Neumann type, an instruction code can be rewritten by an instruction.
In order to maintain program compatibility, it is necessary to detect program rewriting that occurs at an extremely low probability and prevent malfunction by using a refetched instruction word without using a prefetched value of the instruction word. 8n in the drawing is 5) before the store of the processing of 4) in the instruction for storing in the memory 5).
This is an important path in the present invention provided in correspondence with the instruction processing in which the instruction fetch is performed by the above processing. In the ST instruction processing in the figure, the transition is made from 8n to 6), and the instruction word is fetched again and compared. Usually, since they match, the processing performed in 5) is utilized, and only the branch processing by 5f is performed. However, if the instruction word is rewritten, they will not match, and the decoding process will be redone with the correct instruction word 2b replaced in the process of 6). Also, in the case of an instruction which is not frequently executed, even if the processing of separating the processing of 4) and 5) is realized, the effect on the performance is low, so that the processing of 5) is not intentionally performed, and the processing of 8c is performed through the loop of 8c. Return to 2a. In some cases, 6) is performed as a common process without performing the process 6) in 3).

FIG. 1 is a diagram showing the results, so that it is difficult to understand the process of changing from a normal operation flowchart. Therefore, a description will be given with reference to another drawing of the processing time reduction in the simulation in the present embodiment. FIG. 2 is a diagram illustrating preparations for enabling the parallel processing of FIG. FIG. 2A is a diagram illustrating a programming method by a normal simulation, and FIG. 2B is a diagram illustrating a programming method by a simulation after performing preparations in the present embodiment. That is, in FIG. 2 (b), the processing of 2) from the reading of the instruction word for the next instruction operation processing to the branch is performed until the current instruction operation processing of 4) is completed until the end of the current instruction operation processing of 4). If there is more than one, there is a step of copying a plurality of copies and placing them as a process 5) before the branch step of the current instruction operation process. Similarly, FIG. 3 is a diagram for explaining a process of allocating steps in the processes until the processes 4) and 5) are performed in parallel by the superscaler mechanism of the same pipeline. That is, FIG.
FIG. 7 is a diagram in which different processing variables are respectively assigned to, for example, the current process 4) and the next process 5), and are developed in a time series from top to bottom in the order of calculation steps in consideration of conditions for processing as separate systems. FIG. 3B is a diagram showing that the current processing 4) is a critical path, in which an instruction operation step is further expressed as an execution cycle level as a critical path requiring a longer instruction operation processing time. That is, there is a step of obtaining a critical path. FIG. 3C is a diagram in which the next process 5) is assigned to a cycle of an idle time in the execution cycle of the current process 4) that is a critical path if resources are free. That is, there is a step of allocating a unit process constituting another operation instruction to the idle time.

The operation will be described with reference to FIGS. In the normal simulation program shown in FIG. 2A, the processing from the extraction of the instruction code to the fetch of the branch table in 2) which is the processing common to the read instruction codes is completed, and 3) the branch corresponding to each instruction is performed. A process is prepared, and 4) from decoding and calculation of an instruction to updating the program counter for the next calculation. In this embodiment, in addition to this processing, as shown by a bold frame in FIG. 2B, the processing from 2) from reading of the next instruction word to branching is copied to the processing of 4) as 5) processing. And transfer. Next, specific instructions will be described with reference to FIGS. FIG. 4 is an operation flow in which one of the load instructions is described in correspondence with the format of FIG. In the figure, the next instruction written as 5 (5a, 5b # 1, etc.) in the leftmost symbol column 411 is conventionally the current instruction of 4 (4d # 1, 4d # 2, etc.) in the leftmost symbol column of FIG. Was performed after the end of the unique processing of. That is, FIG.
As the 2) processing of (a), the processing of updating the program counter of 4) and then cutting out the next instruction has been performed.
As described above, the next instruction 5 shown in the bold frame in FIG.
, The current instruction 4) processing and the next instruction 5) processing are prepared for one branch as one large processing.

What I want to explain in detail is from the large process prepared in this way to a flow in which 4) process and 5) process are operated in parallel. Even for the same large processing, different processing variables are assigned to the current instruction and the next instruction, so that 4) processing and 5) processing can be separated by using the same resources. First, as shown in FIG. 3A, the respective execution orders are described from top to bottom. Note that the execution contents are shown by the assembler code 414 in FIG. 4, and the operation contents are explained in the explanation column 415. Since it is difficult to describe all the contents, it is abbreviated as an identification symbol 412. In this load instruction, each execution content is abbreviated by such an identification symbol, and if the execution order is followed in each drawing, a symbol 4 such as 2 representing processing stages 2) to 7) can be obtained.
Reference numeral 11 indicates the unit operation processing correspondence shown in FIGS. 1 to 5 and the like. In the state of FIG. 3 (a), only the order of the 4) processing is known, but FIG. 3 (b) takes into account its execution cycle. For example, the code of abbreviation H is 3
It takes a cycle. Similarly, the execution of the abbreviation N is three cycles,
Execution of the abbreviation A is also three cycles. Thus, an execution time (cycle) is obtained. As a result, the process 4) takes longer than the process 5), and the process 4) has 15 cycles,
Process 5) is 10 cycles, and process 4) is a critical path.

Next, in the prior art, nothing is performed in the empty cycle 311. However, as shown in FIG. 3C, the next instruction of the process 5) is executed in the empty cycle. Of course, if resources conflict, it is impossible, but the arithmetic unit of the pipeline performs data parallel processing, and if different register parts are used,
Apparent parallel operation is possible. In this way, when the instruction of the process 5) that does not use the resource redundantly is assigned to the empty cycle in the process 4) of the critical path,
The parallel operation flow shown in FIG. In the example of FIG. 3, the coding order of the instructions is abbreviated as H, A, J, M,
N, B, C, D, F, O, G, P, Q, R, I, S,
K, T, U, V, L, Z, X, W, and E. The total execution cycle is 15 in FIG. 3 (c), which is significantly shorter than the original 25 in FIG. 3 (b). Further, in order to fill an empty cycle in FIG. 3 (c), the positions of Q, U and V are moved to shorten the cycle by 2 as shown in FIG. 3 (d).

FIG. 4 for explaining a concrete simulation time reduction of a load instruction is shown in FIG.
It is described including 2) processing which is the cutout. The lower part from the center, the parallel program part of the 4) processing and the 5) processing are arranged and displayed in the coding order of FIG. 3D. FIG. 5 is a view showing a corresponding execution cycle. In the twelfth to twenty-eighth cycles, the instruction fetch 452, the instruction decode 453, the operation # 1 454, and the operation # 2 45 that do not duplicate resources are executed.
5, memory access 456, instruction cache 457, and data cache 458 are executed.

The lower-case alphabets a, b, f, c, g, d, i, n, and e shown in FIG.
When the L instruction processing sequence is described and executed continuously, this path is not executed. When the L instruction is processed continuously, the calculation from the row H to the row E in FIG. 4 is repeated with cycle numbers 15 to 29 in FIG. For the sake of simplicity, the instruction cache and the data cache memory are limited to a state in which the store buffer for hitting, temporarily storing data stored in the memory or the cache, and discharging them when they are free is not overflown.

The processing of A, B, C, D, and E shown in FIG. 5 must be executed sequentially, and is a processing flow that becomes critical when branching to the processing of the next instruction. . Specifically, in cycles 16 to 18A, B in cycle 19, C in cycle 20, C in cycles 21 to 23, D in 24 to 25, E in cycle 27, and 11
Only three cycles are wasted for this pass during the cycle. This path takes nine cycles even though there are only five instructions. In addition, the processing of F and G is an upfront investment based on the assumption that the address of the index register is calculated and the next instruction is used in the processing corresponding to the next instruction, but the processing that requires sequential execution of two cycles or more is required. Since two cycles are required,
Allocated to 3 cycles of 20 to 22 cycles. K
And L are also upfront investments for the base register, but there is no penalty due to the use of an empty cycle until the loading of T in cycle 24 is performed. These A to G and I, K, L correspond to the processing 5), and the other H, J, M to W correspond to the processing 4). X is an update of the program counter, which may be considered 4) or 5). Among the processes 4), there is a process of “fetching the values of the index register and the base register, adding the address, fetching from the memory, and storing it at the address corresponding to the register”. Among them, M, N, O, P, S,
T and W need to be executed sequentially, and this path alone executes seven instructions during eleven cycles between cycles 17 to 27. However, since there is a vacancy in the 15-cycle pipeline, processing 5 ) To fill the empty cycle and utilize the pipeline and superscaler.

In FIG. 5, 15 cycles indicated by a bold frame are substantially the number of processing cycles of one instruction of the second party, and 25 cycles are obtained for 30 instructions multiplied by the maximum instruction execution number 2 by the superscaler.
After executing the instruction, the utilization rate is as high as 83%. The number of processing cycles is 55% of the processing time compared to 27 cycles of 25 instructions in FIG. The ST instruction in FIG. 6 and FIG.
The superscalar utilization rate is 81% because of six instructions, and the execution processing time is 57% of 28 cycles of the conventional example, although not shown. In both cases, the processing of the current instruction and the processing of the next instruction are mixed with each other, thereby enabling the empty pipeline and the simultaneous execution of the superscaler, thereby increasing the utilization rate of the arithmetic unit.

In this embodiment, the processing 4) or the processing 5) may call a common function. Also,
There is no need to have 3) as many as the number of instruction codes, and a plurality of instruction codes may correspond to one 3) and may be separately branched therein. 3) does not correspond to the instruction code, and may correspond to the one including the instruction code and other fields, or may correspond to some bits of the instruction code. In the above embodiment, the branch table is provided on the memory, but may be provided on the register. Alternatively, the branch destination address may be determined directly from the instruction code without using a table. In FIG. 1, the process 5) is an example in which the process 2) is entirely copied. However, the process 5) may be partially copied and jumped into the process 2).
For instruction simulations that do not allow program rewriting by executing instructions, 7 is provided instead of 6 and 8p ~
The 8q path need not be provided.

FIGS. 4 and 5 show the case of a load instruction.
The case of a store instruction is also exemplified. 6 and 7 are a final coding diagram and an execution cycle at the time of a store instruction, respectively, and correspond to FIG. 4 and FIG. FIGS. 8 to 13 are diagrams showing the process of shortening the operation flow including the load instruction and the store instruction, and correspond to the load instruction in detail. FIG. 8 shows an initial coding sequence when 5d and 5e shown in FIGS. 1 and 3 are not performed. That is, for the load instruction, the flow on the left side represents the processing more generally, and the right column (632) shows the corresponding assembly language. The middle column (631) corresponds to the symbol in FIG. Here, S601 to S618 are the processing of the current instruction (4).
S619 to 623 and 625 correspond to (5), and S624 corresponds to (7). In FIG. 8, independent registers are assigned to the registers as intermediate variables so that the dependence is minimized in the order of the individual processes. FIG. 9 shows each unit process for each identification symbol 631 that abbreviates the series of processes of FIG.
, The input 641 and the output 64 in the unit process
2 is a relationship diagram in which a parent instruction symbol 643 is extracted as a constraint condition. That is, based on this flow, the parallelism and the dependency of the processing are found, and the order of the processing is rearranged. First, as shown in FIG. 9, a register (642) updated for each instruction and a register (641) as an operation input thereof are described. The corresponding column of the column (644) of the update instruction symbol, that is, (642)
The value of (631) is transcribed to the column including. Parent instruction symbol (6
In the column 43), a symbol in a lower row is written when the column of the column 644 described in the column 641 is viewed from above. Command symbol J
For example, J is entered in 643. In the sixth column of 644 corresponding to rt_Rxd of “right side”, “H” is set.
Is found. In rt_Rxm, “I” in the fifth column of 644 is found. Repeat these steps 6
Ask for 43.

FIG. 10 is an expanded view of the connection relationship between the unit processes of FIG. 9. For example, the abbreviation P indicates that the execution must be performed after R and O, and the operations are required in the order of the arrows. ing. In the graph showing the dependency relationship in FIG. 10, the root of the arrow indicates the parent and the tip of the arrow indicates the child, and FIG.
This indicates an algorithm for generating 0. FIG.
The dashed arrow indicates that the execution of the process must be delayed. That is, Z must be performed after all of Q, F, K, U, and A have been performed.
Although this rule is not shown in FIG. 9, “ro” which is the value of “left side” (642) of the row where (631) is “Z” is used.
It indicates that "_Instrword" must be after the symbol (631) in any row containing 641. FIG.
1 is a diagram representing the longest critical path in FIG. 10, and the processing from the abbreviations F and K has the longest processing time. That is, FIG. 10 shows the number of cycles in addition to the operation status of the pipeline. I, H, M,
The number of cycles of N, A, D, E, and T is extended to three. This indicates that the path from F and K to W is longer. FIG. 11 does not consider serialization due to resource duplication. The solid arrow is the critical path that governs time,
Dashed lines indicate paths that are not.

FIG. 12 is a diagram simply counting the number of required cycles of resources used in FIG. FIG.
Now we want the total number of resources handled. Dispatch and operation are 2 for one memory access unit.
It can be seen that 13, 9, and 8 cycles are logical limits, respectively, and that 13 cycles are ideal optimal solutions. FIG. 13 is a diagram in which the operation timing of the memory access unit having the strictest resource constraint in FIGS. 11 and 12 is assigned. In the figure, the numeral 651 at the bottom is the number of activations of the memory access unit, and the unit processing H, N
For example, the processing timing has been changed. FIG. 13 shows a state in which the execution timing is allocated focusing on the memory access unit having the least resource. FIG.
At the same time, I, H, N, and M, which are simultaneously operating at 1, are operated by shifting one cycle at a time. Q is delayed by three cycles, but Q and P differ by one cycle, and W requires only two cycles. In. Further, the timings of the memory access units A to D are allocated. Next, the arithmetic units are assigned from a more critical path, and Q, U,
V, X, and Z are assigned to empty cycles. E is assigned so that execution is started at the same time as W. The order of the instructions in the source code is rearranged according to the order of these execution timings. The meaning of FIGS. 8 to 13 is that there is an empty cycle in the pipeline, and F, G,
K and L are changed to 5d and I which is 4e is changed to 5e, and FIG.
FIG. 3D, FIG. 4, and FIG. 5 are completed when the processes of Nos. To 13 are performed.

A to G, I, K, and L shown in a bold line frame in FIG. 4 and in bold italic characters in FIG. 5 are processes corresponding to the next instruction of the program counter. That is, it is the part that performs the parallel processing described in the present embodiment. The hatched portion indicates a substantial execution cycle of the load instruction. B to G, I, K, and L shown in a bold frame in FIG. 6 and in bold italics in FIG. 7 are processes corresponding to the next instruction of the program counter. In FIGS. 4 and 6, since speculative fetching of a register corresponding to 5e in FIG. 1 is limited to mask data, a register conflict condition does not occur in an instruction following the L instruction of B. That is, the comparison step is unnecessary.
Therefore, logic for avoiding register conflicts is unnecessary.

Although the present embodiment does not use a linked branch (subroutine call) such as a function call,
A connection branch may be used at a branch point. In the present embodiment, in the store-related instructions, the refetch data of the instruction issued after the store operation to the memory is compared with the fetch data of the instruction issued before the store operation to the memory. However, a) comparison of parts of the command word,
b) comparison of the address of the instruction word and the address of the store data; c) comparison of some bits constituting the address of the instruction word and the store data; d) the address of the instruction word is the address of the store data + store E) the address of the instruction word in the range of the data length is within the range of the address of the store data + the fixed value; f) the address of the instruction word is
A) that the value is within a range of a value obtained by adding a fixed value and a value obtained by adding a part of the bits of the address of the store data to zero.
Or f).

In this embodiment, the case where the degree of parallelism of the superscaler is 2 has been described, but it may be 3 or more. Further, in the present embodiment, a specific example of speculatively executing the writing of the register and the memory for the next instruction is not described in advance. Since it is partially understood, the same effect can be obtained even if execution is performed in advance or error detection and error processing for speculative execution are added. Further, in the present embodiment, an example is shown in which only the execution of the current instruction and the execution of the next instruction are performed in parallel. However, if the degree of parallelism of the superscaler increases, the parallel processing must be performed on three or more instructions. The effect may be less likely to appear, and parallel processing may be performed.

Processing of the instruction indicated by the program counter;
Next, in order to be able to execute in parallel the process of decoding the instruction indicated by the program counter and the process of reading the register value used by the instruction indicated by the program counter, a machine instruction sequence that performs those processes is described in a mixed manner. Then, parallelism occurs in the operation with poor parallelism by itself, and the parallelism by the pipeline acceleration function of the processor used for simulation execution and the superscaler is utilized,
The number of clock cycles required for processing is greatly reduced, and high-speed instruction simulation can be realized. Also,
According to the present invention, compared to the difficulty of optimization in which the order is changed in one large dependent process, considerable optimization is performed by changing the execution order of two independent processes. Performance improvement is easy at the time of new design.

Further, the processing of the instruction indicated by the program counter and the processing of the instruction indicated by the next program counter are not mixed, and the processing is executed in the pipeline gap generated in the branch processing using the table arranged in the memory. A method of apparently reducing the time by filling in the decoding and speculatively executable processing with the information before processing, or performing the processing that can only be performed sequentially for each field in parallel with the processing that requires the number of cycles of another field , The existing instruction simulation can be sped up with few changes.

In general, when performing meaningful processing by a program mounted on computer hardware, the performance is slightly improved by the optimization function of the compiler that is aware of the pipeline and superscaler. It is very difficult to perform the optimization by analyzing the variables constituting the steps or the algorithm, and the investment efficiency of the optimization is not good. On the other hand, in the instruction simulation of the present invention, since the simulator itself that simulates another computer is frequently used, it is not necessary to analyze and optimize the algorithm of the application other than the simulator, and the performance can be improved.

[0042]

As described above, according to the present invention, the current instruction and the next and subsequent instructions are grouped into one large process, and another processing variable is assigned to each. Since the unit process of another instruction is assigned to the idle time of the execution cycle, the operation can be shortened by performing the parallel operation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a concept and an operation flow of emulation according to Embodiment 1 of the present invention.

FIG. 2 is a diagram illustrating instruction copy and change of an operation flow position which are part of the concept of the present invention.

FIG. 3 is an explanatory diagram of a program order change for performing a parallel operation with reduced time, which is a part of the concept of the present invention.

FIG. 4 is a coding diagram for performing a parallel operation of a load instruction according to the first embodiment;

FIG. 5 is an execution cycle diagram for performing a parallel operation of a load instruction according to the first embodiment.

FIG. 6 is a coding diagram for performing a parallel operation of a store instruction in the first embodiment.

FIG. 7 is an execution cycle diagram for performing a parallel operation of a store instruction in the first embodiment.

FIG. 8 is a coding diagram detailing unit processing of another load instruction in the first embodiment.

FIG. 9 is a diagram showing a table of constraints on the execution order between instructions by decomposing the process of FIG. 8 into unit processes.

FIG. 10 is a diagram showing the relationship of FIG. 9 as a connection relationship.

FIG. 11 is a diagram illustrating a critical path in FIG. 10;

12 is a diagram illustrating a required count number of resources in the critical path in FIG. 11;

FIG. 13 is an explanatory diagram of allocating another unit process to an idle time of an execution cycle.

FIG. 14 is an operation flowchart of a conventional serial instruction simulation.

FIG. 15 is a diagram showing an example of a conventional program for simulating one instruction.

FIG. 16 is a diagram showing a relationship between a decoding bit width of a cache and a required amount of hardware.

FIG. 17 is a diagram illustrating an example of an instruction format.

FIG. 18 is a diagram showing the processing content of a conventional load instruction.

FIG. 19 is a diagram showing a conventional load instruction execution example using a superscaler computer.

20 is an execution cycle diagram in the pipeline stage of FIG.

FIG. 21 is a diagram showing codes, notations, and meanings of a conventional instruction set.

[Explanation of symbols]

1 Initialization processing (common processing), 2 instruction word fetch / decoding, 2a instruction word fetch processing, 2b instruction code field cutout processing, 2c instruction code corresponding branch table fetch processing, 2d instruction register field cutout processing, 2e Processing for speculatively fetching a part of a register used for instruction processing, processing for branching to a routine specific to each instruction 2f, instruction 1 to be simulated 1
4 processes related to the instruction indicated by the program counter, 4e a register or memory read process of a processor (A) that simulates an instruction, 4g a field extraction and decoding process from an instruction word, 4h address calculation process, 4i instruction simulation Processing for reading data from the memory of the processor (A) that performs
Arithmetic processing (data access of registers), 4l Write processing to the register or memory of the processor (A) performing the instruction simulation, processing related to the instruction indicated by the next program counter, 5a fetch of the next instruction word, 5b next instruction code Extraction, 5c Fetch of branch table of next instruction code, 5d Extraction processing of field indicating register number of next instruction, 5e Partial speculative fetch of register contents used in next instruction, 5f
Branching to a routine specific to each instruction, 6 Setting the refetched instruction word after the store operation to the main memory to the next instruction word variable, comparing speculatively fetched instruction words in advance, 7 Copying instruction word variables , 8 Flow transition to move to next instruction processing after processing for each instruction code, 8a 5f, path directly branching to 3 corresponding to next instruction, 8c
Depending on the instruction, a path for branching to the common unit 2 instead of providing 5 corresponding to the next instruction processing, a path for checking whether the instruction word fetched before the data store in the processing of 8n 5 has been changed, A path for checking whether the instruction fetched before the data store outside the processing of 8o5 is changed, and comparing the instruction fetched before the data store and the instruction fetched after the store outside the processing of 8p5. A path in the case of a match, a path in the case where the instruction words fetched before and after the 8q data store are compared and they do not match.

Claims (5)

[Claims] A program created for another machine instruction set is simulated using a simulation program combining a machine instruction set of a processor having a pipeline mechanism and a multiple instruction simultaneous execution mechanism (super scaler mechanism). A method of copying the operation of the next instruction after the operation of the current instruction for simulation, and allocating processing variables to the operation of the current instruction and occupying resources for executing the operation. And a processing variable different from that of the current instruction operation is allocated to the next instruction operation processing, and the time required to execute the operation while occupying resources is compared. The use of the other short instruction arithmetic processing overlaps with the step of obtaining the arithmetic processing) and the execution cycle idle time included in the step during the long instruction arithmetic processing. A step of allocating a step of the short instruction operation processing to the idle time and performing a parallel operation when using a resource not to be used. 2. A step of reading the next instruction word and comparing it with an instruction of the next instruction operation processing which has already been performed in parallel in a subsequent step of the current instruction operation processing. 2. The instruction emulation method according to claim 1, further comprising a step of discarding a next instruction operation that is being performed in parallel and performing a next instruction operation process again. 3. The critical path cuts out a unit process constituting an instruction operation process for each unit process, determines an order between the unit processes in the cut-out unit process based on an operation execution condition, and determines the determined critical process. If the execution cycle idle time included in the instruction execution step of the unit processing group that gives the path uses resources that do not overlap in use by other unit arithmetic processing other than the unit arithmetic processing group in the critical path, the idle time is 2. The instruction emulation method according to claim 1, further comprising a step of allocating steps of the other unit operation processing to perform parallel operations. 4. The instruction emulation method according to claim 1, wherein when a branch step is present during the instruction operation processing, the branch step is provided after both the current instruction operation processing and the next instruction operation processing. 5. The instruction emulation method according to claim 1, wherein, when the resource is a pipeline operation mechanism, steps are allocated on the assumption that different register portions of the pipeline are not used repeatedly.