JP2002176323A - Coupling circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coupling circuit for improving the rise performance of a received signal. SOLUTION: This coupling circuit having a capacitor (C1) where a first direct current bias voltage is applied to one end when a signal is not inputted, and a signal is applied together with a second direct current bias voltage to the one end and a signal from which a direct current component is eliminated is outputted from the other end when the signal is inputted, has bias compensating circuits (R5 and Q3) for performing compensation so that the direct current bias voltage of the one end of the capacitor (C1) can be the second direct current bias voltage when the signal is not inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a coupling circuit,
In particular, the present invention relates to a coupling circuit that can suppress a voltage transient that occurs when switching between transmission and reception of a signal.

[0002]

2. Description of the Related Art FIG. 5 shows a wireless LAN (Local Ar).
FIG. 2 is an example of a system configuration diagram of FIG.
FIG. 5 shows a personal computer 10, wireless LAN devices 11, 12, a printer 13, an access point 14, and an Ethernet LA.
N15. In FIG. 5, the personal computer 10 is connected by a wireless line to an access point 14 connected to an Ethernet 15 by a wireless LAN device 11 connected to the personal computer 10. The printer 13 is connected to an access point 14 connected to an Ethernet 15 by a wireless line by a wireless LAN device 12 connected to the printer 13. Access point 14,
The personal computer 10, the printer 13, and the like constitute a wireless LAN. The access point 14 is connected to the Ethernet 15, and the personal computer 10, the printer 13, and the like exchange signals with devices connected to the Ethernet 15 via the wireless LAN.

A conventional wireless LAN device 1 shown in FIG.
The internal configuration and operation of the first and second embodiments will be described with reference to FIG. FIG. 6 is a diagram showing a circuit configuration of a wireless LAN device 11 as an example of the related art, in which an antenna 20, a BPF (Band Pas
s Filter) 21, transmission / reception switching circuit 22, amplifier 2
3, 24, mixers 25 and 26, modulator 27, demodulator 2
8, oscillators 29 and 30, buffer 31, D / A converter 32, A / D converter 33, digital processing circuit 3
4. It is composed of a microcomputer 35, a RAM 37, and an IF 36.

In FIG. 6, a wireless LAN device 11 is connected to a personal computer 10, and a signal is supplied from the personal computer 10 when transmitting a signal. A signal from the personal computer 10 is transmitted to the access point 14 via the IF 36, digital processing circuit 34, D / A converter 32, modulator 27, mixer 25, amplifier 23, transmission / reception switching circuit 22, BPF 21, and antenna 20. . The signal from the access point 14 is transmitted to the antenna 20, the BPF 21, the transmission / reception switching circuit 22, the amplifier 24, the mixer 26, the demodulator 28,
The data is supplied to the personal computer 10 via a buffer 31, an A / D converter 33, a digital processing circuit 34, and an IF 36.

In the wireless LAN device 11, a reception enable signal RXEN and a transmission enable signal TXEN are supplied from the microcomputer 35 to the transmission / reception switching circuit 22. The transmission / reception switching circuit 22 responds to a signal from the microcomputer 35,
3 and the amplifier 24, the signal transmission and reception are switched.

At the time of reception, a signal received from the antenna 20 is demodulated by the demodulator 28 and supplied to the buffer 31. The data is supplied to the A / D converter 33 via the buffer 31. The A / D converter 33 includes a buffer 31
Is converted into a digital signal and supplied to the digital processing circuit 34. Hereinafter, the buffer 31 will be described in detail.

FIG. 7 is a circuit diagram showing an example of a conventional buffer and its peripheral circuits. In FIG. 7, buffer 3
1 is provided at an intermediate stage between the demodulator 28 and the A / D converter 33. The demodulator 28 includes a resistor R1, an npn transistor Q1, a current source 38, and the like. Resistance R1
Has one end connected to the power supply voltage Vcc and the other end connected to the collector of the transistor Q1. Transistor Q
The emitter of the transistor 1 is grounded via a current source 38, and the base of the transistor Q1 is supplied with a DC component and a received signal.

The buffer 31 includes an npn transistor Q
2, a resistor R2 and a capacitor C1. The base of the transistor Q2 is composed of the resistor R1 and the transistor Q1.
Connected to the collector connection point. Transistor Q
2 is connected to the power supply voltage Vcc, and the emitter of the transistor Q2 is connected to one end of the resistor R2. The other end of the resistor R2 is grounded. Further, a connection point d between the emitter of the transistor Q2 and the resistor R2 is connected to one end of the capacitor C1.

The A / D converter 33 includes a capacitor C1
, And a resistor R3 is inserted on the input side. Note that the resistor R3 is an input impedance when the A / D converter 33 is viewed from the buffer 31, and is treated as a resistor for convenience of explanation. The DC component is cut by the capacitor C1, and only the signal component is
1 to the A / D converter 33.

Next, the operation of the circuit shown in FIG. 7 will be described with reference to FIG. FIG. 8 is an operation waveform diagram of an example of the related art, and a reception signal is omitted for convenience of explanation. In FIG. 8, the vertical axis represents voltage, and the horizontal axis represents time. 8A shows the voltage at the base a of the transistor Q1, FIG. 8B shows the voltage at the base b of the transistor Q2, and FIG. 8C shows the voltage at one end c of the capacitor C1.

First, the reception OF shown in a period T3 shown in FIG.
At F, the voltage at the base a of the transistor Q1 is
As shown in FIG. 8A, the voltage is v2, and the transistor Q1 is turned off. At this time, the voltage of the base b of the transistor Q2 becomes the voltage v3 (Vc) as shown in FIG.
c). The voltage at one end c of the capacitor C1 is shown in FIG.
The voltage is Vref (= 0) as shown in FIG.

As described above, when reception is OFF, the current I1 flows through the emitter of the transistor Q2, and the voltage V is applied to the connection point d between the emitter of the transistor Q2 and the resistor R2.
A voltage of d = I1 × R2 is generated. The capacitor C1 is charged until both ends of the capacitor C1 reach the voltage Vd. The other end c of the capacitor C1 is connected to an input resistor R3.
Grounded.

Thereafter, when reception is turned on in a period T4 in FIG. 8, the voltage at the base a of the transistor Q1 becomes v1 as shown in FIG. 8A, and the transistor Q1 is turned on. As a result, the collector potential of the transistor Q1 decreases, and the voltage of the base b of the transistor Q2 becomes v4 (v4 <v3) as shown in FIG. 8B. At this time, the connection point d between the emitter of the transistor Q1 and the resistor R2 drops to the voltage v5 as shown in FIG. 8C, and thereafter gradually becomes the reference voltage Vref from the voltage v5.

This operation will be described in detail. When reception is ON, the current I1 'is applied to the emitter of the transistor Q2.
(I1 ′ <I1) flows. As a result, the voltage Vd ′ is applied to the connection point d between the emitter of the transistor Q2 and the resistor R2.
= I1 ′ × R2. At this time,
Since the current I1 'is smaller than the current I1 at the time of the FF, the connection point d changes from the voltage Vd to Vd'. As a result, the discharge current I2 flows from the capacitor C1 in the direction of the resistor R2 so that the voltage across the capacitor C1 changes from Vd to Vd ', and the capacitor C1 is discharged. As shown in FIG. 8C, the other end c of the capacitor C1 drops by the voltage of the difference between the voltages Vd and Vd 'at the moment when the reception is switched from OFF to ON, and becomes the voltage v5. Thereafter, the other end c of the capacitor C1 gradually becomes the reference voltage Vref from the voltage v5 by the time constant of the capacitor C1 and the resistors R2 and R3.

FIG. 9 is a diagram in which a signal component is added to the voltage change shown in FIG. 9A shows the voltage of the base a of the transistor Q1, FIG. 9B shows the voltage of the base b of the transistor Q2, and FIG. 9C shows one end c of the capacitor C1.
Are shown. FIGS. 9A, 9B, and 9C show
When the reception is OFF in the period T3, only the DC component of the signal is shown, and when the reception is ON in the period T4, the DC component and the voltage of the signal component are shown. The A / D converter digitizes a signal in the voltage range dV.

[0016]

Conventionally, as shown in FIG. 9C, the reference voltage Vref decreases at the moment when the reception is switched from OFF to ON, and the signal during the time T5 is shifted from the voltage range dV. . Therefore, the signal at the time of switching is out of the voltage range of the A / D conversion, and is not subjected to the A / D conversion.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a coupling circuit that improves the rising characteristics of a received signal.

[0018]

According to the present invention, the first DC bias voltage is applied to one end in the first state, and the second DC bias voltage is applied to the second state in the second state. In addition, in a coupling circuit having a capacitor (C1) that outputs a signal from which a signal is applied to one end and a DC component is removed from the other end, a DC bias voltage at one end of the capacitor (C1) in the first state Is a second DC bias voltage.
Q3).

According to a second aspect of the present invention, in the first aspect, the capacitor (C1) and the bias compensation circuit (R5, Q
3) a buffer amplifier (Q2) that amplifies the input signal and supplies the signal to the capacitor (C1).
It is characterized by having.

The invention described in claim 3 is the first or second invention.
, The bias compensation circuit (R5, Q3) includes a resistor (R5) having one end connected to the input of the buffer amplifier, and a first transistor (Q3) having the other end of the resistor (R5) connected to the emitter or collector. And an operation signal whose level changes when a signal is input and when no signal is input is supplied to a base of the first transistor (Q3).

According to the present invention, in the first state in which no signal is input, the bias compensating circuit (R5, R5) compensates for the DC bias voltage at one end of the capacitor (C1) to become the second DC bias voltage. By having Q3), the change in the DC bias voltage between the first state where no signal is input and the second state where the signal is input can be made substantially constant, and the rise of the reception signal can be made. The characteristics can be improved.

Note that the reference numerals in the parentheses are provided for easy understanding, are merely examples, and are not limited to the illustrated embodiment.

[0023]

FIG. 1 is a block diagram of a wireless LAN device according to an embodiment of the present invention. 6, the same components as those of FIG. 6 are denoted by the same reference numerals, and the description thereof will be omitted. The wireless LAN device 13 of the present invention is different from the conventional wireless LAN device 11 in that the configuration of the buffer 40 and the reception enable signal RXEN for controlling the operation of the receiving system circuit are supplied to the buffer 40 from the microcomputer 35. I do. The reception enable signal RXEN controls the bias voltage so that it does not change during transmission and reception. Hereinafter, the buffer 40 will be described in detail.

FIG. 2 is a circuit diagram of a buffer and its peripheral circuits according to an embodiment of the present invention. In the figure,
The same parts as those in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted. The buffer 40 of the present invention is different from the conventional buffer 31 in that a bias compensation circuit is provided at the base of the npn transistor Q2. The buffer 40 of the present embodiment
It comprises a pnp transistor Q3, resistors R4, R5 and the like. One end of a resistor R5 is connected to the base of the transistor Q2.

The other end of the resistor R5 is connected to the emitter of the transistor Q3, the collector of the transistor Q3 is grounded, and the base of the transistor Q3 is connected to one end of the resistor R4. The other end of the resistor R4 is connected to the terminal 42. The terminal 42 is supplied with a reception enable signal RXEN signal from the microcomputer 35.

Next, the operation of the circuit shown in FIG. 2 will be described with reference to FIG. FIG. 3 is an operation waveform diagram of the buffer according to the embodiment of the present invention. 3A shows the voltage of the base e of the transistor Q1, FIG. 3B shows the voltage of the base f of the transistor Q2, and FIG. 3C shows one end g of the capacitor C1.
FIG. 3D shows the level of the signal supplied to the terminal 42.

First, the reception OF shown in a period T1 shown in FIG.
At F, the voltage at the base e of the transistor Q1 is
As shown in FIG. 3A, the voltage is v7, and the transistor Q1 is turned off. Further, as shown in FIG. 3D, the reception enable signal RXEN is at a low level. Therefore,
The transistor Q3 is turned on, and the current I3 is drawn from the base f of the transistor Q2 via the resistor R5.
At this time, a voltage Vh = I4 × R2 is generated at a connection point h between the emitter of the transistor Q2 and one end of the resistor R2. Note that the current I3 is set to be equal to the amount of the bias drawn into the collector of the transistor Q1 at the time of transmission, as described later.

When the reception is ON as indicated by time T2 in FIG. 3, the voltage at the base e of the transistor Q1 becomes v6 as shown in FIG. 3A, and the transistor Q1 is turned on.

When the transistor Q1 is turned on, a predetermined amount of current is drawn into the collector of the transistor Q1.
At this time, the predetermined amount of current drawn is the transistor Q
3 is set to be equal to the current drawn into the emitter of the transistor Q3 when turned on.

At this time, as shown in FIG. 3D, the reception enable signal RXEN is at a high level, and the transistor Q3 is off. Thus, the transistor Q
1 is on, the transistor Q3 is off, and the resistor R1
, The voltage of the base f of the transistor Q2 hardly changes. Therefore, the current I4 flowing to the resistor R2 via the transistor Q2 hardly changes. Therefore, the voltage V is applied to the connection point h between the emitter of the transistor Q2 and one end of the resistor R2 as in the transmission.
A voltage of h = I4 × R2 is generated.

Thus, when switching to reception ON,
Since the voltage at the base f of the transistor Q2 does not change, the voltage Vh at the connection point h hardly changes. Accordingly, the voltage at both ends of the capacitor C1 does not change, so that the other end g of the capacitor C1 is connected to A / A as shown in FIG.
The voltage Vref of the D converter 33 is constant.

Accordingly, by turning on / off the transistor Q3 in response to the reception enable signal RXEN from the microcomputer 35, there is no change in the potential of the base f of the transistor Q2 between reception ON and reception OFF, and the capacitor C1 Also hardly changes at both ends. Therefore, a voltage change at the other end g of the capacitor C1 can be suppressed.

FIG. 4 is a diagram in which signal components are added to the voltage changes shown in FIGS. 3 (A), 3 (B) and 3 (C). FIG.
(A), (B), and (C) show reception O indicated by period T1.
In the case of FF, it indicates the voltage of only the DC component of the signal,
2 shows the DC component of the signal and the voltage of the signal component when the reception is indicated by 2. 4 (A), (B), (C)
When reception is ON, the signal of the signal component is received during the voltage range dV. In FIG. 4C, since the voltage does not change at the moment when the reception is switched from OFF to ON and is within the voltage range dV, the A / D converter can digitize the signal. Therefore, the performance of the signal rising characteristic can be improved.

Further, by using the buffer 40 shown in FIG. 2, it is not necessary to turn on the demodulator 28 at the time of transmission so that the demodulator 28 is continuously operated, so that the current consumption can be reduced.
Functionality can be improved. Further, the transistor Q3 may be formed of an npn transistor, and the signal supplied to the base may be controlled by the transmission enable signal TXEN for controlling the operation of the transmission circuit.

The transistor Q in the buffer 40
2. Without providing the resistor R2, it is possible to prevent the occurrence of an offset, improve the performance of the signal rising characteristic, and simplify the circuit configuration.

Further, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the present invention.

[0037]

According to the coupling circuit of the present invention, the bias compensating circuit for compensating the DC bias voltage at one end of the capacitor to the second DC bias voltage in the first state where no signal is input is provided. With this configuration, the change in the DC bias voltage in the first state where no signal is input and the change in the DC bias voltage in the second state where the signal is input can be made substantially constant, and the rising characteristics of the received signal can be improved. Can be done.

[Brief description of the drawings]

FIG. 1 is a block diagram of a wireless LAN device according to an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a buffer and its peripheral circuit according to an embodiment of the present invention.

FIG. 3 is an operation waveform diagram of one embodiment of the present invention.

FIG. 4 is a diagram in which a signal component is added to the voltage changes shown in FIGS. 3A, 3B, and 3C.

FIG. 5 is an example of a system configuration diagram of a wireless LAN.

FIG. 6 is a circuit configuration diagram of an example of a conventional buffer and its peripheral circuit.

FIG. 7 is a circuit configuration diagram of an example of a conventional buffer and its peripheral circuits.

FIG. 8 is an operation waveform diagram of a conventional example.

FIG. 9 is a diagram in which a signal component is added to the voltage change shown in FIG. 8;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Personal computer 11, 12, 13 Wireless LAN 13 Printer 20 Antenna 21 BPF (Band Pass Filter) 22 Transmission / reception switching circuit 23, 24 Amplifier 25, 26 Mixer 27 Modulator 28 Demodulator 29, 30 Oscillator 31, 40 Buffer 32 D / A converter 33 A / D converter 34 Digital processing circuit 35 Microcomputer 37 RAM 36 IF

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Satoshi Tanaka 8-8-8 Kokuryo-cho, Chofu-shi, Tokyo Mitsumi Electric Co., Ltd. F-term (reference) 5J091 AA01 AA45 CA65 FA10 FP01 HA02 HA25 HA29 KA00 KA05 KA34 KA32 KA34 KA44 KA53 KA55 MA21 QA04 SA13 TA01 TA06 5K011 DA21 GA04 JA00 KA13

Claims (3)

[Claims] 1. A first DC bias voltage is applied to one end in a first state, a signal is applied to one end together with a second DC bias voltage in a second state, and a DC component is applied from the other end. A coupling circuit having a capacitor that outputs the signal from which the signal has been removed, wherein in the first state, a bias compensation circuit that compensates for a DC bias voltage at one end of the capacitor to be the second DC bias voltage. A coupling circuit comprising: 2. The coupling circuit according to claim 1, further comprising a buffer amplifier connected between the capacitor and the bias compensation circuit, for amplifying an input signal and supplying a signal to the capacitor. 3. The bias compensation circuit includes: a resistor having one end connected to an input of the buffer amplifier; and a first transistor having the other end of the resistor connected to an emitter or a collector. 3. The coupling circuit according to claim 1, wherein an operation signal whose level changes in the first state and in the second state is supplied to a base of the transistor.