JP2002175180A - Reciprocal operation method and reciprocal operation device, and computer-readable recording medium with reciprocal operation program recorded thereon - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reciprocal operation method suitable for shortening the time taken for an operation and reducing the circuit scale, a reciprocal operation device and a recording medium with reciprocal operation program recorded thereon. SOLUTION: This device is provided with 5 registers Ua, Ub, Va, Vb and W, 2 adders, a 1-bit arithmetic right shifter and a selector group. By repeating parallel update for the 5 registers Ua, Ub, Va, Vb and W, a reciprocal is calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reciprocal operation method and a reciprocal operation device based on a binary Euclidean algorithm.

[0002]

2. Description of the Related Art Conventionally, a binary Euclidean algorithm (Binary extended gcd algorithm) is known as a method for calculating a reciprocal number on a remainder field using a prime number p as a modulus. For example, the reference Handbook of Applied Cryptography (by A.
Menezes, P. van Oorschot, and S. Vanstone, CRC Pre
ss, 1996), p.608, Binary Euclidean Algorithm (Bin
ary extended gcd algorithm). The Binary Euclidean algorithm was introduced in 1962 by R.
Invented by Silver and J. Tersian.

FIG. 28 is a diagram showing an algorithm described in the above document. As can be seen from the figure, the algorithm (binary Euclidean algorithm) 2800 described in the above-mentioned document receives two positive integers x and y, and as a result, integers a, b, and satisfies the relationship of ax + by = v. Calculate v. Here, v = gcd (x, y), and gc
d (x, y) means the greatest common divisor of x and y.

The algorithm 2800 includes a process 2801 for initializing the variables u, v, A, B, C and D, a process 2802 for dividing and updating the variables u, A, B by 2 and a process 2802 for updating the variables v, C and D. The process 2803 of updating by dividing by 2, the variable u,
Processing 280 for updating each variable based on the magnitude relation of v
4. Processing 2805 based on the value of the variable u.
FIGS. 29 and 30 show an algorithm 280 as an example.
4 shows a flowchart of a reciprocal operation method based on 0. Note that, in the above document, the reciprocal (gcd (x, y) = 1)
It is shown that there is no need to calculate the values of the variables A and C in the algorithm shown in FIG. Thus, the calculation of A and C is omitted in the flowchart. Also, the calculation of the variable g is omitted because v = 1.

[0005] As shown in FIG.
800 (hereinafter, reciprocal operation method 28)
First, two positive integers are input to variables x and y (step S2901), and while x and y are even numbers (step S2902), x is x / 2 and y is y.
/ 2 is substituted (step S2903). Then, x is substituted into u, y is substituted into v, 0 is substituted into B, 1 is substituted into D, and variables u, v,
B and D are initialized (step S2904).

Next, as shown in FIG.
02, it is determined whether or not the variable u is an even number. If the result of the determination is that u is an odd number, the processing proceeds to step 2803. If u is an even number, the following processing is performed (step S30).
01). Substitute u / 2 for the variable u (step S300)
2). Then, it is determined whether B is an even number (step S3003). As a result of the determination, if B is an even number, B / 2 is substituted for the variable B (step S3004), and if B is an odd number, (B−x) / 2 is substituted for the variable B (step S3005). ). As described above, the process returns to step S3001 and is repeated.

A process 2803 determines whether or not the variable v is an even number. If the result of the determination is that the variable v is an odd number, the process 2803
Proceeding to 04, if v is an even number, the following processing is performed (step S3011). Substitute v / 2 for the variable v (step S3012). Then, it is determined whether D is an even number (step S3013). If the result of the determination is that D is an even number, D / 2 is substituted for the variable D (step S
3014), if D is odd, the variable D is set to (D−
x) / 2 is substituted (step S3015). As described above, the process returns to step S3011 to repeat the process.

In step 2804, the magnitude relationship between the variables u and v is determined (step S3021). If the result of the determination is that u is greater than v, uv is substituted for the variable u and BD is substituted for the variable B (step S3021). If u is smaller than v, vu is substituted for the variable v and DB is substituted for the variable D (steps S3024 and S3025). And FIG.
As can be seen from FIG.
0) is determined (step S2911).
Processing 280 until the condition (u = 0) is satisfied as a result of the determination.
2 (step S3001) or processing 2803 (step S3011), the processing is repeated, and when the condition (u = 0) is satisfied, D is substituted for the variable b (step S291).
2) The value of the variable b is output, and the process ends (step S2913).

(Supplementary Items) Here, the flowcharts of FIGS. 29 and 30 will be supplemented. (Supplement-1) The processing 2802 and the processing 2803 are the same as the processing except that the variables to be processed are different. (Supplement-2) As the arithmetic processing, a subtraction processing (f (x,
y) = xy) and shift processing (g (z) = z / 2) only. Note that, instead of the subtraction processing, an addition processing (f (x, y) = x + (− y)) may be performed.

(Supplement-3) In step 2802, variables u and B are independent of each other.
The variables v and D are independent of each other. Similarly, processing 280
Also in 4, the variables u and B are independent, and the variables v and D are independent. Thereby, step S
It is possible to process 3002 and S3004 or S3005 in parallel, and update variables u and B in parallel. Similarly, steps S3012 and S3014 or S301
5 can be processed in parallel, and variables v and D can be updated in parallel. Steps S3022 and S302
3 or Steps S3024 and S3025 can be processed in parallel to update variables u and B or v and D in parallel.

The above (Supplement-1) to (Supplement-
In consideration of 3), two types of reciprocal operation devices based on the algorithm 2800 can be considered: a sequential processing device and a parallel processing device. Here, the sequential processing device refers to a reciprocal operation device that includes one subtractor or one adder and one 1-bit arithmetic right shifter and sequentially processes variables u, v, B, and D. The parallel processing device includes two subtracters or two adders and two 1-bit arithmetic right shifters, and based on (Supplement-3), variables u, v, B, D
Are processed in parallel.

[0012]

However, the sequential processing device has a smaller circuit scale than the parallel processing device, but instead of processing the variables u, v, B, and D sequentially, the time spent for the operation is reduced. become longer. On the other hand, the parallel processing device requires two subtractors or two adders and two 1
The provision of the bit arithmetic right shifter has a problem that the circuit scale is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a reciprocal operation method suitable for reducing the time required for the operation and reducing the circuit scale, and an apparatus based on the reciprocal operation method. It is an object of the present invention to provide a reciprocal operation device and a computer-readable recording medium in which the reciprocal operation method is recorded as a program.

[0014]

In order to solve the above-mentioned problem, a reciprocal operation method according to the present invention comprises a reciprocal operation method for obtaining a reciprocal of an integer A on a modulo modulo a predetermined positive prime p. And the five intermediate value holding registers U
a, Ub, Va, Vb, W, Ua = A, Ub = 2, V
an initialization step of initializing a = -p, Vb = 0, W = A-p, an update step of executing the following (a) to (e) in parallel, and (a) first setting the value of Ua The first value is (a1) Ub or (a2) (Ub / 2 mod p), and the value of (b) Ub is changed to (b1) W or (b2) Ua. Updating, (c) updating the value of Va to a second value, the second value being (c1) (Vb / 2 modp), or (c2) Vb
And (d) updating the value of Vb to (d1) W or (d2) Va, and updating the value of (e) W to a value obtained by adding the first value and the second value. That is, when the value of Ub is not 0, the updating step is executed again.
And an output step of outputting as a reciprocal to the updating step, wherein the updating step selects the pair of (a1) and (c1) and the pair of (a2) and (c2), and for (b) and (d), A set other than the set of b1) and (d1) is selected, and the five intermediate value holding registers are updated in parallel.

Further, the updating step manages four flags F1 to F4 indicating a state, and
2), (b1) or (b2), (c1) or (c2), (d1) or (d2)
Are selected according to the values indicated by the flags F1 to F4. Further, in the initialization step, the four flags F1, F2, F3, and F4 are set as follows: F1 = 0, F2 = Ua
[0] (the value of the least significant bit of Ua), F3 = 0, F4 =
W [s] (the value of the sign bit of W), the updating step executes the following (f) to (i) in parallel, and (f) inverts the value of the flag F1, (g) ) When the value of the flag F2 is 1 and the value of the flag F3 is 0,
(g1) Update to the value of the least significant bit of the first value, and
Is 1 and the value of the flag F3 is 1, the (g2) second
Is updated to the value of the least significant bit of the value of (a), otherwise (g3) is not updated, (h) the value of the flag F3 is 0, and the value of the flag F1 is 0 and the value of the flag F2 is 1. Contains (h
1) Update to the value of F4, otherwise (h2) Do not update, (i) Change the value of flag F4 to 1
In the case of (i1), update to the value of the sign bit of the value obtained by adding the first value and the second value, and if the value of the flag F1 is 0, (i2) do not update. I do.

Further, in the updating step, in (a), when the value of the flag F3 is 1, (a1) is selected, and when the value of the flag F3 is 0, (a2) is selected. Then, in (b), if the value of the flag F2 is 1 and the value of the flag F4 is 0, (b1) is selected; otherwise,
(b2) is selected, and in (c), the value of the flag F3 is set to 1
In the case of (c), (c1) is selected, and when the value of the flag F3 is 0, (c2) is selected. In (d), the value of the flag F2 is 1 and the value of the flag F4 is 1 In this case, select (d1). Otherwise, select (d2).

Further, in the initialization step, the integer A may be repeatedly subtracted by the value of p until the integer A becomes less than the prime number p, and the intermediate value holding registers Ua and W may be initialized based on the subtraction result. Further, the updating step includes the step (a2) (U
b / 2 mod p), when Ub is an even number,
If Ub is arithmetically shifted right by one bit, and if Ub is an odd number, the value of p is added or subtracted to Ub, arithmetically shifted right by one bit, and Vb is calculated as (c1) (Vb / 2 mod p).
Is an even number, Vb is arithmetically shifted right by one bit,
If b is odd, add or subtract the value of p to Vb,
Arithmetic shift by one bit right may be performed.

Further, n is 1 or more and 2 ^n-1 <p <2 ⁿ
Is a positive integer that satisfies the relationship of
As (a2), when Ub is an odd number, Ub is 2
If ^n-1 or less, adds the value of p in Ub, if Ub is 2 ^n-1 or more, the value of p by subtracting the Ub, as the (c1), V
When b is an odd number and Vb is 2 ^n-1 or less, V
The value of p may be added to b, and the value of p may be subtracted from Vb if Vb is 2 ^n-1 or more.

In order to solve the above problem, a reciprocal operation device of the present invention is a reciprocal operation device for obtaining a reciprocal of an integer A on a modulo modulo a predetermined positive prime p. , Intermediate values registers Ua, Ub, Va, Vb, which hold integers A, 2, -p, 0, Ap, respectively.
W, a first selector for selecting one of the intermediate value registers Ub and Vb, a division unit for dividing the selection result of the first selector by 2 on the remainder field, and a division result for the intermediate value register Ub and the division unit. A second selector for selecting one and outputting the result to the intermediate value register Ua; a third selector for selecting one of the intermediate value register Vb and the division result of the division unit and outputting the result to the intermediate value register Va; An adder that adds the result and the selection result of the third selector and outputs the result to the intermediate value register W, a fourth selector that selects one of the intermediate value register Ua and the addition result and outputs the result to the intermediate value register Ub,
A fifth selector that selects one of the intermediate value register Va and the addition result and outputs the selected result to the intermediate value register Vb, and controls selection of the first to fifth selectors until the value of the intermediate value register Ub becomes 0, The intermediate value registers Ua, Ub,
A control unit that repeatedly updates Va, Vb, and W repeatedly and outputs the value of the intermediate value register Ua as the reciprocal of the integer A when the value of the intermediate value register Ub becomes 0.

Further, the control section includes a flag section for holding four flags F1 to F4 for indicating states, and a selector control section for controlling selection of the first to fifth selectors according to the values of the four flags. And the value of the intermediate value register Ub is 0
, The four flags F1 to F4 are updated simultaneously, and the five intermediate value registers Ua, Ub, Va, V
b, an updating unit for updating W.

Further, the division unit includes an adder for adding and subtracting a prime number p when the selection result of the first selector is an odd number, and a 1-bit right arithmetic shifter for right-arithmically shifting the addition result by the adder. Is provided.

[0022]

(Embodiment 1) A reciprocal operation method according to Embodiment 1 of the present invention calculates an inverse of a positive integer A on a remainder field modulo an n-bit prime p. The method is executed in hardware as shown in FIGS. 8 and 9, for example. This hardware shows five intermediate value holding registers for holding five intermediate values Ua, Ub, Va, Vb, and W, two adders, a 1-bit arithmetic right shifter, a plurality of selectors, and states. A plurality of flip-flops that hold flags F1 to F4.
Here, it is assumed that n is 160 bits, and each intermediate value holding register is a 162 bit register with the most significant bit as a sign bit.

(Configuration of Reciprocal Calculation Method) FIGS.
5 is a flowchart illustrating a reciprocal operation method according to the first embodiment. As can be seen in FIG.
0 (hereinafter, referred to as a reciprocal operation method 100) receives an input of an operation number A for performing a reciprocal operation (step S101);
A for Ua, 2 for Ub, -p for Va, 0 for Vb, A- for W
Substitute p and initialize variables Ua, Ub, Va, Vb, and W (step S102). Then, F1 is 0, Fa is Ua [0], F3 is 0, F4 is W [s], and F5 is Ub.
[0] is substituted, and the flags F1 to F5 are initialized (step S103). Here, Ua [0] is a variable Ua
And W [s] indicates the value of the sign bit of the variable W (the bit indicating the sign of the variable). When indicating the value of the k-th bit of the variable Ua,
Ua [k]. Note that the same applies to the variables Ub, Va, Vb, and W.

Next, the variables Ua, Ub, Va, Vb are updated in parallel (steps S111 to S114). (Process of Updating Variable Ua) As shown in FIG. 2, step S111 determines the values of the flags F3 and F5 (steps S201 and S202). Then, based on the result of the determination, if the value of the flag F3 is 1, the variable Ua is set to U
If the value of the flag F3 is 0 and the value of the flag F5 is 0, the value of the flag F3 is 0 and the value of the flag F3 is set to Ub / 2.
When the value of 5 is 1 (when Ub is an odd number), (Ub−
p) / 2 (steps S211 to S21)
3).

(Update of Variable Ub) Step S112
Determines the values of the flags F2 and F4 (step S22).
1). Then, based on the result of the determination, when the value of the flag F2 is 1 and the value of the flag F4 is 0,
W is updated to Ua in other cases (steps S231 and S232).

(Update of Variable Va) Step S113
Determines the values of the flags F3 and F5 (step S24).
1, S242). Based on the result of the determination, the variable Va is set to Vb when the value of the flag F3 is 0, and to Vb when the value of the flag F3 is 1 and the value of the flag F5 is 0.
b / 2, the value of the flag F3 is 1 and the value of the flag F5 is 1
(Vb is an odd number), it is updated to (Vb + p) / 2 (steps S251 to S253).

(Update of Variable Vb) Step S114
Determines the values of the flags F2 and F4 (step S26).
1). Then, based on the result of the determination, when the value of the flag F2 is 1 and the value of the flag F4 is 1,
W is updated to Va in other cases (steps S271 and S272).

(Update process of variable W) Then, as shown in FIG. 1, the variables Ua and Va are added to update the variable W (step S115). Next, in parallel, the flag F1
To F4 (Steps S121 to S12)
4).

(Update of Flag F1) As shown in FIG. 3, in step S121, the flag F1 is updated by inverting the value of the flag F1 to 0 if it is 1 and 1 if it is 0 (step S30).
1). (Update processing of flag F2) In step S122, the values of the flags F1 and F3 are determined (step S311). Then, based on the result of the determination, the flag F2 is changed to the flag F1.
Is 1 and the value of the flag F3 is 0, Ua
In [0], the value of the flag F1 is 1 and the value of the flag F3 is 1
Is updated to Va [0] (Step S321,
S322) Otherwise, it is not updated.

(Update of Flag F3) Step S12
3 judges the values of the flags F1 and F2 (step S3
31). Then, based on the result of the determination, the flag F3
Is updated to the value of the flag F4 when the value of the flag F1 is 0 and the value of the flag F2 is 1 (step S341),
Otherwise, do not update.

(Update of Flag F4) Step S12
4 judges the value of the flag F1 (Step S35)
1). Then, the flag F4 is set based on the result of the determination.
When the value of the flag F1 is 1, it is updated to W [s] (the value of the sign bit) (step S361), and when the value of the flag F1 is 0, it is not updated.

(Update of Flag F5) As shown in FIG. 1, the flag F5 is updated based on the value of the flag F3.
5 to Vb [0] when the value of the flag F3 is 1,
If the value of the flag F3 is 0, it is updated to Ub [0] (step S125). In addition, “Expression 1? Expression 2: Expression 3”
Means a ternary operator, determines whether the expression 1 is true or false, and sets true (0
In the case of (other than), the value of Expression 2 is taken, and in the case of false (0), the value of Expression 3 is taken.

Next, it is determined whether the condition (Ub = 0) is satisfied (step S131). As a result of the judgment, the condition (Ub
= 0) is not satisfied, the processing in steps S111 to S111
Returning to 114, the process is repeated, and if the condition (Ub = 0) is satisfied, the value of the variable Ua is output as the reciprocal of the operation number A, and the process ends (step S132). (Supplementary Information-A) Here, the reciprocal operation method 100 will be supplemented.

(Supplement-A1) Flags F1 to F5 are set to 0
Or one of the values 1, and by combining the values of the flags F1 to F5, the variables Ua, Ub, Va, Vb,
W update processing is controlled. (Supplement-A2) In steps S111 to S114, when the variables Ua and Va are updated in parallel, the variable to be divided by two (1-bit arithmetic right shift processing) is set to the flag F
3 controls one. That is, S2 in FIG.
12 (or S213), “Ua ← Ub / 2 (or Ua ← (Ub−p) / 2)” and S252 (or S25).
3) “Va ← Vb / 2 (or Va ← (Vb−p)
/ 2) "is executed alternatively. As a result, the adder and the 1-bit arithmetic right shifter can be shared by S111 and S113.

(Supplement-A3) Variables Ua, Ub, Va, V
The process from the update process (b) (steps S111 to S114) to the condition determination process (step S131) is defined as one loop. For example, speaking of three loops, variables Ua, Ub,
Update processing of Va and Vb (Steps S111 to S11
This refers to executing the processing from 4) to the condition determination processing (step S131) three times.

(Regarding Variables Ua, Ub, Va, Vb, W) Next, the variables Ua, U
b, Va, Vb, and W will be described in association with the reciprocal operation method 2800 described in the related art. FIG. 4 shows the variables Ua,
9 is a table showing the correspondence between Ub, Va, Vb, W and variables u, v, B, D.

As can be seen from FIG.
Based on 00, when the value of the flag F1 is 0, the variable Ua corresponds to v, the variable Ub corresponds to D, the variable Va corresponds to -u, the variable Vb corresponds to -B, and the variable W corresponds to v-u. I do. Flag F1
Is 1, the variable Ua is D, and the variable Ub is v
, The variable Va is -B, the variable Vb is -u, and the variable W is D
Corresponds to -B.

(Flags F1 to F5) Next, the flags F1 to F5 in the reciprocal operation method 100 will be described in association with the reciprocal operation method 2800 described in the conventional art. FIG. 5 is a table in which the processing of updating the flags F1 to F5 is associated with the processing of the reciprocal operation method 2800.

As can be seen from FIG.
If it is associated with 00, the flag F1 indicates in the process 2802 which of the variables u or B is to be updated,
Processing 2803 indicates which of the variables v or D is to be updated.
3005, S3012, S3014, S3015, S3
It is updated when any one of the processes S022, S3023, S3024, and S3025 is executed.

The flag F2 indicates whether or not to execute the processing 2804.
2, S3023 and S3025 are updated when any of the processes is executed. The flag F3 indicates which of the processing 2802 and the processing 2803 is to be executed,
It is updated when any of the processes of 3022 and S3024 is executed.

The flag F4 indicates which of the variables u or v in the processing 2804 is to be updated.
It is updated when any of the processes of 002, S3012, S3023, and S3025 is executed. The flag F5 indicates whether the variable to be updated is an even number or an odd number. Steps S3002, S3004, S3005, S3012
S3014, S3015, S3022, S3023, S
It is updated when any one of the processes 3024 and S3025 is executed.

As described above, the update timing of each flag in the reciprocal operation method 100 is determined based on the table 500. FIG. 6 corresponds to the reciprocal operation method 2800,
It is a table of a process performed by flags F1 to F5. In the table 600, the reciprocal operation method 10
Each flag is set to 0, the column is processed in the reciprocal operation method 2800, and “○” indicates a process to be executed (processable), “
“×” indicates that the processing is not executed (processing is impossible), and “−” indicates that the processing may or may not be executed.

As can be seen from the figure, when the value of the flag F1 is 0, steps S3004, S3005, S3
014, S3015, S3022, and S3024 are allowed to be processed, and steps S3002, S3012, S3023,
S3025 is set to processing impossible. If the value of the flag F1 is 1, steps S3002, S3012, S302
Steps S3004 and S3025
3005, S3014, S3015, S3022, S3
024 cannot be processed.

If the value of the flag F2 is 0, steps S3022 to S3025 cannot be processed. Flag F
If the value of 2 is 1, steps S3022 to S30
25 can be processed. When the value of the flag F3 is 0,
Steps S3012, S3014, and S3015 are allowed to be processed, and steps S3002, S3004, and S3005 are disabled. If the value of the flag F3 is 1, steps S3002, S3004, and S3005 are allowed to be processed, and steps S3012, S3014, and S3015 are disabled.

If the value of the flag F4 is 0, steps S3024 and S3025 are permitted to be processed, and step S30
22 and S3023 cannot be processed. If the value of the flag F4 is 1, steps S3022 and S3023 are allowed to be processed, and steps S3024 and S3025 are disabled. If the value of the flag F5 is 0, step S30
02, S3004, S3012, and S3014 can be processed, and steps S3005 and S3015 cannot be processed. If the value of the flag F5 is 1, step S300
5, S3015 can be processed, and steps S3002, S3015
Steps 3004, S3012, and S3014 are disabled.

FIG. 7 is a table showing processing executed based on a combination of the values of the flags F1 to F5 based on the table 600. In the table 700, the row is a process in the reciprocal operation method 2800, and the column is a combination of the values of the flags F1 to F5 in the reciprocal operation method 100. No processing (processing not possible).

As can be seen from FIG.
Combination of values of 1 to F5 {F1, F2, F3, F
When 4, F5} = {0,0,0,0,0}, step S3014 is executed. ｛F1, F2, F3, F
When 4, F5} = {0,1,0,1,0}, steps S3014 and S3022 are executed. The variables u, v, B, and D are independent variables, and can be updated at the same time. That is, the flags F1 to F
Depending on the combination of the values of step 5, step S3002,
While any of the variables u and v is updated by any of S3012, in parallel, steps S3023 and S30
3025, any of the variables B and D is updated. Similarly, step S3004 (or S30)
05) and S3014 (or S3015), while the variables B and D are updated, and in parallel, the variables u and v are updated by one of steps S3022 and S3024.
Is updated.

As described above, based on the table 700, the variable U
The update processing of a, Ub, Va, Vb, and W is controlled. (Initial Value in Reciprocal Operation Method 100) Next, an initial value in the reciprocal operation method 100 will be described. Based on the table 400 and step S2904, the variable U
The initial values of a, Ub, Va, Vb, and W are {Ua, U
b, Va, Vb, W} = {A, 1, −p, 0, Ap}
Can be considered. Here, x = p and y = A.

However, based on the following considerations, the variables Ua, Ub, Va, V
b, W and initial values of the flags F1 to F5 are determined. In the reciprocal operation method 2800, when the operation number A is an odd number, one of steps S3022 and S3024 is executed. On the other hand, according to the table 700, step S3
022, flags F1 to F for executing S3024 independently
It is shown that there is no combination of values of 5.
That is, in the reciprocal operation method 100, when the operation number A is an odd number, steps S3022 and S3024 are not executed independently, and steps S3004, S3005, and S
A pair is formed with any of the processes 3014 and S3015.

Further, among the combinations of the values of the flags for controlling steps S3004 and S3005, the flag F2
F5 is based on the evenness of the variables Va and Vb. On the other hand, among the combinations of the values of the flags that control steps S3014 and S3015, the flags F2 and F5
a, Ub. As a result, steps S3004 and S3005 are processes that do not depend on the evenness of the operation number A, and are excluded from the processes to be performed on the initial values. As a result, steps S3014 and S3015 are given as processing performed on the initial values.

As described above, the combination of the values of the flags F1 to F5 for executing any one of steps S3014 and S3015 is determined by using the flags F1 to F5 in the reciprocal operation method 100.
The initial value of. Further, steps S3014 and S30
15, the variables Ua, Ub, Va,
When the values of Vb and W are {Ua, Ub, Va, Vb, W} =
Variables Ua, Ub, which become {A, 1, −p, 0, Ap}
The values of Va, Vb, and W are set as initial values of the variables Ua, Ub, Va, Vb, and W in the reciprocal operation method 100.

Specifically, according to the table 700, the combination of the values of the flags F1 to F5 for executing the step S3014 {F1, F2, F3, F4, F5} = {0,
0,0,0,0} (when the operation number A is even and A> p), or {0,1,0,0,0} (when the operation number A is odd and A> p), or { 0,0,0,1,0}
(If the operand A is even and A <p), or {0,
1,0,1,0} (when the operation number A is odd and A <p)
Is the initial value. The same applies to step S3015.

Also, {Ua, Ub, Va, Vb, W} =
Back calculation from {A, 1, −p, 0, Ap} gives {U
a, Ub, Va, Vb, W} = {A, 2, -p, 0, A
−p} (in the case of step S3014) or {Ua, U
b, Va, Vb, W} = {A, 2 + p, -p, 0, A-
p｝ (in the case of step S3015) is the initial value. In the reciprocal operation method 2800, when the operation number A is an even number, step S3012 is executed. On the other hand, according to the table 700, there is a combination of the values of the flags F1 to F5 for executing the step S3012 independently. That is, in the reciprocal operation method 100, when the operation number A is an even number, step S3012 is executed independently, and the behavior is the same as that of the reciprocal operation method 2800.

(Configuration of Reciprocal Arithmetic Apparatus) The configuration of the reciprocal arithmetic apparatus implemented as the above based on the reciprocal arithmetic method 100 will be described. FIG. 8 shows a reciprocal operation method 100.
FIG. 2 is a block diagram of a reciprocal operation device implemented as a device based on FIG.

As can be seen from FIG.
0 includes an initial value setting unit 801, a correction value storage unit 802, a calculation unit 803, a control unit 804, and an output unit 805. The initial value setting unit 801 receives the operation number A and reads the value of the prime number p from the correction value storage unit 802. And
Variables Ua, Ub, Va, Vb, W and flags F1 to F5
And the variables Ua, Ub, Va, Vb, W
Is transferred to the arithmetic unit 803, and the flags F1 to F5
Is transferred to the control unit 804.

The correction value storage unit 802 stores the value of the prime number p and transfers it to the initial value setting unit 801. Further, based on the value of the prime number p, a correction value (p, -p, 0) used for correction in the calculation unit 803 is transferred. The prime number p is 160 bits. The calculation unit 803 receives the initial values of the variables Ua, Ub, Va, Vb, and W from the initial value setting unit 801.
Then, it receives the values of the flags F1 to F5 from the control unit 804, updates the values of the variables Ua, Ub, Va, Vb, W, and transfers the values of the variables Ua, Ub to the output unit 805. further,
The value of the least significant bit of the variables Ua, Ub, Va, Vb and the value of the sign bit of the variable W are transferred to the control unit 804. Also, the correction value (p, -p, 0) is received from the correction value storage unit 802.

The control unit 804 receives the initial values of the flags F1 to F5 from the initial value setting unit 801. Then, the value of the least significant bit of the variables Ua, Ub, Va, Vb and the value of the sign bit of the variable W are received from the arithmetic unit 803, and the flag F1
Update the values of F5 through F5 and transfer them to the calculation unit 803. The output unit 805 receives and analyzes the values of the variables Ua and Ub from the calculation unit 803. As a result of the analysis, when the condition (Ub = 0) is satisfied, the value of the variable Ua is output as the reciprocal of the operation number A.

FIG. 9 is a detailed block diagram of the arithmetic unit 803 and the control unit 804. In the description of the block diagram, when a plurality of input lines such as a selector are provided,
Input lines (input values) are distinguished by inputting a left input line (L), inputting a middle input line (C), and inputting a right input line (R). (Configuration of the arithmetic unit 803) As shown in FIG.
The operation unit 803 includes registers 901 to 905, selectors 911 to 916, adders 921 and 922, and a 1-bit arithmetic right shifter 931.

The registers 901 to 905 are the registers 9
01 is the value of the variable Ua, the register 902 is the value of the variable Ub,
The register 903 receives the value of the variable Va, the register 904 receives the value of the variable Vb, and the register 905 receives the value of the variable W. The values input to the registers 901 and 902 are transferred to the output unit 805. It is assumed that the number of bits in each register is 162 bits with the most significant bit as a sign bit.

The selectors 911 to 916 select and output an input value (input line) according to a value input as a control input or a combination of the values. Adders 921, 9
22 adds the input values of the input (L) and the input (R),
Output. 1-bit arithmetic right shifter 931 shifts the input value by 1-bit arithmetic right and outputs the result. The number of bits of each adder and each selector is 162 bits as in each register.

(Configuration of Control Unit 804) As shown in FIG. 9B, the control unit 804 includes a flip-flop 941
To 945, selectors 951 to 954, and a NOT gate 961. Flip-flops 941 to 9
45 is the value of the flag F1 in the flip-flop 941, the value of the flag F2 in the flip-flop 942, the value of the flag F3 in the flip-flop 943, and the flip-flop 944.
To the value of the flag F4, and the flip-flop 945 to the flag F
This is a flip-flop to which a value of 5 is input. And
The value input to the flip-flops 941 to 945 is
It is output as a control input of each selector.

The selectors 951 to 954 select and output a data input according to a value or a combination of values input as a control input. The NOT gate 961 outputs a value of 1 when a value of 0 is input, and outputs a value of 0 when a value of 1 is input. (Supplementary item-B) Here, the arithmetic unit 803 and the control unit 804
And supplement.

(Supplement-B1) Registers 901 to 905
The initial value setting unit 801 sets an initial value of the operation number A in the register 901, 2 in the register 902, −p in the register 903, 0 in the register 904, and Ap in the register 905. (Supplement-B2) The flip-flops 941 to 945 are
The initial value setting unit 801 sets the flip-flop 941 to 0, the flip-flop 942 to the value of the least significant bit of the register 901, the flip-flop 943 to 0, the flip-flop 944 to the sign bit value of the register 905, and the flip-flop 945 to the register 902. Is set as the initial value.

(Supplement-B3) The selectors 911, 912, and 915 receive flip-flops 943 as control inputs.
Is input. The selectors 913 and 916 include:
Output values of the flip-flops 942 and 944 are input. The selector 914 includes flip-flops 943, 9
Forty-five output values are input. The output values of the flip-flops 941 and 943 are input to the selector 951. The output value of the flip-flop 942 is input to the selector 952. The selector 953 has a flip-flop 9
41 output values are input. The input value of the flip-flop 943 is input to the selector 954.

(Supplement-B4) A cycle in which the value of the flip-flop 941 is inverted from 0 to 1 or 1 to 0 is defined as one cycle, and the time required for one cycle is defined as one clock. (Input Selection of Each Selector) FIG. 10 is a table showing input selection of each selector. In the description of each table, the flip-flops 941 to 945 are omitted, and
Notated as F1 to F5.

As shown in FIG. 10A, the selector 911 selects the input (L) when the value of F3 is 0, and selects the input (R) when the value of F3 is 1. Select
As shown in FIG. 10B, the selector 912 outputs
When the value of 3 is 0, the input (R) is selected, and when the value of F3 is 1, the input (L) is selected. FIG. 10 (c)
As shown in the above, the selector 913 selects the input (R) when the value of F2 is 1 and the value of F4 is 0, and otherwise selects the input (L).

As shown in FIG. 10D, the selector 914 selects the input (R) when the value of F5 is 0, and selects the input (R) when the value of F3 is 0 and the value of F5 is 1. Selects the input (L), and selects the input (C) when the value of F3 is 1 and the value of F5 is 1. When the input (R) is selected, it means that the correction is not performed. FIG.
As shown in (e), the selector 915 selects the input (R) when the value of F3 is 0, and selects the input (L) when the value of F3 is 1.

As can be seen from FIG. 10 (f), when the value of F2 is 1 and the value of F4 is 1,
Select input (L), otherwise input (R)
Select As shown in FIG. 10G, the selector 951 selects the input (R) when the value of F1 is 0, and selects the input (R) when the value of F1 is 1 and the value of F3 is 0. If (C) is selected and the value of F1 is 1 and the value of F3 is 1, the input (L) is selected.

As can be seen from FIG. 10 (h), the selector 952 selects the input (R) when the value of F2 is 0, and selects the input (L) when the value of F2 is 1. Select
As shown in FIG. 10 (i), the selector 953
When the value of 1 is 0, the input (R) is selected, and when the value of F1 is 1, the input (L) is selected. FIG. 10 (j)
, The selector 954 selects the input (L) when the value of F3 is 0, and selects the input (R) when the value of F3 is 1.

(Reciprocal operation device 800 and reciprocal operation method 10
Next, the correspondence between the reciprocal operation device 800 shown in FIGS. 8 and 9 and the reciprocal operation method 100 shown in FIG. 1 will be described. FIG. 11 is a table showing the correspondence between each component of the reciprocal operation device 800 and each process in the reciprocal operation method 100.

As can be seen from FIG.
1 accepts an input of the operation number A and outputs the variables Ua, Ub, V
a, Vb, W and the processing of initializing the flags F1 to F5 (steps S101 to S103). The calculation unit 803 corresponds to the process of updating the variables Ua, Ub, Va, Vb, and W (Steps S111 to S115). In FIG. 1, after executing S111 to S114 in parallel, S
Although step S115 is executed, the calculation unit 801 executes steps S111 to S114 and S115 in parallel. That is, S11
5 to calculate W = Ua + Va.
01 (Ua) and the input data, not the output data of the register 902 (Va), are pre-fetched and the adder 911 is configured to add them. This allows five registers 90
1, 902, 903, 904, and 905 can be updated simultaneously at the same clock timing.

The control unit 804 corresponds to the processing for updating the flags F1 to F5 (steps S121 to S125). In FIG. 1, the determination in S125 is performed after S121 to S124 are executed in parallel, but the control unit 804 determines
Steps 121 to S124 and S125 are executed in parallel with one clock. In addition, the update of the variables (S111 to S115) in the arithmetic unit 803 and the update of the flags (S121 to S125) in the control unit 804 are simultaneously executed at the same clock timing. As a result, the reciprocal operation device 800 executes one loop from S111 to S131 with one clock.

The output unit 805 corresponds to the process of outputting the reciprocal (steps S131 and S132). Register 90
1 to 905 correspond to variables Ua, Ub, Va, Vb, and W. The selector 911 determines which of the variables Ub and Vb is to be shifted (step S20).
1, S241).

The selector 912 determines whether to assign the result of the shift operation to the variable Ua (step S20).
This corresponds to 1). The selector 913 sets the variable W to the variable Ub
(Step S221). The selector 914 corresponds to a process (steps S202 and S242) of determining whether the prime number p is added and corrected, subtracted and corrected, or whether the correction process is not performed.

The selector 915 determines whether to assign the result of the shift operation to the variable Va (step S24).
This corresponds to 1). The selector 916 sets the variable W to the variable Vb.
(Step S261). The adder 921 corresponds to the process of adding or subtracting the value of the prime number p to or from the value of the variable Ub or Vb in the reciprocal operation method 100 and correcting the value (steps S213 and S253).

The adder 922 corresponds to the process of adding the values of the variables Ua and Va (step S115). The 1-bit arithmetic right shifter 931 performs a shift operation on the variable Ub or Vb (steps S212, S213, and S25).
2, S253). The flip-flops 941 to 945 correspond to the flags F1 to F5.

The selector 951 corresponds to the processing for determining whether to update the value of the flag F2 (step S311). The selector 952 corresponds to the process of determining whether to update the value of the flag F3 (Step S331). The selector 953 corresponds to the process of determining whether to update the value of the flag F4 (Step S351).

The selector 954 corresponds to the process of determining whether to update the value of the flag F5 (the ternary operator in step S125). NOT gate 961 has a flag F
This corresponds to the process of updating the value of 1 (step S301). (Steps S111 to S115 and step S121
12 to FIG. 16 are circuits corresponding to
Steps S111 to S115 and steps 121 to S
125 shows a block diagram of a circuit corresponding to 125. The arithmetic unit 803 and the control unit 804 are indicated by broken lines, and circuits corresponding to the processing are indicated by solid lines.

As shown in FIG. 12A, the circuit corresponding to step S111 includes registers 901 and 902,
It comprises selectors 911, 912, 914, an adder 921 and a 1-bit arithmetic right shifter 931. The input line (L) of the selector 912 is connected to the output line of the register 902, and the input line (R) of the selector 912 is connected to the output line of the 1-bit arithmetic right shifter 931.
The output line 2 is connected to the input line of the register 901.
Then, by switching the selector 912, the register 9
Either the value obtained by shifting the value of 02 and the value of the register 902 are selected and transferred to the register 901.

As shown in FIG. 12B, the circuit corresponding to step S121 includes a flip-flop 941,
And a NOT gate 961. NOT gate 9
The input line 61 is connected to the output line of the flip-flop 941, and the output line of the NOT gate 961 is connected to the input line of the flip-flop 941. Then, the value of the flip-flop 941 is inverted to 1 if 0 and 0 if 1 by the NOT gate 961 and transferred to the flip-flop 941.

As shown in FIG. 13A, the circuit corresponding to step S112 includes registers 901, 902,
905 and a selector 913. Selector 9
13 is connected to the output line of the register 901, and the input line (R) of the selector 913 is connected to the register 90.
5, and the output line of the selector 913 is connected to the input line of the register 902. Then, by switching the selector 913, one of the value of the register 901 and the value of the register 905 is selected, and
2

As shown in FIG. 13B, the circuit corresponding to step S122 includes a flip-flop 942,
And a selector 951. The input line (L) of the selector 951 is connected to a line separately branched from the least significant bit line of the input line of the register 903, and the input line (C) of the selector 951 is connected to the least significant bit of the input line of the register 901. The selector 951 is connected to a line separately branched from the line.
Is connected to the output line of the flip-flop 942, and the output line of the selector 951 is connected to the input line of the flip-flop 942. And the selector 95
By switching 1, one of the value of the least significant bit of the register 903, the value of the least significant bit of the register 901 and the value of the flip-flop 942 is selected and transferred to the flip-flop 942.

As shown in FIG. 14A, the circuit corresponding to step S113 includes registers 903, 904,
It comprises selectors 911, 915, 914, an adder 921, and a 1-bit arithmetic right shifter 931. The input line (R) of the selector 915 is connected to the output line of the register 904, and the input line (L) of the selector 915 is connected to the output line of the 1-bit arithmetic right shifter 931.
The output line of No. 5 is connected to the input line of the register 903.
Then, by switching the selector 915, the register 9
One of the value obtained by shifting the value of the value 04 and the value of the register 904 is selected and transferred to the register 903.

As shown in FIG. 14B, the circuit corresponding to step S123 includes a flip-flop 943,
944 and a selector 952. Selector 9
The input line (L) of 52 is connected to the output line of the flip-flop 944, the input line (R) of the selector 952 is connected to the output line of the flip-flop 943, and the selector 95
The output line 2 is connected to the input line of the flip-flop 943. By switching the selector 952, the value of the flip-flop 944 and the flip-flop 94
3 is selected and flip-flop 943 is selected.
Is forwarded to

As shown in FIG. 15A, the circuit corresponding to step S114 includes registers 903, 904,
905 and a selector 916. Selector 9
The input line (L) of the selector 916 is connected to the output line of the register 905, and the input line (R) of the selector 916 is connected to the register 90.
3, and the output line of the selector 916 is connected to the input line of the register 904. Then, by switching of the selector 916, one of the value of the register 905 and the value of the register 903 is selected, and
4 is transferred.

As shown in FIG. 15B, the circuit corresponding to step S124 includes a flip-flop 944,
And a selector 953. The input line (L) of the selector 953 is connected to a line separately branched from the sign bit line of the input line of the register 905, and the input line (R) of the selector 953 is connected to the output line of the flip-flop 944. The output line of 953 is a flip-flop 94
4 input lines. Then, the selector 953 selects one of the value of the sign bit of the register 905 and the value of the flip-flop 944, and is transferred to the flip-flop 944.

As shown in FIG. 16A, the circuit corresponding to step S115 includes registers 901, 903,
905 and an adder 922. Adder 922
Is connected to the line branched from the input line of the register 901, the input line (R) of the adder 922 is connected to the line branched from the input line of the register 903, and the output of the adder 922. The line is connected to the input line of the register 905. Then, the adder 922 adds the input value of the register 901 and the input value of the register 903 and transfers the result to the register 905.

As shown in FIG. 16B, the circuit for executing step S125 includes a flip-flop 945,
And a selector 954. The input line (L) of the selector 954 is connected to the least significant bit line branched from the input line of the register 902, and the input line (R) of the selector 954 is connected to the least significant bit line branched from the input line of the register 904. , And the output line of the selector 954 is connected to the input line of the flip-flop 945. And
Either the value of the least significant bit of the register 902 or the value of the least significant bit of the register 904 is selected by the selector 954 and transferred to the flip-flop 945.

(Supplementary Information-C) Here, the reciprocal arithmetic unit 8
The correspondence between 00 and the reciprocal operation method 100 will be supplemented. (Supplement-C1) “1 loop” in the reciprocal operation method 100 is “1 cycle” in the reciprocal operation device 800.

(Supplement-C2) In the reciprocal arithmetic unit 800, the selector 911 controls one register to be shifted. This corresponds to (supplement-A5) in the reciprocal operation method 100. (Supplement-C3) When the apparatus is implemented (Supplement-C2), steps S212, S213, S252, and S253 are performed.
In the adders 921 and 1
Shared with bit arithmetic right shifter 931.

(Supplement-C4) The control input of the selector 954 is input from a line branched from the input line of the flip flap 943. (Supplement-C5) All input lines of the selector 914 are connected to the correction value storage unit 802. Output lines of the selector 914 are connected to the input (R) of the adder 931. And
One of the correction values (p, -p, 0) is selected by the selector 914 and transferred to the adder 931.

(Supplementary Items for Deviceization) Here,
Supplementary explanation will be given for the implementation of the reciprocal operation method 100. In the reciprocal operation method 100, steps S111 to S11
4 (update of variables Ua, Ub, Va, Vb) is executed in parallel, and then step S115 (update of variable W) is executed. Here, step S115
Is a process of assigning the result of addition of the variable Ua and the variable Va to the variable W. Therefore, "the output data of the register storing the variable Ua and the output data of the register storing the variable Va are added by the adder. Then, the configuration in which the addition result is stored in the register W may be "implemented A", or as shown in FIG. 9, "the input data of the register to which the variable Ua is input and the input data of the register to which the variable Va is input. A configuration of adding the input data and storing the addition result in the register W (B).

In other words, in implementing the reciprocal operation method 100, the circuit configuration differs depending on whether (mounting A) or (mounting B) is used. For example, a reciprocal operation device employing (implementation A) performs an addition process on an “output value” of a register corresponding to variables Ua and Va,
The updating process of the registers corresponding to the variables Ua, Ub, Va, and Vb and the updating process of the register corresponding to the variable W are executed “sequentially”. On the other hand, the reciprocal operation device adopting (implementation B) uses the "input value" of the register corresponding to the variables Ua and Va.
To the variables Ua, Ub, Va, V
It is possible to execute the update processing of b and W “in parallel”. As a result, compared to the case where (Mounting A) is adopted,
When (Implementation B) is adopted, the variables Ua, Ub, Va,
The update processing of Vb and W can be executed at the same clock timing, and the speed can be further increased. Then, the reciprocal operation device 800 executes the reciprocal operation method 10 based on (Implementation B).
0 was instrumented.

(Register Transfer) FIG. 17 shows, as an example,
{F1, F2, F3, F4, F5} = {1, 1, 0,
Operation unit 803 and control unit 804 in the case of 0,0｝
FIG. 3 shows a schematic diagram of register transfer in one cycle. The arithmetic unit 803 and the control unit 804 are indicated by broken lines, and the data flow of the register is indicated by solid lines.

As shown in the figure, the value output from the register 902 passes through a selector 911, an adder 921, a 1-bit arithmetic right shifter 931 and a selector 912.
The data is transferred to the register 901. Note that “0” is added by the adder 921, and the 1-bit arithmetic right shifter 931 is added.
Shifts right by one bit arithmetically. Register 905
Are transferred to the register 902 via the selector 913.

The value output from the register 904 is transferred to the register 903 via the selector 915. The value output from the register 903 is transferred to the register 904 via the selector 916. In addition, register 9
02, 904 are stored in registers 901, 9
03, and via the adder 922, the register 905
Is forwarded to The register 9 is added by the adder 922.
02, 904 are added.

The value of the sign bit of the value input to the register 905 is set separately from the register 905 by the selector 9.
The data is also transferred to the flip-flop 944 via 53. The value output from the flip-flop 944 is transferred to the flip-flop 943 via the selector 952. The value of the least significant bit of the value input to the register 901 is transferred to the flip-flop 942 via the selector 951 separately from the register 901.

The value output from the flip-flop 941 passes through a NOT gate 961 and the flip-flop 9
41. The value of the least significant bit of the value input to the register 902 is also transferred to the flip-flop 945 via the selector 954 separately from the register 902. Further, the value input to the flip-flop 943 is different from the value input to the flip-flop 943 by the selector 954.
Is also input as a control input.

Then, the reciprocal arithmetic unit 800 updates the registers 901 to 905 and the flip-flops 941 to 945 in one cycle in parallel. (Operations of Reciprocal Operation Method 100 and Reciprocal Operation Device 800) Operations of the reciprocal operation method 100 and the reciprocal operation device 800 configured as described above will be described.

FIG. 18 shows an example in which the number of operations A is 271
In this case, the calculation results by the reciprocal calculation method 100 and the reciprocal calculation device 800 are shown. FIG.
As can be seen in (a), the table has columns 1801
Is the number of loops (number of cycles), and column 1802 is the variable Ua
(Register 901) value, variable Ub in column 1803
(Register 902), variable Va in column 1804
(Register 903), variable Vb in column 1805
(Register 904), the value of variable W (register 905) in column 1806, the value of flag F1 (flip-flop 941) in column 1807, the value of flag F2 (flip-flop 942) in column 1808, column 1809
The value of the flag F3 (flip-flop 943), the value of the flag F4 (flip-flop 944) in the column 1810, and the flag F5 (flip-flop 9) in the column 1811.
45).

As can be seen from FIG. 18B, the horizontal axis indicates time (the number of clocks), and the vertical axis indicates CLK (clock), flag F1 (flip-flop 941), and flag F2 in order from the top. (Flip-flop 94
2), a flag F3 (flip-flop 943), a flag F4 (flip-flop 944), and a flag F5 (flip-flop 945).

For example, according to the reciprocal operation method 100, 1
From the results of the third loop, according to the table 400, the variables Ua, Ub, Va, Vb, and W in the fourteenth loop are
{Ua, Ub, Va, Vb, W} = {D, v, -B,-
u, D-B}. Further, according to the table 700, the processing of the fourteenth loop is performed in step S3012 (v ←
v / 2). Then, in the fourteenth loop, {Ua, Ub, Va, Vb, W} = {33,
−281, −7, 24, 26}, {F1, F2, F3,
F4, F5} = {0, 1, 0, 0, 1} is calculated.

Similarly, from the result of the 14th loop, the variables Ua and U
b, Va, Vb, W are {Ua, Ub, Va, Vb,
W} = {v, D, -u, -B, vu}. Further, according to the table 700, the processing of the fifteenth loop is
Step S3015 (D ← (Dx) / 2), S302
4 (v ← v−u). Then, in the fifteenth loop, {Ua, Ub, Va, Vb, W}
= {333,26,24, -7, -308},｝ F
1, F2, F3, F4, F5} = {1,1,0,0,
0 ° is calculated.

As described above, the reciprocal operation method 100 outputs 106 as the reciprocal of 271 in the 25th loop. Note that the reciprocal operation device 800 similarly outputs 106 as the reciprocal of 271 in the 25th cycle, leading to the same result as the operation result shown in FIG. (Others) Note that it is also possible to repeatedly subtract the value of p until the operation number A becomes less than the prime number p, and initialize the variables Ua and W with the subtraction result.

The reciprocal operation method 100 according to the present embodiment can be performed by executing a reciprocal operation program describing the reciprocal operation method 100 on hardware such as a computer capable of performing parallel processing. Then, the reciprocal operation program is stored in an optical recording medium (for example, CD-RO).
M), a magnetic recording medium (for example, a hard disk), a magneto-optical recording medium (for example, an MO), a semiconductor memory (for example, a ROM), and the like. It can also be executed on a computer. In addition, by recording on a computer-readable recording medium such as a hard disk provided on general hardware such as a computer connected by a network, other data read via a transmission path such as a network can be used. It can also be executed on a computer.

(Embodiment 2) Hereinafter, the same points as those in FIGS. 1 to 18 shown in describing the reciprocal operation method 100 and the reciprocal operation device 800 in Embodiment 1 are denoted by the same reference numerals in the drawings. The second embodiment will be described focusing on the differences. (Configuration Different from Reciprocal Calculation Method 100) FIGS. 19 and 20
9 is a flowchart illustrating a reciprocal operation method according to Embodiment 2.

As shown in FIG. 19, reciprocal operation method 1
900 is different from the reciprocal operation method 100 shown in FIG.
The difference is that the flag F5 is not provided. Thus, the updating process of the flag F5 (step S125) is not provided.
As a result, the number of flags to be initialized is changed from five to four (step S1903).

Next, in parallel, the variables Ua, Ub, Va,
Vb is updated (steps S1911, S112, S1
913, S114). As seen in (variable update processing Ua) Figure 20, step S1911 is compared with the step S111, instead of determining the value of the flag F5, or variable Ub is even or odd, 2 ⁿ determines ^-1 or less (step S
2002, S2003). Then, based on the result of the determination, the variable Ua is set to Ub / 2 when the variable Ub is an even number (Ub [0] = 0), and the variable Ub is set to an odd number (Ub [0] =
1) and when it is 2 ^n-1 or less, (Ub + p) / 2
If the variable Ub is an odd number (Ub [0] = 1) and ^{equal to} or greater than 2 ⁿ⁻¹ , it is updated to (Ub−p) / 2 (steps S2012 to S2014).

(Update of Variable Va) Step S191
3 does not determine the value of the flag F5 as compared with step S113, but determines whether the variable Vb is an even number, an odd number, or 2 ^n-1 or less (steps S2042, S204).
2043). Then, based on the result of the determination, the variable Va
When the variable Vb is an even number (Vb [0] = 0),
The variable Vb is an odd number (Vb [0] = 1) and 2
^When the variable Vb is an odd number (Vb [0] = 1) and ^2n-1 or more,
(Vb-p) / 2 (steps S2052 to S2054).

As described above, in the reciprocal operation method 1900, the respective determination processes related to the flag F5 in the reciprocal operation method 100 are not the flag F5 but the determination process of determining whether the variable to be shifted is an even number or an odd number. ^It is replaced by the judgment processing of whether it is ^n-1 or less. (Supplementary Item-D) Here, the reciprocal operation method 1900 will be supplemented.

(Supplement -D1) n is 1 or more and 2 ^n-1 <
It is a positive integer satisfying the relational expression of p <2 ⁿ . (Supplement-D2) Under the method p, f (x) = (x + p) /
2, g (x) = (x−p) / 2, (x∈Z _p ) is f
According to (x) = g (x) + p, f (x) ≡g (x),
(Mod p). That is, the process of adding and correcting the prime number p and the process of subtracting and correcting it are synonymous under the modulus p.

(Supplement-D3) When calculating with a limited number of digits, overflow may occur. Therefore, when performing the correction process using the prime number p, steps S2003 and S2043 are provided in consideration of overflow. Accordingly, for example, in step S2003, Ub + p <2 ⁿ +2 ^n-1 <2 ^{n + 1} is indicated from Ub <2 ⁿ⁻¹ , and the variable Ub has n + 1 bits excluding the bit representing the sign. It is shown to calculate within.
The same applies to the variable Vb.

(Supplement -D4) Variables Ua, Ub, Va, Vb are set to n + 2 bits in consideration of the carry of the bit by the addition, the bit representing the sign, and (Supplement -D3). (Differences from Table 600) FIG. 21 is a table of processing executed by the flags F1 to F4 in association with the reciprocal operation method 2800. The table 2100
Represents each flag in the reciprocal operation method 1900 in a row,
The column is a process in the reciprocal operation method 2800, where “○” indicates a process to be executed (processable), “△” indicates a process to be executed conditionally (processable with a condition), and “×” indicates a process not to be executed (process not possible). ) And "-" are processing that may or may not be performed.

As can be seen from FIG.
When the value of the flag F1 is 0 as compared with the table 600, steps S3004, S3005, S301
4, S3015, S3022, and S3024 are processable conditionally. Here, "Processable with conditions"
Means that a process (for example, steps S2002 and S2042 in the reciprocal operation method 1900) for separately determining whether a variable is an even number or an odd number is provided for a variable to be processed, and based on the determination result. , "Processing possible" or "processing not possible".

If the variable to be processed is an even number, steps S3004 and S3014 are "processing possible", and steps S3005 and S3015 are "processing not possible". If the variable to be processed is an odd number, step S300
5, S3015 is "processable", and step S30
04 and S3014 are "processing not possible". FIG.
21 is a table showing processing executed based on a combination of values of flags F1 to F4 based on a table 2100. In the table 2200, the reciprocal operation method 2
800, and the column is a combination of the values of the flags F1 to F4 in the reciprocal operation method 1900.
“” ”Indicates a process to be executed (processable),“ △ ”indicates a process to be executed conditionally (processable with a condition), and“ × ”indicates a process not executed (process not possible).

As can be seen from FIG.
Combination of values of 1 to F4 {F1, F2, F3, F
If 4} = {0,0,0,0}, step S30
14, S3015 is executed conditionally. If the variable to be processed is an even number, step S3014 is executed. If the variable to be processed is an odd number, step S3015 is executed.
Is executed, and depending on whether the variable is even or odd,
Alternatively, the processing is selected.

Further, the combination of flags ｛F1, F2,
When F3, F4} = {0, 1, 0, 1}, if the variable to be processed is an even number, step S3014 is executed, and if it is an odd number, step S3015 is executed. Step S3022 is also executed at the same time. As described above, based on the table 2200, the variables Ua, Ub, Va, V
Calculation processing to be performed on b and W is determined.

(Configuration Different from Reciprocal Operation Device 800) Based on the reciprocal operation method 1900 configured as described above,
A reciprocal operation device that has been implemented will be described. FIG. 23 is a block diagram of a reciprocal operation device implemented based on the reciprocal operation method 1900.

As can be seen from FIG.
00 is different from the reciprocal arithmetic unit 800 in that the initial value setting unit 8
01, an initial value setting unit 2301 is provided, and instead of the calculation unit 803, a calculation unit 2303 is provided.
4 in that a control unit 2304 is provided instead of 4. The initial value setting unit 2301 is different from the initial value setting unit 801 in that
The difference is that the initial values of the flags F1 to F4 are set and the initial values of the flags F1 to F4 are transferred to the control unit 2304.

The operation unit 2303 receives the values of the flags F1 to F4 from the control unit 2304 as compared with the operation unit 803. Further, the value of the least significant bit of the variable Ua, the value of the least significant bit of the variable Va, and the value of the sign bit of the variable W are transferred to the control unit 2304, and the value of the least significant bit of the variables Ub, Vb is not transferred. The points are different. The control unit 2304 is different from the control unit 804 in that the initial value setting unit 2301
Through F4. Then, the calculation unit 2303
Receive the values of the least significant bits of the variables Ua and Va and the value of the sign bit of the variable W, update the values of the flags F1 to F4, and transfer them to the arithmetic unit 2303.

FIG. 24 shows the operation section 2303 and the control section 230.
4 is a detailed block diagram of FIG. In the description of the circuit configuration diagram, when a plurality of input lines such as a selector are provided, the left input line is input (L), the middle input line is input (C), and the right input line is input ( An input line (input value) is distinguished as R). (Configuration Different from Operation Unit 803) As shown in FIG. 24A, the operation unit 2303 differs from the operation unit 803 in that a selector 2414 is provided instead of the selector 914.

The selector 2414 is used as a control input.
, The value of the (n−1) th bit of the output value of the selector 911 and the value of the least significant bit are input. As shown in FIG. 24B, the control unit 2304 is different from the control unit 804 in that the control unit 2304 does not include the flip-flop 945 and the selector 954. FIG. 25 is a table showing the input selection of the selector 2414. In the description of the table, the value of the (n-1) th bit and the value of the least significant bit of the output value of the selector 911 are abbreviated as [n-1] and [0].

As shown in FIG. 25, the selector 241
4 selects the input (R) when the value of [0] is 0, and selects the input (C) when the value of [n-1] is 0 and the value of [0] is 1 If the value of [n-1] is 1 and the value of [0] is 1, the input (L) is selected. (Register transfer) FIG. 26 shows, as an example, $ F1, F
2, a schematic diagram of register transfer in one cycle between the arithmetic unit 2303 and the control unit 2304 when 2, F3, F4} = {1, 1, 0, 0}. The operation unit 2
303 and the control unit 2304 are indicated by broken lines, and the data flow of the register is indicated by solid lines.

As shown in the figure, the value output from the register 902 passes through a selector 911, an adder 921, a 1-bit arithmetic right shifter 931 and a selector 912.
The data is transferred to the register 901. Here, the value output from the register 902 is set to an even number, and “0” is added by the adder 921, and the 1-bit arithmetic right shifter 931
Shifts right by one bit arithmetically.

The value output from the register 905 is transferred to the register 902 via the selector 913. The value output from the register 904 is transferred to the register 903 via the selector 915. The value output from the register 903 passes through the selector 916,
4 is transferred.

Further, the values output from the registers 902 and 904 are transferred to the register 905 via the adder 922 separately from the registers 901 and 903. In addition,
The values output from the registers 902 and 904 are added by the adder 922. The value of the sign bit of the value input to the register 905 is different from that of the register 905.
The data is also transferred to the flip-flop 944 via the selector 953.

The value output from the flip-flop 944 passes through the selector 952 and
Is forwarded to The value of the least significant bit of the value input to the register 901 is determined separately from the register 901 by the selector 95.
1 and also transferred to the flip-flop 942.
The value output from the flip-flop 941 is transferred to the flip-flop 941 via the NOT gate 961.

Further, the output value of the selector 911 is n-1
The value of the bit and the value of the least significant bit are
4 is input as a control input. Then, the reciprocal operation unit 2300 performs one cycle by using the registers 901 to 905.
And the flip-flops 941 to 944 are updated in parallel. (Operation of reciprocal operation method 1900 and reciprocal operation device 2300) The reciprocal operation method 1900 configured as described above,
And the operation of the reciprocal operation device 2300 will be described.

FIG. 27 shows an example in which the number of operations A is 271.
In this case, the calculation results by the reciprocal calculation method 1900 and the reciprocal calculation device 2300 are shown. FIG.
As can be seen in (a), the table has column 2701
Is the number of loops (number of cycles), and column 2702 is the variable Ua
(Register 901) value, column 2703 contains variable Ub
(Register 902) value, variable Va in column 2704
(Register 903) value, variable Vb in column 2705
(Register 904), the value of variable W (register 905) in column 2706, the value of flag F1 (flip-flop 941) in column 2707, the value of flag F2 (flip-flop 942) in column 2708, column 2709
Shows the value of the flag F3 (flip-flop 943), and the column 2710 shows the value of the flag F4 (flip-flop 944).

As can be seen from FIG. 27B, the horizontal axis indicates time (the number of clocks), and the vertical axis indicates CLK (clock), flag F1 (flip-flop 941), and flag F2 in order from the top. (Flip-flop 94
2), a flag F3 (flip-flop 943), and a flag F4 (flip-flop 944). For example, according to the reciprocal operation method 1900, the variables Ua, Ub, Va, Vb, and W in the fourteenth loop are represented by {Ua, Ub,
Va, Vb, W} = {D, v, -B, -u, DB}. Further, the table 2200 indicates that the processing of the fourteenth loop is determined in step S3012 (v ← v / 2). And on the 14th loop,
{Ua, Ub, Va, Vb, W} = {33, 102, −
7, 24, 26}, {F1, F2, F3, F4} =
{0,1,0,0} is calculated.

Similarly, based on the result of the 14th loop, the variables Ua, U
b, Va, Vb, W are {Ua, Ub, Va, Vb,
W} = {v, D, -u, -B, vu}. Further, according to the table 2200, the processing in the fifteenth loop is conditionally performed in steps S3014 (D ← D / 2), S3
015 (D ← (D−x) / 2) and step S 3024
(V ← v−u). However, the variable to be updated (variable D
In step S301, the variable Ub) corresponding to
4 (D ← D / 2) and S3024 (v ← v−u). Then, on the fifteenth loop, $ U
a, Ub, Va, Vb, W} = {51, 26, 24, −
7,75}, {F4, F3, F2, F1} = {0,0,
1,1} is calculated.

As described above, the reciprocal operation method 100 outputs 106 as the reciprocal of 271 in the 25th loop. Note that the reciprocal arithmetic unit 2300 similarly outputs 106 as the reciprocal of 271 in the 25th cycle, leading to the same result as the calculation result shown in FIG.

[0133]

The reciprocal operation method according to the present invention is a reciprocal operation method for obtaining the reciprocal of an integer A on a modulo modulo a predetermined positive prime number p, and comprises five intermediate value holding registers Ua. , Ub, Va, Vb, W, Ua = A, Ub
= 2, Va = −p, Vb = 0, W = A−p, an update step of executing the following (a) to (e) in parallel, and (a) the value of Ua Is updated to a first value, and the first value is (a1) Ub or (a2) (Ub / 2 mo
d p), and (b) the value of Ub is calculated as (b1) W or (b2)
Uc, (c) updating the value of Va to a second value, and the second value is (c1) (Vb / 2 modp) or (c2) Vb, and (d) Value is (d1) W or (d
2) updating to Va, and (e) changing the value of W to the first value and the second value.
And updating the value of Ub as a reciprocal to the integer A when the value of Ub is not 0, and executing the updating step again when the value of Ub is not 0. The updating step is a combination of (a1) and (c1), (a
A pair of (2) and (c2) is selected, and for (b) and (d), a pair other than the pair of (b1) and (d1) is selected, and the five intermediate value holding registers are updated in parallel.

With this configuration, the reciprocal operation method of the present invention, when implemented as a device, makes it possible to parallelize part of the processing that has been performed sequentially and update the five intermediate value holding registers in parallel. This has the effect of shortening the time spent for computation as compared with the sequential processing device. Also, the variables Ua,
When updating Va in parallel, since the pair of (a2) and (c1) is not selected, the variable to be divided by 2 (1-bit arithmetic right shift processing) is selected from the variables Ub and Vb. And it can be shared by one 1-bit arithmetic right shifter, which has the effect of reducing the circuit scale as compared with a parallel processing device.

In the reciprocal operation method according to the present invention, further, in the updating step, four flags F1 to F4 indicating states are managed, and (a1) or (a2), (b1) or (b2), (c1 ) Or (c2), (d1) or (d2) is set to the flag F1.
Selection is made according to the values indicated by F4. Further, the initialization step includes four flags F1, F2, F3, F4
Are initialized to F1 = 0, F2 = Ua [0] (the value of the least significant bit of Ua), and F3 = 0, F4 = W [s] (the value of the sign bit of W). (F) to (i)
(F) inverting the value of the flag F1;
(g) When the value of the flag F1 is 1 and the value of the flag F3 is 0, the value of the flag F2 is updated to (g1) the value of the least significant bit of the first value, and the value of the flag F1 becomes 1 And if the value of the flag F3 is 1, (g2) update to the value of the least significant bit of the second value; otherwise, (g3) do not update, (h)
If the value of the flag F3 is 0 and the value of the flag F2
Is updated to the value of (h1) F4 when the value of the flag is 1; otherwise, (h2) is not updated. (I) When the value of the flag F4 is 1, the value of the flag F1 is 1. In (2), it is assumed that (i1) the value of the sign bit of the value obtained by adding the first value and the second value is updated, and (i2) is not updated when the value of the flag F1 is 0.

Further, in the updating step, in (a), when the value of the flag F3 is 1, (a1) is selected, and when the value of the flag F3 is 0, (a2) is selected. Then, in (b), if the value of the flag F2 is 1 and the value of the flag F4 is 0, (b1) is selected; otherwise,
(b2) is selected, and in (c), the value of the flag F3 is set to 1
In the case of (c), (c1) is selected, and when the value of the flag F3 is 0, (c2) is selected. In (d), the value of the flag F2 is 1 and the value of the flag F4 is 1 In this case, select (d1). Otherwise, select (d2).

With this configuration, the reciprocal operation method of the present invention further updates the five intermediate value holding registers ((a) to (a)) by using the four flags F1 to F4 indicating the states.
(e)) and the update processing ((f) to (i)) of the four flags are controlled. In the reciprocal operation method according to the present invention, the initialization step may further comprise repeatedly subtracting the integer A by a value of p until the integer A becomes less than a prime number p, and initializing the intermediate value holding registers Ua and W with the subtraction result. Is also good.

With this configuration, the reciprocal operation method according to the present invention further provides A≡A
-P (mod p) also subtracts the integer A that is greater than or equal to the prime number p by the prime number p to make the integer A less than the prime number p,
There is an effect that the initial value can be smaller than the prime number p. In the reciprocal operation method according to the present invention, further, in the updating step, when the Ub is an even number, the Ub is shifted by one bit right arithmetically as (a2) (Ub / 2 mod p),
Is odd, the value of p is added to or subtracted from Ub,
Arithmetic shift right by bit, and the above (c1) (Vb / 2 mod
As p), when Vb is an even number, Vb is arithmetically shifted right by 1 bit, and when Vb is an odd number, the value of p is added or subtracted from Vb and arithmetically shifted right by 1 bit. Good.

Further, n is 1 or more and 2 ^n-1 <p <2 ⁿ
Is a positive integer that satisfies the relationship of
As (a2), when Ub is an odd number, Ub is 2
If ^n-1 or less, adds the value of p in Ub, if Ub is 2 ^n-1 or more, the value of p by subtracting the Ub, as the (c1), V
When b is an odd number and Vb is 2 ^n-1 or less, V
The value of p may be added to b, and if Vb is 2 ^n-1 or more, the value of p may be subtracted from Vb.

With this configuration, the reciprocal operation method according to the present invention further provides, on the remainder field, under the modulus p, Ub≡
By Ub−p≡Ub + p (mod p), if the variable Ub is odd, by adding or subtracting the prime number p,
There is an effect that it is possible to make an even number and divide by two.
Vb has the same effect. The reciprocal operation device of the present invention is a reciprocal operation device that obtains a reciprocal of an integer A on a modulo modulo a predetermined positive prime p.
Intermediate value registers Ua, Ub, Va, Vb, W respectively holding integers A, 2, -p, 0, Ap as initial values
A first selector for selecting one of the intermediate value registers Ub and Vb, a division unit for dividing the selection result of the first selector by 2 on the remainder, and one of the division results for the intermediate value register Ub and the division unit , A second selector that outputs the result to the intermediate value register Ua, a third selector that selects one of the intermediate value register Vb and the division result of the divider, and outputs the result to the intermediate value register Va, and a selection result of the second selector An adder that adds the intermediate value and the selection result of the third selector and outputs the result to the intermediate value register W; a fourth selector that selects one of the intermediate value register Ua and the addition result and outputs the result to the intermediate value register Ub; A fifth selector that selects one of the register Va and the addition result and outputs it to the intermediate value register Vb, and controls selection of the first to fifth selectors until the value of the intermediate value register Ub becomes zero. The intermediate value register Ua, Ub, V
a control section that repeatedly updates a, Vb, and W repeatedly and outputs the value of the intermediate value register Ua as the reciprocal of the integer A when the value of the intermediate value register Ub becomes 0.

With this configuration, the reciprocal operation device of the present invention can parallelize a part of the processing that has been performed sequentially, and can update the five intermediate value registers in parallel. Has the effect of reducing the time spent on When the registers Ua and Va are updated in parallel, the value to be divided by two (1-bit arithmetic right shift processing) by the first selector is selected from one of the intermediate value registers Ub and Vb. And a single 1-bit arithmetic right shifter can also be used, which has the effect of reducing the circuit scale as compared with a parallel processing device.

Further, the control section includes a flag section for holding four flags F1 to F4 for indicating states, and a selector control section for controlling selection of the first to fifth selectors in accordance with the values of the four flags. And the value of the intermediate value register Ub is 0
, The four flags F1 to F4 are updated simultaneously, and the five intermediate value registers Ua, Ub, Va, V
b, an updating unit for updating W.

With this configuration, in the reciprocal operation device of the present invention, the selection of the first to fifth selectors is further controlled by the four flags F1 to F4 indicating the states, and the update processing of the five intermediate value registers is controlled. This has the effect.
Further, the division unit includes an adder that adds and subtracts a prime number p when the selection result of the first selector is an odd number, and a 1-bit right arithmetic shifter that performs a 1-bit right arithmetic shift on the addition result by the adder.

With this configuration, the reciprocal operation device of the present invention further provides a prime p
Is added or subtracted, the prime number p is added or subtracted according to the value to make the selection result an even number and divided by 2 (one-bit right arithmetic shift). The computer-readable recording medium on which the reciprocal operation program of the present invention has been recorded is formed of an integer A on a modulo modulo a predetermined positive prime number p.
Recording medium for recording a reciprocal operation program for calculating the reciprocal of the five intermediate value holding registers Ua, Ub, V
a, Vb, W, Ua = A, Ub = 2, Va = −p, V
an initialization step of initializing b = 0, W = A−p, an update step of executing the following (a) to (e) in parallel, and (a) U
updating the value of a to a first value, the first value being (a1) U
b or (a2) (Ub / 2 mod p), and (b)
Updating the value of Ub to (b1) W or (b2) Ua;
(c) updating the value of Va to a second value, wherein the second value is (c
1) (Vb / 2 modp) or (c2) Vb,
(d) updating the value of Vb to (d1) W or (d2) Va, (e) updating the value of W to a value obtained by adding the first value and the second value, When the value of Ub is not 0, the updating step is executed again. When the value of Ub is 0, an output step of outputting the value of Ua as an inverse of the integer A is recorded. Select the pair (a2) and (c2), and for (b) and (d), select a pair other than the pair (b1) and (d1), and update the five intermediate value holding registers in parallel Recording a program that causes a computer to do what it does.

The computer readable recording medium having the reciprocal operation program according to the present invention recorded thereon by this configuration can be implemented by executing the reciprocal operation program on hardware such as a computer capable of parallel processing. Part of the processing that has been performed sequentially can be parallelized, and the five intermediate value holding registers can be updated in parallel. This has the effect of shortening the time spent for computation as compared with the sequential processing device. Also, the variables Ua, Va
When updating in parallel, division by 2 (1-bit arithmetic right shift processing) because the pair of (a2) and (c1) is not selected
The variable to be executed is selected from among the variables Ub and Vb, and can be shared by one 1-bit arithmetic right shifter, which has the effect of reducing the circuit scale as compared with the parallel processing device. .

In the computer-readable recording medium storing the reciprocal operation program according to the present invention, the updating step manages four flags F1 to F4 indicating a state, and the updating step (a1) or (a2), (a (b1) or (b2), (c1) or (c2), (d1) or (d2) is set to a flag F1.
A program for causing a computer to execute selection according to the values indicated by F4 is recorded.

Further, in the initialization step, four flags F1, F2, F3, and F4 are set as follows: F1 = 0, F2 = Ua
[0] (the value of the least significant bit of Ua), F3 = 0, F4 =
W [s] (the value of the sign bit of W), the updating step executes the following (f) to (i) in parallel, and (f) inverts the value of the flag F1, (g) ) When the value of the flag F2 is 1 and the value of the flag F3 is 0,
(g1) Update to the value of the least significant bit of the first value, and
Is 1 and the value of the flag F3 is 1, the (g2) second
Is updated to the value of the least significant bit of the value of (a), otherwise (g3) is not updated, (h) the value of the flag F3 is 0, and the value of the flag F1 is 0 and the value of the flag F2 is 1. Contains (h
1) Update to the value of F4, otherwise (h2) Do not update, (i) Change the value of flag F4 to 1
In the case of (i1), update to the value of the sign bit of the value obtained by adding the first value and the second value, and if the value of the flag F1 is 0, (i2) do not update. Recording a program that causes a computer to do what it does.

Further, in the updating step, in (a), when the value of the flag F3 is 1, (a1) is selected, and when the value of the flag F3 is 0, (a2) is selected. Then, in (b), if the value of the flag F2 is 1 and the value of the flag F4 is 0, (b1) is selected; otherwise,
(b2) is selected, and in (c), the value of the flag F3 is set to 1
In the case of (c), (c1) is selected, and when the value of the flag F3 is 0, (c2) is selected. In (d), the value of the flag F2 is 1 and the value of the flag F4 is 1 In this case, a program that causes the computer to select (d1), and otherwise select (d2) is recorded.

With this configuration, a computer-readable recording medium on which the reciprocal operation program of the present invention is recorded can be executed by executing the reciprocal operation program on hardware such as a computer capable of parallel processing. Further, four flags F indicating the state
With 1 to F4, there is an effect that the update processing of the five intermediate value holding registers ((a) to (e)) and the update processing of the four flags ((f) to (i)) are controlled.

The computer-readable recording medium on which the reciprocal operation program of the present invention is recorded is further characterized in that in the initialization step, the integer A is repeatedly subtracted by the value of p until it becomes less than the prime number p, and the result of the subtraction is an intermediate value. A program for causing a computer to initialize the holding registers Ua and W may be recorded. With this configuration, a computer-readable recording medium on which the reciprocal operation program of the present invention is recorded can be executed by executing the reciprocal operation program on hardware such as a computer capable of performing parallel processing. On the body, under the modulus p, A≡A-p (mod p)
As a result, even for an integer A equal to or larger than the prime number p, there is an effect that the integer A can be subtracted by the prime number p, the integer A can be set to a value smaller than the prime number p, and the initial value can be set to be smaller than the prime number p.

In the computer-readable recording medium recording the reciprocal operation program according to the present invention, the updating step may further include: (a2) (Ub / 2 mod p), when Ub is an even number, Ub If the arithmetic operation is shifted right by one bit and Ub is an odd number, the value of p is added or subtracted from Ub, the arithmetic operation is shifted right by one bit, and the above (c1) (Vb / 2
mod p), when Vb is an even number, Vb is arithmetically shifted right by 1 bit, and when Vb is an odd number, Vb is Vb.
, A program that causes a computer to add or subtract the value of p and perform a right arithmetic shift by one bit may be recorded.

Further, n is 1 or more and 2 ^n-1 <p <2 ⁿ
Is a positive integer that satisfies the relationship of
As (a2), when Ub is an odd number, Ub is 2
If ^n-1 or less, adds the value of p in Ub, if Ub is 2 ^n-1 or more, the value of p by subtracting the Ub, as the (c1), V
When b is an odd number and Vb is 2 ^n-1 or less, V
A program that causes a computer to add the value of p to b and, if Vb is ^equal to or greater than 2 ⁿ⁻¹ , to subtract the value of p from Vb may be recorded.

With this configuration, a computer-readable recording medium storing the reciprocal operation program of the present invention can be implemented by executing the reciprocal operation program on hardware such as a computer capable of parallel processing. Furthermore, on the remainder field, under the modulus p, if Ub≡Ub−p≡Ub + p (mod p), if the variable Ub is an odd number, the prime number p is added or subtracted to obtain an even number and divided by 2 The effect is that it is possible. Vb has the same effect.

[Brief description of the drawings]

FIG. 1 is a first flowchart illustrating a reciprocal operation method.

FIG. 2 is a second flowchart illustrating a reciprocal operation method;

FIG. 3 is a third flowchart illustrating a reciprocal operation method;

FIG. 4 shows variables Ua, Ub, Va, Vb, W and variables u,
6 is a table showing a correspondence relationship with v, B, and D.

FIG. 5 is a table in which processing of updating flags F1 to F5 is associated with processing of a conventional reciprocal operation method.

FIG. 6 shows a flag F1 in association with a conventional reciprocal operation method.
7 is a table of processing executed by F5.

FIG. 7 is a table showing a process executed based on a combination of values of flags F1 to F5.

FIG. 8 is a block diagram of a reciprocal operation device.

FIG. 9 is a detailed block diagram of a calculation unit and a control unit.

FIG. 10 is a table showing input selection of each selector.

FIG. 11 is a table showing a correspondence relationship between each component of the reciprocal operation device and each process in the reciprocal operation method.

FIG. 12 is a block diagram of a circuit corresponding to steps S111 and S121.

FIG. 13 is a block diagram of a circuit corresponding to steps S112 and S122.

FIG. 14 is a block diagram of a circuit corresponding to steps S113 and 123.

FIG. 15 is a block diagram of a circuit corresponding to steps S114 and 124.

FIG. 16 is a block diagram of a circuit corresponding to steps S115 and 125.

FIG. 17 is a schematic diagram of register transfer between an arithmetic unit and a control unit in one cycle.

FIG. 18 is a table and a timing chart showing a reciprocal calculation method and a calculation result by a reciprocal calculation device when the number of operations A is 271;

FIG. 19 is a first flowchart illustrating a reciprocal operation method.

FIG. 20 is a second flowchart illustrating the reciprocal operation method;

FIG. 21 is a diagram showing a flag F associated with a conventional reciprocal operation method.
It is a table of processing performed by 1 to F4.

FIG. 22 is a table showing a process executed by a combination of values of flags F1 to F4.

FIG. 23 is a block diagram of a reciprocal operation device.

FIG. 24 is a detailed block diagram of a calculation unit and a control unit.

FIG. 25 is a table showing input selection of a selector.

FIG. 26 is a schematic diagram of register transfer between an arithmetic unit and a control unit in one cycle.

FIG. 27 is a table and a timing chart showing a reciprocal calculation method and a calculation result by a reciprocal calculation device when the number of calculations A is 271;

FIG. 28 is an algorithm of a conventional reciprocal operation method (binary Euclidean mutual division method).

FIG. 29 is a flowchart of a conventional reciprocal operation method (1);
It is.

FIG. 30 is a flowchart of a conventional reciprocal operation method, part 2
It is.

[Explanation of symbols]

 801 Initial value setting unit 802 Correction value storage unit 803 Operation unit 804 Control unit 805 Output unit 901 to 905 Registers 911 to 916 Selectors 921 and 922 Adder 931 1-bit arithmetic right shifter 941 to 945 Flip-flop 951 to 954 Selector 961 NOT Gate

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yasuo Okumura 1006 Kazuma Kadoma, Kadoma-shi, Osaka Matsushita Electric Industrial Co., Ltd. F-term (reference) 5J104 AA18 AA21 JA23 NA22

Claims (17)

[Claims] 1. A reciprocal operation method for obtaining a reciprocal of an integer A on a modulo modulo a predetermined positive prime p, comprising: five intermediate value holding registers Ua, Ub, Va, Vb, W
Ua = A, Ub = 2, Va = −p, Vb = 0, W =
An initialization step of initializing to Ap; an update step of executing the following (a) to (e) in parallel; (a) updating the value of Ua to a first value, a first value Is (a
1) Ub or (a2) (Ub / 2 mod p), (b) updating the value of Ub to (b1) W or (b2) Ua, and (c) changing the value of Va to the second And the second value is (c
1) (Vb / 2 modp) or (c2) Vb, (d) updating the value of Vb to (d1) W or (d2) Va, (e) changing the value of W to the first And updating the value of Ub to a value obtained by adding the value of Ub and the second value. When the value of Ub is not 0, the updating step is performed again.
When 0, an output step of outputting the value of Ua as the reciprocal to the integer A, wherein the updating step selects the set of (a1) and (c1) and the set of (a2) and (c2) (B) (d)
, A set other than the set of (b1) and (d1) is selected, and the five intermediate value holding registers are updated in parallel. 2. The updating step manages four flags F1 to F4 indicating a state, wherein (a1) or (a2), (b1) or (b2), (c1) or (c
2), (d1) or (d2) is set to one of the flags F1 to F
2. A method according to claim 1, wherein the selection is made in accordance with a value indicated by the value (4).
The reciprocal calculation method described. 3. The initialization step comprises: setting four flags F1, F2, F3, and F4 as F1 = 0, F
2 = Ua [0] (value of the least significant bit of Ua), F3 =
0, F4 = W [s] (the value of the sign bit of W). The updating step executes the following (f) to (i) in parallel, and (f) inverts the value of the flag F1. (G) When the value of the flag F1 is 1 and the value of the flag F3 is 0, the value of the flag F2 is updated to the value of the least significant bit of the (g1) first value, and the value of the flag F1 is updated. Is 1 and the value of the flag F3 is 1, (g2) update to the value of the least significant bit of the second value; otherwise, (g3) do not update, (h) the flag F3 Is updated to the value of (h1) F4 when the value of the flag F1 is 0 and the value of the flag F2 is 1, otherwise, (h2) is not updated. When the value of the flag F1 is 1, the value of the flag F1 is updated to (i1) the value of the sign bit of the value obtained by adding the first value and the second value, and when the value of the flag F1 is 0, Contains (i2)
3. The reciprocal operation method according to claim 2, wherein updating is not performed. 4. In the updating step, in the step (a), when the value of the flag F3 is 1, (a1) is selected, and when the value of the flag F3 is 0, (a2) is selected. In the above (b), when the value of the flag F2 is 1 and the value of the flag F4 is 0,
(b1) is selected; otherwise, (b2) is selected. In (c), when the value of the flag F3 is 1, (c1) is selected, and the value of the flag F3 is changed. In the case of 0, (c2) is selected. In the above (d), when the value of the flag F2 is 1 and the value of the flag F4 is 1,
4. The reciprocal operation method according to claim 3, wherein (d1) is selected, and in other cases, (d2) is selected. 5. The initialization step: repeatedly subtracting an integer A by a value of p until the integer A becomes less than a prime number p;
5. The reciprocal operation method according to claim 1, wherein the intermediate value holding registers Ua and W are initialized with the subtraction result. 6. The updating step is as follows: (a2) (Ub / 2 mod p), when Ub is an even number, Ub is right-shifted by 1 bit, and when Ub is an odd number, Ub is shifted to Ub. The value of p is added or subtracted, and arithmetically shifted right by 1 bit. As (c1) (Vb / 2 mod p), when Vb is even, Vb is arithmetically shifted right by 1 bit and Vb is odd. 6. The reciprocal operation method according to claim 1, wherein, in such a case, the value of p is added or subtracted from Vb and arithmetically shifted right by one bit. 7. n is a positive integer that is 1 or more and satisfies a relational expression of 2 ^{n -1} <p <2 ⁿ , and the updating step comprises: (a2) when Ub is an odd number, If Ub is 2 ^n-1 or less, the value of p is added to Ub. If Ub is 2 ^n-1 or more, the value of p is subtracted from Ub. As (c1), when Vb is an odd number, 7. The reciprocal operation according to claim 6, wherein if Vb is 2 ^n-1 or less, the value of p is added to Vb, and if Vb is 2 ^n-1 or more, the value of p is subtracted from Vb. Method. 8. A reciprocal arithmetic unit for calculating a reciprocal of an integer A on a modulo modulo a predetermined positive prime number p, wherein integers A, 2, -p, 0, A- intermediate value registers Ua, Ub, Va, Vb, W respectively holding p
A first value for selecting one of the intermediate value registers Ub and Vb
A selector, a division unit for dividing the selection result of the first selector by 2 on the remainder field, a second selector for selecting one of the intermediate value register Ub and the division result of the division unit, and outputting the selected result to the intermediate value register Ua. A third selector that selects one of the value register Vb and the division result of the division unit and outputs the result to the intermediate value register Va, and adds the selection result of the second selector and the selection result of the third selector to the intermediate value register W. An adder to be output, a fourth selector for selecting one of the intermediate value register Ua and the addition result, and outputting to the intermediate value register Ub, and selecting one of the intermediate value register Va and the addition result for output to the intermediate value register Vb And the first to fifth selectors until the value of the intermediate value register Ub becomes zero.
In addition to controlling the selection of the selector, the intermediate value register U
and a control unit that repeatedly updates a, Ub, Va, Vb, and W repeatedly and outputs the value of the intermediate value register Ua as the reciprocal of the integer A when the value of the intermediate value register Ub becomes 0. A reciprocal operation device characterized by the above-mentioned. 9. The control unit includes: a flag unit that holds four flags F1 to F4 for indicating a state; and a selector control unit that controls selection of the first to fifth selectors according to the values of the four flags. And an updating unit for simultaneously updating the four flags F1 to F4 until the value of the intermediate value register Ub becomes 0 and updating the five intermediate value registers Ua, Ub, Va, Vb, W. 9. The reciprocal operation device according to claim 8, wherein 10. A division unit, comprising: an adder for adding and subtracting a prime number p when a selection result of the first selector is an odd number; a 1-bit right arithmetic shifter for right-arithmically shifting the addition result by the adder; The reciprocal operation device according to claim 8, comprising: 11. A recording medium recording a reciprocal operation program for obtaining a reciprocal of an integer A on a modulo modulo a predetermined positive prime number p, comprising: five intermediate value holding registers Ua, Ub, Va, Vb, W
Ua = A, Ub = 2, Va = −p, Vb = 0, W =
An initialization step of initializing to Ap; an update step of executing the following (a) to (e) in parallel; (a) updating the value of Ua to a first value, a first value Is (a
1) Ub or (a2) (Ub / 2 mod p), (b) updating the value of Ub to (b1) W or (b2) Ua, and (c) changing the value of Va to the second And the second value is (c
1) (Vb / 2 modp) or (c2) Vb, (d) updating the value of Vb to (d1) W or (d2) Va, (e) changing the value of W to the first And updating the value of Ub to a value obtained by adding the value of Ub and the second value. When the value of Ub is not 0, the updating step is performed again.
When 0, an output step of outputting the value of Ua as the reciprocal of the integer A is recorded, and the updating step selects the set of (a1) and (c1) and the set of (a2) and (c2). (B) (d)
, A computer-readable recording medium storing a program for causing a computer to select a set other than the set of (b1) and (d1) and update the five intermediate value holding registers in parallel. 12. The updating step manages four flags F1 to F4 indicating a status, wherein (a1) or (a2), (b1) or (b2), (c1) or (c
2), (d1) or (d2) is set to one of the flags F1 to F
2. A method according to claim 1, wherein the selection is made in accordance with a value indicated by the value (4).
The computer-readable recording medium according to claim 1. 13. The initialization step includes: setting four flags F1, F2, F3, and F4 to F1 = 0, F1
2 = Ua [0] (value of the least significant bit of Ua), F3 =
0, F4 = W [s] (the value of the sign bit of W). The updating step executes the following (f) to (i) in parallel, and (f) inverts the value of the flag F1. (G) When the value of the flag F1 is 1 and the value of the flag F3 is 0, the value of the flag F2 is updated to the value of the least significant bit of the (g1) first value, and the value of the flag F1 is updated. Is 1 and the value of the flag F3 is 1, (g2) update to the value of the least significant bit of the second value; otherwise, (g3) do not update, (h) the flag F3 Is updated to the value of (h1) F4 when the value of the flag F1 is 0 and the value of the flag F2 is 1, otherwise, (h2) is not updated. When the value of the flag F1 is 1, the value of the flag F1 is updated to (i1) the value of the sign bit of the value obtained by adding the first value and the second value, and when the value of the flag F1 is 0, Contains (i2)
13. The computer-readable recording medium according to claim 12, wherein a program for causing a computer to execute the updating is recorded. 14. In the updating step, in (a), when the value of the flag F3 is 1, (a1) is selected, and when the value of the flag F3 is 0, (a2) is selected. In the above (b), when the value of the flag F2 is 1 and the value of the flag F4 is 0,
(b1) is selected; otherwise, (b2) is selected. In (c), when the value of the flag F3 is 1, (c1) is selected, and the value of the flag F3 is changed. In the case of 0, (c2) is selected. In the above (d), when the value of the flag F2 is 1 and the value of the flag F4 is 1,
14. The computer-readable recording medium according to claim 13, wherein a program for causing a computer to select (d1) and otherwise select (d2) is recorded. 15. The initialization step comprises repeatedly subtracting an integer A by a value of p until the integer A becomes less than a prime number p.
15. The computer-readable recording medium according to claim 11, wherein a program for causing a computer to initialize the intermediate value holding registers Ua and W with the subtraction result is recorded. 16. The updating step is as follows: (a2) (Ub / 2 mod p), when Ub is an even number, Ub is arithmetically shifted right by 1 bit, and when Ub is an odd number, Ub is shifted to Ub. The value of p is added or subtracted, and arithmetically shifted right by 1 bit. As (c1) (Vb / 2 mod p), when Vb is even, Vb is arithmetically shifted right by 1 bit and Vb is odd. 16. The computer-readable recording medium according to claim 11, wherein a program for causing a computer to add or subtract a value of p to or from Vb and to perform a right arithmetic shift by one bit is recorded. 17. n is a positive integer that satisfies a relational expression of 1 or more and 2 ⁿ⁻¹ <p <2 ⁿ , and the updating step includes the step of: (a2) when Ub is an odd number, If Ub is 2 ^n-1 or less, the value of p is added to Ub. If Ub is 2 ^n-1 or more, the value of p is subtracted from Ub. As (c1), when Vb is an odd number, if Vb is 2 ^n-1 or less, adds the value of p to Vb, claim Vb is if 2 ^n-1 or more, which records a program for executing the subtracting the value of p in Vb to the computer 17. The computer-readable recording medium according to item 16.