JP2002170382A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform sufficiently polarization of a ferroelectric capacitor at the time of rewrite-in after read-out and at the time of write-in of data, in a ferroelectric memory. SOLUTION: In a TC parallel and unit series connection type ferroelectric memory, a period from rise to fall (selection released) of a selection word line WL is extended by providing a fourth delay circuit 4 in a control circuit controlling a potential of a word line and delaying fall of a second chip enable- delay signal CED2, and a sufficient data write-in time is obtained by leaving write-in voltage at both ends of a ferroelectric capacitor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device using a ferroelectric film, and more particularly to a highly integrated semiconductor memory device.

[0002]

2. Description of the Related Art A ferroelectric memory has the advantage that it has both non-volatility like a flash memory, high-speed access and high-speed rewriting like a DRAM, and can operate at a low voltage / low power consumption. Regarding the cell structure of the ferroelectric memory, one transistor 1 is similar to a DRAM cell.
Development with capacitor-type memory cells has been widely pursued.

A ferroelectric memory cell stores a "1" state and a "0" state when the polarization direction is upward or downward as shown in FIG. As shown in FIG. 27, a cell transistor 100 whose gate is connected to word line WL and whose source is connected to bit line BL is a node that is the other electrode of capacitor 101 whose one electrode is connected to plate line PL. It is connected to C. The amount of polarization of this ferroelectric capacitor depends on the time for applying a voltage to the ferroelectric capacitor,
When the time is increased, the amount of polarization becomes closer to the saturation polarization amount. Therefore, when the writing time is extended in the device, a sufficient polarization amount is obtained, and the data retention characteristics are improved.

In a conventional general one-transistor, one-capacitor type memory cell, in order to increase the reliability of cell data retention, the voltage across the ferroelectric capacitor is retained after data is written, and sufficient polarization is performed. That is, after the active state is completed, the word line is deselected and the potential of the bit line is confined to node C shown in FIG. This is a method of performing sufficient writing by applying voltage.

Here, a unit cell in which both ends of a capacitor (C) are connected between a source and a drain of a cell transistor (T) is defined as a unit cell, and a plurality of such unit cells are connected in series. (Hereinafter referred to as a TC parallel unit serial connection type ferroelectric memory) has been attracting attention because it can improve high speed and high integration. This ferroelectric memory is described in "ISSCC Tech. Dig. Papers, pp. 102-103, Feb.
1999 `` A Sub-40ns Random-Access Chain FRAM Archite
cture with a 7ns Cell-Plate-Line Drive "”.

In this configuration, as shown in FIG.
Cell transistor 10 composed of a channel transistor
2 and the capacitor 103 are connected in parallel to form one memory cell 104. A plurality of memory cells 104 are connected in series to form a memory cell block 105. The pairs of memory cell blocks 105 are arranged in multiple stages (one stage in FIG. 28), and each pair of memory cell blocks 105 has a corresponding bit line BL, BLB.
And the plate lines PL1 and PL2.
Bit lines BL, BL of each memory block 105
Block select transistors 106 each having a gate connected to block select lines BS0 and BS1 are connected between B and the memory cell 104, respectively.

Here, in the standby mode, all word lines WL are set at "H" level, and both electrodes of each capacitor are short-circuited. In the activation mode, the selected word line WL is changed from “H” level to “L”.
Level, and the block selection line BS changes from “L” level to “H” level. Thereafter, the plate line PL is displaced to the Vdd level, and Vdd is applied to the selected capacitor.
Apply potential. Then, data of the memory cell is read to the bit line BL. On the other hand, the unselected capacitors are kept short-circuited. In this way, random access is performed.

FIG. 29 shows a configuration of a control circuit for controlling read / write to a memory cell. The control circuit includes first to third serially connected multi-stages.
And fifth to ninth delay circuits 107 to 114, a NAND circuit 115, an inverter circuit 116, and a NOR circuit 117. The control circuit receives the chip enable signal CE1 and receives the two chip enable delay signals CED1 and CE2 by the logic circuits and the delay circuit.
D2, address pass signal BADPAS, row address latch signal BRAT, row address enable signal RA
E, a block selection enable signal BSEBL, a sense amplifier enable signal SAEBEL, and a plate line enable signal PLEBL are generated and output.

Here, the first chip enable delay signal CED1 controls signals for driving a block selection line drive circuit (not shown) for controlling the memory cell array, a plate line PL, and a sense amplifier (not shown), respectively. Signal. Further, the second chip enable delay signal CE
D2 is a signal for controlling the timing of the word line WL by controlling an address buffer (not shown), and controls a row address latch signal BRAT for driving the address buffer and a row address enable signal RAE. The address pass signal BADPAS controls the timing of sending an external address signal to the address buffer, and the block selection enable signal BSEBL is a signal for controlling the block selection line driving circuit. The sense amplifier enable signal SAEBEL is a signal for controlling the sense amplifier. Further, the plate line enable signal PLEBL is a signal for controlling the plate line PL.

Here, the chip enable signal CE1 is an output signal of the input buffer (not shown) which receives the external signal CEB, and is at the "H" level during the active operation and at the "L" level during the standby state.

FIG. 30 shows an input / output signal and a signal chart of each node at the time of reading in the circuits shown in FIGS. 28 and 29 of the conventional TC parallel unit series connection type ferroelectric memory. In the figure, each signal is synchronized at the timing shown by the dotted line.

The external chip enable signal CEB is shown as changing from "H" level to "L" level for a predetermined period.

When the external chip enable signal CEB changes from "H" level to "L" level, the chip enable signal CE1 output from the chip enable buffer changes from "L" level to "H" level. . External chip enable signal CEB is "L"
At the timing when the chip enable signal CE1 changes from the “H” level to the “H” level, the chip enable signal CE1 changes from the “H” level to the “L” level.

First chip enable delay signal CED1
Changes from the “L” level to the “H” level after a lapse of time in addition to the time from the timing of the change of the chip enable signal CE1 from the “L” level to the “H” level. Further, the first chip enable delay signal CED1 changes from the “H” level of the chip enable signal CE1 to “L”.
The level shifts from the “H” level to the “L” level after the lapse of time in addition to the time and the time from the timing of the shift to the level. The total of this time is about 20 ns.

Second chip enable delay signal CED2
Changes from "L" level to "H" level after a lapse of time after the chip enable signal CE1 changes from "L" level to "H" level. Further, the second chip enable delay signal CED2 changes from “H” level to “L” level at the timing when the first chip enable delay signal CED1 changes to “L” level.

The address pass signal BADPAS changes from "H" level to "L" level when the chip enable signal CE1 changes from "L" level to "H" level. After the "L" level shift, the "L" level is again shifted to the "H" level after a lapse of time.

The row address latch signal BRAT changes from "H" level to "L" level when the second chip enable delay signal CED2 changes from "L" level to "H" level. The row address latch signal BRAT is the second chip enable delay signal CED2
Changes from the “H” level to the “L” level, and after a lapse of time, changes from the “L” level to the “H” level.

The row address enable signal RAE shifts from the "L" level to the "H" level after a lapse of time from the timing of the shift of the second chip enable delay signal CED2 from the "L" level to the "H" level. . Also,
The row address enable signal RAE changes from “H” level to “L” level at the timing when the second chip enable delay signal CED2 changes from “H” level to “L” level.

The word line WL1 is selected by a decoder (not shown) at the timing when the row address enable signal RAE is changed from "L" level to "H" level, and the "potential thereof is changed from H level to" L ". Displace to level. The word line WL1 is connected to a row address enable signal RA.
At the timing when E changes from the “H” level to the “L” level, it is deselected, and its potential changes from the “L” level to the “H” level.

The potential of the block select line BS0 changes from "L" level to "H" level when the first chip enable delay signal CED1 changes from "L" level to "H" level. Also, the block selection line BS0
Changes from "H" level to "L" level at the timing when the first chip enable delay signal CED1 changes from "H" level to "L" level. Here, when the block selection line BS0 is at "H" level, the bit line and the memory cell are connected.

The potential of the plate line PL2 changes from "L" level to "H" at the timing when the first chip enable delay signal CED1 changes from "L" level to "H" level.
Displace to level. The potential of the plate line PL2 changes from “H” level to “L” at the timing when the chip enable signal CE1 changes from “H” level to “L” level.
Displace to level.

The sense amplifier control signal SA changes from "L" level to "H" level after a lapse of time in addition to the time from when the first chip enable delay signal CED1 is changed from "L" level to "H" level. Is displaced. Further, the sense amplifier control signal SA changes from “H” level to “L” level after a lapse of time from the timing when the first chip enable delay signal CED1 changes from “H” level to “L” level.

The potential of the bit line BLB is applied to the plate line PL
When the potential of No. 2 changes from the “L” level to the “H” level, the charge of the selected memory cell is transferred to the bit line, and the potential of the selected memory cell becomes a potential corresponding to the data of the memory cell. Bit line BLB
Is further amplified to "H" level or "L" level by the operation of the sense amplifier at the timing when the sense amplifier SA changes from "L" level to "H" level. Also, the bit line BLB
When the potential is at the "H" level, it shifts to the "L" level at the timing when the sense amplifier control signal SA changes from the "H" level to the "L" level.

The potential of the node A is connected to the bit line BLB after the block selection line BS0 is changed from "L" level to "H" level. At the timing when the plate line PL2 changes from "L" level to "H" level, the bit line BL
B changes to a bit line potential corresponding to the data of the memory cell, and node A also changes to the bit line potential. further,
At the timing when the sense amplifier control signal SA changes from “L” level to “H” level, the node A goes to “H” level or “L” level like the bit line. Further, the cell transistor 102 is turned on at the timing when the block selection line BS0 changes from “H” level to “L” level, and thereafter, when the potential of the word line WL1 changes from “L” level to “H” level. Then, the nodes A and B are short-circuited. At this time, since all the cell transistors of the memory cell are on, the nodes A and B
Becomes equal to the level of the plate line PL2.

[0025]

The following problems arise in the conventional semiconductor memory device as described above.

In the conventional cell structure of the TC parallel unit serial connection type ferroelectric memory, the operation of setting the word line to the non-selection state at the same time as the end of the active state is performed similarly to the conventional one-transistor one-capacitor type memory cell. In this case, both ends of the ferroelectric capacitor are short-circuited. Therefore, the application of the write voltage cannot be continued.

That is, in the cell structure of the conventional TC parallel unit serial connection type ferroelectric memory, one transistor
It has been difficult to secure the long rewrite time and write time obtained in the capacitor cell and obtain the same write characteristics as those obtained in the one-transistor, one-capacitor cell.

In particular, depending on the characteristics of the ferroelectric thin film, 10
When high-speed writing with a writing time of n seconds to 40 n seconds is performed, a difference occurs in data retention characteristics when the writing voltage fluctuates between 10 mV and 20 mV.

In particular, in the operation of rewriting after reading, the potential of the selected word line WL instructing the writing is set to the "L" level immediately from the timing when the block selection line BS changes from the "H" level to the "L" level. To the “H” level.

As described above, in the conventional semiconductor memory device, since the block selection line BS and the word line WL are in the non-selected state almost at the same time, the time required for rewriting is not sufficiently secured.

As shown on the signal waveform line of the word line WL1 potential shown in FIG.
"1" write time is set. In particular, the "1" rewrite time is set by the delay time of the delay circuits 1 to 3, and is set to about 20 ns.

For this reason, the polarization of the cell is not sufficiently performed,
The bit line potential at the time of reading decreases. For this reason, the retention characteristics of the cell data were deteriorated, and the reliability was significantly deteriorated.

An object of the present invention is to solve the above-mentioned problems of the prior art. In particular, it is an object of the present invention to provide a semiconductor memory device having a ferroelectric memory device capable of sufficiently writing cell data and having improved data retention characteristics.

[0034]

A semiconductor memory device according to a first aspect of the present invention includes a cell transistor for selecting a memory cell, a ferroelectric capacitor connected between a source and a drain of the cell transistor, and And a plurality of memory cells, which are connected in series and form a memory cell block, are read and written, a word line connected to the gate of the cell transistor, and one end of the plurality of memory cells A memory cell block selection transistor connected to the memory cell block selection transistor; a bit line connected to the memory cell block selection transistor; a plate line connected to the other ends of the plurality of memory cells; And a word line control circuit that controls the word line so that the cell transistor remains selected after It is characterized in Rukoto.

A semiconductor memory device according to a second aspect of the present invention comprises:
A plurality of read and write units each having a cell transistor for selecting a memory cell and a ferroelectric capacitor connected between the source and the drain of the cell transistor and connected in series to form a memory cell block A memory cell, a word line connected to the gate of the cell transistor, a block select transistor connected to one end of the plurality of memory cells, a bit line connected to the block select transistor, A plate line selection transistor connected to the other end of the plurality of memory cells; a plate line connected to the plate line selection transistor; and a cell even after the block selection transistor and the plate line selection transistor are turned off. A word line control circuit that keeps the transistor selected. It is characterized by having a word line control circuit.

[0036]

Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.

(First Embodiment) A first embodiment according to the present invention
1 to 6 show a semiconductor memory device according to the first embodiment.
This will be described with reference to FIG.

FIG. 2 shows the configuration of the semiconductor memory device according to the first embodiment of the present invention.

The chip enable buffer 30 receiving the external signal CEB outputs the chip enable signal CE1 to the control circuit 31. The control circuit 31 outputs an address pass signal BADPAS, a row address latch signal BRAT, and a row address enable signal RAE to the address buffer 32.

The external address signal Ai is input to the address buffer 32, and the address signal Ali and BAli are output to the predecoder 33 (hereinafter, i is an integer of 0 or more).

The input / output buffer 34 inputs and outputs data Di.

The block selection line control circuit 35 receives a block selection enable signal BSEB from the control circuit 31.
L is input, and address signals XA, XB, XC are input from the predecoder 33.

The word line drive circuit 36 includes a predecoder 3
3 receives address signals XA, XB, XC.

The plate line control circuit 37 receives the plate line enable signal PLEBL from the control circuit 31 and receives the address signals XA,
XB and XC are input.

A plurality of block select signals BSi decoded by the address signals XA, XB, XC from the block select line control circuit 35 are input to the memory cell array 38, and the address signals XA, XA,
A plurality of word lines WL decoded by XB and XC
j (j is an integer of 0 or more) is input, and the potentials of the plurality of plate lines PLi decoded by the address signals XA, XB, XC are input from the plate line control circuit 37. From the memory cell array 38, the data line potential V
BITi is output.

The sense amplifier / input / output circuit 39 receives the data line potential VBITi from the memory cell array 38 and the sense amplifier enable signal SAEBL from the control circuit 31. This sense amplifier /
The input / output circuit 39 outputs read / write data RWDi to the input / output buffer 34.

FIG. 1 shows a configuration of a control circuit 31 according to the first embodiment of the present invention. The control circuit includes first to ninth delay circuits 1 to 9, first to eleventh inverters 10 to 20, first to sixth NAND circuits 21 to 2,
6 and a first NOR circuit 27. Each delay circuit is composed of, for example, an even number of inverters connected in series.

The chip enable signal CE 1 is input to the first delay circuit 1, and the delayed signal is output to the second delay circuit 2 and the first NOR circuit 27.

The second delay circuit 2 outputs a signal to the first inverter 10. The first inverter 10 outputs a signal to the third delay circuit 3 and the first NAND circuit 21.

The first NAND circuit 21 outputs a first chip enable delay signal CED1, and outputs the output signal CED1.
Are input to the fourth delay circuit 4 and the fourth inverter 13.

The fourth delay circuit 4 outputs an output signal to the first NOR circuit 27, and the first NOR circuit 27 outputs an output signal to the second inverter 11. This second inverter 1
1 is a second chip enable delay signal C
ED2 is output, and this signal is output to the eighth inverter 17.

The chip enable signal CE 1 is input to the fifth delay circuit 5, and an output signal is output to the third inverter 12. The output of the third inverter 12 and the chip enable signal CE1 are input to the second NAND circuit 22, and the address pass signal BADPAS is output.

The fourth inverter 13 is connected to the fifth inverter 14
The fifth inverter 14 outputs a block selection enable signal BSEBL, which is output to the eighth delay circuit 8 and the fourth NAND circuit 24.

The eighth delay circuit 8 includes a ninth delay circuit 9 and a third
The output signal is output to the NAND circuit 23.

The ninth delay circuit 9 outputs an output signal to the third NAND circuit 23.

The third NAND circuit 23 is connected to the sixth inverter 15
Output signal.

The sixth inverter 15 outputs a sense amplifier enable signal SAEBL.

The fourth NAND circuit 24 receives the chip enable signal CE 1 and outputs an output signal to the seventh inverter 16. The seventh inverter 16 outputs a plate line enable signal PLEBL.

The eighth inverter 17 outputs its output signal to the sixth inverter.
The signal is output to the delay circuit 6, the fifth NAND circuit 25, and the tenth inverter 19.

The sixth delay circuit 6 outputs the output signal to the fifth NAND circuit 25. The fifth NAND circuit 25 outputs the output signal to the ninth inverter 18. The ninth inverter 18 outputs the row address latch signal BRAT.
Is output.

The tenth inverter 19 outputs its output signal to the seventh delay circuit 7 and the sixth NAND circuit 26.
The seventh delay circuit outputs the output signal to the sixth NAND circuit 26. The sixth NAND circuit 26 outputs an output signal to the eleventh inverter 20.

The eleventh inverter 20 outputs a row address enable signal RAE.

FIG. 3 is a graph showing the relationship between T and T in the first embodiment of the present invention.
The configuration of a memory cell array 38 of a C (Transistor-Capacitor) parallel unit serial connection type ferroelectric memory is shown.

The ferroelectric memory cell array 38 shown in FIG. 3 has one N-channel cell transistor 40 and the cell transistor 40 at the intersection of a word line and a bit line.
And a plurality of ferroelectric memory cells (hereinafter, referred to as memory cells) 42 each including one ferroelectric capacitor 41 connected between the source and the drain.

For example, a plurality of pairs of memory cell groups 43 in which eight memory cells 42 are connected in series (one pair is shown as an example)
One end of the memory cell group 43 is connected to a corresponding bit line BL, via a selection transistor 44 controlled by block selection signals BS0 and BS1, respectively.
The other end is connected to the plate lines PL1 and PL2.

Cell transistor 40 in memory cell 42
Is a word line which is a memory cell selection line at the gate, for example, W
When the word line drive signal input to the word line WL1 is at H level, the transistor 41 conducts when the word line drive signal is at the H level, and the two electrodes of the capacitor 41 connected between the source and the drain are set to the same potential. Then, the capacitor 41 is set to the non-selected state. When the word line drive signal is at L level, the cell transistor 40 is turned off, and its source,
The capacitor 41 connected between the drains is selected.
Here, the number of memory cells may be 16 or another number.

FIG. 4 shows a circuit configuration of the address buffer 32 in the present embodiment.

The NOR circuit 50 has an address path signal BA
The DPAS and the address signal Ai are input, and an output signal is output to the first inverter 54.

From the first inverter 54, two transistors whose source and drain are connected to each other are output to one of two source / drain nodes of the transfer gate 51 connected in parallel.

One of the two gates of transfer gate 51 is connected to row address latch signal BRAT. The row address latch signal BRAT is input to the second inverter 55. This second inverter 5
5 is input to the other of the two gates of the transfer gate 51.

The two sources of the transfer gate 51
The other of the drain nodes has third and fourth inverters 56 and 57 having one output terminal connected to the other input terminal.
Connected to one of the two nodes.

The other of the two nodes of the third and fourth inverters 56 and 57 is connected to the fifth inverter 58 and the input terminal of the second NAND circuit 53.

The output signal of the fifth inverter 58 and the row address enable signal RAE are input to the first NAND circuit 52.

The output signal of the first NAND circuit 52 is the sixth
It is input to the inverter 59. This sixth inverter 59
Outputs an address signal Ali.

The row address enable signal RAE is input to the second NAND circuit 53, and an output signal is output to the seventh inverter 60. This seventh inverter 60 outputs an address signal BAli.

In the address buffer 32, the output level of the inverter 54 is determined according to the external address signal Ai while the address pass signal BADPAS is at "L" level. When Ai is at “H” level, the output of inverter 54 is also at “H” level, and when Ai is at “L” level, the output of inverter 54 is also at “L” level. The output of the inverter 54 is transferred to the input of the inverter 56 because the transfer gate 51 is ON when the row address latch signal BRAT is at “H” level. Thereafter, when the row address latch signal BRAT changes to "L" level,
The transfer gate 51 is turned off, and the output of the inverter 56 is latched by the interconnected inverters 56 and 57. Therefore, even if the address pass signal BADPAS changes from "L" level to "H" level while the row address latch signal BRAT is at "L" level, the transfer gate 51 is in the OFF state. Does not change. Further, the NAND to which the row address enable signal RAE is input
When the RAE is at the “L” level, the outputs of the inverter 52 and the NAND 53 are fixed at the “H” level,
Ali and BAli of the output of the inverter 60 are fixed at the “L” level. After the output latch of the inverter 56, R
When AE changes to “H” level, NAND 52 and NAN
The output of D53 is "H" according to the output level of inverter 56.
Level or "L" level, the address buffer 32
Outputs Ali and BAli are the address pass signals BADPA
When S is at the "L" level, the level becomes the level according to the external address Ai taken in.

Next, the operation of the memory cell array will be described.

In the standby state, the chip enable signal CEB = "H" and the word line potentials WL0 to WL7 =
"H", each block selection line potential BS0-BS1 =
“L”, each plate line potential PL1 to PL2 = “L”, each bit line potential BL, BLB = “L”, memory cell group 43
Internal nodes (node A, node B, etc.) = “L”. Here, the “H” level is set between 3V and 2V. The bit line precharge potential is a ground potential.

At the time of reading, the memory cell selection signal line WLi and the block selection line BSi are activated by the external chip enable signal CEB = "L" and selected by an external address.
(I is a natural number) is selected. FIG. 5 shows a signal chart when data is read. In FIG. 5, the signal waveforms of the two bit lines BL and BLB of one bit line pair are shown in an overlapping manner. Here, the memory cell 42 selected by WL1 and BS0 is connected to the bit line BLB. The case will be described.

Each signal and each node shown in FIG. 5 use those shown in the circuit diagram in the semiconductor memory device shown in FIGS. In the figure, each signal is synchronized at the timing shown by the dotted line.

"H" of the chip enable signal CEB
At the timing when the level shifts from the level to the “L” level, the chip enable signal CE1 output from the chip enable buffer 30 shifts from the “L” level to the “H” level. After a lapse of a predetermined period, the external chip enable signal C
At the timing when EB changes from “L” level to “H” level, the chip enable signal CE1 changes from “H” level to “L” level.

First chip enable delay signal CED1
Changes from the “L” level to the “H” level after a lapse of time in addition to the time from the timing of the change of the chip enable signal CE1 from the “L” level to the “H” level. Further, the first chip enable delay signal CED1 changes from the “H” level of the chip enable signal CE1 to “L”.
The level shifts from the “H” level to the “L” level after the lapse of time in addition to the time and the time from the timing of the shift to the level. The total of this time is about 20 ns.

Second chip enable delay signal CED2
Changes from "L" level to "H" level after a lapse of time after the chip enable signal CE1 changes from "L" level to "H" level. Further, the second chip enable delay signal CED2 changes from "H" level to "L" level after a lapse of time after the first chip enable delay signal CED1 has finished shifting to "L" level. This time is a delay time in the fourth delay circuit 4, and is about 20 ns to 30 ns.

The address path signal BADPAS changes from "H" level to "L" level at the timing when the chip enable CE1 changes from "L" level to "H" level. After the "L" level displacement, "L"
The level shifts from the level to the “H” level.

The row address latch signal BRAT changes from "H" level to "L" level at the timing when the second chip enable delay signal CED2 changes from "L" level to "H" level. The row address latch signal BRAT is the second chip enable delay signal CED2
Changes from the “H” level to the “L” level, and after a lapse of time, changes from the “L” level to the “H” level.

The row address enable signal RAE shifts from the “L” level to the “H” level after a lapse of time from the timing of the shift of the second chip enable delay signal CED2 from the “L” level to the “H” level. . Also,
The row address enable signal RAE changes from “H” level to “L” level at the timing when the second chip enable delay signal CED2 changes from “H” level to “L” level.

The selected word line WL1 is selected by the predecoder at the timing when the row address enable signal RAE changes from "L" level to "H" level, and its potential changes from "H" level to "L" level. When the selected word line WL1 is displaced to the “L” level, the cell transistor 42 is in a selected state, that is, an off state. When the cell transistor 42 is turned off, both ends of the ferroelectric capacitor 41 are not short-circuited. Further, the word line WL1 is deselected at the timing when the row address enable signal RAE is changed from “H” level to “L” level, and its potential is changed from “L” level to “H” level.

The potential of the block selection line BS0 changes from "L" level to "H" level at the timing when the first chip enable delay signal CED1 changes from "L" level to "H" level. Also, the block selection line BS0
Changes from "H" level to "L" level at the timing when the first chip enable delay signal CED1 changes from "H" level to "L" level.

The potential of the plate line PL2 changes from “L” level to “H” at the timing when the first chip enable delay signal CED1 changes from “L” level to “H” level.
Displace to level. The potential of the plate line PL2 changes from “H” level to “L” at the timing when the chip enable signal CE1 changes from “H” level to “L” level.
Displace to level.

The sense amplifier control signal SA changes from the “L” level to the “H” level after a lapse of time in addition to the time from when the first chip enable delay signal CED1 is changed from the “L” level to the “H” level. Is displaced. Further, the sense amplifier control signal SA changes from “H” level to “L” level after a lapse of time from the timing when the first chip enable delay signal CED1 changes from “H” level to “L” level.

The potential of the bit line BLB is
When the potential of No. 2 changes from the “L” level to the “H” level, the charge of the selected memory cell is transferred to the bit line, and the potential of the selected memory cell becomes a potential corresponding to the data of the memory cell. Bit line BLB
Is further amplified by the sense amplifier at the timing when the sense amplifier SA changes from the "L" level to the "H" level, and changes to the "H" level or the "L" level according to the data of the memory cell. Also, the bit line BLB
Is shifted to “L” level when the sense amplifier control signal SA is changed from “H” level to “L” level, when the sense amplifier control signal SA is at “H” level.

In the node A, the block selection line BS0 is set at "L".
After the bit line BLB is displaced from
Connected to At the timing when the plate line PL2 changes from "L" level to "H" level, the bit line BLB changes to the bit line potential corresponding to the data of the memory cell, and the node A also changes to the bit line potential. Further, at the timing when the sense amplifier control signal SA changes from “L” level to “H” level, the node A is switched in the same manner as the bit line.
Goes to the “H” level or the “L” level. Also, at the timing when the block selection line BS0 changes from “H” level to “L” level, and thereafter, when the potential of the word line WL1 changes from “L” level to “H” level, the cell transistor 40 is turned on. By becoming, node A and node B
(FIG. 3) is shorted. At this time, the cell transistors of all the memory cells are on, and nodes A and B become equal to the level of plate line PL2.

As shown in FIG. 5, since the delay time by the delay circuit 4 (FIG. 4) is newly set, the "1" rewriting time of the word line WL1 is a conventional example.
It is set longer than the rewrite time in the operation shown in FIG. That is, time is added to and the total time can be set to a length of 40 ns to 50 ns. Even if the delay time is extended in this manner, the block selection signal BS0 is already at "L" level during the time period, so that the block selection transistor 44 is off, and the bit line BLB and the memory cell The group 43 is separated by a selection transistor 44. Therefore, it is possible to prepare for the next operation by setting the bit line precharge to the ground potential or the like, and the operation speed is not reduced.

The external chip enable signal CEB is about 50
The state is set to the “L” level state for a period from n seconds to 100 n seconds. The reading here will be described by way of an example in which a dummy cell that generates a potential exactly intermediate between the “1” and “0” signal lines is connected to the bit line BL side to generate a reference voltage.

After the chip enable signal CE1 changes from "L" level to "H" level, the potential of the word line WL1 changes from "H" level to "L" level, and then the block selection signal BS0 changes to "L" level. The level shifts from the level to the “H” level.

Thereafter, the plate signal line PL2 shifts from "L" level to "H" level, and information of the ferroelectric capacitor 41 of the memory cell 42 is transferred to the bit line BLB. After being amplified at 39, the bit lines BL and BLB are determined to be in a complementary state of either "H" or "L" or "L" or "H". When the selected memory cell 42 stores “1” data, the bit line BLB = “H” and the bit line BL =
When the selected memory cell stores “0” data, the bit line BLB = “L” and the bit line BL =
It becomes "H". The bit line potential is amplified by the sense amplifier / input / output circuit 39, and the sense result is output from the input / output buffer 34, whereby the data reading of "1" or "0" is performed.

Here, reading of a ferroelectric memory cell does not involve polarization inversion when reading "0" data, but reading "1" data involves polarization inversion.

At the time of reading "1" data, since the polarization direction of the ferroelectric capacitor is broken, it is necessary to write after reading.

As shown in FIG. 5, rewriting after reading is performed by rewriting "0" data is performed by the plate line PL2.
= H and the bit line BLB = “L”.

In the case of reading "1" data,
Rewriting of "1" data is performed with the plate line PL2 = "L"
After that, the operation is performed with the bit line BLB = "H".

The TC (Transistor-Ca) as shown in FIG.
pacitor) In a parallel unit series connection type ferroelectric memory,
When reading is completed with the external chip enable signal CEB = “H”, all the word lines WL are set to “H” level and all are unselected, so that the selected word line WL1 is set to “H”.
Level, both ends of the ferroelectric capacitor are short-circuited, the potential difference between both ends of the ferroelectric capacitor disappears, and the write state ends.

In the present embodiment, in order to take a sufficient time for writing “1” data to be rewritten into the domain-inverted ferroelectric capacitor, the plate line PL is changed from “H” level to “L” level. The word line WL is kept in the selected state for a certain period of time, so that a voltage is applied to the ferroelectric capacitor in the memory cell even after writing.

After writing "0" data while the plate line PL is at the "H" level, the potential of the plate line PL is lowered to start "1" data writing. Immediately after that, the block selection line BS falls to disconnect the memory cell group 43 from the bit line BLB. After the potential of the plate line PL falls, the selected word line WL1 is kept in a selected state ("L" state) for a certain period of time. As a result, the potential of the bit line BLB is applied to the node A, and the potential of the plate line PL (“L” level) is continuously applied to the node B, and a write voltage is applied to the ferroelectric capacitor 41 of the memory cell 42. During this time, the ferroelectric capacitor 41 can keep the state of writing “1” data, thereby enabling sufficient writing and securing data reliability. Thereafter, the write state ends at the rise of the selected word line WL1, and the standby state is entered.

In the data writing, information according to an external input is written instead of writing the read information. The writing operation is performed at the same timing as the rewriting after the reading. That is, after the potential of the plate line PL falls, the selected state of the selected word line WLi is maintained for a certain period of time, so that a voltage can be applied to the ferroelectric capacitor 41 of the memory cell 42 even after writing, and "1" Data can be sufficiently written.

Here, FIG. 6 shows the relationship between the writing time and the signal amount at the time of reading of the ferroelectric memory cell in the present embodiment. Here, the results are shown when a PZT film having a thickness of 0.22 μm is used and measured at room temperature. The drive voltage of the memory cell is two of 2.2V and 2.5V.
Two cases are shown.

First, when the power supply voltage is high, ie, 2.5 V, and the memory cell drive voltage is set to 2.5 V, a signal amount of 180 mV is obtained when the writing time is 20 ns in the conventional example. In the first embodiment, the write time is extended to 50 ns, and the signal amount is 210 mV, which is 17% larger than in the conventional example.

If the power supply voltage is further reduced to 2.2 V and the memory cell drive voltage is set to 2.2 V, a signal amount of 70 mV is obtained when the writing time is 20 ns in the conventional example. On the other hand, in the writing time of 50 ns of the present embodiment,
The signal amount is 120 mV, which is 70% larger than the conventional example. By using the present embodiment when the drive voltage of the memory cell is reduced as described above, it is possible to secure a larger signal line than in the conventional example, and particularly in a semiconductor memory device operated at a low voltage. ,
The effect of this embodiment for improving the memory cell characteristics is remarkable.

According to the present embodiment, in the TC parallel unit serial connection type ferroelectric memory, the period from the fall of the plate line PL to the rise (deselection) of the word line WL as the memory cell selection signal line. By providing a time delay and leaving a write voltage between both ends of the ferroelectric capacitor, it is possible to have a sufficient data write time. That is, by using the TC parallel unit serial connection type ferroelectric memory, sufficient writing is performed by continuously applying the writing voltage to the ferroelectric capacitor constituting the memory cell even after the end of the writing operation, and the data holding characteristic of the cell is improved. It is possible to improve.

(Second Embodiment) In the present embodiment,
The overall configuration of the device, the configuration of the cell array, and the configuration of the address buffer are the same as in the first embodiment, as shown in FIGS.
4. The method at the time of reading is the same as that of the first embodiment, but the timing at the time of rewriting is different.

As shown in FIG. 7, the configuration of the control circuit of this embodiment is almost the same as that of the first embodiment shown in FIG. That is, the fourth in FIG.
Instead of the delay circuit 4, a flip-flop circuit including second and third NOR circuits 65 and 66 is added. The second NOR circuit 65 has a first chip enable delay signal CED
The outputs of the first and third NOR circuits 66 are input. Third
The output of the second NOR circuit 65 and the chip enable signal CE1 are input to the NOR circuit 66. The output of the third NOR circuit 66 and the output signal of the first delay circuit 1 which is a delay signal of the chip enable signal CE1 are output from the first NOR circuit 27.
Is input to The output of the first NOR circuit via the second inverter 11 is the second chip enable delay signal CED2.

In this control circuit, a twelfth inverter 67 is replaced by a seventh inverter 17 and an eighth inverter 18 instead of the sixth delay circuit 6 and the fifth NAND circuit 25 in the control circuit of the first embodiment. And a row address latch signal BRAT is output from the eighth inverter 18.

FIG. 8 shows a signal chart at the time of reading of main signals and nodes according to the second embodiment. In the figure, each signal is synchronized at the timing shown by the dotted line.

As shown in FIG. 8, the bit line BLB is changed from "1" or "0" level to "0" level from the initial "H" level change of the external chip enable signal CEB to "L" level. Is the same as that of the first embodiment.

Here, the external chip enable signal CE
At the timing when B changes from “H” level to “L” level again, the chip enable signal CE1 changes from “L” level to “H” level, and the second chip enable delay signal CED2 and the address path signal BADPAS change to “ H "
The level shifts from the level to the “L” level.

The second chip enable delay signal CED2,
At the timing when the address pass signal BADPAS changes from “H” level to “L” level, the row address latch signal BRAT changes from “L” level to “H” level, and the row address enable signal RAE changes from “H” level. Displaced to “L” level.

At the timing when the row address enable signal RAE changes from "H" level to "L" level, the decoder is not selected and the potential of the word line WL1 changes from "L" level to "H" level.

When the potential of the word line WL1 changes from "L" level to "H" level, the node A goes to "0".
Displace to level.

As shown in FIG. 8, rewriting after reading is performed by rewriting “0” data is performed by the plate line PL.
= H and the bit line BLB = “L”.

Regarding the rewriting of the "1" data, the timing at which the selected word line WL1 is deselected after the potential of the plate line PL2 falls is determined by the external chip enable signal C.
It goes on the falling edge of EB. By doing so, "1" data can be written until the start of the next read cycle, and sufficient "1" data can be written.

Similarly, at the time of data writing, the plate line PL
The timing to deselect the selected word line WL1 after the fall of the potential of 2 is performed at the fall of the external chip enable signal CEB.

In this embodiment, the same effects as in the first embodiment can be obtained.

(Third Embodiment) In the present embodiment,
The overall configuration of the device, the configuration of the cell array, and the configuration of the address buffer are the same as in the first embodiment, as shown in FIGS.
4.

In this embodiment, the voltage of plate line PL is fixed (for example, の of the power supply voltage). Also, the bit line precharge potential is １ ／ of the power supply voltage.

That is, the method at the time of reading is the same as that of the first embodiment, and the timing at the time of rewriting is the same, but the voltage of the plate line is fixed (for example, 電源 of the power supply voltage). The points are different.

As shown in FIG. 9, the configuration of the control circuit of this embodiment is almost the same as that of the first embodiment shown in FIG. However, the fourth NAND circuit 24 and the seventh inverter circuit 16 in FIG. 1 have been removed, and the plate line enable signal PLEBL has not been generated. In the present embodiment, there is no need to control the clock of the plate line PL, and the plate line enable signal PLEBL is not required.

FIG. 10 is a signal chart at the time of reading of a main signal and a node according to the second embodiment. In the figure, each signal is synchronized at the timing shown by the dotted line.

As shown in FIG. 10, the potential of the bit line BLB and the potential of the node A are initially set to 1 / power supply voltage.
It is set to 2. External chip enable signal CEB
From the first “H” level to the “L” level,
The change of the bit line BLB from the half level of the power supply voltage to the “1” or “0” level, and further from the “1” level or the “0” level to the displacement of the power supply voltage to the half level. The timing is the same as in the first embodiment.

As shown in FIG. 10, the potential of the bit line BLB and the potential of the node A are changed to the level of the block selection signal BS0 = "L".
Since the memory cell is connected to the bit line at the timing of “H” to “H”, it becomes slightly higher in the case of reading “1” data. In the case of "0" data read, the value is slightly lower. The potential of the bit line BLB and the potential of the node A are changed from the “L” level to the “H” level at the timing when the sense amplifier control signal SA is changed from the “L” level to the “H” level after a lapse of time. Shifts to the “H” level, and shifts to the “L” level when reading “0” data.

Thereafter, at the same timing as in the first embodiment, the potential of the bit line BLB and the potential of the node A are set to 1 of the power supply voltage.
/ 2. Here, the first embodiment differs from the first embodiment in that the potentials of the bit line BLB and the node A are not at the “L” level,
The difference is that it is displaced to half of the power supply voltage.

In the standby state, the external chip enable signal CEB = "H" and the word line potentials WL0 to WL7
= “H”, block selection signals BS0 to BS1 = “L”,
Plate line potential PL1 to PL2 = “1/3 of power supply voltage”
2 ", bit line potentials BL and BLB =" 1 / (supply voltage)
2 ″, internal nodes of the memory cell group (node A, node B
Etc.) = １ ／ of the power supply voltage. At the time of reading, the word line WLi and block selection line BSi selected by the external address are activated by the external chip enable signal CEB = "L". Here, the word line WL
1. The case where the memory cell 42 is selected by the block selection line BS0 and connected to the bit line BLB will be described.

In this embodiment, no reference cell is used, and it is determined whether the cell information is "1" or "0" depending on whether the bit line potential is higher or lower than 1/2 of the power supply voltage.

Rewriting after reading is performed by applying the bit line potential after bit line sensing and the plate line potential to both ends of the ferroelectric capacitor. After the bit line is amplified by the sense amplifier, the selected word line WL is kept in the selected state even when the block selection signal BS falls. As a result, the write voltage is continuously applied to the ferroelectric capacitor 41 until the word line is deselected and the potential at both ends of the ferroelectric capacitor 41 in the memory cell 42 is short-circuited.

In this embodiment, “0” data,
The "1" data is also in a write state at this timing. As shown in FIG. 10, in the case of writing “0” data, node A is at the bit line potential GN
D, for example, 0V.
It is 1/2 (1.6 V) of the power supply voltage which is the potential of L.
As a result, "0" data is written. “1”
In the case of data writing, node A is at a power supply voltage which is the bit line potential after sensing, for example, 3.3 V, and node B is １ ／ of the power supply voltage at the plate line PL.
(1.6 V). As a result, a "1" data write state is set.

Non-selection (falling) of block selection signal BS
After that, the selected word line WL is kept in the selected state for a certain period of time, and sufficient data can be written to both "0" and "1".

In the case where the characteristics of the ferroelectric film can be sufficiently written at half the power supply voltage and the data can be held, the reference cell is not used in this embodiment.
Further, it is preferable in that reading and writing operations can be performed without clock control of the plate potential.

In this embodiment, effects similar to those of the first embodiment can be obtained.

(Fourth Embodiment) In the present embodiment,
The overall configuration of the device, the configuration of the cell array, and the configuration of the address buffer are the same as in the first embodiment, as shown in FIGS.
4. The method at the time of reading is the same as that of the first embodiment, but the timing at the time of rewriting is different.

This embodiment is a combination of the second embodiment and the third embodiment.

That is, in this embodiment, the timing at the time of rewriting is the same as the timing at the time of rewriting of the second embodiment, and the voltage of the plate line PL is the third.
(For example, fixed to 電源 of the power supply voltage). Also, the bit line precharge potential is １ ／ of the power supply voltage.

As shown in FIG. 11, the configuration of the control circuit of this embodiment is almost the same as that of the second embodiment shown in FIG. However, the fourth NAND circuit 24 and the seventh inverter circuit 16 in FIG. 7 have been removed, and the plate line enable signal PLEBL has not been generated. Here, since there is no need to control the clock of the plate line PL, the plate line enable signal PLE is used.
BL is not required.

FIG. 12 is a signal chart at the time of reading of main signals and nodes according to the fourth embodiment. In the figure, each signal is synchronized at the timing shown by the dotted line.

As shown in FIG. 12, bit line BLB
The potential and the potential of the node A are initially set to 1 of the power supply voltage.
/ 2. External chip enable signal CE
From the first displacement of B from “H” level to “L” level, the potential of bit line BLB from の level of power supply voltage to “1” or “0” level, and further “1” or “1” The timing from the “0” level to the displacement to the half level of the power supply voltage is the same as in the third embodiment.

As shown in FIG. 12, the potentials of the bit line BLB and the node A slightly increase in the case of "1" data read, and slightly decrease in the case of "0" data read. Then, after a lapse of time plus the time, the sense amplifier control signal SA is shifted to “H” level in the case of “1” data reading at the timing of shifting from “L” level to “H” level, In the case of reading “0” data, the signal shifts to “L” level. Then the second
At the same timing as in the embodiment, the potentials of the bit line BLB and the node A are changed to the level of 1/2 of the power supply voltage.

In the standby state, the external chip enable signal CEB = "H" and the word line potentials WL0 to WL7
= “H”, block selection signals BS0 to BS1 = “L”,
Plate line potential PL1 to PL2 = “1/3 of power supply voltage”
2 ", bit line potentials BL and BLB =" 1 / (supply voltage)
2 ″, internal nodes of the memory cell group (node A, node B
Etc.) = １ ／ of the power supply voltage. At the time of reading, the word line WLi and the block selection line BSi selected by an external address are activated by the chip enable signal CEB = "L". Here, the word line WL
1. The case where the memory cell 42 is selected by the block selection line BS0 and connected to the bit line BLB will be described.

In this embodiment, no reference cell is used, and it is determined whether the cell information is "1" or "0" depending on whether the bit line potential is higher or lower than 1/2 of the power supply voltage.

The rewriting after the reading is performed by applying the bit line potential after the bit line sensing and the plate line potential to both ends of the ferroelectric capacitor. After the bit line is amplified by sense-up, the selected word line WL is kept in the selected state even if the block selection signal BS falls. As a result, the write voltage is applied to the ferroelectric capacitor 41 until the word line is deselected and the potential at both ends of the ferroelectric capacitor 41 of the memory cell 42 is short-circuited.

In this embodiment, “0” data,
The "1" data is also in a write state at this timing. As shown in FIG. 12, in writing “0” data, the node A is connected to the bit line potential GND after sensing,
For example, the voltage becomes 0 V, and the potential at the node B becomes の (1.6 V) of the power supply voltage which is the potential of the plate line PL. As a result, "0" data is written.

In writing "1" data, the power supply voltage which is the bit line potential after sensing, for example, 3.3, is applied to node A.
V, and に は (1.6 V) of the power supply voltage which is the potential of the plate line PL is applied to the node B. As a result, a "1" data write state is set.

Non-selection (falling) of block selection signal BS
After that, the selected word line WL remains in the selected state until the start of the next cycle in which the external chip enable signal CEB falls, and sufficient data can be written to both "0" and "1".

When writing external data, the write operation of “0” and “1” is performed at the same timing as the rewrite at the time of reading, and sufficient data can be written.

When the characteristics of the ferroelectric film can be sufficiently written at half the power supply voltage and data can be retained, the reference cell is not used in this embodiment.
Further, it is preferable in that reading and writing operations can be performed without clock control of the plate voltage.

In this embodiment, the same effects as in the first embodiment can be obtained.

(Fifth Embodiment) In the present embodiment,
The configuration of the address buffer is the configuration of FIG. 4 as in the first embodiment. The method at the time of reading is the same as that of the first embodiment, but a switch drive circuit 7 for connecting and disconnecting the memory cell and the plate line is used.
0 is newly added, and the driving method at the time of canceling the word line selection is different from that of the first embodiment.

The overall configuration of the fifth embodiment is as shown in FIG. 13, and is almost the same as that of the first embodiment. Unlike the first embodiment, a new signal, that is, a plate line connection enable signal PSEBL is generated from the control circuit, and a switch driving circuit 70 for connecting and disconnecting a memory cell and a plate line is provided. Newly added.

The configuration of the memory cell array according to the fifth embodiment is as shown in FIG. The first shown in FIG.
In the configuration of the memory cell array of the embodiment, a plate line selection transistor 71 is provided between the memory cell group 43 and the plate lines PL1 and PL2. here,
The plate line selection transistor 71 receives plate line connection signals PS0 and PS1 at its gate.

The control circuit according to the fifth embodiment is as shown in FIG. 15 and has substantially the same configuration as that of the first embodiment. Unlike the first embodiment, the tenth delay circuit 7 to which the output signal of the eighth inverter 17 is input
2 and a second NOR circuit 73 to which the output signal of the tenth delay circuit 72, the first chip enable delay signal CED1, and the chip enable signal CE1 are input. Further, a twelfth inverter 74 to which an output signal of the second NOR circuit 73 is input is provided.
The twelfth inverter 74 outputs a plate line connection enable signal PSEBL.

A signal chart of main signals and nodes in the fifth embodiment is as shown in FIG. 16 and is almost the same as the signal chart in the first embodiment. In the figure, each signal is synchronized at the timing shown by the dotted line.

Unlike the first embodiment, the waveform of the plate line connection signal PS is added. The plate line connection signal PS is set to the “H” level from the read operation to the middle stage of the rewrite operation, and at the timing when the first chip enable delay signal CED1 changes from the “H” level to the “L” level. , "H" level to "L" level. After that, the second chip enable delay signal CED2 changes from “L” level to “H” level after a lapse of time (10) from the timing of changing from “H” level to “L” level.

In the fifth embodiment, in the standby state, the external chip enable signal CEB = "H",
Words WL0 to WL7 = "H", block select signal BS
0 to BS1 = “L”, plate lines PL0 to PL2 =
“L”, bit lines BL and BLB = “L”, plate line connection signals PS0 to PS1 = “H”, and internal nodes (node A, node B, etc.) of the memory cell group = “L”.

At the time of reading, the external chip enable signal CEB is activated by "L", and the word line fall, the block line select signal BS rise, and the sensing operation are the same as in the first embodiment. . During that time, the plate line connection signal PS is “H”, the selected cell transistor 5 is on, and the plate line PL and the memory cell group 4 are connected.

The rewriting in the fifth embodiment is the same as that of the first embodiment.
Similarly to the embodiment, the rewriting of “0” data is performed by
The plate line PL2 is applied to the cell whose bit line is at the “L” level during the “H” period. To rewrite “1” data, after writing “0” data, the potential of the plate line PL is lowered, and This is performed for cells at the “H” level. After rewriting is completed, the selected word line is set to (“L”).
State) Before the block selection signal BS and the plate line connection signal PS are lowered from “H” to “L” before the non-selection state (“H” state), the memory cell group and the bit line, and the memory cell group Disconnect from the plate line PL. Plate line PL
After the potential falls, the selected word line WL continues to be in the selected state ("L" state) for a certain period of time. After bringing the selected word line WL into the non-selected state (rising), the plate line connection signal PS rises. While the word line is in the selected state, the bit line potential is continuously applied to the node A, and the plate line PL voltage (“L”) is continuously applied to the node B, and the write voltage is applied to the ferroelectric capacitor of the memory cell A. During this time, the ferroelectric capacitor can keep the state of writing “1” data, and sufficient writing can be performed.

In this embodiment, when the word line rises and the potentials at both ends of the ferroelectric capacitor of the memory cell 42 are short-circuited, the time constants of the nodes A and B are substantially the same.

In the first embodiment, since the plate line PL has a large capacitance (plate capacitance) to which many bit lines are commonly connected, the time constants of the node A and the node B are significantly different. Although there is a possibility that an unintended stress may be applied to the cell due to a change in potential, in this embodiment, the capacitance imbalance between the node A and the node B can be removed, and the stress can be hardly generated.

Also in the present embodiment, even if writing of memory cells is continued after the block selection line BS is lowered,
Since the bit line and the memory cell group are separated by the selection transistor, the bit line precharge is performed by GN in this example.
Since the potential can be set to the D potential, the next read cycle can be prepared, and a high-speed cycle time can be realized.

In data writing, information according to an external input is written instead of writing read information. As a writing operation, the same operation as the rewriting operation after reading is performed at the same timing.
In other words, after the fall of the potential of the plate line PL, the voltage can be applied to the ferroelectric capacitor of the memory cell 42 even after writing by maintaining the selected state of the word line for a certain period of time.
"1" data can be sufficiently written.

In this embodiment, effects similar to those of the first embodiment can be obtained.

(Sixth Embodiment) In the present embodiment,
The configuration of the address buffer, the overall configuration of the device, and the configuration of the cell array are the same as in the fifth embodiment, as shown in FIGS.
3 and 14. The method at the time of reading is the same as that of the fifth embodiment, but the timing at the time of rewriting is different.

FIG. 17 shows a configuration of a control circuit according to the present embodiment. The control circuit according to the present embodiment is almost the same as the control circuit according to the second embodiment. Unlike the second embodiment, the eighth embodiment
A tenth delay circuit 72 to which the output signal of the inverter 17 is input is provided, and an eleventh delay circuit 75 to which the chip enable signal CE1 is input is further provided. A second NOR circuit 73 to which the output signals of the tenth delay circuit 72 and the eleventh delay circuit 75 and the first chip enable delay signal CED1 are input is provided. Further, a twelfth inverter 74 to which an output signal of the second NOR circuit 73 is input is provided. The twelfth inverter 74 outputs the plate line connection enable signal PSEBL.

FIG. 18 shows main signals and operation waveforms of the nodes in the present embodiment. In the figure, each signal is synchronized at the timing shown by the dotted line.

In this embodiment, block selection signal BS
Is the same as that of the fifth embodiment up to the timing when the signal changes from the "H" level to the "L" level. The subsequent operation waveforms are the same as those of the second embodiment except for the plate line connection signal PS. The plate line connection signal PS indicates that the second chip enable delay signal CED2 has changed from “H” level to “L”.
After a lapse of time (10) from the timing when the shift to the level ends, the shift from the “L” level to the “H” level occurs.

In this embodiment, the rewriting of "1" data is performed at the falling edge of the external chip enable signal CEB at the timing of deselecting the selected word line WL1 after the potential of the plate line PL2 falls. By doing so, "1" is kept until the start of the next read cycle.
Data can be written, and sufficient "1" data can be written.

In this embodiment, the same effect as in the fifth embodiment can be obtained.

(Seventh Embodiment) In the present embodiment,
The configuration of the address buffer, the overall configuration of the device, and the configuration of the cell array are the same as in the fifth embodiment, as shown in FIGS.
3 and 14. The reading method is the same as that of the fifth embodiment, except that the voltage of the plate line is fixed (for example, の of the power supply voltage). Another difference is that the bit line precharge potential is also １ ／ of the power supply voltage.

The configuration of the control circuit according to the seventh embodiment is as shown in FIG. 19, and is substantially the same as the configuration of the control circuit according to the third embodiment. However, in addition to the control circuit in the third embodiment, a tenth delay circuit 72 to which the output signal of the eighth inverter 17 is input is provided, and the output signal of the tenth delay circuit 72, the first chip enable A second NOR circuit 73 to which the delay signal CED1 and the external chip enable signal CE1 are input is provided. Further, a twelfth inverter 74 to which an output signal of the second NOR circuit 73 is input is provided. The plate line connection enable signal PSEBL is output from the twelfth inverter 74.

FIG. 20 is a signal chart of main signals and nodes at the time of reading according to the seventh embodiment. In the figure, each signal is synchronized at the timing shown by the dotted line.

The third embodiment is the same as the third embodiment except that the waveform of the plate line connection signal PS is added. The waveform of the plate line connection signal PS is the same as that of the fifth embodiment.

In this embodiment, the plate line PL voltage is fixed (for example, １ ／ of the power supply voltage).

In the standby state, the chip enable signal CEB = "H" and the word lines WL0 to WL7 =
“H”, block selection signals BS0 to BS1 = “L”, plate lines PL1 to PL2 = “1/2 of power supply voltage”, bit lines BL and BLB = “1/2 of power supply voltage”, plate line connection signal PS0 ＰＳPS1 = “H”, internal node of memory cell group (node A, node B, etc.) = １ ／ of power supply voltage
It has become. At the time of reading, the word line WLi and the block selection signal BSi selected by the external address are activated by the external chip enable signal CEB = "L". Here, the word line WL1, the block selection signal BS
When 0, the memory cell 42 is selected and connected to the bit line BLB.

In this embodiment, no reference cell is used, and it is determined whether the cell information is "1" or "0" depending on whether the bit line potential is higher or lower than 1/2 of the power supply voltage.

Rewriting after reading is performed by applying the bit line potential after bit line sensing and the plate line potential to both ends of the ferroelectric capacitor. After the bit line is amplified by the sense amplifier, the word line WL is kept in the selected state even when the block selection line BS and the plate line connection signal PS fall. As a result, the write voltage is applied to the capacitor until the word line is deselected and the potential at both ends of the ferroelectric capacitor 41 of the memory cell 42 is short-circuited.

In this embodiment, “0” data,
The "1" data is also in a write state at this timing.

As shown in FIG. 20, for writing "1" data, node A becomes a power supply voltage which is a bit line voltage after sensing, for example, 3.3 V, and node B is a power supply voltage which is a plate line PL potential. (1.6 V). As a result, "1" data is written.

To write "0" data, the node A is at GND, which is the bit line voltage after sensing, for example, 0 V, and the node B is の (1.6 V) of the power supply voltage, which is the potential of the plate line PL. Becomes As a result, "0" data is written.

After the word line is activated, the plate line connection signal PS is activated, and the memory cell group 43 and the plate line P are activated.
And L. After the bit line potential is determined and until the word line is deselected, the ferroelectric capacitor can continue to write "0" or "1" data, and sufficient writing can be performed.

In this embodiment, when the word line is activated and the potentials at both ends of the ferroelectric capacitor of the memory cell 42 are short-circuited, the time constants of the nodes A and B are substantially the same.

In the first embodiment, since the plate line PL has many bits connected in common and has a large capacitance (plate capacitance), the time constants of the node A and the node B are significantly different. Although there is a possibility that an unintended stress may be applied to the cell due to a change in potential, in this embodiment, the capacitance imbalance between the node A and the node B can be removed, and the stress can be hardly generated.

In this embodiment, the same effects as in the fifth embodiment can be obtained.

(Eighth Embodiment) In the present embodiment,
The configuration of the address buffer, the overall configuration of the device, and the configuration of the cell array are the same as in the fifth embodiment, as shown in FIGS.
3 and 14. The method at the time of reading is the same as that of the fifth embodiment, but the timing at the time of rewriting is different.

This embodiment is a combination of the sixth embodiment and the seventh embodiment.

That is, in this embodiment, the timing at the time of rewriting is the same as the timing at the time of rewriting of the sixth embodiment, and the voltage of the plate line PL is the seventh.
(For example, fixed to 電源 of the power supply voltage).

The configuration of the control circuit according to the eighth embodiment is as shown in FIG. 21, and is substantially the same as the configuration of the control circuit according to the fourth embodiment. However, in addition to the control circuit in the fourth embodiment, a tenth delay circuit 72 to which the output signal of the eighth inverter 17 is input is provided, and an eleventh delay circuit 75 to which the external chip enable signal CE1 is input is provided. Further provided. A second NOR circuit 73 to which the output signals of the tenth delay circuit 72 and the eleventh delay circuit 75 and the first chip enable delay signal CED1 are input is provided. Further, a twelfth inverter 74 to which an output signal of the second NOR circuit 73 is input is provided. From the twelfth inverter 74, the plate line connection signal PSEB
L is output.

FIG. 22 shows a signal chart of main signals and nodes at the time of reading in the eighth embodiment. In the figure, each signal is synchronized at the timing shown by the dotted line.

The fourth embodiment is the same as the fourth embodiment except that the waveform of the plate line connection signal PS is added. The waveform of the plate line connection signal PS is the same as that of the sixth embodiment.

In this embodiment, the potential of plate line PL is fixed (for example, 電源 of the power supply voltage). Also,
The bit line precharge potential is also １ ／ of the power supply voltage.

In this embodiment, the same effect as in the fifth embodiment can be obtained.

(Ninth Embodiment) In the present embodiment,
The overall configuration of the device, the configuration of the cell array, and the configuration of the address buffer are the same as in the first embodiment, as shown in FIGS.
4. The control circuit also has the configuration of the control circuit of FIG. 1 as in the first embodiment. The method at the time of reading is the same as that of the first embodiment, and the timing at the time of rewriting is the same as that of the first embodiment. However, the bit line precharge potential is different and the power supply voltage is used. Regarding the operation of the present embodiment, only the parts different from the first embodiment will be mainly described.

FIG. 23 shows a signal chart at the time of reading of main signals and nodes according to the ninth embodiment. In the figure, each signal is synchronized at the timing shown by the dotted line.

When the potential of the block selection signal BS0 is "L", the memory cell group is disconnected from the bit line BLB, and the potential of the bit line BLB is at "H" level (power supply potential in this embodiment). The potential of the block selection signal BS0 changes from “L” to “H”, and the memory cell group is
Connected to LB, the electric potential of the selected memory cell is transferred to the bit line BLB. Further, the potential of the plate line PL2 changes from the “L” level to the “H” level, so that the potential of the plate line PL2 becomes a potential corresponding to the data of the memory cell. The potential of the bit line BLB is further amplified by the sense amplifier at the timing when the level of the sense amplifier SA changes from the “L” level to the “H” level, and changes to the “H” level or the “L” level according to the data of the memory cell. I do. Further, the potential of the bit line BLB is equal to the sense amplifier control signal S.
At the timing when A is changed from “H” level to “L” level, if A is at “H” level, it is changed to “L” level.

At the timing when the second chip enable delay signal CED2 changes from "H" level to "L" level, the row address enable signal RAE changes from "H" level to "L" level.

At the timing when the row address enable signal RAE changes from "H" level to "L" level, the decoder is deselected and the potential of the word line WL1 changes from "L" level to "H" level, and the word line WL1 changes. Is also not selected, and both ends of the memory cell are short-circuited.

When the potential of the word line WL1 changes from "L" level to "H" level, the node A goes to "0".
It is displaced to the level and becomes the same potential as the plate line.

As shown in FIG. 23, rewriting after reading is performed by rewriting “0” data by plate line P.
The operation is performed in a state where the bit line BLB = "L" while L = "H".

The rewriting of "1" data is performed for a certain period of time after the potential of the plate line PL2 has fallen until the selected word line WL1 is deselected.

Similarly, at the time of data writing, the plate line PL
After the fall of the potential of No. 2, the operation is performed for a predetermined time until the timing at which the selected word line WL1 is deselected.

In this embodiment, the same effects as in the first embodiment can be obtained.

(Tenth Embodiment) In the present embodiment, the overall configuration of the device, the configuration of the cell array, and the configuration of the address buffer are the same as those of the first embodiment, as shown in FIG.
These are the configurations 3 and 4. The control circuit has the configuration of the control circuit of FIG. 7 as in the second embodiment.
The method at the time of reading is the same as in the first embodiment,
The timing at the time of rewriting is different. Further, in this embodiment, the bit line precharge potential is a power supply voltage, unlike the first embodiment. Regarding the operation of the present embodiment, only the portions different from the second embodiment will be mainly described.

FIG. 24 is a signal chart at the time of reading of main signals and nodes according to the tenth embodiment.
In the figure, each signal is synchronized at the timing shown by the dotted line.

When the potential of block select signal BS0 is "L", the memory cell group is disconnected from bit line BLB, and the potential of bit line BLB is at "H" level (power supply potential in this embodiment). The potential of the block selection signal BS0 changes from “L” to “H”, and the memory cell group is
Connected to LB, the electric potential of the selected memory cell is transferred to the bit line BLB. Further, the potential of the plate line PL2 changes from the “L” level to the “H” level, so that the potential of the plate line PL2 becomes a potential corresponding to the data of the memory cell. The potential of the bit line BLB is further amplified by the sense amplifier at the timing when the level of the sense amplifier SA changes from the “L” level to the “H” level, and changes to the “H” level or the “L” level according to the data of the memory cell. I do. Further, the potential of the bit line BLB is equal to the sense amplifier control signal S.
At the timing when A is changed from “H” level to “L” level, if A is at “H” level, it is changed to “L” level.

At the timing when the second chip enable delay signal CED2 changes from “H” level to “L” level, the row address enable signal RAE changes from “H” level to “L” level.

At the timing when the row address enable signal RAE changes from "H" level to "L" level, the decoder is not selected and the potential of the word line WL1 changes from "L" level to "H" level.

At the timing when the potential of the word line WL1 is changed from "L" level to "H" level, the node A is set to "0".
Displace to level.

As shown in FIG. 24, rewriting after reading is performed by rewriting “0” data is performed by the plate line P.
The operation is performed in a state where the bit line BLB = "L" while L = "H".

Regarding the rewriting of the "1" data, the external chip enable signal C is used to deselect the selected word line WL1 after the potential of the plate line PL2 falls.
It goes on the falling edge of EB. By doing so, "1" data can be written until the start of the next read cycle or the start of the next write cycle, and sufficient "1" data can be written.

Similarly, at the time of data writing, the plate line PL
The timing to deselect the selected word line WL1 after the fall of the potential of 2 is performed at the fall of the external chip enable signal CEB.

In this embodiment, the same effect as in the second embodiment can be obtained.

(Eleventh Embodiment) In this embodiment, the configuration of the address buffer is the same as that of the first embodiment shown in FIG. The method at the time of reading is the same as that of the first embodiment, and the control circuit has the configuration of the control circuit of FIG. 15 similarly to the fifth embodiment. As in the fifth embodiment, as shown in FIG. 13, in this embodiment, a switch drive circuit 70 for connecting and disconnecting a memory cell and a plate line is newly added. Therefore, the driving method at the time of canceling the word line selection is different from that of the first embodiment.

Further, in the present embodiment, the bit line precharge potential is the power supply voltage, unlike the first embodiment. Regarding the operation of the present embodiment, only the parts different from the fifth embodiment will be mainly described.

FIG. 25 is a signal chart at the time of reading of main signals and nodes according to the eleventh embodiment.
In the figure, each signal is synchronized at the timing shown by the dotted line.

When the potential of block select signal BS0 is "L", the memory cell group is disconnected from bit line BLB, and the potential of bit line BLB is at "H" level (power supply potential in this embodiment). The potential of the block selection signal BS0 changes from “L” to “H”, and the memory cell group is
Connected to LB, the electric potential of the selected memory cell is transferred to the bit line BLB. Further, the potential of the plate line PL2 changes from the “L” level to the “H” level, so that the potential of the plate line PL2 becomes a potential corresponding to the data of the memory cell. The potential of the bit line BLB is further amplified by the sense amplifier at the timing when the level of the sense amplifier SA changes from the “L” level to the “H” level, and changes to the “H” level or the “L” level according to the data of the memory cell. I do. Further, the potential of the bit line BLB is equal to the sense amplifier control signal S.
At the timing when A is changed from “H” level to “L” level, if A is at “H” level, it is changed to “L” level.

At the timing when the second chip enable delay signal CED2 changes from "H" level to "L" level, the row address enable signal RAE changes from "H" level to "L" level.

At the timing when the row address enable signal RAE changes from "H" level to "L" level, the decoder is not selected, the potential of the word line WL1 changes from "L" level to "H" level, and the word line WL1 changes. Is also not selected, and both ends of the memory cell are short-circuited.

When the potential of the word line WL1 changes from "L" level to "H" level, the node A goes to "0".
It is displaced to the level and becomes the same potential as the plate line.

As shown in FIG. 25, for rewriting after reading, rewriting of “0” data is performed for the plate line P.
The operation is performed in a state where the bit line BLB = "L" while L = "H".

Rewriting of "1" data is performed for a certain period of time after the potential of the plate line PL2 falls until the timing of deselecting the selected word line WL1.

Similarly, at the time of data writing, the plate line PL
After the fall of the potential of No. 2, the operation is performed for a predetermined time until the timing at which the selected word line WL1 is deselected.

In this embodiment, the same effects as in the fifth embodiment can be obtained.

(Twelfth Embodiment) In the twelfth embodiment, the configuration of the address buffer, the overall configuration of the device, and the configuration of the cell array are the same as those of the fifth embodiment, as shown in FIG.
13 and 14. The method at the time of reading is the same as that of the fifth embodiment, but the timing at the time of rewriting is different. The control circuit has the configuration of the control circuit of FIG. 17 as in the sixth embodiment. Further, in this embodiment, the bit line precharge potential is a power supply voltage, unlike the first embodiment. Regarding the operation of the present embodiment, only the parts different from the sixth embodiment will be mainly described.

FIG. 26 shows main signals and operation waveforms of the nodes in this embodiment. In the figure, each signal is synchronized at the timing shown by the dotted line.

Each signal is synchronized at the timing shown by the dotted line.

When the potential of block select signal BS0 is "L", the memory cell group is disconnected from bit line BLB, and the potential of bit line BLB is at "H" level (power supply potential in this embodiment). The potential of the block selection signal BS0 changes from “L” to “H”, and the memory cell group is
Connected to LB, the electric potential of the selected memory cell is transferred to the bit line BLB. Further, the potential of the plate line PL2 changes from the “L” level to the “H” level, so that the potential of the plate line PL2 becomes a potential corresponding to the data of the memory cell. The potential of the bit line BLB is further amplified by the sense amplifier at the timing when the level of the sense amplifier SA changes from the “L” level to the “H” level, and changes to the “H” level or the “L” level according to the data of the memory cell. I do. Further, the potential of the bit line BLB is equal to the sense amplifier control signal S.
At the timing when A is changed from “H” level to “L” level, if A is at “H” level, it is changed to “L” level.

At the timing when the second chip enable delay signal CED2 changes from "H" level to "L" level, the row address enable signal RAE changes from "H" level to "L" level.

At the timing when the row address enable signal RAE changes from "H" level to "L" level, the decoder is not selected and the potential of the word line WL1 changes from "L" level to "H" level.

At the timing when the potential of the word line WL1 is changed from "L" level to "H" level, the node A is set to "0".
Displace to level.

Rewriting after reading is performed with bit line BLB = “L” while plate line PL = “H” while rewriting “0” data.

As shown in FIG. 26, when rewriting "1" data, the timing to deselect the selected word line WL1 after the potential of the plate line PL2 falls is determined by the fall of the external chip enable signal CEB. Is going.
By doing so, "1" data can be written until the start of the next read cycle or the start of the next write cycle, and sufficient "1" data can be written.

Similarly, at the time of data writing, the plate line PL
The timing to deselect the selected word line WL1 after the fall of the potential of 2 is performed at the fall of the external chip enable signal CEB.

In this embodiment, the same effects as in the sixth embodiment can be obtained.

[0238]

As is clear from the above embodiments, according to the present invention, a semiconductor memory having a ferroelectric memory device in which cell data can be sufficiently written and data retention characteristics are improved. A device can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a control circuit according to a first embodiment.

FIG. 2 is a configuration diagram of a semiconductor memory device according to the first to fourth embodiments.

FIG. 3 is a circuit diagram showing a configuration of a memory cell array according to the first to fourth embodiments.

FIG. 4 is a circuit diagram showing an address buffer according to the first to twelfth embodiments.

FIG. 5 is a timing chart illustrating the operation of the first embodiment.

FIG. 6 is a characteristic diagram showing a write voltage dependency of a read signal amount of the ferroelectric memory.

FIG. 7 is a configuration diagram of a control circuit according to a second embodiment.

FIG. 8 is a timing chart illustrating the operation of the second embodiment.

FIG. 9 is a configuration diagram of a control circuit according to a third embodiment.

FIG. 10 is a timing chart illustrating the operation of the third embodiment.

FIG. 11 is a configuration diagram of a control circuit according to a fourth embodiment.

FIG. 12 is a timing chart illustrating the operation of the fourth embodiment.

FIG. 13 is a configuration diagram of a semiconductor memory device according to fifth to eighth embodiments.

FIG. 14 is a circuit diagram showing a configuration of a memory cell array according to the fifth to eighth embodiments.

FIG. 15 is a configuration diagram of a control circuit according to a fifth embodiment.

FIG. 16 is a timing chart showing the operation of the fifth embodiment.

FIG. 17 is a configuration diagram of a control circuit according to a sixth embodiment.

FIG. 18 is a timing chart illustrating the operation of the sixth embodiment.

FIG. 19 is a configuration diagram of a control circuit according to a seventh embodiment.

FIG. 20 is a timing chart illustrating the operation of the seventh embodiment.

FIG. 21 is a configuration diagram of a control circuit according to an eighth embodiment.

FIG. 22 is a timing chart illustrating the operation of the eighth embodiment.

FIG. 23 is a timing chart showing the operation of the ninth embodiment.

FIG. 24 is a timing chart showing the operation of the tenth embodiment.

FIG. 25 is a timing chart showing the operation of the eleventh embodiment.

FIG. 26 is a timing chart showing the operation of the twelfth embodiment.

FIG. 27 is a circuit diagram showing a polarization direction and memory contents of a conventional ferroelectric memory.

FIG. 28 is a circuit diagram showing a memory cell array configuration of a conventional TC parallel unit serial connection type ferroelectric memory.

FIG. 29 is a configuration diagram of a control circuit of a conventional ferroelectric memory.

FIG. 30 is a timing chart showing the operation of a conventional ferroelectric memory.

[Explanation of symbols]

 1 to 9 1st to 9th delay circuits 10 to 20 1st to 11th inverters 21 to 26 1st to 6th NAND circuits 27, 65 1st NOR circuit 30 chip enable buffer 31 control circuit 32 address buffer 33 predecoder 34 I / O buffer 35 Block select line drive circuit 36 Word line drive circuit 37 Plate line drive circuit 38 Memory cell array 39 Sense amplifier / I / O circuit 40 Cell transistor 41 Capacitor 42 Memory cell 43 Memory cell group 44 Block select transistor 50 NOR circuit 51 Transfer Gate 52 First NAND circuit 53 Second NAND circuit 54-60 First through seventh inverters 66, 73 Second NOR circuit 67 Eighth inverter 70 Switch drive circuit 71 Plate line select transistor 72 Tenth delay Circuit 74 ninth inverter 75 11 delay circuit

Claims (12)

[Claims] 1. A plurality of cell transistors each including a cell transistor for selecting a memory cell, and a ferroelectric capacitor connected between a source and a drain of the cell transistor and connected in series to form a memory cell block A plurality of memory cells to be read and written; a word line connected to the gate of the cell transistor; a memory cell block selection transistor connected to one end of the plurality of memory cells; and a memory cell block selection transistor And a plate line connected to the other ends of the plurality of memory cells, and a word line controlled so that the cell transistors remain selected even after the block selection transistor is turned off. And a word line control circuit. 2. A plurality of cell transistors each comprising a cell transistor for selecting a memory cell, and a ferroelectric capacitor connected between the source and the drain of the cell transistor, and connected in series to form a memory cell block A plurality of memory cells to be read and written; a word line connected to the gate of the cell transistor; a block selection transistor connected to one end of the plurality of memory cells; and a memory cell connected to the block selection transistor. A bit line, a plate line selection transistor connected to the other end of the plurality of memory cells, a plate line connected to the plate line selection transistor, and an off state of the block selection transistor and the plate line selection transistor. To keep the cell transistor selected even after The semiconductor memory device characterized by having a word line control circuit for controlling the line. 3. The device according to claim 1, further comprising: a unit that sets the cell transistor to a selected state until the next read cycle or write cycle after the block select transistor is turned off. The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 1, further comprising means for setting said cell transistor in a selected state for a predetermined time after said block selection transistor is turned off. 5. The semiconductor memory device according to claim 4, further comprising a delay circuit as a means for setting said cell transistor to a selected state for a predetermined time after said block selection transistor is turned off. 6. The word line control circuit controls the control,
After the block select transistor is turned off,
3. The semiconductor memory device according to claim 1, wherein the operation is performed by keeping the word line in a selected state and keeping the cell transistor in a selected state until a chip enable signal next changes in level. 7. The word line control circuit controls the control,
After the block select transistor is turned off,
3. The semiconductor memory device according to claim 1, wherein the word line is kept selected and the cell transistor is kept selected until the next read cycle or write cycle. 8. The cell transistor according to claim 1, wherein said word line control circuit has a delay circuit, and said control is performed by keeping said word line in a selected state for a predetermined time by said delay circuit after said block selection transistor is turned off. 3. The method according to claim 1, wherein the step is performed by keeping the selected state.
The semiconductor memory device according to claim 1. 9. The cell transistor according to claim 1, wherein maintaining the cell transistor in a selected state comprises maintaining the cell transistor in an off state and non-shorting both ends of the ferroelectric capacitor. 2. The semiconductor memory device according to claim 1. 10. The semiconductor memory device according to claim 1, wherein said bit line precharge potential is a ground potential. 11. The semiconductor memory device according to claim 1, wherein said bit line precharge potential is a half of a power supply voltage. 12. The device according to claim 1, wherein the bit line precharge potential is a power supply voltage.
13. The semiconductor memory device according to claim 1.