JP2002169850A - Simulation method, storage medium, and method for manufacturing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the precision of circuit simulation. SOLUTION: When a model expression of a device is used to perform circuit simulation in a computer (S16), the model expression is made to include a part indicating a forward current component flowing to a pn junction part in the forward direction with voltage dependence and a part indicating a reverse current component flowing to the pn junction part in the reverse direction with voltage dependence. Therefore, the forward current component and the reverse current component can be individually adapted to the model expression, and thus both of forward characteristics and reverse characteristics of the pn junction part are obtained with a high precision, and the precision of circuit simulation performed by using the computer is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage medium storing design data or a program to be supplied to a computer (electronic computer) for designing a circuit to be formed on one semiconductor chip. The present invention relates to a simulation method for supporting circuit design, and a method for manufacturing a semiconductor integrated circuit. And technology that is effective for use in manufacturing.

[0002]

2. Description of the Related Art An LSI (semiconductor integrated circuit) design process includes a function design process, a logic design process, a device design process, and the like.
It includes a circuit design process, a layout design process, and the like. Among them, in the circuit design process, a basic logical unit used for a logic cell library and a transistor library obtained by device design are used, and these are appropriately combined. The circuit performance can be predicted by a circuit simulator. In addition, power fluctuation, temperature fluctuation,
More detailed verification, such as clock distribution, critical path margin, and fan-out margin, is verified based on the electrical circuit model.

[0003] As a circuit simulation program, SPICE developed by UCB (University of California, Berkeley) and whose source code is open to the public.
(Simulation Program with Integrated Circuit Empha
sis) is widely used. As a MOS transistor model, that is, a current source model, various models have been proposed with the progress of MOS transistor process technology. For example, BSIM3 (Berkele
y Short IGFET Model Version3).

The accuracy of a device model used in circuit simulation becomes very important in LSI design. For example, the BSIM3 is a physics-based MOS transistor model, and corresponds to the accuracy required for submicron design. In addition, geometrical and temperature effects are also taken into account, and its features include being able to be scaled and being suitable for statistical analysis. As compared with the old models (BSIM1 and BSIM2), it is possible to provide the microfabrication process with effective characteristics in terms of accuracy and parameter extraction.

An example of a document describing a circuit simulation method for a semiconductor device is disclosed in Japanese Patent Laid-Open No. 9-1.
No. 06416.

[0006]

When the impurity concentration at the junction between the source / drain and the well region increases, the leakage current at the junction increases, and the diode characteristics due to the pn junction are reduced by a standard diode model. Greatly deviated from This is because electrons in the conduction band and holes in the valence band recombine directly (this is referred to as “inter-band recombination”) due to impurities inside the semiconductor.
This phenomenon is called SRH (Shockley-Read-Hall) phenomenon.
The above “inter-band recombination” is described in August 1991.
"Basics of Semiconductor Devices (Pages 141 to 147)" issued by McGraw-Hill Publishing Co., Ltd. on March 20
It is described in.

For example, in an n-channel MOS transistor, as shown in FIG.
An n.sup. ⁺ region is formed in a well (well) region, and a source electrode or a drain electrode is formed on the n.sup. ⁺ region.
e Drain) structure, an LDD structure in which an n ⁻ region is provided next to the n ⁺ region as shown in FIG. 9B to prevent hot carriers, and an n ⁺ region as shown in FIG. 9C. And a Halo structure in which a short-channel effect is suppressed by providing ap ⁻ region having an impurity concentration higher than that of the p well region between the n ⁻ region and the p well region. Among them, in the SD structure and the LDD structure, the above-mentioned SRH phenomenon can be ignored because the impurity concentration of the well region in the pn junction is relatively low, but the impurity in the pn junction is different from the case of the Halo structure. When the concentration increases, the SRH phenomenon appears remarkably. Note that S
The RH phenomenon similarly occurs in the case of a p-channel MOS transistor.

FIG. 11 shows a characteristic curve and actual measurement points when fitting the standard parameters of the BSIM3 with emphasis on the forward current at the pn junction of the MOS transistor.

The abscissa represents a well-source voltage (bias voltage) Vbs (V), and the ordinate represents a well-source current Ibs.

In FIG. 11, solid lines, broken lines, and dashed lines are based on the standard parameters of the BSIM3, and are parameter-fitted under the conditions of temperatures T25, T85, and T125, respectively. On the other hand, ○ indicates an actual measurement point around the temperature T25, Δ indicates an actual measurement point around the temperature T85, and □ indicates an actual measurement point around the temperature T125.

As is apparent from FIG. 11, when the well-source voltage Vbs is positive and the forward bias is applied, BS
The characteristic curve based on the standard parameters of the IM3 substantially coincides with the actual measurement point, but in the case of a reverse bias in which the bias voltage is negative, the characteristic curve based on the standard parameters of the BSIM3 deviates greatly from the actual measurement point.

For example, at an actual measurement point, the current value differs according to the change in the reverse bias voltage value,
In the characteristic curve based on the SIM3 standard parameters, the current value in the case of reverse bias is saturated. In other words, even though the pn junction actually has voltage dependence in the case of reverse bias, it does not appear in the characteristic curve according to the standard parameters of the BSIM3.

On the other hand, as is clear from comparison between the case of the temperature T25 and the case of the temperature T125, the temperature dependence in the case of the reverse bias is larger in the characteristic curve based on the standard parameters of the BSIM3 than in the actual measurement point. .

In the characteristic curve based on the standard parameters of the BSIM3, the current value in the case of reverse bias is saturated, and the current level in the characteristic curve based on the standard parameters of the BSIM3 does not match the current level at the actual measurement point.

As described above, the pn of the MOS transistor
Focusing on the junction, and fitting the standard parameters of the BSIM3 with emphasis on the forward current of this pn junction, the BSI is reversed when the pn junction is reverse biased.
The characteristic curve based on the standard parameter of M3 greatly deviates from the actual measurement point. Actually, the standard parameters of the BSIM3 are fitted by giving priority to the temperature characteristics and the current characteristics in the reverse direction of the pn junction in the MOS transistor.
The forward characteristics of the pn junction of the transistor greatly deviate from the actual measurement points. As a result, in a place where the pn junction between the source / drain and the well region becomes forward-biased, a circuit design error cannot be determined by circuit simulation, or a circuit that positively utilizes the forward diode characteristics due to the pn junction. It has been confirmed by the present inventor that it becomes impossible to accurately analyze.

For example, in the case of a level shift circuit which shifts the input voltage level and outputs the level, this level shift circuit should be correctly coupled as shown in FIG. As shown, although a circuit design error has occurred, the circuit design error cannot be found in the circuit simulation.
Further, as shown in FIG. 10A, when the MOS transistor is represented by a three-terminal symbol, the connection state of the well region is not shown, and therefore, Vboost> Vc
Under the condition c, even if the high-potential-side power supply Vcc is coupled to the well region of the p-channel MOS transistor, it cannot be determined. p-channel type MO
The source electrode of the S transistor is connected to the high potential side power supply Vboos.
Under the condition of Vboost> Vcc, the well region of the p-channel MOS transistor must be connected to the high potential side power supply Vboost. If the well region of the p-channel MOS transistor is coupled to the high potential side power supply Vcc, the pn junction becomes forward biased and the output terminal O
The output voltage from the UT is clamped at about Vcc + 0.6 V, and the circuit does not operate normally. However, p
Focusing on the reverse current at the n-junction, the standard parameters of the BSIM3 are fitted, and when the circuit simulation is performed with the forward current being extremely small relative to the actually measured value, pn Since no forward current flows through the junction, for example, as shown in FIG.
Although the well region of the transistor is coupled to the high-potential-side power supply Vcc and cannot operate normally, the circuit may be erroneously recognized as operating normally.

An object of the present invention is to improve the accuracy of circuit simulation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0019]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the first means is that when a circuit simulation is performed by a computer using a model equation of a device, a portion indicating a forward current component flowing forward in a pn junction with voltage dependency, And a portion indicating a reverse current component flowing in the reverse direction with voltage dependency at the junction.

According to the first means, the model formula includes a portion indicating a forward current component flowing forward in a pn junction with a voltage dependency, and a reverse current component flowing in the pn junction with a voltage dependency. And a portion indicating a reverse current component flowing to the pn junction portion, since the forward current component and the reverse current component can be individually adapted to the model formula, Both of the reverse characteristics can be obtained with high accuracy, which achieves an improvement in the accuracy of the circuit simulation performed using the computer.

In addition, the model equation includes a first equation representing a bottom surface component of a saturation current at a pn junction and a second equation representing a side component of a saturation current at the pn junction. Equations (1) and (2) show that a portion indicating a forward current component flowing in the pn junction in the forward direction with voltage dependence and a reverse current component flowing in the pn junction in the reverse direction with voltage dependence are included in the expression. Parts shown.

At this time, in the portion indicating the reverse current component, a first calculation term indicating the temperature dependency of the reverse current component and a second calculation term indicating the voltage dependency of the reverse current component are provided. Term and a third operation term that enables a smoothing process to suppress a sudden change in the function.

The second means is that when a simulation program for circuit simulation is stored in a storage medium in a readable manner by a computer, the simulation program includes a forward current flowing in a pn junction in a forward direction with a voltage dependency. A circuit analysis process using a model expression in which the component and a reverse current component flowing in the reverse direction in the pn junction in a voltage-dependent manner are separately performed.

According to the second means, since the model formula expresses the forward current component and the backward current component separately, the model formula expresses the forward current component and the reverse current component separately. Can be individually adapted to the above model equation, so that both the forward characteristics and the backward characteristics of the pn junction can be obtained with high accuracy. This is the result of the circuit simulation performed using the computer. Achieve higher accuracy.

The third means is that, when a simulation program for circuit simulation is stored in a storage medium in a readable manner by a computer, the simulation program comprises: a bottom component of a current flowing through the pn junction; In each of the side components of the current flowing through the pn junction, a forward current component flowing forward in the pn junction with voltage dependency and a reverse current component flowing in the reverse direction with voltage dependency in the pn junction are divided. Circuit analysis using the model formula represented by the above.

According to the third means, when a simulation program for circuit simulation is executed by a computer, a model formula expressing the forward current component and the reverse current component separately is used. Thus, the forward current component and the reverse current component can be individually adapted to the model equation, and both the forward and reverse characteristics of the pn junction can be obtained with high accuracy. Therefore, by using the storage medium, highly accurate circuit simulation can be easily performed.

At this time, by setting a predetermined coefficient to 0, the above model equation is equivalent to another model equation in which the backward component of the pn junction is not considered.

As a fourth means, parameter fitting is performed for a model formula used for circuit simulation according to an actual device. Coefficients for the parameter fitting are stored in a computer-readable storage medium. provide. The coefficients include a first coefficient in the forward direction of the pn junction and a second coefficient in the reverse direction of the pn junction. The first coefficient includes a forward emission coefficient of the pn junction,
The second coefficient includes a reverse emission coefficient of the pn junction, a bottom component and a peripheral component of a voltage-dependent coefficient of a reverse current at the pn junction, and further includes the first coefficient and the peripheral component. The second coefficient includes a temperature-dependent coefficient of the current flowing through the pn junction.

According to the fourth means, the first coefficient includes the forward emission coefficient of the pn junction, and the second coefficient includes the reverse emission coefficient of the pn junction and the pn junction. By including the bottom component and the peripheral component of the voltage dependence coefficient of the reverse current at the junction, and further including the temperature dependence of the current flowing through the pn junction in the first and second coefficients, By using the storage medium, the model formula used for the simulator, which can accurately obtain both the forward characteristics and the backward characteristics of the pn junction, can be easily adapted to an actual device.

The fifth means includes a first step of designing a circuit, a second step of simulating the circuit designed in the first step by a computer, and a second step of
A third step of performing a layout design for an electric performance verified in a step simulation, wherein the second step includes a first step in a forward direction of a pn junction. And the coefficient of
The method includes a circuit analysis step using a model equation in which the second coefficient relating to the reverse direction of the pn junction is adapted, wherein the model equation includes a first equation indicating a bottom surface component of a current flowing through the pn junction. And a second expression indicating a side component of the current flowing through the pn junction, and the first expression and the second expression
Includes a portion indicating the forward component of the current and a portion indicating the reverse component of the current.

According to the fifth means, in the simulation in the second step, the first expression and the second expression include a portion indicating the forward current component and a portion indicating the reverse current component. Is included, p
Both the forward and reverse characteristics of the n-junction can be obtained with high accuracy, and this improves the accuracy of circuit simulation performed using the computer. This makes it possible to optimize the layout design performed based on the simulation result in the second step.

[0033]

FIG. 1 shows a manufacturing process of an LSI (semiconductor integrated circuit).

As shown in FIG. 1, the LSI manufacturing process includes a function design process (S10) and a logic design process (S1).
1), device design process (S12), element device prototype process (S13), parameter extraction process (S14), circuit design process (S15), circuit simulation process (S1)
6), a layout design process (S17), a mask fabrication process (S18), a chip fabrication process (S19), and the like.

In the function design process of step S10,
An LSI function specification is created based on a predetermined system specification, and details of the operation of the LSI are designed. At this time, the LSI internal logic is expressed as a combination of a logical resource and a signal flow by a predetermined function description language, a state transition diagram, or the like. The bit width and number of function registers in the logic block, the number and usage of control lines and bus lines,
The architecture of the LSI, such as the type and usage of the clock, is determined in this functional design. The function design data whose function is described in a predetermined function description language is checked by a function simulator or the like for design verification, and then passed to the next logic design step (S11).

In the logic design process of step S11,
Based on the function design data obtained in the function design step of step S10, the LSI is embodied to a level in units of logic gates. In the functional design of step S10, the design work was performed with an emphasis on the operation of the LSI. On the other hand, in this logic design, the focus was on the logic circuit design having a gate-to-gate connection relationship, and a predetermined structure was established. The design proceeds using a description language and logic diagrams. The basic gate used in the logic design can be appropriately selected from a logic cell library that has been compiled into a database through device design and circuit design. For example, a logic cell library contains simple basic gates as well as decode gates,
A cell having a scale of several to several tens gates, such as a flip-flop and a three-state driver, is prepared, and can be selectively used. In this logic design, a logic error can be eliminated by performing a delay simulation with a delay time predicted from the electrical performance of each gate.

In the device design process of step S12, the shape and electrical characteristics of the transistor to be used are designed based on the LSI manufacturing conditions. In this device design, the performance of the transistor is predicted by performing numerical experiments using various device simulators and process simulators. Usually, an appropriate transistor is selected from a menu of transistors according to the capacity of the production line and used, but if the performance is insufficient, a new element device is designed.

When a MOS transistor having a new structure is designed in the device design process in step S12, an element device is experimentally created in the next element device trial manufacturing process (S13).

The element devices prototyped in step S13 are registered in the transistor library after their electrical characteristics are confirmed. At this time, parameter extraction for circuit simulation is performed by a parameter extraction device described later (S14).

In the circuit design process of step S15,
The basic circuit or circuit cell design and the overall circuit design are included. In the former, a basic logic unit in a logic cell library and a transistor library obtained by device design are used, and they are appropriately combined. Then, the performance of the circuit is confirmed by a circuit simulation performed by a simulation system described later (S16). In the latter, more detailed verification such as power supply fluctuation, temperature fluctuation, clock distribution, margin of critical path, and margin of fan-out is performed based on an electric circuit model. Moreover, the logic design in step S11 and the step S17
The work is carried out in close relation to both processes of the layout design.

In the layout design process of step S17, an LSI mask pattern is designed for the electrical performance verified by the circuit simulation in step S16. The arrangement and wiring of the logic gates are performed using the connection information obtained by the logic design and the logic cell library obtained by the circuit design. At this time, the chip area is reduced according to the design rules. After the layout design, the electrical performance of the data is again verified by a logic simulator, a circuit simulator, or the like, if necessary. The data after the layout design is completed is passed to the subsequent mask manufacturing process.

In the mask manufacturing process of step S18, a mask is manufactured according to the mask pattern designed in the layout design process of step S17. Then, in the chip manufacturing process of step S19, chip manufacturing is performed using the mask manufactured in step S18.

Next, the parameter extracting step of step S14 will be described in detail.

FIG. 2 shows a parameter extraction device for performing the parameter extraction in step S14.

The parameter extracting device 20 shown in FIG.
Although not particularly limited, a measurement unit 21 for measuring the device under test 24, a control unit and an operation for obtaining a parameter 23 of a model corresponding to an element device based on the measurement data obtained by the measurement unit 21 And a part 22. The device under test 24 is a MOS transistor prototyped in the element device trial production process of step S13. The measuring unit 21 includes various measuring devices such as a voltage source for supplying a power supply voltage to the device under test 24 and an ammeter for measuring current. In the control unit and the calculation unit 22, by controlling the operation of the voltage source and the current source in the measurement unit 21 to measure the DUT 24,
The value of the parameter set is determined so that the parameter set matches the actual value measured by the measurement unit 21. Although this processing is not particularly limited, it is performed by a microcomputer included in the control unit and the arithmetic unit 22. Parameter 2 extracted by the control unit and the operation unit 22
3 is a computer-readable storage medium 2
5 and used in a simulation described later. Here, the storage medium 25 includes appropriate storage means such as a floppy (registered trademark) disk and a CD-ROM.

FIG. 3 shows a simulation system for performing the circuit simulation performed in step S16.

Although the simulation system 30 shown in FIG. 3 is not particularly limited, the parameter set information 3
1. An operation unit and a processing unit 34 for taking in circuit connection information 32 called a netlist and the like and input signal information 33 to perform a circuit simulation, and a circuit simulation program executed by the operation unit and the processing unit 34 A storage medium 35 for storing the (simulator) so as to be readable by the arithmetic unit and the processing unit 34, and an output unit 36 for outputting a processing result (output signal or the like) of the arithmetic unit and the processing unit 34. Comprising. The parameter set information 31 is a parameter extracted by the parameter extracting device 20 shown in FIG. 2 and stored in the storage medium 25. The storage medium 35,
Although not particularly limited, a hard disk drive or a CD-RO
It is an appropriate storage means such as M. The arithmetic unit and the processing unit 34 include, but are not particularly limited to, a microcomputer and a RAM (random access memory). After the simulator stored in the storage medium 35 is loaded into the RAM, and executed by the microcomputer, a circuit simulation can be performed.

FIG. 4 shows a parameter set extracted by the parameter extracting device 20. The parameter set extracted by the parameter extraction device 20 is not particularly limited, but is basically a BSIM3v3.
A reverse SRH characteristic fitting parameter of a pn junction in a MOS transistor is added to the parameter of No. 1. That is, as a parameter of the BSIM3v3.1, a forward current N value (emission coefficient) N
j, bottom component Js of saturation current, peripheral component Js of saturation current
sw, the temperature-dependent coefficient X _TI , and the reverse SRH characteristic fitting parameter of the pn junction:
N-value bottom component Njs, N-value peripheral component Njsw, saturation current bottom component Js1, and saturation current peripheral component Js1sw
Is newly added.

Further, in this example, the bottom component Kjs of the reverse voltage dependency coefficient and the peripheral component Kjssw of the reverse voltage dependency coefficient at the pn junction are added, so that the pn junction is added.
The joint can be represented more accurately.

Here, the “bottom component” means that the channel is
The component on the surface directly in contact with the well immediately below (or the impurity region having the Halo structure) indicates a component, and the “peripheral component” refers to the well (or Halo).
It refers to a component on a surface that is in contact with a region such as an element isolation region other than an impurity region forming a structure).

Next, the model formula of the pn junction in the MOS transistor will be described in detail. This model formula is coded in a machine language program executable by the simulation system 30 shown in FIG.

The model formula shown in FIG. 5 is to be compared with the model formula in the system according to the present invention.
This corresponds to “BSIM3v3.1 capmod2”.

The model equation showing the junction between the source electrode and the p-well is such that when the well-source voltage Vbs is smaller than 0.5 (Vbs <0.5), the well-source voltage Vbs is 0.5 Larger (Vbs> 0.5). The characteristic curve 51 indicates the relationship between the well-source voltage Vbs and the well-source current Ibs. If Vbs> 0.5, the tangent at Vbs = 0.5, that is, the derivative of the slope is taken and extended to obtain the well-source current Ids. A
s indicates the source area, and Ps indicates the source peripheral length. J
s (T) indicates the bottom component of the saturation current, and Jssw (T)
Indicates a saturation current side component, (T / Tnom) ^XTI indicates a temperature-dependent coefficient, and an exp term indicates an emission (current level). (T / Tnom) In ^XTI , T indicates a temperature to be analyzed, and Tnom indicates a reference temperature. When the well-source voltage Vbs is smaller than 0.5 (Vbs
Vbs included in the exp term in <0.5) functions as a proportional term, whereby the well-source current increases in proportion to the horizontal axis. GminVbs indicates an inverse resistance component obtained by multiplying the voltage by the inverse number Gmin of the resistance.

A model equation showing the junction between the drain electrode and the p-well is similarly shown, and the well-drain voltage Vb
d is smaller than 0.5 (Vbd <0.5) and when the well-drain voltage Vbd is larger than 0.5 (Vbd <0.5).
bd> 0.5). Note that the drain electrode and p
In the model formula indicating the junction with the well, the subscript "d" is used to indicate the drain electrode, thereby distinguishing it from the junction between the source electrode and the p-well.

FIG. 6 shows a model formula used in the system according to the present invention. The model formula shown in FIG. 6 is a modification of the standard model formula of “BSIM3v3.2 capmod3”, and the model formula shown in FIG. 6 is significantly different from the model formula shown in FIG.
Js0 indicating the forward direction at the pn junction (Js0sw)
And Js1 (Js1) indicating the opposite direction at the pn junction.
1sw) and BSIM3v
This is a point including a backward SRH characteristic fitting parameter (see FIG. 4) of the pn junction in addition to the parameters used as the standard model of 3.1.

A term Js0 (Js0sw) indicating a forward current component flowing in the pn junction in the forward direction with voltage dependency, and a term Js1 (Js1sw) indicating a reverse current component flowing in the pn junction in the reverse direction with voltage dependency. ) Are connected by an addition sign (+). That is, in this model equation, Js0 (Js0) indicating the forward current component is used.
sw) and Js1 (Js) indicating the reverse current component.
1sw) and the parameters shown in FIG. 4 are adapted to accurately analyze both the forward and reverse directions of the pn junction.

The reverse direction (Js) in the bottom component of the saturation current
1) is that the exp term is Nj + Njsf (Vbs),
It is slightly different from the exp term in the forward direction of the pn junction. This considers the temperature dependence of the reverse current at the pn junction so that it can take a different value from the forward direction.
For the same reason, the reverse direction (Js1s
In w), the exp term is Nj + Njsswf (Vbs). Here, the exp term corresponds to a first operation term in the present invention.

Further, in both equations of the bottom component of the saturation current and the peripheral component of the saturation current, the voltage dependence of the pn junction in the reverse direction is expressed.
The term (Vbs) exp has been added. This f (Vb
s) Of the terms of exp, the exp term has the value of V as it is when V is negative, and expresses the voltage dependency by exp (-kjsv). Is e
The xp term is ignored by being set to “1”. Here, the term of f (Vbs) exp corresponds to the second operation term in the present invention.

F (V) is a parameter for switching between the forward direction and the reverse direction, and is a smoothing coefficient. Based on this smoothing coefficient f (V), “δ” in the present model equation prevents a sudden change in the coefficient by performing smoothing for suppressing a sudden change in the function including the primary part. Thereby, the convergence of the circuit simulation can be stabilized. The above smoothing coefficient f
(V) is “0” when the substrate bias voltage (V) is in the forward direction and “1” when the substrate bias voltage (V) is in the reverse direction, as shown by the characteristic curve 61 in FIG.
It has the following characteristics. That is, f (V) = 1 when the horizontal axis V is a reverse bias, and f (V) having such a characteristic that f (V) = 0 when the horizontal axis V is a forward bias. By performing weighting, switching between the forward direction and the reverse direction is smoothly performed. Here, the term f (V) corresponds to the third operation term in the present invention.

In the model formula indicating the junction between the drain electrode and the p-well, when the well-drain voltage Vbd is smaller than 0.5 (Vbd <0.5),
When the drain-to-drain voltage Vbd is larger than 0.5 (Vbd
> 0.5), and a term is provided that takes into account the reverse direction of the pn junction as in the case of the junction between the source electrode and the p-well. In the model formula indicating the junction between the drain electrode and the p-well, “d” is used as a suffix to indicate the drain electrode.

If the backward SRH characteristic fitting parameters Js1 and Js1sw of the parameter set shown in FIG. 4 are set to “0”, the model equation shown in FIG. 6 becomes the model equation shown in FIG. Is equal to Therefore, when the reverse SRH characteristic of the pn junction is negligible, for example, the MOS transistor having the structure shown in FIGS.
In a simulation of a semiconductor integrated circuit constituted by transistors, the reverse SRH characteristic of the pn junction is often negligible. In such a case, the reverse SRH characteristic fitting parameter of the parameter set shown in FIG. Even if circuit simulation is performed with certain Js1 and Js1sw set to “0”, the simulation result will not be affected. That is, the backward SRH characteristic fitting parameter Js1,
If Js1sw is set to “0”, another model formula BS that does not include the backward SRH characteristic fitting parameter is used.
It becomes equivalent to the standard model of IM3v3.1.

FIG. 12 shows characteristic curves and actual measurement points when fitting the standard parameters of the BSIM3 with emphasis on the forward current of the pn junction of the MOS transistor in the proposed model shown in FIG. It is.

The horizontal axis represents the well-source voltage (bias voltage) Vbs (V), and the vertical axis represents the well-source current Ibs.

In FIG. 12, solid lines, broken lines, and dashed lines are based on the parameters of the proposed model shown in FIG. 6, and are fitted under the conditions of temperatures T25, T85, and T125, respectively. On the other hand, ○ indicates an actual measurement point around the temperature T25, Δ indicates an actual measurement point around the temperature T85, and □ indicates an actual measurement point around the temperature T125.

When the parameters of the proposed model shown in FIG. 6 are used, both in the case of the forward bias where the well-source voltage Vbs is positive and in the case of the reverse bias where the bias voltage is negative, The characteristic curve based on the parameters of the proposed model and the actual measurement points generally match. As is clear from the comparison with FIG. 11, the forward component and the backward component of the pn junction are individually adapted to the model equation, and particularly, the reverse characteristics of the pn junction are significantly improved. .

According to the above example, the following functions and effects can be obtained.

(1) The model equation shown in FIG.
Since the junction includes a portion indicating a forward current component flowing forward in a voltage-dependent manner and the pn junction includes a portion indicating a reverse current component flowing in the reverse direction in a voltage-dependent manner. The current component and the reverse current component can be individually adapted to the model formula, and p
Since both the forward and reverse characteristics of the n-junction can be obtained with high accuracy, the accuracy of circuit simulation performed using a computer can be improved. For example, in the case where BSIM3 standard parameters are used, BSIM3 is focused on the reverse current of the pn junction.
In the case where the standard parameter of No. 3 is fitted and the circuit simulation is performed with the forward current being extremely smaller than the actually measured value, the forward current does not flow through the pn junction as far as the simulation results are seen. For example, as shown in FIG. 10B, although the well region of the p-channel MOS transistor is coupled to the high-potential-side power supply Vcc and cannot operate normally,
The circuit may be erroneously recognized as operating normally. In contrast, when circuit simulation is performed using the model formula shown in FIG. 6, both the forward and reverse characteristics of the pn junction can be obtained with high accuracy. In the case shown in (1), it can be understood from the circuit simulation result that an undesired forward current flows in the pn junction.

(2) As described above, since both the forward characteristics and the reverse characteristics of the pn junction can be accurately obtained, a circuit design utilizing the forward characteristics of the pn junction is performed. In the circuit simulation for the case
Since the forward characteristics of the n-junction can be obtained with high accuracy, it is possible to facilitate the circuit design utilizing the forward characteristics of the pn-junction.

(3) In order to achieve both high speed and low power consumption of the semiconductor integrated circuit device, a variable threshold MO
MOS transistors using SFETs and having a low threshold voltage for MOS transistors that operate at high speed and do not require high-speed operation
In order to increase the threshold voltage of the transistor and to control such different threshold voltages, a dedicated circuit for controlling the well potential is provided to the well region where the MOS transistor is formed in addition to the base region of the gate array. In some cases, a control circuit for setting a bias voltage is provided.
The level of the bias voltage is controlled by the control circuit, and in such a circuit, the pn junction of the MOS transistor may be biased not only in the reverse direction but also in the forward direction. , And both the forward and reverse characteristics of the pn junction can be obtained with high accuracy, thereby improving the accuracy of circuit simulation performed using a computer.

Next, another model formula will be described.

The model formula shown in FIG. 7 is to be compared with the model formula in the system according to the present invention.
This corresponds to “BSIM3v3.2 capmod3”.
Some of the model formulas are different, and some of the parameters are different from “BSIM3v3.1 capmod2”. For example, a model equation indicating a junction between a source electrode and p-well is such that the well-source voltage Vbs is Vj
sm (Vbs <Vjsm),
When the source-to-source voltage Vbs is higher than Vjsm (Vbs
> Vjsm). Well-source voltage V
The characteristic curve 71 shows the relationship between the current bs and the well-source current Ibs. When Vbs> Vjsm,
By taking the tangent at Vbs = Vjsm, that is, taking the derivative of the slope and extending it, the well-source current Ids is obtained. In this case, a well-source current Ids is obtained by taking a tangent at Vbs = Vjsm, that is, taking the derivative of the slope and extending it.

FIG. 8 shows another model formula used in the system according to the present invention. The model formula shown in FIG. 8 is “BSIM3v3.2 capmode”
3 is a modification of the standard model formula shown in FIG. 8, and the model formula shown in FIG. 8 is largely different from the model formula shown in FIG. 7 in that Js0 (J
s0sw) and J indicating the opposite direction at the pn junction.
s1 (Js1sw) is separated from the term, and B
This is a point including the backward SRH characteristic fitting parameter (see FIG. 4) of the pn junction in addition to the parameters used as the standard model of SIM3v3.1.
This is the same as the case of the model formula shown in FIG. 6, and the same operation and effect as the case where the model formula shown in FIG. 6 is adopted can be obtained.

In FIG. 8, the term Js0 (Js0sw) indicating the forward direction at the pn junction and the term Js1 (Js1sw) indicating the reverse direction at the pn junction are connected by an addition sign (+). . That is, in this model equation, Js0 (Js0) indicating the forward direction at the pn junction is used.
0sw) and Js indicating the opposite direction at the pn junction.
By fitting the parameters shown in FIG. 4 to the term 1 (Js1sw), it is possible to accurately analyze both the forward direction and the reverse direction of the pn junction.

In the backward direction (Js1) of the bottom component of the saturation current, the exp term is Nj + Njsf (Vbs), which is slightly different from the exp term in the forward direction of the pn junction. This considers the temperature dependence of the reverse current at the pn junction so that it can take a different value from the forward direction. For the same reason, the opposite direction (J
s1sw) is obtained when the exp term is Nj + Njsswf (Vb
s).

Further, in both equations of the bottom component of the saturation current and the peripheral component of the saturation current, the voltage dependence of the pn junction in the reverse direction is expressed.
The term (Vbs) exp has been added. This f (Vb
s) In the term of exp, in the exp term, when V is negative, the value of V is left as it is, and by exp (-kjsv), the voltage dependency is expressed. When V is positive, ,
The exp term is ignored by being set to “1”. Ex above
The term p corresponds to the second operation term in the present invention.

Here, f (V) is a parameter for switching between the forward direction and the reverse direction, and is a smoothing coefficient. Based on this smoothing coefficient f (V), “δ” in the present model equation prevents a sudden change in the coefficient by performing smoothing for suppressing a sudden change in the function including the primary part. Thereby, the convergence of the circuit simulation can be stabilized. As shown by the characteristic curve 81 in FIG. 8, the smoothing coefficient f (V) becomes “0” when the substrate bias voltage (V) is in the forward direction, and becomes “0” when the substrate bias voltage (V) is in the reverse direction. It has a characteristic that becomes “1”. That is, the horizontal axis V
Is a reverse bias, f (V) = 1, and the horizontal axis V
Is weighted with a parameter f (V) having such a characteristic that f (V) = 0 when is a forward bias, so that switching between the forward direction and the reverse direction is smoothly performed.

In the model formula indicating the junction between the drain electrode and the p-well, the well-drain voltage Vbd is smaller than Vjsm (Vbd <Vjsm) and the well-drain voltage Vbd is larger than Vjsm (Vbd). > Vjsm), and a term is provided in which the reverse direction of the pn junction is considered as in the case of the junction between the source electrode and the p-well. In the model formula indicating the junction between the drain electrode and the p-well, “d” is used as a suffix to indicate the drain electrode.

Although the invention made by the present inventor has been specifically described above, the present invention is not limited to this, and it goes without saying that various modifications can be made without departing from the gist of the invention.

For example, the step configuration in the flowchart of the manufacturing method shown in FIG. 1, the block configuration of the parameter extracting device shown in FIG. 2, and the block configuration of the simulation system shown in FIG. 3 are appropriately modified. Can be implemented.

In the above model equation, the smoothing coefficient f (V) only needs to be invalid when the substrate bias voltage (V) is in the forward direction. Can be substituted.

[0081]

(Equation 1)

[0082]

(Equation 2)

In the above description, the invention made mainly by the present inventor is a MOS field of application in which the background was used.
The case where the present invention is applied to a system that handles a diode model of a transistor has been described. However, the present invention is not limited to this. For example, a bipolar transistor, a liquid crystal, and a design having a pn junction such as a printed circuit board are widely used. Can be applied.

The present invention can be applied to the condition that at least model parameters are handled.

[0085]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the model formula, a portion indicating a forward current component flowing forward in the pn junction with voltage dependency, and a portion indicating a reverse current component flowing in the pn junction in the reverse direction with voltage dependency. Is included, the forward current component and the reverse current component can be individually adapted to the model formula, so that both the forward characteristics and the reverse characteristics of the pn junction can be accurately obtained. Accordingly, the accuracy of circuit simulation performed using a computer can be improved.
In addition, since the characteristics at the time of reverse bias in addition to the characteristics at the time of forward bias can be analyzed with high accuracy, a circuit simulation mistake that causes a forward bias between the source or drain electrode and the well region can be performed. Can be easily found, and the time required for circuit check can be reduced. Further, since both the forward characteristic and the reverse characteristic of the pn junction can be accurately obtained, the leakage current can be accurately analyzed in the design of the semiconductor integrated circuit, so that the power consumption of the semiconductor integrated circuit can be accurately calculated. Can be estimated.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an example of a method for manufacturing a semiconductor integrated circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a parameter extracting device used in a parameter extracting step in the flowchart shown in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration example of a simulation system used in the circuit simulation in the flowchart illustrated in FIG. 1;

FIG. 4 is an explanatory diagram of an example of a parameter set extracted in the parameter extraction step.

FIG. 5 is an explanatory diagram of a standard model formula in “BSIM3v3.1 capmod2”.

FIG. 6 is an explanatory diagram of a model equation of a pn junction used in the simulation method according to the present invention.

FIG. 7 is an explanatory diagram of a standard model formula in “BSIM3v3.2 capmod3”.

FIG. 8 is an explanatory diagram of a model equation of a pn junction used in the simulation method according to the present invention.

FIG. 9 is a diagram illustrating the structure of a MOS transistor.

FIG. 10 is an explanatory diagram of a design error of a circuit to be simulated by the simulation system.

FIG. 11 is an explanatory diagram of a characteristic curve and an actual measurement point when fitting a standard parameter of the BSIM3 with emphasis on a forward current of a pn junction of a MOS transistor.

FIG. 12 is an explanatory diagram of a characteristic curve and an actual measurement point when the parameter set shown in FIG. 4 is fitted.

[Explanation of symbols]

 Reference Signs List 20 parameter extraction device 21 measurement unit 22 control unit and calculation unit 23 parameter 24 DUT 25 storage medium 30 simulation system 31 parameter set information 32 circuit connection information 33 input signal information 34 calculation unit and processing unit 35 storage medium 36 output unit

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Kazunori Onozawa 5-2-1, Josuihoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5B046 AA08 BA03 JA04 5F040 DA00 DA30

Claims (11)

[Claims] 1. A simulation method for performing a circuit simulation by a computer using a model equation of a device, wherein the model equation includes a portion indicating a forward current component flowing forward in a pn junction with voltage dependency. And a portion indicating a reverse current component flowing in the reverse direction with voltage dependency in the pn junction. 2. A simulation method for performing a simulation by a computer using a model equation of a device, wherein the model equation includes a first equation indicating a bottom surface component of a current flowing through a pn junction, and the pn junction. And a second equation representing a side component of a current flowing through the pn junction. The first equation and the second equation each include a portion indicating a forward current component flowing forward in a pn junction with voltage dependency. And a portion showing a reverse current component flowing in the reverse direction with voltage dependency in the pn junction. 3. The simulation method according to claim 1, wherein the portion indicating the reverse current component includes a calculation term indicating the temperature dependence of the reverse current component. 4. A first operation term indicating a temperature dependence of the reverse current component and a second operation term indicating a voltage dependence of the reverse current component are provided in a portion indicating the reverse current component. 3. The simulation method according to claim 1, further comprising: 5. A first operation term indicating a temperature dependence coefficient of the reverse current component, and a second operation term indicating a voltage dependence of the reverse current component, in a portion indicating the reverse current component. The simulation method according to claim 1, further comprising: a third operation term that enables a smoothing process for suppressing a sudden change in a function. 6. A storage medium in which a simulation program for circuit simulation is stored readable by a computer, the simulation program comprising: a forward current component flowing forward in a pn junction with voltage dependency; A storage medium for executing a circuit analysis process using a model expression in which a reverse current component flowing in the reverse direction with voltage dependency in the pn junction is separately expressed. 7. A storage medium in which a simulation program for circuit simulation is stored so as to be readable by a computer, the simulation program comprising: a bottom component of a current flowing through a pn junction; and a current flowing through the pn junction. In each of the side surface components, a forward current component flowing forward in the pn junction with voltage dependency,
A storage medium for executing a circuit analysis using a model expression in which a reverse current component flowing in the reverse direction with voltage dependency in an n-junction part is divided. 8. A storage medium in which a simulation program for circuit simulation is stored readable by a computer, the simulation program comprising: a bottom component of a current flowing through a pn junction; and a current flowing through the pn junction. In each of the side surface components, a forward current component flowing forward in the pn junction with voltage dependency,
The circuit analysis is performed using a model expression in which a reverse current component flowing in the reverse direction with voltage dependency in the n-junction portion is separately expressed. In the model expression, a predetermined coefficient is set to 0. Thus, the storage medium is equivalent to another model formula in which the reverse current component of the pn junction is not considered. 9. A storage medium in which coefficients for specifying a model formula used for circuit simulation according to the characteristics of an actual device are stored in a computer-readable manner, wherein the coefficients include a pn junction A first coefficient related to the forward direction of the pn junction and a second coefficient related to the reverse direction of the pn junction. The first coefficient includes a forward emission coefficient of the pn junction. Include the reverse emission coefficient of the pn junction, the bottom component and the peripheral component of the voltage-dependent coefficient of the reverse current at the pn junction, and the first coefficient and the second coefficient. The coefficients include the above p
A storage medium comprising a temperature-dependent coefficient of a current flowing through an n-junction. 10. A forward current component flowing in the pn junction in a forward direction with a voltage dependency, in each of a bottom component of the current flowing in the pn junction and a side component of the current flowing in the pn junction, A storage medium in which a coefficient for adapting a model expression in which a reverse current component flowing in the reverse direction flowing in the pn junction in a reverse direction with voltage dependency to an actual device is stored in a computer-readable manner. , The coefficient includes a first coefficient relating to the forward direction of the pn junction, and a second coefficient relating to the reverse direction of the pn junction. The first coefficient includes a forward coefficient of the pn junction. The second coefficient includes a reverse emission coefficient of the pn junction and a bottom component and a peripheral component of a voltage-dependent coefficient of a reverse current at the pn junction. And the first coefficient and the second coefficient include the p
A storage medium comprising a temperature-dependent coefficient of a current flowing through an n-junction. 11. A first step of designing a circuit, a second step of simulating the circuit designed in the first step by a computer, and a method in which electrical performance is verified in the simulation of the second step. A third step of performing a layout design, wherein the second step includes a first coefficient relating to a forward direction of the pn junction and a second coefficient relating to a reverse direction of the pn junction. And a circuit analysis step using a model equation in which the coefficient of 2 is adapted, wherein the model equation includes a first equation indicating the bottom surface component of the current flowing through the pn junction, and the current flowing through the pn junction. And a second expression representing the forward component of the current, and a second expression representing the backward component of the current, in the first expression and the second expression. The method of manufacturing a semiconductor integrated circuit, characterized in that it contains.