JP2002169722A - Plural-memory type module using single memory bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a module which uses a module single memory bus and has memories of plural types. SOLUTION: A plural-memory type module which uses the single memory bus is provided. The module includes plural memory devices including at least one 1st memory device of a 1st memory type and at least one 2nd memory device of a 2nd memory type and the minimum configuration of the plural memory devices includes one memory device of the 1st memory type and one or two memory devices of the 2nd memory type. The module includes the single memory bus which is connected to the plural memory devices and the single memory bus links a processor to the plural memory devices.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to memories, and more particularly, to the modularity of memories.

[0002]

2. Description of the Related Art The modularity of memory has given the computer industry the ability to promote sales, adapt the memory to the needs of the end user, enhance the performance of the memory, prevent obsolescence, counter market changes, and It has provided many benefits, including reduced inventory risk for memory devices. These benefits were significant due to the rapid change in memory standards, die improvement, packaging, manufacturing process technology, memory price and availability instability, and other benefits.

[0003] Typically, the computer industry has developed dual in-line memory modules (DIMs) (DIMs).
M) and single in-line memory modules (shims) (SIMM) as standard form factors for memory modules. DIMM or SIMM
Is a printed circuit board on which up to 18 dynamic random access memory (DRAM) devices in a thin small outline plastic (TSOP) or small outline J bend (SOJ) package, and a serial Small serial EPROM (electrically erasable and writable ROM) used in presence detect mode
(EEPROM). Other memory devices, such as flash memory and static RAM, specifically use DIMM and SIMM form factors. A common feature of these modules is that they have a single memory type, unlike serial EEPROMs.

[0004] However, these existing memory module solutions are not widely used by embedded system applications. Because embedded systems typically use more than one memory type, use moderation to reduce the amount of bits per memory type, and require finer granularity than existing memory modules provide. It is. As used herein, the term "granularity" is defined as the minimum number of memory devices that a memory module can have while maintaining cost efficiency.

In a conventional memory module, the granularity is typically four devices with a given memory type. If a lower level of granularity is desired, computer manufacturers can solder memory devices to the motherboard rather than using modules that require cost adders such as connectors, printed circuit boards, assembly and testing. Is also cost effective. However, soldering the memory device to the motherboard will bring the benefits that modularity will offer, such as the ability to replace, upgrade, expand, and test memory devices independently of the overall system. You have to sacrifice.

Further, if multiple memory types are required in the system, the minimum granularity is 1
It may fit one memory type but not the other. For example, if the system memory requires four DRAMs, two parallel flash memory devices, and one serial flash memory device, the module can be used for DRAM, but the parallel flash device and Serial flash devices are still soldered to the motherboard. This solution is inadequate because the benefits of modularity are not provided to parallel and serial flash memory devices. In addition, separate memory buses must be used for DRAM modules and memory types soldered to the motherboard,
This further complicates the system design.

[0007]

Therefore, there is a need for a multiple memory type module using a single (single) memory bus. Multiple memory type modules and single memory buses should provide greater granularity and be cost effective for use in embedded systems. The present invention addresses such a need.

[0008]

SUMMARY OF THE INVENTION The present invention provides a multiple memory module using a single memory bus. The module includes a plurality of memory devices including at least one first memory device of a first memory type and at least one second memory device of a second memory type, wherein the minimum configuration of the plurality of memory devices is , One memory device of the first memory type and one or two memory devices of the second memory type. The module also includes a single memory bus coupled to the plurality of memory devices, the single memory bus communicating the processor with the plurality of memory devices. A module according to the present invention has a minimal configuration with one or two memory devices per type of memory, depending on the type of memory. The module has the ability to upgrade and expand each type of memory every 1-2 memory devices. Modules can incorporate the entire system memory, which includes an architecture that considers the entire system memory as a unit from the perspective of an embedded system designer. The modules of the present invention provide different memory architectures, data bus widths,
It is effectively used with memory device packages, module form factors, memory vendors, memory performance standards, and connectors or connections to motherboards.
The module may also incorporate a serial data flash memory device or other memory device.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides a multiple memory type module using a single memory bus. The following description is presented to enable one of ordinary skill in the art to make and use the invention.
And provided in connection with the patent application and its requirements. It will be apparent to those skilled in the art that various modifications can be made to the preferred embodiment. The generic principles herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the embodiments illustrated, but is to be accorded the widest scope consistent with the principles and features described herein.

A multiple memory type module according to the present invention comprises:
It has one or more memory types and uses a single memory bus to communicate with the processor. A single memory bus facilitates the configuration of a multiple memory type module with one or two memory devices per memory type, depending on the type of memory, as a minimum working configuration. This increases granularity while maintaining cost efficiency.

The features of the present invention will now be described in more detail. Please refer to FIGS. 1-4 with the following discussion. FIGS. 1A and 1B show two examples of a conventional system memory configuration. System memory is often composed of a mixture of different types of memory to meet different requirements. For example, FIG.
As shown in FIG. 1A, the system memory 100A can include two dynamic random access memory (DRAM) devices 120, one parallel flash memory device 122, and a serial data flash memory device 106. These memory devices are soldered to the motherboard because the number of devices per type of memory is below the level of granularity required for cost effective memory module solutions. However, this technique does not provide modularity. And this limits the ability to upgrade, expand or replace the system.

A conventional way of providing modularity is
Multiple single in-line memory modules (SI
MM). For example, as shown in FIG. 1B, four DRAMs 102
The four parallel flash memory devices 104 are provided on the SIMM
0 is provided. DRAM SIMM 108 and flash SIMM 110 are selected to be scalable. Conventionally, a serial data flash memory device, such as data flash memory device 10
6 has no way to provide modularity. DR
The AM / SIMM 108 has a 32-bit data bus 112 for communicating the SIMM to the processor. The flash SIMM 110 has a 32-bit data bus 114 for communicating with a processor. Serial data flash memory device 160 is soldered to the motherboard and communicates with the processor via copper traces 116. Thus, this conventional configuration requires two independent memory buses 112 and 114. Further, SIMMs 108 and 1
Additional costs are required for each of the 10 (requires a cost adder) and a connector is required. Additional costs
Includes module printed circuit board, assembly, test costs, and other costs associated with having modules.
Therefore, in order to maintain cost efficiency, the DRAM SIMM
8 and four flash memory devices 104 for the flash SIMM 110 are required. This type of configuration for system memory 100B does not provide the necessary granularity or cost efficiency required for many embedded systems.

FIGS. 2A and 2B show two examples of configurations of a multiple memory type module according to the present invention. Multiple memory type module 2 according to the present invention
00 uses a single memory bus 208 for multiple types of memories. As shown in FIG. 2A, the same number and type of memory devices as the memory device shown in FIG.
Has two DRAMs 210, one parallel flash memory device 212, and one serial data flash device 206, and a single memory bus 208 for these memory devices. Module 200 can be a complete system memory. As shown in FIG. 2B, with respect to memory devices of the same number and of the same type as the memory devices shown in FIG.
2, 4 parallel flash memory devices 204,
And one serial data flash memory device 206, and a single memory bus 208 for these memory devices.

FIGS. 3 and 4 show a preferred embodiment of a single memory bus for a multiple memory type module according to the present invention. FIG. 3 shows a structure (architecture) of a single memory bus according to the present invention. The single memory bus 60 is for communicating data to a memory device in the system memory 70 and performing programming access. In a preferred embodiment, the system memory 70 comprises a multi-memory module 20 according to the present invention.
0. The single memory bus was released on July 18, 1997.
U.S. Patent No. 6,062, filed on May 23, 2000, and assigned to the assignee of the present application.
No. 7,593. The applicant of the present application incorporates this patent by reference. As used herein, the term “single memory bus” is used interchangeably with “universal memory bus” used in US Pat. No. 6,067,593.

FIG. 4 shows a channel structure of a single memory bus according to the present invention. A single memory bus 60 communicates boot data to power the host system and then a primary channel 62 for communicating normal data.
An identification channel 64 for communicating data indicative of the device configuration of the system memory 70, and an expansion channel 66 for performing programming and data access to memory devices that are later added to the system memory 70.
And a programming channel 68 for providing programming access to each programmable memory device in the system memory 70.

Main channels 62 generally include power, address, data, and central processing unit (CPU) 60.
And a control line necessary to establish a communication link between the system and the system memory 70.

The identification channel 64 generally stores data and device configurations of the system memory 70 on the host CP.
It comprises a control line for communicating the identification data indicated by U50.

The extension channel 66 generally consists of additional data, address and / or programming lines. The programming lines can be selectively activated to bring address, data or programming signals to the next applied memory device.

The programming channel 68 generally comprises
Consists of lines that provide the programming and control signals necessary to program serial or parallel programmable memory devices in system memory. In a preferred embodiment, the programming channel includes a dedicated sub-channel 68A that operates only during a programming operation, and a dual function sub-channel that communicates programming signals during a programming operation and provides address or control signals during a normal data transfer operation. Channel 68B.

A module 20 having multiple types of memories using a single memory bus 208 according to the present invention.
0 provides several advantages over conventional memory modules. One advantage is that the granularity is finer. The minimum configuration for module 200 requires less memory devices than conventional modules. With a conventional SIMM of one memory type, four devices are used per memory type, but the module 200 has a minimum of one or two devices per memory type, depending on the memory type. be able to. In this manner, the benefits of memory modularity, which were not cost-effective in conventional memories, are provided by the single memory bus 208, which reduces design effort.

For example, FIG.
2 shows a minimum configuration for a multiple memory type module using a single memory bus. For a memory device of the same type as shown in FIG. 1A, a module 200 according to the invention comprises two DRAMs.
502, one parallel flash memory device 50
4, and a minimal configuration consisting of one serial data flash memory device 506. This provides a much finer granularity than the conventional memory 100A and provides cost efficiency.

The multiple memory type module 200 using the single memory bus 208 shown in FIG. 2B also has the advantage of cost savings over the conventional memory module 100B. For example, assume that (a) the cost of each memory device is $ 3, (b) the cost of each cost adder is $ 4, and (c) the cost of each connector is $ 1. For the type and number of devices shown in FIG. 1B, the cost of a conventional module would be $ 37 ($ 27 for nine memory devices, two SIs).
(The cost adder for MM is $ 8 for two SIMM connectors and $ 2 for two SIMM connectors). On the other hand, in the case of the module 200 according to the invention, the cost is $ 32 ($ 27 for 9 memory devices, $ 4 for one cost adder, $ 1 for one connector), at least a significant 14%. Cost savings.

Another advantage is that designs with multiple memory type modules 200 using a single memory bus 208
The required pins and copper traces are
Less than designs with 0A and 100B. This reduces cost, design effort, and use of valuable engineering resources. For example, if a 32-bit DRAM SIMM 108 (FIG. 1B) has 72 pins, a 32-bit flash SIMM 110 has 80 pins, and a serial flash package has 28 pins. For example, the total number of pins in this solution is 180. In a preferred embodiment, module 200 is implemented in a small outline dual in-line module (SODIM) (SODIMM) form factor having 144 pins. Thus, module 200
As a result, the number of pins is reduced by 20%. Even when the system designer solders the memory device to the motherboard, the module shown in FIG.
The total number of pins is 188. Module 200 has fewer memory requirements and reduces the number of pins by 23% compared to soldering to the motherboard.

Another advantage is that the multiple memory module 200 using the single memory bus 208 can be a complete system memory and can be a building block of the overall system design. This minimizes the design effort of the system designer, and also allows the entire system memory to be tested as a single component. Module 200 according to the present invention, unlike conventional memory, incorporates the architecture of system memory, for example, bank or interleave scheme, mixed data bus width, and chip select configuration.

The multiple memory type module 200 using the single memory bus 208 can also be extended from the minimum configuration shown in FIG. This is done by increasing the number of unused memory pads in one or two devices simultaneously until the minimum configuration of the conventional module 100B (FIG. 1B). This has the advantage that the serial data flash memory device 206 can be located in the module 200 and that risk is eliminated from the motherboard.

Although the present invention has been disclosed with respect to the above memory types, device packages, connectors, architectures, and interface bus widths, those skilled in the art
It will be appreciated that other types of memories, packages, connectors and bus widths may be used without departing from the spirit and scope of the present invention.

For example, memory module 200 may implement any type of memory architecture including, but not limited to, bank or interleave schemes, mixed data bus widths, and chip select configurations. Module 200 is DIMM, SIM
It may have different forms, including but not limited to M, SODIMM, multi-chip module and ball grid array (BGA) packages. Module 200
Is a TSOP, small outline integrated circuit (SOI
C), may have different foams, including but not limited to, BGA, fine pitch ball grid array (FBGA), and small outline J bend (SOJ). Module 200 is a standard DIMM, SIM
Various methods of coupling to the system board may be used, including but not limited to M and SODIMM connectors. Module 20 may have different data bus widths, for example, 16 bits, 32 bits, 64 bits, 72 bits, or a combination of different bus widths.

A multiple memory module using a single memory bus has been disclosed. A module according to the invention uses a single memory bus for multiple types of memory. The modules of the present invention increase granularity and save more cost than conventional memories. The module according to the invention has a minimum configuration with one or two memory devices per memory type, depending on the type of memory. The module has the ability to upgrade and expand each type of memory every 1-2 memory devices. Modules can incorporate the entire system memory, which includes an architecture that considers the entire system memory as a unit from the perspective of an embedded system designer. The modules of the present invention are designed to meet customer needs for embedded systems with different memory architectures, data bus widths, memory device packages, module form factors, memory vendors,
Used effectively with memory performance standards, connectors or connections to the motherboard. The module may also incorporate a serial data flash memory device or other memory device.

While the present invention has been described in accordance with the embodiments shown, those skilled in the art will readily appreciate that these embodiments can be modified within the spirit and scope of the invention. . Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the scope and spirit of the claims.

[0030]

As described above, the present invention provides a multiple memory type module using a single memory bus that provides greater granularity and is cost effective in embedded systems. be able to.

[Brief description of the drawings]

1A and 1B show two examples of a conventional system memory configuration.

2A and 2B show two examples of a configuration of a multiple memory module using a single memory bus according to the present invention.

FIG. 3 shows the architecture of a single memory bus according to the invention.

FIG. 4 shows a channel structure of a single memory bus according to the present invention.

[Explanation of symbols]

50: CPU, 70: System memory, 102, 12
0, 202, 210 ... RAM, 104, 122, 20
4, 212: flash, 106, 206: data flash, 200: multiple memory type module.

Claims (37)

[Claims] 1. A method comprising: at least one first memory device of a first memory type; and at least one second memory device of a second memory type, wherein the minimum configuration is the first memory type. And a plurality of memory devices comprising one or two memory devices of a second memory type; a single memory device coupled to the plurality of memory devices for providing communication between the processor and the plurality of memory devices. A memory module including a memory bus. 2. The module according to claim 1, wherein neither the first memory device nor the second memory device stores identification data indicating a device configuration of the memory module. 3. The memory device of claim 2, wherein the plurality of memory devices further include at least one third memory device of a third memory type, wherein the third memory device stores identification data indicating a device configuration of the memory module. A module according to. A single channel for communicating operating system data from the plurality of memory devices to the processor; an identification channel for communicating identification data from the plurality of memory devices to the processor; A programming channel for providing programming and control signals necessary to program at least one of the devices.
A module according to. 5. A programming channel, comprising: a dedicated sub-channel for communicating programming signals to a plurality of memory devices when the single memory bus is in a programming mode; and a data transfer signal when the single memory bus is in a data transfer mode. 5. The module of claim 4, further comprising: one or more bi-functional sub-channel lines configured to communicate to a plurality of memory devices. 6. The module of claim 4, wherein the single memory bus further includes an extension channel for communicating data between the additional memory device and the processor. 7. The module of claim 1, wherein the plurality of memory devices include at least one dynamic random access memory (DRAM). 8. The module according to claim 1, wherein the plurality of memory devices include at least one parallel flash memory device. 9. The method according to claim 9, wherein the third memory device has at least one
4. The module of claim 3, comprising one serial data flash memory device. 10. The module according to claim 1, further comprising a connector and a cost adder. 11. A memory module, comprising: at least one first memory device of a first memory type; and at least one second memory device of a second memory type, wherein:
Neither the first memory device nor the second memory device stores the identification data indicating the device configuration of the memory module, and the minimum configuration includes one memory device of the first memory type and the second memory device. A memory module comprising one or two memory devices of one or more of the following memory types; and a single memory bus coupled to the plurality of memory devices for providing communication between the processor and the plurality of memory devices. 12. The memory device of claim 11, further comprising at least one third memory device of a third memory type, wherein the third memory device stores identification data indicating a device configuration of the memory module.
A module according to. 13. A single memory bus comprising: a primary channel for communicating operating system data from a plurality of memory devices to a processor; an identification channel for communicating identification data from the plurality of memory devices to the processor; A programming channel for providing programming and control signals necessary to program at least one of the devices.
2. The module according to 1. 14. A programming channel, comprising: a dedicated sub-channel for communicating programming signals to a plurality of memory devices when the single memory bus is in a programming mode; and a data transfer signal when the single memory bus is in a data transfer mode. 14. The module of claim 13, comprising: one or more dual function sub-channel lines configured to communicate the plurality of memory devices to a plurality of memory devices. 15. The module of claim 13, wherein the single memory bus further includes an extension channel for communicating data between the additional memory device and the processor. 16. The method according to claim 16, wherein the plurality of memory devices are at least one.
Dynamic random access memory (DRAM)
The module according to claim 11, comprising: 17. The method according to claim 17, wherein the plurality of memory devices are at least one.
2. The method of claim 1, wherein the device comprises two parallel flash memory devices.
2. The module according to 1. 18. The module according to claim 12, wherein said third memory device comprises at least one serial data flash memory device. 19. The module of claim 11, further comprising a connector and a cost adder. 20. A memory module, comprising: a plurality of memory devices including at least one first memory device of a first memory type and at least one second memory device of a second memory type; Neither the first memory device nor the second memory device stores identification data indicating a device configuration of the memory module, and the plurality of memory devices further include at least one third memory device of a third memory type. , A third memory device stores identification data indicating a device configuration of the memory module, wherein the minimum configuration of the memory device is one memory device of the first memory type and one of the second memory type or A plurality of memory devices consisting of two memory devices; Memory module that includes a single memory bus lead coupled to memory devices, the communication between the processor and the plurality of memory devices. 21. A single memory bus comprising: a primary channel for communicating operating system data from a plurality of memory devices to a processor; an identification channel for communicating identification data from a plurality of memory devices to a processor; A programming channel for providing programming and control signals necessary to program at least one of the devices.
Module according to 0. 22. A programming channel, comprising: a dedicated sub-channel for communicating programming signals to a plurality of memory devices when the single memory bus is in a programming mode; and a data transfer signal when the single memory bus is in a data transfer mode. 22. The module of claim 21, further comprising: one or more dual function sub-channel lines configured to communicate with a plurality of memory devices. 23. The module of claim 21, wherein the single memory bus further includes an extension channel for communicating data between the additional memory device and the processor. 24. A method according to claim 24, wherein the plurality of memory devices are at least one.
Dynamic random access memory (DRAM)
21. The module according to claim 20, comprising: 25. At least one of the plurality of memory devices
3. The method of claim 2, wherein the device comprises two parallel flash memory devices.
Module according to 0. 26. The module of claim 20, wherein said third memory device comprises at least one serial data flash memory device. 27. The module of claim 20, further comprising a connector and a cost adder. 28. A plurality of memory devices, including a processor, at least one first memory device of a first memory type, and at least one second memory device of a second memory type, the minimum configuration. A memory module coupled to said processor, comprising: a plurality of memory devices consisting of one memory device of a first memory type and one or two memory devices of a second memory type; And a single memory bus providing communication between the processor and the plurality of memory devices. 29. The system according to claim 28, wherein neither the first memory device nor the second memory device stores identification data indicating a device configuration of the memory module. 30. The plurality of memory devices further include at least one third memory device of a third memory type, wherein the third memory device stores identification data indicating a device configuration of the memory module.
System. 31. A single memory bus comprising: a primary channel for communicating operating system data from a plurality of memory devices to a processor; an identification channel for communicating identification data from a plurality of memory devices to a processor; A programming channel for providing programming and control signals necessary to program at least one of the devices.
9. The system according to 8. 32. A programming channel comprising: a dedicated sub-channel for communicating programming signals to a plurality of memory devices when the single memory bus is in a programming mode; and a data transfer signal when the single memory bus is in a data transfer mode. 32. The system of claim 31, further comprising one or more dual function sub-channel lines configured to communicate a plurality of memory devices to a plurality of memory devices. 33. The system of claim 31, wherein the single memory bus further includes an extension channel for communicating data between the additional memory device and the processor. 34. The method according to claim 34, wherein the plurality of memory devices are at least one.
Dynamic random access memory (DRAM)
29. The system of claim 28, comprising: 35. At least one of the plurality of memory devices
3. The method of claim 2, wherein the device comprises two parallel flash memory devices.
9. The system according to 8. 36. The system of claim 30, wherein said third memory device comprises at least one serial data flash memory device. 37. The system of claim 28, further comprising a connector and a cost adder.