JP2002165460A - Power converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inexpensive and highly reliable power converter by simplifying a switching control means for downsizing. SOLUTION: This converter is provided with a switching control means 4U including gate pulse generating members 12, one of which is provided for each phase and generating a PWM gate pulse by comparing a single carrier wave, with a voltage reference with a voltage level converted in accordance with the single carrier wave, and a distributing means 13a of determining to which of a plurality of switching devices S1 to S4 the generated PWM gate pulse should be distributed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power converter for obtaining multi-phase AC power of variable frequency and variable voltage.

[0002]

2. Description of the Related Art Conventionally, as a multi-level power conversion device for the purpose of suppressing harmonics and lowering the withstand voltage of each switching element, an N-type PWM control system shown in FIG.
A PC (Neutral point clamped) inverter device and a multiplex inverter device shown in FIG. 27 are known.

An NPC inverter shown in FIG. 25 includes a DC power supply 1, voltage dividing capacitors 2a and 2b for dividing a DC voltage from the DC power supply 1 into two, and a voltage dividing capacitor 2a.
a, 2b connected to four switching elements S ₁ -S
₄ and the diode D _P, consisting of D _N NPC switching arm 3U, 3V, and 3W, each phase of the switching control circuit 25 U, 25V, consists 25W, controls the on-off switching element S ₁ to S _4, Output terminals U,
V and W are supplied with three-phase AC power.

The NPC type switching arms 3U, 3
The potential level at which V and 3W can be output is as follows:
/ 2, the neutral point of the two voltage dividing capacitors 2a and 2b is 0,
When the negative and -1/2, the switching element S ₁ to S ₄
Depending on the combination of the ON / OFF states of

[0005]

## EQU1 ## +1/2: S₁= ON, S_Two= ON, S_Three= Off, S_Four= Off 0: S₁= Off, S_Two= ON, S_Three= ON, S_Four= Off -1/2: S₁= Off, S_Two= Off, S_Three= ON, S_Four= On Conventionally, as shown in the NPC inverter shown in FIG.
Controls the switching of elements to obtain multi-level output
The control method is described in “IEEJ Technical Report No. 635 PWM
Latest Technology Trend of Inverter Control Method "(May 1997
26, as described in Chapter 3 of
Two carriers C with different levels ₁, C_TwoFor
Each element by pulse width modulation with a given voltage reference
Is commonly used to control the switching of
You.

FIG. 26 shows an example of an output voltage waveform of the NPC inverter shown in FIG. 25 and 26,
The switching of each element is performed by changing the level of the carrier wave CY, the carrier waves C ₁ and C ₂ , the voltage reference Vuref, and the PWM circuit 27.
a and 27b, and are controlled by gate pulses Gp ₁ and Gp ₂ obtained as a result. Hereinafter, the correspondence of elements that perform switching for each gate pulse will be described.

Gate pulse Gp ₁ : S ₁ and S ₃ are exclusively turned on and off respectively Gate pulse Gp ₂ : S ₂ and S ₄ are exclusively turned on and off respectively In FIG. Although an NPC inverter whose phase output potential level is 3 has been described as an example, in the case where the output potential level is 5 or more, the number of carriers (potential level -1) can be prepared. Obviously, an output waveform that can be easily extended and is closer to a sine wave is obtained.

The multiplex inverter device shown in FIG. 27 has two unit inverters 28U ₁ and 28U ₂ , 28V
₁ and 28V ₂ , 28W ₁ and 28W ₂ are connected in series to form a single phase, and an inverter in which three sets are star-connected to each other. Supply AC power of voltage.

FIG. 28 shows a unit inverter 28. As shown in FIG. 28, the unit inverter 28, a DC power source 1, two DC partial pressure condenser 2a, 2b and this dividing capacitors 2a, the switching element SA ₁ -SA ₄ connected to 2b, SB ₁ ~ SB ₄ and diode D
_It consists of NPC type switching arms 3A and 3B composed of _AP , D _AN , D _BP and D _BN , and controls on / off of the elements.
A single-phase AC power is supplied to the output terminals A and B.

The output potential level of the unit inverter having two phases of the NPC type switching arm is as follows: the positive side of DC is +1/2, the neutral point of the two voltage dividing capacitors is 0, and the negative side is -1/2. Then, the following is obtained depending on the combination of the output potential levels of the output terminals A and B.

[0011] The switching of each element of the unit inverter 28 shown in FIG. 28 is controlled by the unit inverter switching control circuit 30. Unit inverter switching control circuit 30
Is, C ₁ and the carrier C _1, C ₂ and C _1, C _2, which converts the level of the carrier CY phase shifted by 180 ° ', C _2' and a voltage reference Vuref compared with PWM circuit 27a-27d, this Control is performed by the resulting gate pulses Gp ₁ , Gp ₂ and Gp ₁ ′, Gp ₂ ′. The correspondence of the elements that perform switching for each gate pulse is shown below.

Gate pulse Gp ₁ : Operates exclusively ON / OFF operation of SA ₁ and SA ₃ Gate pulse Gp ₂ : Operates exclusively ON / OFF operation of SA ₂ and SA ₄ Gate pulse Gp ₁ ′: SB ₁ and SB ₃ are exclusively turned on / off. Gate pulse Gp ₂ ′: SB ₂ and SB ₄ are turned on / off exclusively. Also, in the multiple inverter device shown in FIG. As a method for obtaining the switching signal of the inverter, there are known a semiconductor power conversion circuit (published by The Institute of Electrical Engineers of Japan / Ohm Corporation), pp. 125 and 126, and US Pat.
As described in U.S. Pat. No. 4,024, U.S. Pat. No. 5,625,545, the phase of a carrier signal is shifted with respect to other unit inverters by using a phase shift circuit, and each element of each unit inverter is used. A method of controlling each is generally performed.

FIG. 29 shows an output waveform when two unit inverters are connected for one phase of the multiplex inverter. C
_11, C ₁₂ and C _11, C is shifted 180 ° the phase of the _{C 12 11 ', C 12'} PWM circuit 27a and a voltage reference Vuref
To 27d, and the resulting gate pulse G
p _11, Gp ₁₂ and Gp ₁₁ ', Gp _12' by controlling the respective elements of 28U _1. The _{C 11, C 12, C 11} ', C 12' C 21, C 22, C 21 which are shifted 90 ° each phase of ', C
Gp ₂₁ , Gp ₂₂ obtained from a comparison between ₂₂ ′ and the PWM circuit
And each element of 28U ₂ is switched by Gp ₂₁ ′ and Gp ₂₂ ′.

As described above, by shifting the phases of the PWM carriers of the _two unit inverters U ₁ and U ₂ , each unit inverter can be switched alternately. A waveform close to a wave is obtained. In FIG. 27, the unit inverter is
Although an example in which two units are connected per phase has been described, it is apparent that an output waveform closer to a sine wave can be obtained when three or more unit inverters are connected.

In FIG. 28, an NPC inverter having a unit inverter capable of outputting a potential level of 5 has been described as an example. However, when the potential level that can be output is set to 7 or more, an output closer to a sine wave is obtained. Obviously, a waveform is obtained.

When an element having a minimum on-pulse constraint is used for a three-level inverter, if the voltage reference is at a level near zero potential, switching below the minimum on-pulse cannot be performed, so that control becomes impossible. As a workaround,
As described in Japanese Patent Application No. 4-11110, a method is used in which the voltage reference is limited so as not to generate a pulse shorter than the minimum on-pulse and the line voltage does not change in the other two phases. . FIG. 30 shows an example of the output voltage waveform. In FIG. 30, a pulse train in which the phase voltage is discontinuous but the line voltage is a continuous sine wave is obtained.

FIG. 31 shows unit inverters 28U, 28
V, 28 W is a three-phase star-connected inverter, and supplies AC power of a variable frequency and a variable voltage to the AC motor 29 from output terminals U, V, W. FIG. 32 shows a case where a single-phase NPC inverter is used as a unit inverter, and switching elements SA _{1 to} SA ₄ and SB _{1 to} SB ₄ and diodes D _AP , D _AN and D connected to the voltage dividing capacitors 2 a and 2 b. _It comprises NPC type switching arms 3A and 3B composed of _BP and _DBN , controls on / off of each switching element, and supplies single-phase AC power to output terminals A and B.

The output potential level of the single-phase NPC inverter having two NPC type switching arms is as follows: the positive potential of the DC power supply is +1; the neutral potential of the two voltage dividing capacitors is 0; If -1, each output terminal A,
The following is obtained depending on the combination of the output potential levels of B.

[0019] The switching of each element of the unit inverters 28U, 28V, 28W shown in FIG. 31 is controlled by the unit inverter switching control circuits 30U, 30V, 30W. Hereinafter, the U phase will be described as a representative, but the same applies to the V and W phases. The unit inverter switching control circuit 30U includes carrier waves C ₁ and C obtained by level-converting the carrier wave CY.
₂ and C ₁ 'obtained by phase-shifting C ₁ and C ₂ by 180 °,
C ₂ ′ and the voltage reference V ref are connected to the PWM circuits 27a to 27d.
, And the resulting gate pulses Gp ₁ , Gp
p ₂ and Gp ₁ ', Gp _2' is controlled by. Hereinafter, the correspondence of elements that perform switching for each gate pulse will be described.

Gate pulse Gp ₁ : Turns on and off exclusively SA ₁ and SA _3. Gate pulse Gp ₂ : Turns on and off exclusively SA ₂ and SA _4. Gate pulse Gp ₁ ′: SB Gate pulse Gp ₂ ′: ON / OFF operation of SB ₂ and SB ₄ exclusively for ON and OFF operations of ₁ and SB ₃ respectively Output voltage when single-phase NPC inverter is switched as described above FIG. 33 shows a waveform example.

In FIG. 32, an NPC inverter in which one switching arm has an output potential level of 3 has been described as an example. However, when the output potential level is 5 or more, an improved result is obtained. It is clear that

As a method using a hysteresis comparator, there is a method of obtaining a PWM signal by a current tracking control circuit described on pages 143 and 144 of “Semiconductor Power Conversion Circuit” (published by the Institute of Electrical Engineers of Japan / Ohm Corporation). PWM control can be performed with a simplified hardware configuration.

[0023]

However, in the conventional method of controlling a power conversion device including a multi-level inverter and a multiplex inverter, a PWM circuit, a phase shift and a circuit level conversion circuit are provided for each switching element. Need to be added, and as the number of elements increases,
Since the device becomes large, there are reliability and economic problems.
Further, as described above, since a PWM circuit is prepared for each switching element and the gate pulse output is fixed and allocated, switching to a specific switching element is concentrated in a specific period, and the DC potential (neutral voltage) at a voltage dividing point is increased. (Point potential) fluctuates.

The present invention has been made in view of the above,
An object of the present invention is to provide a power converter that can achieve the following first to fifth objects.

It is a first object of the present invention to simplify and reduce the size of the switching control means by forming one gate pulse generation means and distribution means for each phase, thereby improving economical reliability.

A second object of the present invention is to prevent switching of elements in individual unit inverters from being concentrated for a specific period in a power converter including multiple inverters, and to balance switching losses.

It is a third object of the present invention to correct a non-controllable region of a switching device having a minimum on-pulse width and apply it to a power conversion device including a multi-level inverter and multiple inverters.

It is a fourth object of the present invention to generate a PWM gate pulse with a simpler hardware configuration by configuring the gate pulse generation means with a hysteresis comparator.

The switching control means is constituted by one gate pulse generating means and switching decision means for each unit inverter, so that the switching element capable of suppressing the unbalance of the DC voltage is switched with priority. A fifth object is to suppress the fluctuation of the potential at the point and to increase the cost and reliability.

[0030]

According to the first aspect of the present invention, a DC voltage from a DC power supply is divided into a plurality of potentials, and the divided DC voltage is supplied. 3 by ON / OFF control of multiple switching elements
In a power conversion device having two or more phases of a switching arm that outputs an AC voltage having the above-described potential level and obtaining multi-phase AC power of variable frequency and variable voltage, one is provided for each phase, and a single phase and Gate pulse generation means for generating a pulse pulse modulated by comparing a carrier having an amplitude with a voltage reference obtained by converting a voltage level corresponding to the carrier having a single phase and amplitude; It is a gist of the present invention to control on / off of the plurality of switching elements by switching control means including distribution means for determining to which of the plurality of switching elements the gate pulse output from the switching element is to be distributed.
With this configuration, in the power conversion device including the multi-level inverter, the carrier having the single phase and the amplitude and the voltage reference having the voltage level converted to the predetermined level are converted by the gate pulse generation unit provided for each phase. The PWM gate pulse is generated by the comparison. This PWM gate pulse is distributed by the distribution means to the selected switching element in the switching arm of that phase, and polyphase AC power is obtained.

According to a second aspect of the present invention, in the power converter according to the first aspect, the distribution means outputs the switching arm when the switching element is switched by a gate pulse output from the gate pulse generation means. Output potential level determining means for determining a potential level to be performed, and a switching element for changing an output state to output the determined potential level from a current switching state of each switching element is selected as a next switching element. Switching element selecting means, and a gate pulse allocating means for outputting a gate pulse output from the gate pulse generating means to the selected switching element, and outputting a gate pulse for maintaining a current state to a switching element not selected. The gist is to have With this configuration, in the distribution unit of the power conversion device including the multilevel inverter, among the plurality of switching elements in the switching arm of that phase,
The element to be switched next is selected from the potential level to be output by the switching arm, and the PWM output from the gate pulse generation means to the selected switching element
A gate pulse is output, and a PWM gate pulse that maintains the current state is output to a switching element that is not selected, so that polyphase AC power is obtained.

According to a third aspect of the present invention, a DC voltage from a DC power supply is divided into a plurality of potentials, and three or more potentials are obtained by on / off control of a plurality of switching elements supplied with the divided DC voltage. A power converter that has two or more unit inverters having two switching arms for outputting levels to form an inverter group, and that has two or more inverter groups to obtain multi-phase DC power of variable frequency and variable voltage. , One provided for each phase and pulse width modulated by comparing a carrier of a single phase and amplitude with a voltage reference that has been converted to a voltage level corresponding to the carrier of a single phase and amplitude. A gate pulse generating means for generating a gate pulse, and a gate pulse output from the gate pulse generating means to any switching element in any of the unit inverters. And summarized in that to control the on and off a plurality of switching elements in said two unit inverters by the switching control means and a dispensing means for determining whether the distribution. With this configuration, in the power conversion device including the multiple inverters, the carrier having a single phase and amplitude is compared with the voltage reference whose voltage level has been converted to a predetermined level by the gate pulse generation unit provided for each phase. By doing so, a PWM gate pulse is generated.
This PWM gate pulse is distributed by the distribution means to the selected switching elements in the two unit inverters constituting the phase, and multiphase AC power is obtained.

According to a fourth aspect of the present invention, in the power converter according to the third aspect, the distribution means outputs each phase when a switching element is switched by a gate pulse output from the gate pulse generation means. Output potential level determining means for determining a power potential level, and the current output potential level of each of the unit inverters is stored, and the longest one of the unit inverters capable of realizing the output of the determined potential level in one switching operation. A unit inverter selecting means for selecting a unit inverter whose state has not changed, and a current switching state of each switching element in each of the unit inverters and an order of occurrence of switching are stored, and a current switching of each switching element is stored. The selected unit input depends on the status of A switching element in a unit inverter for selecting a switching element that changes the output state to output the determined potential level in the inverter as a next switching element; and the gate pulse to the selected switching element. A gate pulse allocating unit that outputs a gate pulse output from the generation unit and outputs a gate pulse that maintains the current state to all switching elements that are not selected and all switching elements in the unit inverter that is not selected are provided. Is the gist. With this configuration, in the distribution unit of the power conversion device including the multiplexed inverters, the unit inverter control unit determines, by the unit inverter control unit, the unit inverter that has not changed in the output state for the longest time among the unit inverters that can change the output potential level in the phase The selected, and then the switching element selection means in the unit inverter, in the selected unit inverter, the element to be switched next from the current switching state of each switching element, the switching generation order, and the determined potential level to be output. The PWM gate pulse output from the gate pulse generation means is output to the selected and selected switching element, and the current state is maintained for the unselected switching elements and all the switching elements in the unselected unit inverters. Gate pulse Is force, polyphase AC power is obtained.

According to a fifth aspect of the present invention, in the power conversion device according to the first or third aspect, the voltage reference is corrected such that a gate pulse width output from the gate pulse generating means does not become smaller than a specific width. The gist of the present invention is to have a voltage reference correction unit that performs the operation. With this configuration, even a switching element having a minimum on-time can be applied to a power conversion device including a multilevel inverter or a multiplexed inverter to output a desired potential level.

According to a sixth aspect of the present invention, in the power converter according to the fifth aspect, the voltage reference correction means corrects the voltage reference such that the time average is equal to the voltage reference of each phase. Make a summary. With this configuration, it is possible to obtain a line voltage closer to a sine wave even if the voltage reference is corrected.

According to a seventh aspect of the present invention, a DC voltage from a DC power supply is divided into a plurality of potentials, and three or more potentials are controlled by on / off control of a plurality of switching elements supplied with the divided DC voltage. In a power converter that has one or more phases of unit inverters having two switching arms that output alternating voltages having different levels and obtains multi-phase AC power of a variable frequency and a variable voltage, one is provided for each phase and provided. Voltage reference conversion means for converting a voltage level corresponding to a carrier having a single phase and amplitude with respect to a voltage reference, voltage reference level determination means for determining a voltage region to which the voltage reference belongs, and the carrier and the conversion Gate pulse generating means for generating a pulse width-modulated gate pulse by comparison with the voltage reference, and DC voltage monitoring means for monitoring each of the divided DC voltages Output current detection means for detecting an output current of the unit inverter of each phase; switching state storage means for storing a current state of each switching element in the unit inverter; the divided DC voltage; and the output current Switching decision means for deciding the next switching state of all switching elements in the unit inverter from the gate pulse, the voltage range and the current state of each switching element. The gist is to control on / off of the element. With this configuration, the next switching state of each switching element is determined by the switching determination means so that the DC voltages in the unit inverters are balanced, and the fluctuation of the neutral point potential is suppressed.

According to an eighth aspect of the present invention, in the power conversion device according to the seventh aspect, the switching determining means determines that the potential at the neutral point, which is each DC voltage dividing point, is higher than the equilibrium point. The state of the switching element is changed so that the current flows out of the neutral point, and when the potential of the neutral point is lower than the equilibrium point, the next switching state is determined so that the current flows into the neutral point. The point is to do. With this configuration, the fluctuation of the neutral point potential is suppressed.

According to a ninth aspect of the present invention, in the power converter according to the seventh aspect, instead of the output current detecting means,
The gist is to use a given current command value.
With this configuration, the output current of the unit inverter is usually
Since the control is performed so as to follow the current command value given from the outside, the same operation and effect can be obtained even if the current command value is input to the switching determination means instead of providing the output current detection means.

According to a tenth aspect of the present invention, a DC voltage from a DC power supply is divided into a plurality of potentials, and three or more potentials are obtained by on / off control of a plurality of switching elements supplied with the divided DC voltage. In a power converter that has one or more phases of unit inverters having two switching arms that output alternating voltages having different levels and obtains multi-phase AC power of a variable frequency and a variable voltage, one is provided for each phase and provided. Voltage reference conversion means for converting a voltage level corresponding to a carrier having a single phase and amplitude with respect to a voltage reference, voltage reference level determination means for determining a voltage region to which the voltage reference belongs, and the carrier and the conversion A gate pulse generating means for generating a pulse pulse modulated by comparing with a voltage reference, and a current state of each switching element in the unit inverter. Switching arm storage means for storing the arm that has just switched among the two arms in the unit inverter; information on the switching arm that has just switched, the gate pulse, the voltage area, Switching on / off of the plurality of switching elements by switching control means including: a switching determination means for determining a next switching state of all switching elements in the unit inverter from a current state of each of the switching elements. Is the gist. With this configuration,
By inputting switching arm information instead of the DC voltage and output current in the unit inverter as input information to the switching determination means, similarly to the above, the next DC voltage in each unit inverter is balanced so that the DC voltage in the unit inverter is balanced. Is determined, and the fluctuation of the neutral point potential is suppressed.

According to an eleventh aspect of the present invention, in the power converter according to the tenth aspect, when there are a plurality of outputable switching states, the switching determination means performs the switching immediately before the switching state is stored in the switching arm storage means. The gist is to determine a switching state so that another arm is switched with respect to the selected arm. With this configuration, when there is a different switching state at the same output potential level according to the switching arm information, the switching determining unit distributes the switching by giving priority to the switching element that has not been switched last time, thereby distributing the switching to the neutral point. Reduce potential fluctuation.

The twelfth aspect of the present invention provides the seventh aspect or the first aspect.
0, the next switching state determined by the switching determination means is a state that can be shifted to the current switching state by performing one switching of any of the switching elements. The gist is that the output of the phase unit inverter changes with the divided DC voltage as the minimum unit. With this configuration, the switching of the two switching elements is prohibited at the same time, and the switching is distributed. In addition, by changing the output of the unit inverter of each phase by using the divided DC voltage as the minimum unit, it is possible to obtain polyphase AC power which is approximated to a sine wave as a whole.

According to a thirteenth aspect of the present invention, in the power conversion device according to the first, seventh or tenth aspect, the gate pulse generating means includes a carrier having a single phase and a single amplitude and a voltage reference having a converted voltage level. Instead of a comparator configuration that generates a pulse width modulated gate pulse by comparison, a hysteresis comparator that generates a pulse width modulated gate pulse when the error signal between the current reference and the output current exceeds a specific hysteresis The gist is to do it. With this configuration, it is possible to generate a PWM gate pulse with a simplified hardware configuration.

[0043]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 to FIG. 4 are views showing a first embodiment of the present invention. This embodiment is applied to a power conversion device including a multi-level inverter. In FIG. 1, components that are the same as or equivalent to the components in FIG. 25 are denoted by the same reference numerals as those described above, and redundant description will be omitted. In the present embodiment, as shown in FIG. 1, a voltage reference conversion circuit that converts a voltage reference so that a switching control circuit can be pulse width modulation controlled by a single phase and amplitude carrier and a single comparison circuit. 11, a PWM circuit 12 as a gate pulse generating means including a carrier wave having a single phase and a single amplitude and a single comparing circuit, and a distribution control circuit 4U as a switching control means composed of a distribution circuit 13a as a distribution means. , 4V, 4W. Hereinafter, the U phase will be described as a representative, but the same applies to the V phase and the W phase.

FIGS. 2 and 3 show the concept of the correspondence of the output potential level of the NPC inverter and the conversion of the voltage reference. Here, the voltage reference is normalized from -1 to +1. FIG. 2 shows the carrier C with respect to the voltage reference before conversion.
₁ and C ₂ are shown. In the NPC inverter, when the potential level of the neutral point of the DC power supply is 0 level, the positive side is +1/2, and the negative side is -1/2, when the voltage reference is in the range of 0 to +1, the carrier wave C ₁ the output from the magnitude relation of 0 and +1/2 alternately when the voltage reference is in the range from -1 to 0, and outputs the -1/2 and 0 on the magnitude relationship between the carrier C ₂ alternately. As shown in FIG. 3, in the present embodiment, the voltage reference is converted such that the amplitude of the carrier is -1 to +1 in consideration of the relative relationship between the voltage reference and the carrier. For example, FIG.
As shown in FIG. 3, when the voltage reference is in the range of 0 to +1, a phase voltage having a pulse width determined from the relationship between the carrier and the voltage reference can be obtained, and a similar pulse width is shown in FIG. In order to output using a single carrier, the following conversion is performed.

Eu = (Vuref − ／) × 2 (1) Eu: U-phase voltage reference after conversion Vuref: U-phase voltage reference before conversion Even when the voltage reference is in the range of −1 to 0, Similarly, conversion is performed as follows.

Eu = (Vuref + ／) × 2 (2) The converted reference voltage is subjected to PWM control by the PWM circuit 12 to output a gate pulse p.

In the distribution circuit 13a, the next switching element m is determined, and the determined switching element m is determined.
, And outputs a gate pulse to the other switching elements to continue the previous switching state.

The configuration and operation of the distribution circuit 13a for the NPC switching arm 3U will be described in detail with reference to FIG. First, the potential level 1 of the phase voltage to be output from the voltage reference Vref in the output potential level determination circuit 14 as output potential level determination means is determined as shown in FIG. 2 by the magnitude of the voltage reference Vref and the carrier waves C ₁ and C ₁ . Determined according to the magnitude relationship with ₂ . Next, a switching element selection circuit 15a as a switching element selection unit starts from the potential level 1.
Then, the element m to be switched next is determined. The switching element selection circuit 15a determines the switching element m according to the following theory.

[0050] When the voltage reference Vuref ranges from 0 +1: If S ₁ and the voltage reference Vuref to each exclusively switching the S ₃ is in the range of -1 to 0: exclusive S ₂ and S _4, respectively The switching element selection circuit 15a that performs the switching in succession includes the next switching element m and the current switching state Gp of each element.
_1-0 and Gp _2-0 are output to a gate pulse allocating circuit 18a as gate pulse allocating means. The gate pulse allocating circuit 18a outputs the gate pulse p output from the PWM circuit 12 to the element m selected by the switching element selection circuit 15a, and outputs the gate pulse p to the other elements from the switching element selection circuit 15a. The current switching pulses Gp _1-0 and Gp _2-0 are controlled to be output.

As described above, in the first embodiment, in the power conversion device including the multi-level inverter, control can be performed using one PWM circuit 12 for each phase and the distribution circuit 13a for distributing the gate pulse. The circuit configuration can be made compact. Further, even when the number of switching elements increases and the number of levels increases, the switching control circuit can be configured by expanding the distribution method in the distribution circuit 13a without increasing the number of PWM circuits.

FIGS. 5 to 10 show a second embodiment of the present invention. The present embodiment is applied to a power converter including multiple inverters. In FIG. 5, the same or equivalent components as those in FIG.
The same reference numerals are used to denote the same parts, and duplicate description is omitted. In the present embodiment, the switching control circuits 5U, 5V, and 5W of the individual unit inverters are different in that the number of output levels of the voltage reference conversion circuit 11 is increased and that the distribution circuit 13b
1 is different from the gate pulse control circuit in FIG.

In this way, when two NPC single-phase inverters are multiplex-connected per phase, the potential levels that can be output for each phase are +2, +3/2, +1, +1/2, 0, -1 /
There are nine levels of 2, -1, -3/2 and -2.

FIG. 6 shows the relative relationship between the potential level of the output of the same phase as in FIG. 2 and the voltage reference. As in the first embodiment, the following conversion is performed based on the voltage reference value.

When the voltage reference is in the range of +3/4 to +1 Eu = (Vuref−7 / 8) × 8 (3) When the voltage reference is in the range of +1/2 to +3/4 Eu = (Vuref) −5/8) × 8 (4) When the voltage reference is in the range of + ／ to + ／ Eu = (Vuref−3 / 8) × 8 (5) When the voltage reference is 0 to + ／ Eu = (Vuref − ／) × 8 (6) When the voltage reference is in the range of − ／ to 0 Eu = (Vuref + ／) × 8 (7) The voltage reference is − Eu = (Vuref + 3/8) × 8 (8) When the voltage reference is in the range of −3/4 to − ／ Eu = (Vuref + 5/8) × 8 (9) When the voltage reference is in the range of −1 to −3/4 Eu = (Vuref + 7/8) × 8 (10) FIG. Showing the detailed structure of the b. First, the output potential level determining circuit 14 determines the potential level 1 of the phase voltage to be output from the voltage reference according to the magnitude relationship between the magnitude of the voltage reference and the carrier as shown in FIG. Next, switching from the potential level 1 to the switching element selection circuit 15b
Then, the element m to be switched next is determined. The switching element selection circuit 15b includes a unit inverter selection circuit 16 as unit inverter selection means and a unit inverter element selection circuit 17 as unit inverter element selection means. In the unit inverter selection circuit 16, FIG.
As shown in the figure, for the potential levels -1, -1/2, 0, +1/2, and +1 that can be output from the unit inverter,
First-in first-out queues 19a, 19b, 19c, 1
9d and 19e are prepared. Each unit inverter belongs to any one queue from each output state. At this time, the queues 19a, 19b, 19c, 19d, and 19e also have information as to the order in which the output state of each unit inverter has changed to its potential level. The output potential level of a phase can be determined by adding the outputs of these unit inverters. For example, in FIG. 8, U ₁ and U ₂ belong to the level 19 queue 19c.
Earlier shows that had become U ₁ level 0. In addition, U ₁ = 0 and U ₂ = 0 indicate that the output potential level of the phase is 0.

The unit inverter selection circuit 16 receives the potential level 1 of the phase voltage to be output from the output potential level determination circuit 14, compares it with the current output potential level before switching, which is known from the state of the queue, and outputs the potential to be output. If the level is high, the output level of the unit inverter at the head of the minimum level of the queue is increased by one, and the output potential level of the phase is increased. In this way, the unit inverter q to be switched is determined.

Next, the element selection circuit 17 in the unit inverter
Will be described. Element selection circuit in unit inverter 17
Here, the element to be switched is determined for the unit inverter q that changes the potential level determined by the unit inverter selection circuit 16. FIG. 9 shows the switching state of each element and its transition with respect to the output potential level when the unit inverter is the NPC single-phase inverter shown in FIG. The number indicates the output potential level of the unit inverter,
+, 0,-in parentheses indicate the state of the two arms in the unit inverter, + indicates that the upper two elements are on, 0 indicates that the inner two elements are on, and-indicates that the lower two elements are on. Indicates that it is on. The dashed arrow indicates a state transition when there is no room for selection, and the solid arrow indicates a state transition when switching is selected according to the state of the flag.
The number "1" indicates the flag status at that time. The switching status of the two arms is 20a, 20b, 20
c, 20d, 20e, 20f, 20g, 20h, 20i
There are nine types. Here, the switching states in which the output potential level of the unit inverter is + は are 20b and 20b.
There are two types of switching c, two types of switching with the output potential level of 0, 20d, 20e, and 20f, and two types of switching with the output potential level of -1/2, 20g and 20.
h.

Next, a method for selecting an element will be described. 20b
Has a switching state, and the potential level of the unit inverter changes from +1/2 to +1, there is no room for selecting the switching, and the element to be switched next is uniquely determined. However, when the output potential level of the unit inverter changes from +1 to + ／, the output potential level changes from 20a to 20b.
There are two options for changing to 20c and for changing to 20c. In this embodiment, in order to disperse the switching of the elements, if it is possible to select which arm is to be switched as described above, a flag (FLG = 0 or FLG = 0 or
The arm that has been stored in 1) and has not been switched in the previous selection is switched next.

FLG = 0: Previously selected A-phase arm FLG = 1: Previously selected B-phase arm Then, when the selection is made and switching is performed, the flag is inverted from 0 → 1 or 1 → 0. For example, if the output potential level of the unit inverter changes next from +0 to + ／ while the A-phase arm is selected and FLG = 0, it is possible to change from the state of 20a to 20b and 20c. ,
Since FLG = 0, the arm of the B phase is selected next, the state is changed to 20c, and FLG = 1 is set. Conversely, when the B-phase arm is selected and FLG = 1, the A-phase is selected so as to be 20b and FLG = 0 is reset. In each phase, the switching element m is determined as follows based on the change in the output potential level.

[0060] +1/2 potential level change between 0: exclusively potential level change between switching 0 and -1/2 for S ₁ and S _3: not exclusively switching select S ₂ and S ₄ For elements, queues 20a, 20a
The previous switching signal is continuously output from the states of b, 20c, 20d, and 20e.

The switching element selection circuit 15b outputs the element m to be switched next and the current switching state Gp _11-0 and Gp _22-0 ′ of each element to the gate pulse allocating circuit 18b. The gate pulse allocating circuit 18b supplies a gate pulse p output from the PWM circuit 12 to the element m selected by the switching element selecting circuit 15b.
And outputs the current switching signal Gp output from the switching element selection circuit 15b to the other elements.
_11-0 and Gp _22-0 ′ are output.

FIG. 10 shows switching waveforms in the unit inverter. Switching based on the intersection of the voltage reference and the carrier is given to any of the elements in the unit inverter, and an output voltage waveform close to a sine wave can be obtained as a whole.

As described above, in the second embodiment, in the power conversion device including the multiple inverters in which two unit inverters are connected in series for each phase, one PWM circuit 1
2 and a distribution circuit 13b for distributing the gate pulse, and the circuit configuration can be made compact. Also, using the queues 19a, 19b, 19c, 19d, and 19e,
Among the unit inverters capable of realizing the change of the output potential level, the switching method of each unit inverter can be dispersed by the control method of switching the unit inverter in which the output state has not changed for the longest period, so that the switching loss can be balanced. The case where two unit inverters are connected per phase has been described above. However, when three or more unit inverters are connected, the queues 19a, 19b, 1
Similar processing can be performed by increasing the number of unit inverters accommodated in 9c, 19d, and 19e. In the above description, the unit inverter is an NPC single-phase inverter. However, even in the case of a multi-level single-phase inverter having five or more levels, the same processing is performed by extending the switching state transition shown in FIG. Can be performed. Therefore, each element of the multiplex inverter, in which two or more multi-level single-phase inverters are connected per phase, can be controlled by one PWM circuit and gate pulse distribution circuit for each phase, and the number of parts is reduced, and The switching loss of the element can be balanced.

FIG. 11 shows a third embodiment of the present invention. In FIG. 11, the same or equivalent components as those in FIG. 1 are denoted by the same reference numerals as those described above, and redundant description will be omitted. In this embodiment, in a power conversion device including a multi-level inverter, pre-emphasis is provided before and after a voltage reference conversion circuit 11 that converts a voltage reference so that pulse width modulation control can be performed by a single carrier and a single comparison circuit. Voltage reference correction circuit 2 composed of a circuit and the like
1 and 22 are added. Hereinafter, among the switching control circuits 6U, 6V, and 6W, the U phase will be described as a representative.
The same applies to the phase and the W phase. The case where the carrier is a triangular wave will be described.

In the voltage reference correction circuit, a value Eu ^* obtained by limiting the voltage reference by the following voltage limit Eulmt with respect to the required minimum pulse width Tmin is input to the PWM circuit 12 to output a gate pulse less than Tmin. Disappears.

Eulmt = ± (1-2 × Tmin / Tc) (11) Tc: period of carrier wave In this case, ε shown below is a limited error, and the output voltage is shifted from the reference voltage by this amount. Will shift.

Ε = Eu−Eu ^* (12) In the present embodiment, the time average is made equal to the original voltage reference by adding the limited error ε to the voltage reference of the next sample period.

[0068]

[Formula 2] Vuref (n) = Vuref (n) + ε (n−1) (13) In this way, even when an element having a minimum on-time is used, it can be applied to a multilevel inverter. it can.

FIG. 12 shows a fourth embodiment of the present invention. In FIG. 12, the same or equivalent components as those in FIG. 11 are denoted by the same reference numerals as those described above, and redundant description will be omitted. In the present embodiment, the main circuit configuration is changed from a multi-level inverter to a multiple inverter, and switching control circuits 7U, 7
The distribution circuits in V and 7W are replaced by the distribution circuit 13b for multiplex inverters shown in FIG. Even if the hardware configuration is changed, an element having a minimum on-time can be applied to a multiplexed inverter in which multilevel inverters are multiplexed in the same manner as in the third embodiment.

FIGS. 13 to 15 show a fifth embodiment of the present invention. In FIG. 13, the same or equivalent components as those in FIG. 1 are denoted by the same reference numerals as those described above, and redundant description will be omitted. In the present embodiment, in the switching control circuits 8U, 8V, 8W, the PWM circuit is replaced by a hysteresis comparator 23 which receives an error signal from the current references Iuref, Ivref, Iwref and current feedback Iu, Iv, Iw. As shown in FIG. 15, when the error signal exceeds the hysteresis width, the switching signals U ₁ , V ₁ , and W ₁ are turned on.
Toggle off. The output from the hysteresis comparator 23 is input to the distribution circuit 13c. FIG. 14 shows the configuration of the distribution circuit 13c of the present embodiment. 4 in that the output potential level determination circuit is replaced by an output potential level holding circuit 24. FIG. 15 shows a conceptual diagram of current reference, current feedback, and gate pulse input. The output potential level holding circuit 24 stores the current potential level output from the inverter, detects the rise and fall of the gate pulse from the hysteresis comparator 23, and sets the potential level to 1 when the gate pulse rises. In the case of increase and falling, the potential level is decreased by one. Then, the current potential level 1 is input to the switching element selection circuit 15a.

By doing so, the subsequent processing can be the same as in the first embodiment, and the hysteresis comparator 23 can be applied to a multi-level inverter.

FIGS. 16 and 17 show a sixth embodiment of the present invention. In FIG. 16, the same or equivalent components as those in FIG. 13 are denoted by the same reference numerals as those described above, and duplicate description will be omitted. In this embodiment, the main circuit configuration is replaced by a multi-level inverter to a multiplexed inverter, and the switching circuits in switching control circuits 9U, 9V, and 9W are replaced by the distribution circuits shown in FIG. Distribution circuit 13 shown in FIG.
d is different from the multiplex inverter distribution circuit shown in FIG. 7 in that the output potential level determination circuit is replaced by an output potential level holding circuit 24, and the operation of the output potential level holding circuit 24 is the same as that of the fifth embodiment. Same as the form.

By doing so, the hysteresis comparator 23 can be applied to a multiple inverter.

FIGS. 18 to 21 are views showing a seventh embodiment of the present invention. Note that FIG.
Components that are the same as or equivalent to those in 1 are denoted by the same reference numerals as those described above, and redundant description is omitted. In the present embodiment, as shown in FIG. 18, a voltage reference conversion circuit for converting a voltage level so that a switching control circuit can be controlled by pulse width modulation with a single phase and amplitude carrier and a single comparison circuit. 11, a voltage reference level determination circuit 35 as voltage reference level determination means for determining a voltage region to which the voltage reference belongs, a PWM circuit 12 including a carrier having a single phase and a single amplitude, and a single comparison circuit; The switching control circuits 31U, 31V and 31W, which are constituted by a switching decision circuit 36 as means, are replaced with a voltage detection circuit 37 as DC voltage monitoring means, a current detection circuit 38 as output current detection means, and switching as switching state storage means. State storage circuit 39
Has been added. Hereinafter, the U phase will be described as a representative.
The same applies to the phase and the W phase. Also, hereinafter, a single-phase NP
Although the C inverter has been described, a single-phase multi-level inverter having five or more levels can be realized with the same configuration.

FIGS. 19 and 20 show the concept of the correspondence between the output potential level of the single-phase NPC inverter and the conversion of the voltage reference. Here, the voltage reference is normalized from -1 to +1. FIG. 19 shows the correlation between the voltage reference and the carriers C ₁ , C ₂ , C ₃ and C ₄ for the single-phase NPC inverter. When the potential level of the neutral point of the DC power supply 1 is 0,
Assuming that the positive potential is +1 and the negative potential is -1, a single-phase NPC
The voltage that can be output from the inverter (the voltage between A and B) is +
There are five levels of 2, +1, 0, -1, and -2, with the following relationship.

When the voltage reference is in the range of +1/2 to +1: +1 and +2 are alternately output based on the magnitude relationship with the carrier C _{1. When the} voltage reference is in the range of 0 to +1/2: The carrier C
0 and +1 are alternately output based on the magnitude relationship with _{2. When the} voltage reference is in the range of -1/2 to 0: carrier C
If ₃ and the output voltage reference alternately -1 and 0 from the magnitude relationship in the range of -1/2 -1: output Figure 21 alternately -2 and -1 from the magnitude relationship between the carrier C ₄ The output state of the single-phase NPC inverter and the range in which transition can be performed by one switching are shown. Numbers are single phase NPC
Indicates the output potential level of the inverter.
− Indicates the state of the two arms in the single-phase NPC inverter, + indicates that only the upper two elements are on, and 0 indicates the inner element 2
Only one is on, and-indicates that only the two lower elements are on. A broken arrow indicates a state transition when there is no room for selection, and a solid arrow indicates a state transition when switching is selected because there are a plurality of switching states even at the same output potential level. The switching states of the single-phase NPC inverter are 40a, 40b, 40c, 40d, 40
e, 40f, 40g, 40h, and 40i. Here, there are two switching states of 40b and 40c in which the output potential level of the single-phase NPC inverter is +1, and 40d and 40d in which the output potential level is 0.
There are three types of switching states 40e and 40f and an output potential level of −1, and two types of switching states 40g and 40h. These can select the switching state even when outputting the same potential.

As shown in FIG. 20, in the present embodiment,
Considering the relative relationship between the voltage reference and the carrier, the voltage reference is converted such that the amplitude of the carrier is from -1 to +1. For example, as shown in FIG.
, A phase voltage having a pulse width determined from the relationship between the carrier and the voltage reference can be obtained. In order to output a similar pulse width using a single carrier shown in FIG. The following conversion is performed.

Eu = (Vuref − ／) × 4 (14) Eu: U-phase voltage reference after conversion Vuref: U-phase voltage reference before conversion Hereinafter, similar conversion is performed even in the respective ranges. .

When the voltage reference is in the range from +1/2 to +1: Eu = (Vuref − ／) × 4 (15) When the voltage reference is in the range from − ／ to 0: Eu = ( (Vuref + ／) × 4 (16) When the voltage reference is in the range of −1 to − ／: Eu = (Vuref + ３) × 4 (17) The converted voltage reference is supplied to the PWM circuit 12. PWM control to output a gate pulse p. At this time, in the voltage reference level determination circuit 35, information as to which region the voltage reference is in, that is, which carrier is to be compared, is input to the switching determination circuit 36 as the voltage reference level Iv. In the switching decision circuit 36, the gate pulse p,
Voltage reference level Iv, magnitude relationship between DC voltages Vdc _- P and Vdc _- N detected by voltage detection circuit 37, current detection circuit 38
Then, the next switching state is determined from the direction of the output current detected and the current switching state. Here, the direction in which the current is output from the switching arm 3A is a positive direction. By storing this switching determination theory in a ROM, PLD, or the like as a decision table, the switching state can be determined without software processing.

The logic details of the switching decision circuit decision table will be described below.

(1) If the voltage level that can be output in the current switching state is equal to the output voltage indicated by the input gate pulse p and the voltage reference level Iv, no switching is performed.

(2) If the above (1) is not equal, the switching state is changed so as to match. However, 1
Only one element is switched and two switchings are prohibited at the same time.

Here, if there are two options for switching to match the voltage to be output, which arm element is to be switched is selected by the following determination.

(A) When the output potential level is ± 1, (i) (positive side voltage is large and arm A current is positive) or (negative side voltage is large and arm A current is negative): arm B is connected to the neutral point =
Select 40c and 40g (ii) (High positive voltage and negative arm A current) or (High negative voltage and positive arm A current): Connect arm A to neutral point =
Select 40b and 40h. (B) When the output potential level is 0, the arms A and B are switched alternately.

For example, when the switching state is at 40b and the potential level of the single-phase NPC inverter changes from +1 to +2, there is no room for selecting the switching, and the element to be switched next is uniquely determined. The switching state is established. However, when the output potential level of the unit inverter changes from +2 to +1 from the state of 40a, there are two options of changing from 40a to 40b and changing to 40c. When the current of A flows to the negative side, 40b is selected according to the above. In the state of 40b, the arm A is connected to the neutral point, a current flows into the neutral point, the neutral point potential rises, and the operation is performed so that there is no difference in the DC voltage.

As described above, in the seventh embodiment, in a power converter in which single-phase NPC inverters are star-connected for each phase, when controlling using one PWM circuit 12 and switching decision circuit 36, When there are different switching states at the same output potential level, the switching of the switching element that balances the DC voltage is preferentially performed, so that the fluctuation of the neutral point potential can be suppressed. The case of a single-phase NPC inverter has been described above with respect to the unit inverter. However, even in the case of a multilevel single-phase inverter having five or more levels, the same processing can be performed by extending the switching state transition. Therefore, single-phase NPC
Inverter control can be performed by one PWM circuit and switching decision circuit for each phase, so that the number of components can be reduced and the neutral point potential fluctuation can be suppressed.

FIG. 22 shows an eighth embodiment of the present invention. In FIG. 22, components that are the same as or equivalent to the components in FIG. 18 are denoted by the same reference numerals as those described above, and redundant description will be omitted. In the present embodiment, the current reference Iuref is input to the switching determination circuit 36 in the switching control circuit 32U instead of the output of the output current detection circuit. Normally, the output current is controlled so as to follow the current reference, so that the same operation and effect as in the seventh embodiment can be obtained.

FIG. 23 shows a ninth embodiment of the present invention. In FIG. 23, the same or equivalent components as those in FIG. 18 are denoted by the same reference numerals as those described above, and redundant description will be omitted. In the present embodiment, a switching arm storage circuit 41 as switching arm storage means is added to the switching control circuit 32U instead of the voltage detection circuit and the current detection circuit.

The switching arm storage circuit 41 is a circuit for storing as a flag which of the arms A and B has switched in the previous switching, and inputs the result to the switching decision circuit 36. The meaning of the flags is as follows.

FLG = A: The element of the B-arm was previously switched. FLG = B: The element of the A-arm was previously switched. The logical details of the switching determination circuit 36 will be described below.

(1) If the voltage level that can be output in the current switching state is equal to the voltage to be output indicated by the input gate pulse p and the voltage reference level Iv, no switching is performed. Since no switching is performed, the switching arm storage circuit 41 does not switch the flag.

(2) If the above (1) is not equal, switching is performed so as to match. However, only one element is switched, and two switchings are prohibited at the same time. After the switching, the switching arm storage circuit 41 switches the flag.

Here, if there are two options for switching to match the voltage to be output, the element of the arm that has not been switched last time is switched from the current switching arm flag. After switching,
The switching arm storage circuit 41 switches the flag.

(A) When FLG = A: Change state of arm A (arrow A in FIG. 21). (B) When FLG = B: Change state of arm B (arrow B in FIG. 21). For example, 40b has a switching state and a single-phase NPC
When the potential level of the inverter changes from +1 to +2,
There is no room for selecting the switching, and the next element to be switched is uniquely determined, and the switching state of 40a is established. However, when the output potential level of the unit inverter changes from +2 to +1 from the state of 40a, there are two options of changing from 40a to 40b and changing to 40c. If the A-arm is switched in the previous switching and FLG = B, then 40c is output and FLG = A is set. Conversely, when the B arm was previously switched and FLG = A, 40b is output and FLG = B is set. In each single-phase NPC inverter, the switching state is determined as described above from the change in the output potential level, and a gate pulse is applied to each switching element.

The switching waveforms in the single-phase NPC inverter are substantially the same as in FIG.

As described above, in the ninth embodiment, in a power converter in which a single-phase NPC inverter is star-connected for each phase, control can be performed using one PWM circuit 12 and a switching decision circuit 36. The configuration can be made compact. In addition, when there are different switching states at the same output potential level, by switching the switching element that has not been switched last time preferentially, the switching of each switching element in the single-phase NPC inverter can be dispersed, and the neutral point Since the flowing current can be equalized positively and negatively, the voltage fluctuation at the neutral point can be suppressed. The case of a single-phase NPC inverter has been described above with respect to the unit inverter. However, even in the case of a multi-level single-phase inverter having five or more levels, the same processing can be performed by extending the switching state transition.

FIG. 24 shows a tenth embodiment of the present invention. In FIG. 24, components that are the same as or equivalent to those in FIG. 18 are denoted by the same reference numerals as those described above, and redundant description will be omitted. In the present embodiment,
In the switching control circuit 34U, the PWM circuit is replaced with a hysteresis comparator 23 and an output potential level holding circuit 24 which receive an error signal between the current references Iuref, Ivref, Iwref and current feedback Iu, Iv, Iw. When the error signal exceeds the hysteresis width as shown in FIG. 15, the hysteresis comparator 23 outputs a pulse in which the switching signals U ₁ , V ₁ and W ₁ are switched on and off. The output potential level holding circuit 24 stores the current potential level output from the inverter, detects the rise and fall of the gate pulse from the hysteresis comparator 23, and increases the potential level by 1 when the gate pulse rises. In the case of falling, the potential level is reduced by one. Then, it is input to the switching determination circuit 36 as the potential level Iv1 to be output by the unit inverter.

In the seventh, eighth, and ninth embodiments, the output potential of the single-phase NPC inverter is obtained from the gate pulse and the output of the voltage reference level determination circuit 35. However, the hysteresis comparator 23 and the output potential level holding By using the circuit 24, the same operation and effect can be obtained.
By doing so, the subsequent processing can be the same as in the seventh, eighth, and ninth embodiments, and the hysteresis comparator can be applied to a multilevel single-phase inverter.

[0099]

As described above, according to the present invention,
First, by configuring the switching control means with one gate pulse generation means and distribution means for each phase, it is possible to simplify and reduce the size, and to increase the cost and reliability.

Secondly, in a power converter composed of multiple inverters, switching loss can be balanced by avoiding switching being concentrated on elements in each unit inverter for a specific period.

Third, even in a switching element having a limitation on the minimum on-pulse width, by correcting the uncontrollable region,
The present invention can be applied to a power converter including a multi-level inverter and multiple inverters.

Fourth, by configuring the gate pulse generation means with a hysteresis comparator, a PWM gate pulse can be generated with a simpler hardware configuration.

Fifth, since the switching control means is constituted by one gate pulse generation means and switching decision means for each unit inverter, the switching element capable of suppressing the imbalance of the DC voltage is given priority. Switching can suppress fluctuations in the neutral point potential, and can be economical and increase reliability.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a power conversion device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an output potential level and a voltage reference before conversion in the first embodiment.

FIG. 3 is a diagram showing a relationship between an output potential level and a converted voltage reference in the first embodiment.

FIG. 4 is a block diagram illustrating an internal configuration of a distribution circuit in FIG. 1;

FIG. 5 is a block diagram of a second embodiment of the present invention.

FIG. 6 is a diagram showing a relationship between an output potential level and a voltage reference before conversion in the second embodiment.

FIG. 7 is a circuit diagram showing an internal configuration of a distribution circuit in FIG.

FIG. 8 is a diagram showing a queue for determining a unit inverter to be switched in the second embodiment.

FIG. 9 is a diagram showing a switching state change of an element for determining an element to be switched in the second embodiment.

FIG. 10 is a diagram showing an example of a switching waveform of a unit inverter in the second embodiment.

FIG. 11 is a circuit diagram according to a third embodiment of the present invention.

FIG. 12 is a block diagram of a fourth embodiment of the present invention.

FIG. 13 is a circuit diagram according to a fifth embodiment of the present invention.

14 is a block diagram showing an internal configuration of a distribution circuit in FIG.

FIG. 15 is a diagram showing an example of a switching waveform in the fifth embodiment.

FIG. 16 is a block diagram of a sixth embodiment of the present invention.

17 is a circuit diagram showing an internal configuration of a distribution circuit in FIG.

FIG. 18 is a block diagram of a seventh embodiment of the present invention.

FIG. 19 is a diagram showing a relationship between an output potential level and a voltage reference before conversion in the seventh embodiment.

FIG. 20 is a diagram showing a relationship between an output potential level and a converted voltage reference in the seventh embodiment.

FIG. 21 is a diagram showing a switching state change of an element for determining an element to be switched in the seventh embodiment.

FIG. 22 is a block diagram of an eighth embodiment of the present invention.

FIG. 23 is a block diagram of a ninth embodiment of the present invention.

FIG. 24 is a block diagram according to a tenth embodiment of the present invention.

FIG. 25 is a circuit diagram of a conventional NPC inverter device.

FIG. 26 is a diagram showing an output waveform of the conventional NPC inverter device.

FIG. 27 is a block diagram of a conventional multiple inverter device.

FIG. 28 is a circuit diagram showing an internal configuration of a unit inverter in FIG. 27.

FIG. 29 is a diagram showing an output waveform of the conventional multiplex inverter device.

FIG. 30 is a diagram showing output waveforms when a minimum on-pulse width measure is taken in a conventional inverter device.

FIG. 31 is a block diagram of a conventional multiple inverter device of a single-phase multi-level three-phase star connection system.

FIG. 32 is a circuit diagram showing an internal configuration of the single-phase NPC inverter in FIG. 31.

FIG. 33 is a diagram showing an output voltage waveform of the multiplex inverter device of FIG. 31.

[Explanation of symbols]

 1 DC power supply 3A, 3B, 3U, 3V, 3W Switching arm 4U-4W, 5U-5W, 6U-6W, 7U-7W, 8
U ~ 8W, 9U ~ 9W, 31U ~ 31W, 32U ~ 32
W, 33U-33W, 34U-34W Switching system
Control circuit (switching control means) 11 voltage reference conversion circuit 12 PWM circuit (gate pulse generation means) 13a to 13d distribution circuit (distribution means) 14 output potential level determination circuit (output potential level determination means)
Stage) 15a, 15b Switching element selection circuit (switch)
Element selection means) 16 unit inverter selection circuit (unit inverter selection
17) Element selection circuit in unit inverter (unit inverter)
18a, 18b Gate pulse allocation circuit (gate pulse
21 and 22 Voltage reference correction circuit (voltage reference correction means) 23 Hysteresis comparator (gate pulse generation means)
Stage) 28U, 28V, 28W, 28U₁, 28U_Two, 28V
₁, 28V_Two, 28W ₁, 28W_Two  Unit inverter S₁~ S_Four  Switching element 35 Voltage reference level determination circuit (voltage reference level determination circuit)
Stage) 36 switching decision circuit (switching decision means) 37 voltage detection circuit (DC voltage monitoring means) 38 current detection circuit (output current detection means) 39 switching state storage circuit (switching state record)
41) Switching arm storage circuit (switching arm)
Storage means)

Claims (13)

[Claims] A DC voltage from a DC power supply is divided into a plurality of potentials, and an AC voltage having three or more potential levels is obtained by ON / OFF control of a plurality of switching elements supplied with the divided DC voltage. 2 output switching arms
In a power converter that has more than one phase and obtains multi-phase AC power of variable frequency and variable voltage, one is provided for each phase, and a single phase and amplitude carrier and a single phase and amplitude carrier are provided. A gate pulse generating means for generating a pulse width-modulated gate pulse by comparing with a voltage reference having a correspondingly converted voltage level; and a gate pulse output from the gate pulse generating means being transmitted to any of the plurality of switching elements. A power converter characterized in that on / off of the plurality of switching elements is controlled by switching control means having distribution means for determining whether to distribute. 2. The output potential level determining means for determining a potential level to be output by the switching arm when a switching element is switched by a gate pulse output from the gate pulse generating means; Switching element selecting means for selecting a switching element that changes the output state to output the determined potential level from the current switching state of the switching element as an element to be switched next; and the gate to the selected switching element. 2. The power converter according to claim 1, further comprising a gate pulse allocating unit that outputs a gate pulse output from the pulse generating unit and outputs a gate pulse that maintains a current state to a switching element that is not selected. . 3. A switching arm that divides a DC voltage from a DC power supply into a plurality of potentials and outputs three or more potential levels by on / off control of a plurality of switching elements to which the divided DC voltage is supplied. , Two or more unit inverters having two are connected in multiplex to form an inverter group,
In a power converter having two or more inverter groups and obtaining multi-phase DC power of variable frequency and variable voltage, one is provided for each phase, a carrier having a single phase and amplitude, A gate pulse generating means for generating a pulse pulse modulated by comparing with a voltage reference obtained by converting a voltage level corresponding to a carrier wave having an amplitude, and a gate pulse output from the gate pulse generating means, Power conversion control means for controlling on / off of a plurality of switching elements in the two unit inverters by switching control means having distribution means for deciding which switching element to distribute to which of the unit inverters. apparatus. 4. The output potential level determining means for determining a potential level to be output by each phase when a switching element is switched by a gate pulse output from the gate pulse generating means; A unit inverter selecting means for storing a current output potential level of the inverter and selecting a unit inverter whose state has not changed for a longest time among unit inverters capable of realizing the output of the determined potential level in one switching operation And the current switching state of each switching element in each of the unit inverters and the order of occurrence of switching are stored, and the current state of switching of each switching element and the order of occurrence of switching are stored in the selected unit inverter according to the current state. Output state to output the determined potential level Switching element selecting means in the unit inverter for selecting a switching element for changing the switching element as a next switching element; and outputting a gate pulse output from the gate pulse generating means to the selected switching element, and selecting a switching element not selected. 4. The power converter according to claim 3, wherein all switching elements in the unit inverter and the unselected unit inverter have a gate pulse allocating unit that outputs a gate pulse that maintains a current state. 5. The apparatus according to claim 1, further comprising voltage reference correction means for correcting the voltage reference so that a gate pulse width output from the gate pulse generation means does not become smaller than a specific width. Power converter. 6. The power converter according to claim 5, wherein said voltage reference correction means corrects the voltage reference so that the time average is equal to the voltage reference of each phase. 7. A DC voltage from a DC power supply is divided into a plurality of potentials, and an AC voltage having three or more potential levels is obtained by on / off control of a plurality of switching elements supplied with the divided DC voltage. 2 output switching arms
In a power converter that has one or more unit inverters and obtains multi-phase AC power of variable frequency and variable voltage, one is provided for each phase and has a single phase and amplitude with respect to a given voltage reference. Voltage reference conversion means for converting a voltage level corresponding to a carrier, voltage reference level determination means for determining a voltage region to which the voltage reference belongs, and pulse width modulation by comparing the carrier with the converted voltage reference A gate pulse generating means for generating a gate pulse, a DC voltage monitoring means for monitoring the divided DC voltages, an output current detecting means for detecting an output current of the unit inverter of each phase, Switching state storage means for storing a current state of each switching element, the divided DC voltage, the output current, the gate pulse, and the voltage Switching control means for determining the next switching state of all the switching elements in the unit inverter from the current state of the switching elements and the current state of each of the switching elements. A power converter characterized by the following. 8. The switching determining means changes the state of the switching element so that current flows out of the neutral point when the potential of the neutral point, which is each DC voltage dividing point, is higher than the equilibrium point. The power converter according to claim 7, wherein when the potential at the neutral point is lower than the equilibrium point, the next switching state is determined so that the current flows into the neutral point. 9. The apparatus according to claim 7, wherein a given current command value is used in place of said output current detecting means.
The power converter according to any one of the preceding claims. 10. A DC voltage from a DC power supply is divided into a plurality of potentials, and an AC voltage having three or more potential levels is obtained by on / off control of a plurality of switching elements supplied with the divided DC voltage. It has one or more unit inverters with two switching arms to output, variable frequency,
In a power converter that obtains multi-phase AC power of variable voltage,
Voltage reference conversion means provided for each phase for converting a voltage level corresponding to a carrier having a single phase and amplitude with respect to a given voltage reference, and a voltage for determining a voltage region to which the voltage reference belongs Reference level determining means, gate pulse generating means for generating a pulse pulse modulated by comparing the carrier with the converted voltage reference, and switching for storing a current state of each switching element in the unit inverter. State storage means, switching arm storage means for storing the last switched arm of the two arms in the unit inverter, switching arm information just switched, the gate pulse, the voltage domain, and each of the switching elements From the current state of the next switching of all the switching elements in the unit inverter Power conversion apparatus characterized by controlling the on and off of said plurality of switching elements by a switching control means and a switching determination means for determining the switching state. 11. When there are a plurality of switching states that can be output, the switching determination means determines a switching state such that another arm is switched with respect to an arm that has been switched immediately before and stored in the switching arm storage means. 11. The method according to claim 10, wherein
The power converter according to any one of the preceding claims. 12. The next switching state determined by the switching determination means is a state that can be shifted to the current switching state by performing one switching operation of any one of the switching elements. The power converter according to claim 7 or 10, wherein the output of the inverter changes with the divided DC voltage as a minimum unit. 13. The gate pulse generation means according to claim 1, wherein said comparator is configured to generate a pulse width-modulated gate pulse by comparing a carrier having a single phase and amplitude with a voltage reference obtained by converting a voltage level. And a hysteresis comparator for generating a pulse width-modulated gate pulse when an error signal between the current and the output current exceeds a specific hysteresis.
Or the power converter according to 10.